17fb6577bSAlexander Graf /* 27fb6577bSAlexander Graf * QEMU ICH Emulation 37fb6577bSAlexander Graf * 47fb6577bSAlexander Graf * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de> 57fb6577bSAlexander Graf * Copyright (c) 2010 Alexander Graf <agraf@suse.de> 67fb6577bSAlexander Graf * 77fb6577bSAlexander Graf * This library is free software; you can redistribute it and/or 87fb6577bSAlexander Graf * modify it under the terms of the GNU Lesser General Public 97fb6577bSAlexander Graf * License as published by the Free Software Foundation; either 1061f3c91aSChetan Pant * version 2.1 of the License, or (at your option) any later version. 117fb6577bSAlexander Graf * 127fb6577bSAlexander Graf * This library is distributed in the hope that it will be useful, 137fb6577bSAlexander Graf * but WITHOUT ANY WARRANTY; without even the implied warranty of 147fb6577bSAlexander Graf * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 157fb6577bSAlexander Graf * Lesser General Public License for more details. 167fb6577bSAlexander Graf * 177fb6577bSAlexander Graf * You should have received a copy of the GNU Lesser General Public 187fb6577bSAlexander Graf * License along with this library; if not, see <http://www.gnu.org/licenses/>. 197fb6577bSAlexander Graf * 207fb6577bSAlexander Graf * 217fb6577bSAlexander Graf * lspci dump of a ICH-9 real device 227fb6577bSAlexander Graf * 237fb6577bSAlexander Graf * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0]) 247fb6577bSAlexander Graf * Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] 257fb6577bSAlexander Graf * Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ 267fb6577bSAlexander Graf * Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 277fb6577bSAlexander Graf * Latency: 0 287fb6577bSAlexander Graf * Interrupt: pin B routed to IRQ 222 297fb6577bSAlexander Graf * Region 0: I/O ports at d000 [size=8] 307fb6577bSAlexander Graf * Region 1: I/O ports at cc00 [size=4] 317fb6577bSAlexander Graf * Region 2: I/O ports at c880 [size=8] 327fb6577bSAlexander Graf * Region 3: I/O ports at c800 [size=4] 337fb6577bSAlexander Graf * Region 4: I/O ports at c480 [size=32] 347fb6577bSAlexander Graf * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K] 357fb6577bSAlexander Graf * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+ 367fb6577bSAlexander Graf * Address: fee0f00c Data: 41d9 377fb6577bSAlexander Graf * Capabilities: [70] Power Management version 3 387fb6577bSAlexander Graf * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) 397fb6577bSAlexander Graf * Status: D0 PME-Enable- DSel=0 DScale=0 PME- 407fb6577bSAlexander Graf * Capabilities: [a8] SATA HBA <?> 417fb6577bSAlexander Graf * Capabilities: [b0] Vendor Specific Information <?> 427fb6577bSAlexander Graf * Kernel driver in use: ahci 437fb6577bSAlexander Graf * Kernel modules: ahci 447fb6577bSAlexander Graf * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00 457fb6577bSAlexander Graf * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00 467fb6577bSAlexander Graf * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29 477fb6577bSAlexander Graf * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00 487fb6577bSAlexander Graf * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 497fb6577bSAlexander Graf * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 507fb6577bSAlexander Graf * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 517fb6577bSAlexander Graf * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 527fb6577bSAlexander Graf * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00 537fb6577bSAlexander Graf * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00 547fb6577bSAlexander Graf * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00 557fb6577bSAlexander Graf * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 567fb6577bSAlexander Graf * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 577fb6577bSAlexander Graf * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 587fb6577bSAlexander Graf * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 597fb6577bSAlexander Graf * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 607fb6577bSAlexander Graf * 617fb6577bSAlexander Graf */ 627fb6577bSAlexander Graf 6353239262SPeter Maydell #include "qemu/osdep.h" 64da9f1172SPhilippe Mathieu-Daudé #include "hw/irq.h" 65a9c94277SMarkus Armbruster #include "hw/pci/msi.h" 66a9c94277SMarkus Armbruster #include "hw/pci/pci.h" 67d6454270SMarkus Armbruster #include "migration/vmstate.h" 680b8fa32fSMarkus Armbruster #include "qemu/module.h" 69a9c94277SMarkus Armbruster #include "hw/isa/isa.h" 709c17d615SPaolo Bonzini #include "sysemu/dma.h" 71a9c94277SMarkus Armbruster #include "hw/ide/pci.h" 72d407be08SPhilippe Mathieu-Daudé #include "hw/ide/ahci-pci.h" 732f73edacSBALATON Zoltan #include "ahci-internal.h" 7403c7a6a8SSebastian Herbszt 75c8b5b20fSJohn Snow #define ICH9_MSI_CAP_OFFSET 0x80 76465f1ab1SDaniel Verkamp #define ICH9_SATA_CAP_OFFSET 0xA8 77465f1ab1SDaniel Verkamp 78465f1ab1SDaniel Verkamp #define ICH9_IDP_BAR 4 79465f1ab1SDaniel Verkamp #define ICH9_MEM_BAR 5 80465f1ab1SDaniel Verkamp 81465f1ab1SDaniel Verkamp #define ICH9_IDP_INDEX 0x10 82465f1ab1SDaniel Verkamp #define ICH9_IDP_INDEX_LOG2 0x04 83465f1ab1SDaniel Verkamp 84a2623021SJason Baron static const VMStateDescription vmstate_ich9_ahci = { 85a2623021SJason Baron .name = "ich9_ahci", 86a2623021SJason Baron .version_id = 1, 878595c054SRichard Henderson .fields = (const VMStateField[]) { 880d3aea56SAndreas Färber VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState), 89a2623021SJason Baron VMSTATE_AHCI(ahci, AHCIPCIState), 90a2623021SJason Baron VMSTATE_END_OF_LIST() 91a2623021SJason Baron }, 92b7ce1b27SGerd Hoffmann }; 93b7ce1b27SGerd Hoffmann 948ab60a07SJan Kiszka static void pci_ich9_reset(DeviceState *dev) 95868a1a52SJan Kiszka { 96aa3c41fbSEduardo Habkost AHCIPCIState *d = ICH9_AHCI(dev); 97868a1a52SJan Kiszka 988ab60a07SJan Kiszka ahci_reset(&d->ahci); 99868a1a52SJan Kiszka } 100868a1a52SJan Kiszka 1010487eea4SPeter Crosthwaite static void pci_ich9_ahci_init(Object *obj) 1020487eea4SPeter Crosthwaite { 1039a4b35f5SPhilippe Mathieu-Daudé AHCIPCIState *d = ICH9_AHCI(obj); 1040487eea4SPeter Crosthwaite 1050487eea4SPeter Crosthwaite ahci_init(&d->ahci, DEVICE(obj)); 1060487eea4SPeter Crosthwaite } 1070487eea4SPeter Crosthwaite 108b8a2dac0SMarkus Armbruster static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) 10903c7a6a8SSebastian Herbszt { 1109a4b35f5SPhilippe Mathieu-Daudé AHCIPCIState *d; 111465f1ab1SDaniel Verkamp int sata_cap_offset; 112465f1ab1SDaniel Verkamp uint8_t *sata_cap; 113aa3c41fbSEduardo Habkost d = ICH9_AHCI(dev); 1141108b2f8SCao jin int ret; 11503c7a6a8SSebastian Herbszt 116be021501SPhilippe Mathieu-Daudé d->ahci.ports = 6; 117be021501SPhilippe Mathieu-Daudé ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev)); 11869c8944fSMichael S. Tsirkin 1190d3aea56SAndreas Färber pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1); 12003c7a6a8SSebastian Herbszt 1210d3aea56SAndreas Färber dev->config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ 1220d3aea56SAndreas Färber dev->config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */ 1230d3aea56SAndreas Färber pci_config_set_interrupt_pin(dev->config, 1); 12403c7a6a8SSebastian Herbszt 12503c7a6a8SSebastian Herbszt /* XXX Software should program this register */ 1260d3aea56SAndreas Färber dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ 12703c7a6a8SSebastian Herbszt 1289e64f8a3SMarcel Apfelbaum d->ahci.irq = pci_allocate_irq(dev); 12903c7a6a8SSebastian Herbszt 1300d3aea56SAndreas Färber pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO, 131465f1ab1SDaniel Verkamp &d->ahci.idp); 1320d3aea56SAndreas Färber pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY, 133465f1ab1SDaniel Verkamp &d->ahci.mem); 134465f1ab1SDaniel Verkamp 13527841278SMao Zhongyi sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA, 136b8a2dac0SMarkus Armbruster ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE, 137b8a2dac0SMarkus Armbruster errp); 138465f1ab1SDaniel Verkamp if (sata_cap_offset < 0) { 139b8a2dac0SMarkus Armbruster return; 140465f1ab1SDaniel Verkamp } 141465f1ab1SDaniel Verkamp 1420d3aea56SAndreas Färber sata_cap = dev->config + sata_cap_offset; 143465f1ab1SDaniel Verkamp pci_set_word(sata_cap + SATA_CAP_REV, 0x10); 144465f1ab1SDaniel Verkamp pci_set_long(sata_cap + SATA_CAP_BAR, 145465f1ab1SDaniel Verkamp (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4)); 146465f1ab1SDaniel Verkamp d->ahci.idp_offset = ICH9_IDP_INDEX; 14796d19bcbSJan Kiszka 148c8b5b20fSJohn Snow /* Although the AHCI 1.3 specification states that the first capability 149c8b5b20fSJohn Snow * should be PMCAP, the Intel ICH9 data sheet specifies that the ICH9 150c8b5b20fSJohn Snow * AHCI device puts the MSI capability first, pointing to 0x80. */ 1511108b2f8SCao jin ret = msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false, NULL); 1521108b2f8SCao jin /* Any error other than -ENOTSUP(board's MSI support is broken) 1531108b2f8SCao jin * is a programming error. Fall back to INTx silently on -ENOTSUP */ 1541108b2f8SCao jin assert(!ret || ret == -ENOTSUP); 15503c7a6a8SSebastian Herbszt } 15603c7a6a8SSebastian Herbszt 157f90c2bcdSAlex Williamson static void pci_ich9_uninit(PCIDevice *dev) 1587fb6577bSAlexander Graf { 1599a4b35f5SPhilippe Mathieu-Daudé AHCIPCIState *d; 160aa3c41fbSEduardo Habkost d = ICH9_AHCI(dev); 1617fb6577bSAlexander Graf 1627fb6577bSAlexander Graf msi_uninit(dev); 1632c4b9d0eSAlexander Graf ahci_uninit(&d->ahci); 1649e64f8a3SMarcel Apfelbaum qemu_free_irq(d->ahci.irq); 1657fb6577bSAlexander Graf } 1667fb6577bSAlexander Graf 16740021f08SAnthony Liguori static void ich_ahci_class_init(ObjectClass *klass, void *data) 16840021f08SAnthony Liguori { 16939bffca2SAnthony Liguori DeviceClass *dc = DEVICE_CLASS(klass); 17040021f08SAnthony Liguori PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 17140021f08SAnthony Liguori 172b8a2dac0SMarkus Armbruster k->realize = pci_ich9_ahci_realize; 17340021f08SAnthony Liguori k->exit = pci_ich9_uninit; 17440021f08SAnthony Liguori k->vendor_id = PCI_VENDOR_ID_INTEL; 17540021f08SAnthony Liguori k->device_id = PCI_DEVICE_ID_INTEL_82801IR; 17640021f08SAnthony Liguori k->revision = 0x02; 17740021f08SAnthony Liguori k->class_id = PCI_CLASS_STORAGE_SATA; 178a2623021SJason Baron dc->vmsd = &vmstate_ich9_ahci; 1798ab60a07SJan Kiszka dc->reset = pci_ich9_reset; 180125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 18140021f08SAnthony Liguori } 18240021f08SAnthony Liguori 1838c43a6f0SAndreas Färber static const TypeInfo ich_ahci_info = { 184fd58922cSPeter Crosthwaite .name = TYPE_ICH9_AHCI, 18539bffca2SAnthony Liguori .parent = TYPE_PCI_DEVICE, 18639bffca2SAnthony Liguori .instance_size = sizeof(AHCIPCIState), 1870487eea4SPeter Crosthwaite .instance_init = pci_ich9_ahci_init, 18840021f08SAnthony Liguori .class_init = ich_ahci_class_init, 189fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 190fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 191fd3b02c8SEduardo Habkost { }, 192fd3b02c8SEduardo Habkost }, 19303c7a6a8SSebastian Herbszt }; 19403c7a6a8SSebastian Herbszt 19583f7d43aSAndreas Färber static void ich_ahci_register_types(void) 19603c7a6a8SSebastian Herbszt { 19739bffca2SAnthony Liguori type_register_static(&ich_ahci_info); 19803c7a6a8SSebastian Herbszt } 19983f7d43aSAndreas Färber 20083f7d43aSAndreas Färber type_init(ich_ahci_register_types) 201