1 /*
2 * QEMU ICH9 Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2009, 2010, 2011
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 *
10 * This is based on piix.c, but heavily modified.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/log.h"
33 #include "cpu.h"
34 #include "qapi/error.h"
35 #include "qapi/visitor.h"
36 #include "qemu/range.h"
37 #include "hw/dma/i8257.h"
38 #include "hw/isa/isa.h"
39 #include "migration/vmstate.h"
40 #include "hw/irq.h"
41 #include "hw/isa/apm.h"
42 #include "hw/pci/pci.h"
43 #include "hw/southbridge/ich9.h"
44 #include "hw/acpi/acpi.h"
45 #include "hw/acpi/ich9.h"
46 #include "hw/acpi/ich9_timer.h"
47 #include "hw/pci/pci_bus.h"
48 #include "hw/qdev-properties.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/sysemu.h"
51 #include "hw/core/cpu.h"
52 #include "hw/nvram/fw_cfg.h"
53 #include "qemu/cutils.h"
54 #include "hw/acpi/acpi_aml_interface.h"
55 #include "trace.h"
56
57 /*****************************************************************************/
58 /* ICH9 LPC PCI to ISA bridge */
59
60 /* chipset configuration register
61 * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
62 * are used.
63 * Although it's not pci configuration space, it's little endian as Intel.
64 */
65
ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS],uint16_t ir)66 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
67 {
68 int intx;
69 for (intx = 0; intx < PCI_NUM_PINS; intx++) {
70 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
71 }
72 }
73
ich9_cc_update(ICH9LPCState * lpc)74 static void ich9_cc_update(ICH9LPCState *lpc)
75 {
76 int slot;
77 int pci_intx;
78
79 const int reg_offsets[] = {
80 ICH9_CC_D25IR,
81 ICH9_CC_D26IR,
82 ICH9_CC_D27IR,
83 ICH9_CC_D28IR,
84 ICH9_CC_D29IR,
85 ICH9_CC_D30IR,
86 ICH9_CC_D31IR,
87 };
88 const int *offset;
89
90 /* D{25 - 31}IR, but D30IR is read only to 0. */
91 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
92 if (slot == 30) {
93 continue;
94 }
95 ich9_cc_update_ir(lpc->irr[slot],
96 pci_get_word(lpc->chip_config + *offset));
97 }
98
99 /*
100 * D30: DMI2PCI bridge
101 * It is arbitrarily decided how INTx lines of PCI devices behind
102 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
103 * INT[A-D] are connected to PIRQ[E-H]
104 */
105 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
106 lpc->irr[30][pci_intx] = pci_intx + 4;
107 }
108 }
109
ich9_cc_init(ICH9LPCState * lpc)110 static void ich9_cc_init(ICH9LPCState *lpc)
111 {
112 int slot;
113 int intx;
114
115 /* the default irq routing is arbitrary as long as it matches with
116 * acpi irq routing table.
117 * The one that is incompatible with piix_pci(= bochs) one is
118 * intentionally chosen to let the users know that the different
119 * board is used.
120 *
121 * int[A-D] -> pirq[E-F]
122 * avoid pirq A-D because they are used for pci express port
123 */
124 for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
125 for (intx = 0; intx < PCI_NUM_PINS; intx++) {
126 lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
127 }
128 }
129 ich9_cc_update(lpc);
130 }
131
ich9_cc_reset(ICH9LPCState * lpc)132 static void ich9_cc_reset(ICH9LPCState *lpc)
133 {
134 uint8_t *c = lpc->chip_config;
135
136 memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
137
138 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
139 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
140 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
141 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
142 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
143 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
144 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
145 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
146
147 ich9_cc_update(lpc);
148 }
149
ich9_cc_addr_len(uint64_t * addr,unsigned * len)150 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
151 {
152 *addr &= ICH9_CC_ADDR_MASK;
153 if (*addr + *len >= ICH9_CC_SIZE) {
154 *len = ICH9_CC_SIZE - *addr;
155 }
156 }
157
158 /* val: little endian */
ich9_cc_write(void * opaque,hwaddr addr,uint64_t val,unsigned len)159 static void ich9_cc_write(void *opaque, hwaddr addr,
160 uint64_t val, unsigned len)
161 {
162 ICH9LPCState *lpc = (ICH9LPCState *)opaque;
163
164 trace_ich9_cc_write(addr, val, len);
165 ich9_cc_addr_len(&addr, &len);
166 memcpy(lpc->chip_config + addr, &val, len);
167 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
168 ich9_cc_update(lpc);
169 }
170
171 /* return value: little endian */
ich9_cc_read(void * opaque,hwaddr addr,unsigned len)172 static uint64_t ich9_cc_read(void *opaque, hwaddr addr,
173 unsigned len)
174 {
175 ICH9LPCState *lpc = (ICH9LPCState *)opaque;
176
177 uint32_t val = 0;
178 ich9_cc_addr_len(&addr, &len);
179 memcpy(&val, lpc->chip_config + addr, len);
180 trace_ich9_cc_read(addr, val, len);
181 return val;
182 }
183
184 /* IRQ routing */
185 /* */
ich9_lpc_rout(uint8_t pirq_rout,int * pic_irq,int * pic_dis)186 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
187 {
188 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
189 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
190 }
191
ich9_lpc_pic_irq(ICH9LPCState * lpc,int pirq_num,int * pic_irq,int * pic_dis)192 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num,
193 int *pic_irq, int *pic_dis)
194 {
195 switch (pirq_num) {
196 case 0 ... 3: /* A-D */
197 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num],
198 pic_irq, pic_dis);
199 return;
200 case 4 ... 7: /* E-H */
201 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)],
202 pic_irq, pic_dis);
203 return;
204 default:
205 break;
206 }
207 abort();
208 }
209
210 /* gsi: i8259+ioapic irq 0-15, otherwise assert */
ich9_lpc_update_pic(ICH9LPCState * lpc,int gsi)211 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi)
212 {
213 int i, pic_level;
214
215 assert(gsi < ICH9_LPC_PIC_NUM_PINS);
216
217 /* The pic level is the logical OR of all the PCI irqs mapped to it */
218 pic_level = 0;
219 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
220 int tmp_irq;
221 int tmp_dis;
222 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
223 if (!tmp_dis && tmp_irq == gsi) {
224 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i);
225 }
226 }
227 if (gsi == lpc->sci_gsi) {
228 pic_level |= lpc->sci_level;
229 }
230
231 qemu_set_irq(lpc->gsi[gsi], pic_level);
232 }
233
234 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
ich9_pirq_to_gsi(int pirq)235 static int ich9_pirq_to_gsi(int pirq)
236 {
237 return pirq + ICH9_LPC_PIC_NUM_PINS;
238 }
239
ich9_gsi_to_pirq(int gsi)240 static int ich9_gsi_to_pirq(int gsi)
241 {
242 return gsi - ICH9_LPC_PIC_NUM_PINS;
243 }
244
245 /* gsi: ioapic irq 16-23, otherwise assert */
ich9_lpc_update_apic(ICH9LPCState * lpc,int gsi)246 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
247 {
248 int level = 0;
249
250 assert(gsi >= ICH9_LPC_PIC_NUM_PINS);
251
252 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi));
253 if (gsi == lpc->sci_gsi) {
254 level |= lpc->sci_level;
255 }
256
257 qemu_set_irq(lpc->gsi[gsi], level);
258 }
259
ich9_lpc_set_irq(void * opaque,int pirq,int level)260 static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
261 {
262 ICH9LPCState *lpc = opaque;
263 int pic_irq, pic_dis;
264
265 assert(0 <= pirq);
266 assert(pirq < ICH9_LPC_NB_PIRQS);
267
268 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq));
269 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
270 ich9_lpc_update_pic(lpc, pic_irq);
271 }
272
273 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to
274 * a given device irq pin.
275 */
ich9_lpc_map_irq(PCIDevice * pci_dev,int intx)276 static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
277 {
278 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
279 PCIBus *pci_bus = PCI_BUS(bus);
280 PCIDevice *lpc_pdev =
281 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)];
282 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev);
283
284 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
285 }
286
ich9_route_intx_pin_to_irq(void * opaque,int pirq_pin)287 static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
288 {
289 ICH9LPCState *lpc = opaque;
290 PCIINTxRoute route;
291 int pic_irq;
292 int pic_dis;
293
294 assert(0 <= pirq_pin);
295 assert(pirq_pin < ICH9_LPC_NB_PIRQS);
296
297 route.mode = PCI_INTX_ENABLED;
298 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis);
299 if (!pic_dis) {
300 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) {
301 route.irq = pic_irq;
302 } else {
303 route.mode = PCI_INTX_DISABLED;
304 route.irq = -1;
305 }
306 } else {
307 /*
308 * Strictly speaking, this is wrong. The PIRQ should be routed
309 * to *both* the I/O APIC and the PIC, on different pins. The
310 * I/O APIC has a fixed mapping to IRQ16-23, while the PIC is
311 * routed according to the PIRQx_ROUT configuration. But QEMU
312 * doesn't (yet) cope with the concept of pin numbers differing
313 * between PIC and I/O APIC, and neither does the in-kernel KVM
314 * irqchip support. So we route to the I/O APIC *only* if the
315 * routing to the PIC is disabled in the PIRQx_ROUT settings.
316 *
317 * This seems to work even if we boot a Linux guest with 'noapic'
318 * to make it use the legacy PIC, and then kexec directly into a
319 * new kernel which uses the I/O APIC. The new kernel explicitly
320 * disables the PIRQ routing even though it doesn't need to care.
321 */
322 route.irq = ich9_pirq_to_gsi(pirq_pin);
323 }
324
325 return route;
326 }
327
ich9_generate_smi(void)328 void ich9_generate_smi(void)
329 {
330 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
331 }
332
333 /* Returns -1 on error, IRQ number on success */
ich9_lpc_sci_irq(ICH9LPCState * lpc)334 static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
335 {
336 uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] &
337 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK;
338 switch (sel) {
339 case ICH9_LPC_ACPI_CTRL_9:
340 return 9;
341 case ICH9_LPC_ACPI_CTRL_10:
342 return 10;
343 case ICH9_LPC_ACPI_CTRL_11:
344 return 11;
345 case ICH9_LPC_ACPI_CTRL_20:
346 return 20;
347 case ICH9_LPC_ACPI_CTRL_21:
348 return 21;
349 default:
350 /* reserved */
351 qemu_log_mask(LOG_GUEST_ERROR,
352 "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel);
353 break;
354 }
355 return -1;
356 }
357
ich9_set_sci(void * opaque,int irq_num,int level)358 static void ich9_set_sci(void *opaque, int irq_num, int level)
359 {
360 ICH9LPCState *lpc = opaque;
361 int irq;
362
363 assert(irq_num == 0);
364 level = !!level;
365 if (level == lpc->sci_level) {
366 return;
367 }
368 lpc->sci_level = level;
369
370 irq = lpc->sci_gsi;
371 if (irq < 0) {
372 return;
373 }
374
375 if (irq >= ICH9_LPC_PIC_NUM_PINS) {
376 ich9_lpc_update_apic(lpc, irq);
377 } else {
378 ich9_lpc_update_pic(lpc, irq);
379 }
380 }
381
smi_features_ok_callback(void * opaque)382 static void smi_features_ok_callback(void *opaque)
383 {
384 ICH9LPCState *lpc = opaque;
385 uint64_t guest_features;
386 uint64_t guest_cpu_hotplug_features;
387
388 if (lpc->smi_features_ok) {
389 /* negotiation already complete, features locked */
390 return;
391 }
392
393 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features);
394 le64_to_cpus(&guest_features);
395 if (guest_features & ~lpc->smi_host_features) {
396 /* guest requests invalid features, leave @features_ok at zero */
397 return;
398 }
399
400 guest_cpu_hotplug_features = guest_features &
401 (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) |
402 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
403 if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) &&
404 guest_cpu_hotplug_features) {
405 /*
406 * cpu hot-[un]plug with SMI requires SMI broadcast,
407 * leave @features_ok at zero
408 */
409 return;
410 }
411
412 if (guest_cpu_hotplug_features ==
413 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) {
414 /* cpu hot-unplug is unsupported without cpu-hotplug */
415 return;
416 }
417
418 /* valid feature subset requested, lock it down, report success */
419 lpc->smi_negotiated_features = guest_features;
420 lpc->smi_features_ok = 1;
421 }
422
ich9_lpc_pm_init(ICH9LPCState * lpc)423 static void ich9_lpc_pm_init(ICH9LPCState *lpc)
424 {
425 qemu_irq sci_irq;
426 FWCfgState *fw_cfg = fw_cfg_find();
427
428 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
429 ich9_pm_init(PCI_DEVICE(lpc), &lpc->pm, sci_irq);
430
431 if (lpc->smi_host_features && fw_cfg) {
432 uint64_t host_features_le;
433
434 host_features_le = cpu_to_le64(lpc->smi_host_features);
435 memcpy(lpc->smi_host_features_le, &host_features_le,
436 sizeof host_features_le);
437 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features",
438 lpc->smi_host_features_le,
439 sizeof lpc->smi_host_features_le);
440
441 /* The other two guest-visible fields are cleared on device reset, we
442 * just link them into fw_cfg here.
443 */
444 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features",
445 NULL, NULL, NULL,
446 lpc->smi_guest_features_le,
447 sizeof lpc->smi_guest_features_le,
448 false);
449 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok",
450 smi_features_ok_callback, NULL, lpc,
451 &lpc->smi_features_ok,
452 sizeof lpc->smi_features_ok,
453 true);
454 }
455 }
456
457 /* APM */
458
ich9_apm_ctrl_changed(uint32_t val,void * arg)459 static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
460 {
461 ICH9LPCState *lpc = arg;
462
463 /* ACPI specs 3.0, 4.7.2.5 */
464 acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
465 val == ICH9_APM_ACPI_ENABLE,
466 val == ICH9_APM_ACPI_DISABLE);
467 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) {
468 return;
469 }
470
471 /* SMI_EN = PMBASE + 30. SMI control and enable register */
472 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
473 if (lpc->smi_negotiated_features &
474 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) {
475 CPUState *cs;
476 CPU_FOREACH(cs) {
477 cpu_interrupt(cs, CPU_INTERRUPT_SMI);
478 }
479 } else {
480 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI);
481 }
482 }
483 }
484
485 /* config:PMBASE */
486 static void
ich9_lpc_pmbase_sci_update(ICH9LPCState * lpc)487 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc)
488 {
489 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
490 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL);
491 int new_gsi;
492
493 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) {
494 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
495 } else {
496 pm_io_base = 0;
497 }
498
499 ich9_pm_iospace_update(&lpc->pm, pm_io_base);
500
501 new_gsi = ich9_lpc_sci_irq(lpc);
502 if (new_gsi == -1) {
503 return;
504 }
505 if (lpc->sci_level && new_gsi != lpc->sci_gsi) {
506 qemu_set_irq(lpc->pm.irq, 0);
507 lpc->sci_gsi = new_gsi;
508 qemu_set_irq(lpc->pm.irq, 1);
509 }
510 lpc->sci_gsi = new_gsi;
511 }
512
513 /* config:RCBA */
ich9_lpc_rcba_update(ICH9LPCState * lpc,uint32_t rcba_old)514 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old)
515 {
516 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
517
518 if (rcba_old & ICH9_LPC_RCBA_EN) {
519 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem);
520 }
521 if (rcba & ICH9_LPC_RCBA_EN) {
522 memory_region_add_subregion_overlap(get_system_memory(),
523 rcba & ICH9_LPC_RCBA_BA_MASK,
524 &lpc->rcrb_mem, 1);
525 }
526 }
527
528 /* config:GEN_PMCON* */
529 static void
ich9_lpc_pmcon_update(ICH9LPCState * lpc)530 ich9_lpc_pmcon_update(ICH9LPCState *lpc)
531 {
532 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1);
533 uint16_t wmask;
534
535 if (lpc->pm.swsmi_timer_enabled) {
536 ich9_pm_update_swsmi_timer(
537 &lpc->pm, lpc->pm.smi_en & ICH9_PMIO_SMI_EN_SWSMI_EN);
538 }
539 if (lpc->pm.periodic_timer_enabled) {
540 ich9_pm_update_periodic_timer(
541 &lpc->pm, lpc->pm.smi_en & ICH9_PMIO_SMI_EN_PERIODIC_EN);
542 }
543
544 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) {
545 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1);
546 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK;
547 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask);
548 lpc->pm.smi_en_wmask &= ~1;
549 }
550 }
551
ich9_lpc_post_load(void * opaque,int version_id)552 static int ich9_lpc_post_load(void *opaque, int version_id)
553 {
554 ICH9LPCState *lpc = opaque;
555
556 ich9_lpc_pmbase_sci_update(lpc);
557 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */);
558 ich9_lpc_pmcon_update(lpc);
559 return 0;
560 }
561
ich9_lpc_config_write(PCIDevice * d,uint32_t addr,uint32_t val,int len)562 static void ich9_lpc_config_write(PCIDevice *d,
563 uint32_t addr, uint32_t val, int len)
564 {
565 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
566 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
567
568 pci_default_write_config(d, addr, val, len);
569 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) ||
570 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) {
571 ich9_lpc_pmbase_sci_update(lpc);
572 }
573 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
574 ich9_lpc_rcba_update(lpc, rcba_old);
575 }
576 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) {
577 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
578 }
579 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
580 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
581 }
582 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) {
583 ich9_lpc_pmcon_update(lpc);
584 }
585 }
586
ich9_lpc_reset(DeviceState * qdev)587 static void ich9_lpc_reset(DeviceState *qdev)
588 {
589 PCIDevice *d = PCI_DEVICE(qdev);
590 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
591 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
592 int i;
593
594 for (i = 0; i < 4; i++) {
595 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
596 ICH9_LPC_PIRQ_ROUT_DEFAULT);
597 }
598 for (i = 0; i < 4; i++) {
599 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
600 ICH9_LPC_PIRQ_ROUT_DEFAULT);
601 }
602 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
603
604 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
605 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
606
607 ich9_cc_reset(lpc);
608
609 ich9_lpc_pmbase_sci_update(lpc);
610 ich9_lpc_rcba_update(lpc, rcba_old);
611
612 lpc->sci_level = 0;
613 lpc->rst_cnt = 0;
614
615 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le);
616 lpc->smi_features_ok = 0;
617 lpc->smi_negotiated_features = 0;
618 }
619
620 /* root complex register block is mapped into memory space */
621 static const MemoryRegionOps rcrb_mmio_ops = {
622 .read = ich9_cc_read,
623 .write = ich9_cc_write,
624 .endianness = DEVICE_LITTLE_ENDIAN,
625 };
626
ich9_lpc_machine_ready(Notifier * n,void * opaque)627 static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
628 {
629 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
630 MemoryRegion *io_as = pci_address_space_io(&s->d);
631 uint8_t *pci_conf;
632
633 pci_conf = s->d.config;
634 if (memory_region_present(io_as, 0x3f8)) {
635 /* com1 */
636 pci_conf[0x82] |= 0x01;
637 }
638 if (memory_region_present(io_as, 0x2f8)) {
639 /* com2 */
640 pci_conf[0x82] |= 0x02;
641 }
642 if (memory_region_present(io_as, 0x378)) {
643 /* lpt */
644 pci_conf[0x82] |= 0x04;
645 }
646 if (memory_region_present(io_as, 0x3f2)) {
647 /* floppy */
648 pci_conf[0x82] |= 0x08;
649 }
650 }
651
652 /* reset control */
ich9_rst_cnt_write(void * opaque,hwaddr addr,uint64_t val,unsigned len)653 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val,
654 unsigned len)
655 {
656 ICH9LPCState *lpc = opaque;
657
658 if (val & 4) {
659 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
660 return;
661 }
662 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
663 }
664
ich9_rst_cnt_read(void * opaque,hwaddr addr,unsigned len)665 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len)
666 {
667 ICH9LPCState *lpc = opaque;
668
669 return lpc->rst_cnt;
670 }
671
672 static const MemoryRegionOps ich9_rst_cnt_ops = {
673 .read = ich9_rst_cnt_read,
674 .write = ich9_rst_cnt_write,
675 .endianness = DEVICE_LITTLE_ENDIAN
676 };
677
ich9_lpc_initfn(Object * obj)678 static void ich9_lpc_initfn(Object *obj)
679 {
680 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
681
682 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
683 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
684
685 object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC);
686
687 qdev_init_gpio_out_named(DEVICE(lpc), lpc->gsi, ICH9_GPIO_GSI,
688 IOAPIC_NUM_PINS);
689
690 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT,
691 &lpc->sci_gsi, OBJ_PROP_FLAG_READ);
692 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
693 &acpi_enable_cmd, OBJ_PROP_FLAG_READ);
694 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
695 &acpi_disable_cmd, OBJ_PROP_FLAG_READ);
696 object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP,
697 &lpc->smi_negotiated_features,
698 OBJ_PROP_FLAG_READ);
699
700 ich9_pm_add_properties(obj, &lpc->pm);
701 }
702
ich9_lpc_realize(PCIDevice * d,Error ** errp)703 static void ich9_lpc_realize(PCIDevice *d, Error **errp)
704 {
705 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
706 PCIBus *pci_bus = pci_get_bus(d);
707 ISABus *isa_bus;
708 uint32_t irq;
709
710 if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) &&
711 !(lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) {
712 /*
713 * smi_features_ok_callback() throws an error on this.
714 *
715 * So bail out here instead of advertizing the invalid
716 * configuration and get obscure firmware failures from that.
717 */
718 error_setg(errp, "cpu hot-unplug requires cpu hot-plug");
719 return;
720 }
721
722 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(),
723 errp);
724 if (!isa_bus) {
725 return;
726 }
727
728 pci_set_long(d->wmask + ICH9_LPC_PMBASE,
729 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
730 pci_set_byte(d->wmask + ICH9_LPC_PMBASE,
731 ICH9_LPC_ACPI_CTRL_ACPI_EN |
732 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK);
733
734 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
735 "lpc-rcrb-mmio", ICH9_CC_SIZE);
736
737 ich9_cc_init(lpc);
738 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
739
740 lpc->machine_ready.notify = ich9_lpc_machine_ready;
741 qemu_add_machine_init_done_notifier(&lpc->machine_ready);
742
743 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc,
744 "lpc-reset-control", 1);
745 memory_region_add_subregion_overlap(pci_address_space_io(d),
746 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
747 1);
748
749 isa_bus_register_input_irqs(isa_bus, lpc->gsi);
750
751 i8257_dma_init(OBJECT(d), isa_bus, 0);
752
753 /* RTC */
754 qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000);
755 if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) {
756 return;
757 }
758 irq = object_property_get_uint(OBJECT(&lpc->rtc), "irq", &error_fatal);
759 isa_connect_gpio_out(ISA_DEVICE(&lpc->rtc), 0, irq);
760
761 pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS);
762 pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq);
763 pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq);
764
765 ich9_lpc_pm_init(lpc);
766 }
767
ich9_rst_cnt_needed(void * opaque)768 static bool ich9_rst_cnt_needed(void *opaque)
769 {
770 ICH9LPCState *lpc = opaque;
771
772 return (lpc->rst_cnt != 0);
773 }
774
775 static const VMStateDescription vmstate_ich9_rst_cnt = {
776 .name = "ICH9LPC/rst_cnt",
777 .version_id = 1,
778 .minimum_version_id = 1,
779 .needed = ich9_rst_cnt_needed,
780 .fields = (const VMStateField[]) {
781 VMSTATE_UINT8(rst_cnt, ICH9LPCState),
782 VMSTATE_END_OF_LIST()
783 }
784 };
785
ich9_smi_feat_needed(void * opaque)786 static bool ich9_smi_feat_needed(void *opaque)
787 {
788 ICH9LPCState *lpc = opaque;
789
790 return !buffer_is_zero(lpc->smi_guest_features_le,
791 sizeof lpc->smi_guest_features_le) ||
792 lpc->smi_features_ok;
793 }
794
795 static const VMStateDescription vmstate_ich9_smi_feat = {
796 .name = "ICH9LPC/smi_feat",
797 .version_id = 1,
798 .minimum_version_id = 1,
799 .needed = ich9_smi_feat_needed,
800 .fields = (const VMStateField[]) {
801 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState,
802 sizeof(uint64_t)),
803 VMSTATE_UINT8(smi_features_ok, ICH9LPCState),
804 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState),
805 VMSTATE_END_OF_LIST()
806 }
807 };
808
809 static const VMStateDescription vmstate_ich9_lpc = {
810 .name = "ICH9LPC",
811 .version_id = 1,
812 .minimum_version_id = 1,
813 .post_load = ich9_lpc_post_load,
814 .fields = (const VMStateField[]) {
815 VMSTATE_PCI_DEVICE(d, ICH9LPCState),
816 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState),
817 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs),
818 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE),
819 VMSTATE_UINT32(sci_level, ICH9LPCState),
820 VMSTATE_END_OF_LIST()
821 },
822 .subsections = (const VMStateDescription * const []) {
823 &vmstate_ich9_rst_cnt,
824 &vmstate_ich9_smi_feat,
825 NULL
826 }
827 };
828
829 static Property ich9_lpc_properties[] = {
830 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, false),
831 DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false),
832 DEFINE_PROP_BOOL("smm-enabled", ICH9LPCState, pm.smm_enabled, false),
833 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
834 ICH9_LPC_SMI_F_BROADCAST_BIT, true),
835 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features,
836 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true),
837 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features,
838 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, true),
839 DEFINE_PROP_BOOL("x-smi-swsmi-timer", ICH9LPCState,
840 pm.swsmi_timer_enabled, true),
841 DEFINE_PROP_BOOL("x-smi-periodic-timer", ICH9LPCState,
842 pm.periodic_timer_enabled, true),
843 DEFINE_PROP_END_OF_LIST(),
844 };
845
ich9_send_gpe(AcpiDeviceIf * adev,AcpiEventStatusBits ev)846 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
847 {
848 ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
849
850 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev);
851 }
852
build_ich9_isa_aml(AcpiDevAmlIf * adev,Aml * scope)853 static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
854 {
855 Aml *field;
856 BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
857 Aml *sb_scope = aml_scope("\\_SB");
858
859 /* ICH9 PCI to ISA irq remapping */
860 aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG,
861 aml_int(0x60), 0x0C));
862 /* Fields declarion has to happen *after* operation region */
863 field = aml_field("PCI0.SF8.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
864 aml_append(field, aml_named_field("PRQA", 8));
865 aml_append(field, aml_named_field("PRQB", 8));
866 aml_append(field, aml_named_field("PRQC", 8));
867 aml_append(field, aml_named_field("PRQD", 8));
868 aml_append(field, aml_reserved_field(0x20));
869 aml_append(field, aml_named_field("PRQE", 8));
870 aml_append(field, aml_named_field("PRQF", 8));
871 aml_append(field, aml_named_field("PRQG", 8));
872 aml_append(field, aml_named_field("PRQH", 8));
873 aml_append(sb_scope, field);
874 aml_append(scope, sb_scope);
875
876 qbus_build_aml(bus, scope);
877 }
878
ich9_lpc_class_init(ObjectClass * klass,void * data)879 static void ich9_lpc_class_init(ObjectClass *klass, void *data)
880 {
881 DeviceClass *dc = DEVICE_CLASS(klass);
882 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
883 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
884 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
885 AcpiDevAmlIfClass *amldevc = ACPI_DEV_AML_IF_CLASS(klass);
886
887 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
888 device_class_set_legacy_reset(dc, ich9_lpc_reset);
889 k->realize = ich9_lpc_realize;
890 dc->vmsd = &vmstate_ich9_lpc;
891 device_class_set_props(dc, ich9_lpc_properties);
892 k->config_write = ich9_lpc_config_write;
893 dc->desc = "ICH9 LPC bridge";
894 k->vendor_id = PCI_VENDOR_ID_INTEL;
895 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
896 k->revision = ICH9_A2_LPC_REVISION;
897 k->class_id = PCI_CLASS_BRIDGE_ISA;
898 /*
899 * Reason: part of ICH9 southbridge, needs to be wired up by
900 * pc_q35_init()
901 */
902 dc->user_creatable = false;
903 hc->pre_plug = ich9_pm_device_pre_plug_cb;
904 hc->plug = ich9_pm_device_plug_cb;
905 hc->unplug_request = ich9_pm_device_unplug_request_cb;
906 hc->unplug = ich9_pm_device_unplug_cb;
907 hc->is_hotpluggable_bus = ich9_pm_is_hotpluggable_bus;
908 adevc->ospm_status = ich9_pm_ospm_status;
909 adevc->send_event = ich9_send_gpe;
910 amldevc->build_dev_aml = build_ich9_isa_aml;
911 }
912
913 static const TypeInfo ich9_lpc_info = {
914 .name = TYPE_ICH9_LPC_DEVICE,
915 .parent = TYPE_PCI_DEVICE,
916 .instance_size = sizeof(ICH9LPCState),
917 .instance_init = ich9_lpc_initfn,
918 .class_init = ich9_lpc_class_init,
919 .interfaces = (InterfaceInfo[]) {
920 { TYPE_HOTPLUG_HANDLER },
921 { TYPE_ACPI_DEVICE_IF },
922 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
923 { TYPE_ACPI_DEV_AML_IF },
924 { }
925 }
926 };
927
ich9_lpc_register(void)928 static void ich9_lpc_register(void)
929 {
930 type_register_static(&ich9_lpc_info);
931 }
932
933 type_init(ich9_lpc_register);
934