1*06e23296SPhilippe Mathieu-Daudé /* SPDX-License-Identifier: GPL-2.0-only */
23a977deeSAkihiko Odaki /*
33a977deeSAkihiko Odaki * This is copied + edited from kernel header files in
43a977deeSAkihiko Odaki * drivers/net/ethernet/intel/igb
53a977deeSAkihiko Odaki */
63a977deeSAkihiko Odaki
73a977deeSAkihiko Odaki #ifndef HW_IGB_REGS_H_
83a977deeSAkihiko Odaki #define HW_IGB_REGS_H_
93a977deeSAkihiko Odaki
103a977deeSAkihiko Odaki #include "e1000x_regs.h"
113a977deeSAkihiko Odaki
123a977deeSAkihiko Odaki /* from igb/e1000_hw.h */
133a977deeSAkihiko Odaki
143a977deeSAkihiko Odaki #define E1000_DEV_ID_82576 0x10C9
153a977deeSAkihiko Odaki #define E1000_DEV_ID_82576_FIBER 0x10E6
163a977deeSAkihiko Odaki #define E1000_DEV_ID_82576_SERDES 0x10E7
173a977deeSAkihiko Odaki #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
183a977deeSAkihiko Odaki #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
193a977deeSAkihiko Odaki #define E1000_DEV_ID_82576_NS 0x150A
203a977deeSAkihiko Odaki #define E1000_DEV_ID_82576_NS_SERDES 0x1518
213a977deeSAkihiko Odaki #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
223a977deeSAkihiko Odaki
233a977deeSAkihiko Odaki /* Context Descriptor */
243a977deeSAkihiko Odaki struct e1000_adv_tx_context_desc {
253a977deeSAkihiko Odaki uint32_t vlan_macip_lens;
263a977deeSAkihiko Odaki uint32_t seqnum_seed;
273a977deeSAkihiko Odaki uint32_t type_tucmd_mlhl;
283a977deeSAkihiko Odaki uint32_t mss_l4len_idx;
293a977deeSAkihiko Odaki };
303a977deeSAkihiko Odaki
313a977deeSAkihiko Odaki /* Advanced Transmit Descriptor */
323a977deeSAkihiko Odaki union e1000_adv_tx_desc {
333a977deeSAkihiko Odaki struct {
343a977deeSAkihiko Odaki uint64_t buffer_addr; /* Address of descriptor's data buffer */
353a977deeSAkihiko Odaki uint32_t cmd_type_len;
363a977deeSAkihiko Odaki uint32_t olinfo_status;
373a977deeSAkihiko Odaki } read;
383a977deeSAkihiko Odaki struct {
393a977deeSAkihiko Odaki uint64_t rsvd; /* Reserved */
403a977deeSAkihiko Odaki uint32_t nxtseq_seed;
413a977deeSAkihiko Odaki uint32_t status;
423a977deeSAkihiko Odaki } wb;
433a977deeSAkihiko Odaki };
443a977deeSAkihiko Odaki
453a977deeSAkihiko Odaki #define E1000_ADVTXD_POTS_IXSM 0x00000100 /* Insert TCP/UDP Checksum */
463a977deeSAkihiko Odaki #define E1000_ADVTXD_POTS_TXSM 0x00000200 /* Insert TCP/UDP Checksum */
473a977deeSAkihiko Odaki
483a977deeSAkihiko Odaki #define E1000_TXD_POPTS_IXSM 0x00000001 /* Insert IP checksum */
493a977deeSAkihiko Odaki #define E1000_TXD_POPTS_TXSM 0x00000002 /* Insert TCP/UDP checksum */
503a977deeSAkihiko Odaki
513a977deeSAkihiko Odaki /* Receive Descriptor - Advanced */
523a977deeSAkihiko Odaki union e1000_adv_rx_desc {
533a977deeSAkihiko Odaki struct {
543a977deeSAkihiko Odaki uint64_t pkt_addr; /* Packet Buffer Address */
553a977deeSAkihiko Odaki uint64_t hdr_addr; /* Header Buffer Address */
563a977deeSAkihiko Odaki } read;
573a977deeSAkihiko Odaki struct {
583a977deeSAkihiko Odaki struct {
593a977deeSAkihiko Odaki struct {
603a977deeSAkihiko Odaki uint16_t pkt_info; /* RSS Type, Packet Type */
613a977deeSAkihiko Odaki uint16_t hdr_info; /* Split Head, Buffer Length */
623a977deeSAkihiko Odaki } lo_dword;
633a977deeSAkihiko Odaki union {
643a977deeSAkihiko Odaki uint32_t rss; /* RSS Hash */
653a977deeSAkihiko Odaki struct {
663a977deeSAkihiko Odaki uint16_t ip_id; /* IP Id */
673a977deeSAkihiko Odaki uint16_t csum; /* Packet Checksum */
683a977deeSAkihiko Odaki } csum_ip;
693a977deeSAkihiko Odaki } hi_dword;
703a977deeSAkihiko Odaki } lower;
713a977deeSAkihiko Odaki struct {
723a977deeSAkihiko Odaki uint32_t status_error; /* Ext Status/Error */
733a977deeSAkihiko Odaki uint16_t length; /* Packet Length */
743a977deeSAkihiko Odaki uint16_t vlan; /* VLAN tag */
753a977deeSAkihiko Odaki } upper;
763a977deeSAkihiko Odaki } wb; /* writeback */
773a977deeSAkihiko Odaki };
783a977deeSAkihiko Odaki
793a977deeSAkihiko Odaki /* from igb/e1000_phy.h */
803a977deeSAkihiko Odaki
813a977deeSAkihiko Odaki /* IGP01E1000 Specific Registers */
823a977deeSAkihiko Odaki #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
833a977deeSAkihiko Odaki #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
843a977deeSAkihiko Odaki #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
853a977deeSAkihiko Odaki #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
863a977deeSAkihiko Odaki #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
873a977deeSAkihiko Odaki #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
883a977deeSAkihiko Odaki #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
893a977deeSAkihiko Odaki #define IGP01E1000_PHY_POLARITY_MASK 0x0078
903a977deeSAkihiko Odaki #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
913a977deeSAkihiko Odaki #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
923a977deeSAkihiko Odaki #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
933a977deeSAkihiko Odaki
943a977deeSAkihiko Odaki /* Enable flexible speed on link-up */
953a977deeSAkihiko Odaki #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
963a977deeSAkihiko Odaki #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
973a977deeSAkihiko Odaki #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
983a977deeSAkihiko Odaki #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
993a977deeSAkihiko Odaki #define IGP01E1000_PSSR_MDIX 0x0800
1003a977deeSAkihiko Odaki #define IGP01E1000_PSSR_SPEED_MASK 0xC000
1013a977deeSAkihiko Odaki #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
1023a977deeSAkihiko Odaki #define IGP02E1000_PHY_CHANNEL_NUM 4
1033a977deeSAkihiko Odaki #define IGP02E1000_PHY_AGC_A 0x11B1
1043a977deeSAkihiko Odaki #define IGP02E1000_PHY_AGC_B 0x12B1
1053a977deeSAkihiko Odaki #define IGP02E1000_PHY_AGC_C 0x14B1
1063a977deeSAkihiko Odaki #define IGP02E1000_PHY_AGC_D 0x18B1
1073a977deeSAkihiko Odaki #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
1083a977deeSAkihiko Odaki #define IGP02E1000_AGC_LENGTH_MASK 0x7F
1093a977deeSAkihiko Odaki #define IGP02E1000_AGC_RANGE 15
1103a977deeSAkihiko Odaki
1113a977deeSAkihiko Odaki /* from igb/igb.h */
1123a977deeSAkihiko Odaki
1133a977deeSAkihiko Odaki #define E1000_PCS_CFG_IGN_SD 1
1143a977deeSAkihiko Odaki
1153a977deeSAkihiko Odaki /* Interrupt defines */
1163a977deeSAkihiko Odaki #define IGB_START_ITR 648 /* ~6000 ints/sec */
1173a977deeSAkihiko Odaki #define IGB_4K_ITR 980
1183a977deeSAkihiko Odaki #define IGB_20K_ITR 196
1193a977deeSAkihiko Odaki #define IGB_70K_ITR 56
1203a977deeSAkihiko Odaki
1213a977deeSAkihiko Odaki /* TX/RX descriptor defines */
1223a977deeSAkihiko Odaki #define IGB_DEFAULT_TXD 256
1233a977deeSAkihiko Odaki #define IGB_DEFAULT_TX_WORK 128
1243a977deeSAkihiko Odaki #define IGB_MIN_TXD 80
1253a977deeSAkihiko Odaki #define IGB_MAX_TXD 4096
1263a977deeSAkihiko Odaki
1273a977deeSAkihiko Odaki #define IGB_DEFAULT_RXD 256
1283a977deeSAkihiko Odaki #define IGB_MIN_RXD 80
1293a977deeSAkihiko Odaki #define IGB_MAX_RXD 4096
1303a977deeSAkihiko Odaki
1313a977deeSAkihiko Odaki #define IGB_DEFAULT_ITR 3 /* dynamic */
1323a977deeSAkihiko Odaki #define IGB_MAX_ITR_USECS 10000
1333a977deeSAkihiko Odaki #define IGB_MIN_ITR_USECS 10
1343a977deeSAkihiko Odaki #define NON_Q_VECTORS 1
1353a977deeSAkihiko Odaki #define MAX_Q_VECTORS 8
1363a977deeSAkihiko Odaki #define MAX_MSIX_ENTRIES 10
1373a977deeSAkihiko Odaki
1383a977deeSAkihiko Odaki /* Transmit and receive queues */
1393a977deeSAkihiko Odaki #define IGB_MAX_RX_QUEUES 8
1403a977deeSAkihiko Odaki #define IGB_MAX_RX_QUEUES_82575 4
1413a977deeSAkihiko Odaki #define IGB_MAX_RX_QUEUES_I211 2
1423a977deeSAkihiko Odaki #define IGB_MAX_TX_QUEUES 8
1433a977deeSAkihiko Odaki #define IGB_MAX_VF_MC_ENTRIES 30
1443a977deeSAkihiko Odaki #define IGB_MAX_VF_FUNCTIONS 8
1453a977deeSAkihiko Odaki #define IGB_MAX_VFTA_ENTRIES 128
1463a977deeSAkihiko Odaki #define IGB_82576_VF_DEV_ID 0x10CA
1473a977deeSAkihiko Odaki #define IGB_I350_VF_DEV_ID 0x1520
1483a977deeSAkihiko Odaki
1494847dabfSAkihiko Odaki /* VLAN info */
1504847dabfSAkihiko Odaki #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
1514847dabfSAkihiko Odaki #define IGB_TX_FLAGS_VLAN_SHIFT 16
1524847dabfSAkihiko Odaki
1533a977deeSAkihiko Odaki /* from igb/e1000_82575.h */
1543a977deeSAkihiko Odaki
1553a977deeSAkihiko Odaki #define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
1563a977deeSAkihiko Odaki #define E1000_MRQC_ENABLE_VMDQ 0x00000003
1573a977deeSAkihiko Odaki #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
1583a977deeSAkihiko Odaki #define E1000_MRQC_ENABLE_VMDQ_RSS_MQ 0x00000005
1593a977deeSAkihiko Odaki #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
1603a977deeSAkihiko Odaki #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
1613a977deeSAkihiko Odaki
1624847dabfSAkihiko Odaki /* Adv Transmit Descriptor Config Masks */
1634847dabfSAkihiko Odaki #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
1644847dabfSAkihiko Odaki #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
1654847dabfSAkihiko Odaki #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
1664847dabfSAkihiko Odaki #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
1674847dabfSAkihiko Odaki #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
1684847dabfSAkihiko Odaki #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
1694847dabfSAkihiko Odaki #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
1704847dabfSAkihiko Odaki #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
1714847dabfSAkihiko Odaki #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
1724847dabfSAkihiko Odaki #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1734847dabfSAkihiko Odaki
1744847dabfSAkihiko Odaki #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1754847dabfSAkihiko Odaki #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1764847dabfSAkihiko Odaki #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1774847dabfSAkihiko Odaki #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1784847dabfSAkihiko Odaki #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
1794847dabfSAkihiko Odaki /* IPSec Encrypt Enable for ESP */
1804847dabfSAkihiko Odaki #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1814847dabfSAkihiko Odaki #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1824847dabfSAkihiko Odaki /* Adv ctxt IPSec SA IDX mask */
1834847dabfSAkihiko Odaki /* Adv ctxt IPSec ESP len mask */
1844847dabfSAkihiko Odaki
1853269ebb3SSriram Yagnaraman /* Additional Transmit Descriptor Control definitions */
1863269ebb3SSriram Yagnaraman #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
1873269ebb3SSriram Yagnaraman
1883a977deeSAkihiko Odaki /* Additional Receive Descriptor Control definitions */
1893a977deeSAkihiko Odaki #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
1903a977deeSAkihiko Odaki
1913a977deeSAkihiko Odaki /* Direct Cache Access (DCA) definitions */
1923a977deeSAkihiko Odaki #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
1933a977deeSAkihiko Odaki #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
1943a977deeSAkihiko Odaki
1953a977deeSAkihiko Odaki #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1963a977deeSAkihiko Odaki #define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
1973a977deeSAkihiko Odaki #define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
1983a977deeSAkihiko Odaki #define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
1993a977deeSAkihiko Odaki #define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
2003a977deeSAkihiko Odaki
2013a977deeSAkihiko Odaki #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
2023a977deeSAkihiko Odaki #define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
2033a977deeSAkihiko Odaki #define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
2043a977deeSAkihiko Odaki #define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
2053a977deeSAkihiko Odaki #define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
2063a977deeSAkihiko Odaki
2073a977deeSAkihiko Odaki /* Additional DCA related definitions, note change in position of CPUID */
2083a977deeSAkihiko Odaki #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
2093a977deeSAkihiko Odaki #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
2103a977deeSAkihiko Odaki #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
2113a977deeSAkihiko Odaki #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
2123a977deeSAkihiko Odaki
2133a9926d9SAkihiko Odaki /* ETQF register bit definitions */
2143a9926d9SAkihiko Odaki #define E1000_ETQF_FILTER_ENABLE BIT(26)
2153a9926d9SAkihiko Odaki #define E1000_ETQF_1588 BIT(30)
2163a9926d9SAkihiko Odaki #define E1000_ETQF_IMM_INT BIT(29)
2173a9926d9SAkihiko Odaki #define E1000_ETQF_QUEUE_ENABLE BIT(31)
2183a9926d9SAkihiko Odaki #define E1000_ETQF_QUEUE_SHIFT 16
2193a9926d9SAkihiko Odaki #define E1000_ETQF_QUEUE_MASK 0x00070000
2203a9926d9SAkihiko Odaki #define E1000_ETQF_ETYPE_MASK 0x0000FFFF
2213a9926d9SAkihiko Odaki
2223a977deeSAkihiko Odaki #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
2233a977deeSAkihiko Odaki #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
2243a977deeSAkihiko Odaki #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
2253a977deeSAkihiko Odaki #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
2263a977deeSAkihiko Odaki #define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31) /* global VF LB enable */
2273a977deeSAkihiko Odaki
2283a977deeSAkihiko Odaki /* Easy defines for setting default pool, would normally be left a zero */
2293a977deeSAkihiko Odaki #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
2303a977deeSAkihiko Odaki #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
2313a977deeSAkihiko Odaki
2323a977deeSAkihiko Odaki /* Other useful VMD_CTL register defines */
2333a977deeSAkihiko Odaki #define E1000_VT_CTL_IGNORE_MAC BIT(28)
2343a977deeSAkihiko Odaki #define E1000_VT_CTL_DISABLE_DEF_POOL BIT(29)
2353a977deeSAkihiko Odaki #define E1000_VT_CTL_VM_REPL_EN BIT(30)
2363a977deeSAkihiko Odaki
2373a977deeSAkihiko Odaki /* Per VM Offload register setup */
2383a977deeSAkihiko Odaki #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
2393a977deeSAkihiko Odaki #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
2403a977deeSAkihiko Odaki #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
2413a977deeSAkihiko Odaki #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
2423a977deeSAkihiko Odaki #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
2433a977deeSAkihiko Odaki #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
2443a977deeSAkihiko Odaki #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
2453a977deeSAkihiko Odaki #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
2463a977deeSAkihiko Odaki #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
2473a977deeSAkihiko Odaki #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
2483a977deeSAkihiko Odaki
2493a977deeSAkihiko Odaki #define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */
2503a977deeSAkihiko Odaki #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
2513a977deeSAkihiko Odaki #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
2523a977deeSAkihiko Odaki
2533a977deeSAkihiko Odaki #define E1000_VLVF_ARRAY_SIZE 32
2543a977deeSAkihiko Odaki #define E1000_VLVF_VLANID_MASK 0x00000FFF
2553a977deeSAkihiko Odaki #define E1000_VLVF_POOLSEL_SHIFT 12
2563a977deeSAkihiko Odaki #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
2573a977deeSAkihiko Odaki #define E1000_VLVF_LVLAN 0x00100000
2583a977deeSAkihiko Odaki #define E1000_VLVF_VLANID_ENABLE 0x80000000
2593a977deeSAkihiko Odaki
2603a977deeSAkihiko Odaki #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
2613a977deeSAkihiko Odaki #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
2623a977deeSAkihiko Odaki
2633a977deeSAkihiko Odaki #define E1000_IOVCTL 0x05BBC
2643a977deeSAkihiko Odaki #define E1000_IOVCTL_REUSE_VFQ 0x00000001
2653a977deeSAkihiko Odaki
2663a977deeSAkihiko Odaki #define E1000_RPLOLR_STRVLAN 0x40000000
2673a977deeSAkihiko Odaki #define E1000_RPLOLR_STRCRC 0x80000000
2683a977deeSAkihiko Odaki
2693a977deeSAkihiko Odaki #define E1000_DTXCTL_8023LL 0x0004
2703a977deeSAkihiko Odaki #define E1000_DTXCTL_VLAN_ADDED 0x0008
2713a977deeSAkihiko Odaki #define E1000_DTXCTL_OOS_ENABLE 0x0010
2723a977deeSAkihiko Odaki #define E1000_DTXCTL_MDP_EN 0x0020
2733a977deeSAkihiko Odaki #define E1000_DTXCTL_SPOOF_INT 0x0040
2743a977deeSAkihiko Odaki
2753a977deeSAkihiko Odaki /* from igb/e1000_defines.h */
2763a977deeSAkihiko Odaki
2772e68546aSSriram Yagnaraman /* Physical Func Reset Done Indication */
2782e68546aSSriram Yagnaraman #define E1000_CTRL_EXT_PFRSTD 0x00004000
2792e68546aSSriram Yagnaraman
2803a977deeSAkihiko Odaki #define E1000_IVAR_VALID 0x80
2813a977deeSAkihiko Odaki #define E1000_GPIE_NSICR 0x00000001
2823a977deeSAkihiko Odaki #define E1000_GPIE_MSIX_MODE 0x00000010
2833a977deeSAkihiko Odaki #define E1000_GPIE_EIAME 0x40000000
2843a977deeSAkihiko Odaki #define E1000_GPIE_PBA 0x80000000
2853a977deeSAkihiko Odaki
2863a977deeSAkihiko Odaki /* Transmit Control */
2873a977deeSAkihiko Odaki #define E1000_TCTL_EN 0x00000002 /* enable tx */
2883a977deeSAkihiko Odaki #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
2893a977deeSAkihiko Odaki #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
2903a977deeSAkihiko Odaki #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
2913a977deeSAkihiko Odaki #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
2923a977deeSAkihiko Odaki
2933a977deeSAkihiko Odaki /* Collision related configuration parameters */
2943a977deeSAkihiko Odaki #define E1000_COLLISION_THRESHOLD 15
2953a977deeSAkihiko Odaki #define E1000_CT_SHIFT 4
2963a977deeSAkihiko Odaki #define E1000_COLLISION_DISTANCE 63
2973a977deeSAkihiko Odaki #define E1000_COLD_SHIFT 12
2983a977deeSAkihiko Odaki
2993a977deeSAkihiko Odaki #define E1000_RAH_POOL_MASK 0x03FC0000
3003a977deeSAkihiko Odaki #define E1000_RAH_POOL_1 0x00040000
3013a977deeSAkihiko Odaki
3023a977deeSAkihiko Odaki #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
3033a977deeSAkihiko Odaki #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
3043a977deeSAkihiko Odaki #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
3053a977deeSAkihiko Odaki /* If this bit asserted, the driver should claim the interrupt */
3063a977deeSAkihiko Odaki #define E1000_ICR_INT_ASSERTED 0x80000000
3073a977deeSAkihiko Odaki /* LAN connected device generates an interrupt */
3083a977deeSAkihiko Odaki #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
3093a977deeSAkihiko Odaki
3103a977deeSAkihiko Odaki /* Extended Interrupt Cause Read */
3113a977deeSAkihiko Odaki #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
3123a977deeSAkihiko Odaki #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
3133a977deeSAkihiko Odaki #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
3143a977deeSAkihiko Odaki #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
3153a977deeSAkihiko Odaki #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
3163a977deeSAkihiko Odaki #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
3173a977deeSAkihiko Odaki #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
3183a977deeSAkihiko Odaki #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
3193a977deeSAkihiko Odaki #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
3203a977deeSAkihiko Odaki
3213a977deeSAkihiko Odaki /* Extended Interrupt Cause Set */
3223a977deeSAkihiko Odaki /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
3233a977deeSAkihiko Odaki #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
3243a977deeSAkihiko Odaki
3253dfc616eSAkihiko Odaki #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */
3263dfc616eSAkihiko Odaki #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */
3273dfc616eSAkihiko Odaki
3283a977deeSAkihiko Odaki /* PCI Express Control */
3293a977deeSAkihiko Odaki #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
3303a977deeSAkihiko Odaki #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
3313a977deeSAkihiko Odaki #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
3323a977deeSAkihiko Odaki #define E1000_GCR_CAP_VER2 0x00040000
3333a977deeSAkihiko Odaki
3343a977deeSAkihiko Odaki #define PHY_REVISION_MASK 0xFFFFFFF0
3353a977deeSAkihiko Odaki #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
3363a977deeSAkihiko Odaki #define MAX_PHY_MULTI_PAGE_REG 0xF
3373a977deeSAkihiko Odaki
3383a977deeSAkihiko Odaki #define IGP03E1000_E_PHY_ID 0x02A80390
3393a977deeSAkihiko Odaki
3403a977deeSAkihiko Odaki /* from igb/e1000_mbox.h */
3413a977deeSAkihiko Odaki
3423a977deeSAkihiko Odaki #define E1000_P2VMAILBOX_STS 0x00000001 /* Initiate message send to VF */
3433a977deeSAkihiko Odaki #define E1000_P2VMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */
3443a977deeSAkihiko Odaki #define E1000_P2VMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
3453a977deeSAkihiko Odaki #define E1000_P2VMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
3463a977deeSAkihiko Odaki #define E1000_P2VMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */
3473a977deeSAkihiko Odaki
3483a977deeSAkihiko Odaki #define E1000_MBVFICR_VFREQ_MASK 0x000000FF /* bits for VF messages */
3493a977deeSAkihiko Odaki #define E1000_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */
3503a977deeSAkihiko Odaki #define E1000_MBVFICR_VFACK_MASK 0x00FF0000 /* bits for VF acks */
3513a977deeSAkihiko Odaki #define E1000_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */
3523a977deeSAkihiko Odaki
3533a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
3543a977deeSAkihiko Odaki
3553a977deeSAkihiko Odaki /*
3563a977deeSAkihiko Odaki * If it's a E1000_VF_* msg then it originates in the VF and is sent to the
3573a977deeSAkihiko Odaki * PF. The reverse is true if it is E1000_PF_*.
3583a977deeSAkihiko Odaki * Message ACK's are the value or'd with 0xF0000000
3593a977deeSAkihiko Odaki */
3603a977deeSAkihiko Odaki /* Messages below or'd with this are the ACK */
3613a977deeSAkihiko Odaki #define E1000_VT_MSGTYPE_ACK 0x80000000
3623a977deeSAkihiko Odaki /* Messages below or'd with this are the NACK */
3633a977deeSAkihiko Odaki #define E1000_VT_MSGTYPE_NACK 0x40000000
3643a977deeSAkihiko Odaki /* Indicates that VF is still clear to send requests */
3653a977deeSAkihiko Odaki #define E1000_VT_MSGTYPE_CTS 0x20000000
3663a977deeSAkihiko Odaki #define E1000_VT_MSGINFO_SHIFT 16
3672431f4f1SMichael Tokarev /* bits 23:16 are used for extra info for certain messages */
3683a977deeSAkihiko Odaki #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT)
3693a977deeSAkihiko Odaki
3703a977deeSAkihiko Odaki #define E1000_VF_RESET 0x01 /* VF requests reset */
3713a977deeSAkihiko Odaki #define E1000_VF_SET_MAC_ADDR 0x02 /* VF requests to set MAC addr */
3723a977deeSAkihiko Odaki /* VF requests to clear all unicast MAC filters */
3733a977deeSAkihiko Odaki #define E1000_VF_MAC_FILTER_CLR (0x01 << E1000_VT_MSGINFO_SHIFT)
3743a977deeSAkihiko Odaki /* VF requests to add unicast MAC filter */
3753a977deeSAkihiko Odaki #define E1000_VF_MAC_FILTER_ADD (0x02 << E1000_VT_MSGINFO_SHIFT)
3763a977deeSAkihiko Odaki #define E1000_VF_SET_MULTICAST 0x03 /* VF requests to set MC addr */
3773a977deeSAkihiko Odaki #define E1000_VF_SET_VLAN 0x04 /* VF requests to set VLAN */
3783a977deeSAkihiko Odaki #define E1000_VF_SET_LPE 0x05 /* VF requests to set VMOLR.LPE */
3793a977deeSAkihiko Odaki #define E1000_VF_SET_PROMISC 0x06 /*VF requests to clear VMOLR.ROPE/MPME*/
3803a977deeSAkihiko Odaki #define E1000_VF_SET_PROMISC_MULTICAST (0x02 << E1000_VT_MSGINFO_SHIFT)
3813a977deeSAkihiko Odaki
3823a977deeSAkihiko Odaki #define E1000_PF_CONTROL_MSG 0x0100 /* PF control message */
3833a977deeSAkihiko Odaki
3843a977deeSAkihiko Odaki /* from igb/e1000_regs.h */
3853a977deeSAkihiko Odaki
3863a977deeSAkihiko Odaki #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
3873a977deeSAkihiko Odaki #define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
3883a977deeSAkihiko Odaki #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
3893a977deeSAkihiko Odaki #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
3903a977deeSAkihiko Odaki #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
3913a977deeSAkihiko Odaki #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
3923a977deeSAkihiko Odaki #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
3933a977deeSAkihiko Odaki #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable; RW */
3943a977deeSAkihiko Odaki #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation Register - RW */
3953a977deeSAkihiko Odaki #define E1000_IVAR_MISC 0x01740 /* Interrupt Vector Allocation Register (last) - RW */
3963a977deeSAkihiko Odaki #define E1000_FRTIMER 0x01048 /* Free Running Timer - RW */
3973a977deeSAkihiko Odaki #define E1000_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
3983a977deeSAkihiko Odaki
3993a9926d9SAkihiko Odaki #define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
4003a9926d9SAkihiko Odaki
4013a9926d9SAkihiko Odaki /* Filtering Registers */
4023a9926d9SAkihiko Odaki #define E1000_SAQF(_n) (0x5980 + 4 * (_n))
4033a9926d9SAkihiko Odaki #define E1000_DAQF(_n) (0x59A0 + 4 * (_n))
4043a9926d9SAkihiko Odaki #define E1000_SPQF(_n) (0x59C0 + 4 * (_n))
4053a9926d9SAkihiko Odaki #define E1000_FTQF(_n) (0x59E0 + 4 * (_n))
4063a9926d9SAkihiko Odaki #define E1000_SAQF0 E1000_SAQF(0)
4073a9926d9SAkihiko Odaki #define E1000_DAQF0 E1000_DAQF(0)
4083a9926d9SAkihiko Odaki #define E1000_SPQF0 E1000_SPQF(0)
4093a9926d9SAkihiko Odaki #define E1000_FTQF0 E1000_FTQF(0)
4103a9926d9SAkihiko Odaki #define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
4113a9926d9SAkihiko Odaki #define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
4123a9926d9SAkihiko Odaki
4133a977deeSAkihiko Odaki #define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40))
4143a977deeSAkihiko Odaki
4153a977deeSAkihiko Odaki #define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
4163a977deeSAkihiko Odaki #define E1000_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
4173a977deeSAkihiko Odaki
4183a977deeSAkihiko Odaki #define E1000_DTXCTL 0x03590 /* DMA TX Control - RW */
4193a977deeSAkihiko Odaki
4203a977deeSAkihiko Odaki #define E1000_HTCBDPC 0x04124 /* Host TX Circuit Breaker Dropped Count */
4213a977deeSAkihiko Odaki #define E1000_RLPML 0x05004 /* RX Long Packet Max Length */
4223a977deeSAkihiko Odaki #define E1000_RA2 0x054E0 /* 2nd half of Rx address array - RW Array */
4233a977deeSAkihiko Odaki #define E1000_PSRTYPE(_i) (0x05480 + ((_i) * 4))
4243a977deeSAkihiko Odaki #define E1000_VT_CTL 0x0581C /* VMDq Control - RW */
4253a977deeSAkihiko Odaki
4263a977deeSAkihiko Odaki /* VT Registers */
4273a977deeSAkihiko Odaki #define E1000_MBVFICR 0x00C80 /* Mailbox VF Cause - RWC */
4283a977deeSAkihiko Odaki #define E1000_MBVFIMR 0x00C84 /* Mailbox VF int Mask - RW */
4293a977deeSAkihiko Odaki #define E1000_VFLRE 0x00C88 /* VF Register Events - RWC */
4303a977deeSAkihiko Odaki #define E1000_VFRE 0x00C8C /* VF Receive Enables */
4313a977deeSAkihiko Odaki #define E1000_VFTE 0x00C90 /* VF Transmit Enables */
4323a977deeSAkihiko Odaki #define E1000_QDE 0x02408 /* Queue Drop Enable - RW */
4333a977deeSAkihiko Odaki #define E1000_DTXSWC 0x03500 /* DMA Tx Switch Control - RW */
4343a977deeSAkihiko Odaki #define E1000_WVBR 0x03554 /* VM Wrong Behavior - RWS */
4353a977deeSAkihiko Odaki #define E1000_RPLOLR 0x05AF0 /* Replication Offload - RW */
4363a977deeSAkihiko Odaki #define E1000_UTA 0x0A000 /* Unicast Table Array - RW */
4373a977deeSAkihiko Odaki #define E1000_IOVTCL 0x05BBC /* IOV Control Register */
4383a977deeSAkihiko Odaki #define E1000_TXSWC 0x05ACC /* Tx Switch Control */
4393a977deeSAkihiko Odaki #define E1000_LVMMC 0x03548 /* Last VM Misbehavior cause */
4403a977deeSAkihiko Odaki /* These act per VF so an array friendly macro is used */
4413a977deeSAkihiko Odaki #define E1000_P2VMAILBOX(_n) (0x00C00 + (4 * (_n)))
4423a977deeSAkihiko Odaki #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
4433a977deeSAkihiko Odaki #define E1000_VMOLR(_n) (0x05AD0 + (4 * (_n)))
4443a977deeSAkihiko Odaki #define E1000_DVMOLR(_n) (0x0C038 + (64 * (_n)))
4453a977deeSAkihiko Odaki #define E1000_VLVF(_n) (0x05D00 + (4 * (_n))) /* VLAN VM Filter */
4463a977deeSAkihiko Odaki #define E1000_VMVIR(_n) (0x03700 + (4 * (_n)))
4473a977deeSAkihiko Odaki
4483a977deeSAkihiko Odaki /* from igbvf/defines.h */
4493a977deeSAkihiko Odaki
4503a977deeSAkihiko Odaki /* SRRCTL bit definitions */
4513a977deeSAkihiko Odaki #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
4523a977deeSAkihiko Odaki #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
4533a977deeSAkihiko Odaki #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
4543a977deeSAkihiko Odaki #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
455560cf339STomasz Dzieciol #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
4563a977deeSAkihiko Odaki #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
4573a977deeSAkihiko Odaki #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
4583a977deeSAkihiko Odaki #define E1000_SRRCTL_DROP_EN 0x80000000
4593a977deeSAkihiko Odaki
4603a977deeSAkihiko Odaki #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
4613a977deeSAkihiko Odaki #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
4623a977deeSAkihiko Odaki
4633a977deeSAkihiko Odaki /* from igbvf/mbox.h */
4643a977deeSAkihiko Odaki
4653a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */
4663a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_ACK 0x00000002 /* Ack PF message received */
4673a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
4683a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
4693a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */
4703a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */
4713a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_RSTI 0x00000040 /* PF has reset indication */
4723a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */
4733a977deeSAkihiko Odaki #define E1000_V2PMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */
4743a977deeSAkihiko Odaki
4753a977deeSAkihiko Odaki #define E1000_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
4763a977deeSAkihiko Odaki
4773a977deeSAkihiko Odaki /*
4783a977deeSAkihiko Odaki * If it's a E1000_VF_* msg then it originates in the VF and is sent to the
4793a977deeSAkihiko Odaki * PF. The reverse is true if it is E1000_PF_*.
4803a977deeSAkihiko Odaki * Message ACK's are the value or'd with 0xF0000000
4813a977deeSAkihiko Odaki */
4823a977deeSAkihiko Odaki /* Messages below or'd with this are the ACK */
4833a977deeSAkihiko Odaki #define E1000_VT_MSGTYPE_ACK 0x80000000
4843a977deeSAkihiko Odaki /* Messages below or'd with this are the NACK */
4853a977deeSAkihiko Odaki #define E1000_VT_MSGTYPE_NACK 0x40000000
4863a977deeSAkihiko Odaki /* Indicates that VF is still clear to send requests */
4873a977deeSAkihiko Odaki #define E1000_VT_MSGTYPE_CTS 0x20000000
4883a977deeSAkihiko Odaki
4893a977deeSAkihiko Odaki /* We have a total wait time of 1s for vf mailbox posted messages */
4903a977deeSAkihiko Odaki #define E1000_VF_MBX_INIT_TIMEOUT 2000 /* retry count for mbx timeout */
4913a977deeSAkihiko Odaki #define E1000_VF_MBX_INIT_DELAY 500 /* usec delay between retries */
4923a977deeSAkihiko Odaki
4933a977deeSAkihiko Odaki #define E1000_VT_MSGINFO_SHIFT 16
4942431f4f1SMichael Tokarev /* bits 23:16 are used for extra info for certain messages */
4953a977deeSAkihiko Odaki #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT)
4963a977deeSAkihiko Odaki
4973a977deeSAkihiko Odaki #define E1000_VF_RESET 0x01 /* VF requests reset */
4983a977deeSAkihiko Odaki #define E1000_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */
4993a977deeSAkihiko Odaki /* VF requests PF to clear all unicast MAC filters */
5003a977deeSAkihiko Odaki #define E1000_VF_MAC_FILTER_CLR (0x01 << E1000_VT_MSGINFO_SHIFT)
5013a977deeSAkihiko Odaki /* VF requests PF to add unicast MAC filter */
5023a977deeSAkihiko Odaki #define E1000_VF_MAC_FILTER_ADD (0x02 << E1000_VT_MSGINFO_SHIFT)
5033a977deeSAkihiko Odaki #define E1000_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */
5043a977deeSAkihiko Odaki #define E1000_VF_SET_VLAN 0x04 /* VF requests PF to set VLAN */
5053a977deeSAkihiko Odaki #define E1000_VF_SET_LPE 0x05 /* VF requests PF to set VMOLR.LPE */
5063a977deeSAkihiko Odaki
5073a977deeSAkihiko Odaki #define E1000_PF_CONTROL_MSG 0x0100 /* PF control message */
5083a977deeSAkihiko Odaki
5093a977deeSAkihiko Odaki /* from igbvf/regs.h */
5103a977deeSAkihiko Odaki
5113a977deeSAkihiko Odaki /* Statistics registers */
5123a977deeSAkihiko Odaki #define E1000_VFGPRC 0x00F10
5133a977deeSAkihiko Odaki #define E1000_VFGORC 0x00F18
5143a977deeSAkihiko Odaki #define E1000_VFMPRC 0x00F3C
5153a977deeSAkihiko Odaki #define E1000_VFGPTC 0x00F14
5163a977deeSAkihiko Odaki #define E1000_VFGOTC 0x00F34
5173a977deeSAkihiko Odaki #define E1000_VFGOTLBC 0x00F50
5183a977deeSAkihiko Odaki #define E1000_VFGPTLBC 0x00F44
5193a977deeSAkihiko Odaki #define E1000_VFGORLBC 0x00F48
5203a977deeSAkihiko Odaki #define E1000_VFGPRLBC 0x00F40
5213a977deeSAkihiko Odaki
5223a977deeSAkihiko Odaki /* These act per VF so an array friendly macro is used */
5233a977deeSAkihiko Odaki #define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
5243a977deeSAkihiko Odaki #define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
5253a977deeSAkihiko Odaki
5263a977deeSAkihiko Odaki /* from igbvf/vf.h */
5273a977deeSAkihiko Odaki
5283a977deeSAkihiko Odaki #define E1000_DEV_ID_82576_VF 0x10CA
5293a977deeSAkihiko Odaki
5303a977deeSAkihiko Odaki /* new */
5313a977deeSAkihiko Odaki
5323a977deeSAkihiko Odaki /* Receive Registers */
5333a977deeSAkihiko Odaki
5343a977deeSAkihiko Odaki /* RX Descriptor Base Low; RW */
5353a977deeSAkihiko Odaki #define E1000_RDBAL(_n) (0x0C000 + (0x40 * (_n)))
5363a977deeSAkihiko Odaki #define E1000_RDBAL_A(_n) (0x02800 + (0x100 * (_n)))
5373a977deeSAkihiko Odaki
5383a977deeSAkihiko Odaki /* RX Descriptor Base High; RW */
5393a977deeSAkihiko Odaki #define E1000_RDBAH(_n) (0x0C004 + (0x40 * (_n)))
5403a977deeSAkihiko Odaki #define E1000_RDBAH_A(_n) (0x02804 + (0x100 * (_n)))
5413a977deeSAkihiko Odaki
5423a977deeSAkihiko Odaki /* RX Descriptor Ring Length; RW */
5433a977deeSAkihiko Odaki #define E1000_RDLEN(_n) (0x0C008 + (0x40 * (_n)))
5443a977deeSAkihiko Odaki #define E1000_RDLEN_A(_n) (0x02808 + (0x100 * (_n)))
5453a977deeSAkihiko Odaki
5463a977deeSAkihiko Odaki /* Split and Replication Receive Control; RW */
5473a977deeSAkihiko Odaki #define E1000_SRRCTL(_n) (0x0C00C + (0x40 * (_n)))
5483a977deeSAkihiko Odaki #define E1000_SRRCTL_A(_n) (0x0280C + (0x100 * (_n)))
5493a977deeSAkihiko Odaki
5503a977deeSAkihiko Odaki /* RX Descriptor Head; RW */
5513a977deeSAkihiko Odaki #define E1000_RDH(_n) (0x0C010 + (0x40 * (_n)))
5523a977deeSAkihiko Odaki #define E1000_RDH_A(_n) (0x02810 + (0x100 * (_n)))
5533a977deeSAkihiko Odaki
5543a977deeSAkihiko Odaki /* RX DCA Control; RW */
5553a977deeSAkihiko Odaki #define E1000_RXCTL(_n) (0x0C014 + (0x40 * (_n)))
5563a977deeSAkihiko Odaki #define E1000_RXCTL_A(_n) (0x02814 + (0x100 * (_n)))
5573a977deeSAkihiko Odaki
5583a977deeSAkihiko Odaki /* RX Descriptor Tail; RW */
5593a977deeSAkihiko Odaki #define E1000_RDT(_n) (0x0C018 + (0x40 * (_n)))
5603a977deeSAkihiko Odaki #define E1000_RDT_A(_n) (0x02818 + (0x100 * (_n)))
5613a977deeSAkihiko Odaki
5623a977deeSAkihiko Odaki /* RX Descriptor Control; RW */
5633a977deeSAkihiko Odaki #define E1000_RXDCTL(_n) (0x0C028 + (0x40 * (_n)))
5643a977deeSAkihiko Odaki #define E1000_RXDCTL_A(_n) (0x02828 + (0x100 * (_n)))
5653a977deeSAkihiko Odaki
5663a977deeSAkihiko Odaki /* RX Queue Drop Packet Count; RC */
5673a977deeSAkihiko Odaki #define E1000_RQDPC_A(_n) (0x02830 + (0x100 * (_n)))
5683a977deeSAkihiko Odaki
5693a977deeSAkihiko Odaki /* Transmit Registers */
5703a977deeSAkihiko Odaki
5713a977deeSAkihiko Odaki /* TX Descriptor Base Low; RW */
5723a977deeSAkihiko Odaki #define E1000_TDBAL(_n) (0x0E000 + (0x40 * (_n)))
5733a977deeSAkihiko Odaki #define E1000_TDBAL_A(_n) (0x03800 + (0x100 * (_n)))
5743a977deeSAkihiko Odaki
5753a977deeSAkihiko Odaki /* TX Descriptor Base High; RW */
5763a977deeSAkihiko Odaki #define E1000_TDBAH(_n) (0x0E004 + (0x40 * (_n)))
5773a977deeSAkihiko Odaki #define E1000_TDBAH_A(_n) (0x03804 + (0x100 * (_n)))
5783a977deeSAkihiko Odaki
5793a977deeSAkihiko Odaki /* TX Descriptor Ring Length; RW */
5803a977deeSAkihiko Odaki #define E1000_TDLEN(_n) (0x0E008 + (0x40 * (_n)))
5813a977deeSAkihiko Odaki #define E1000_TDLEN_A(_n) (0x03808 + (0x100 * (_n)))
5823a977deeSAkihiko Odaki
5833a977deeSAkihiko Odaki /* TX Descriptor Head; RW */
5843a977deeSAkihiko Odaki #define E1000_TDH(_n) (0x0E010 + (0x40 * (_n)))
5853a977deeSAkihiko Odaki #define E1000_TDH_A(_n) (0x03810 + (0x100 * (_n)))
5863a977deeSAkihiko Odaki
5873a977deeSAkihiko Odaki /* TX DCA Control; RW */
5883a977deeSAkihiko Odaki #define E1000_TXCTL(_n) (0x0E014 + (0x40 * (_n)))
5893a977deeSAkihiko Odaki #define E1000_TXCTL_A(_n) (0x03814 + (0x100 * (_n)))
5903a977deeSAkihiko Odaki
5913a977deeSAkihiko Odaki /* TX Descriptor Tail; RW */
5923a977deeSAkihiko Odaki #define E1000_TDT(_n) (0x0E018 + (0x40 * (_n)))
5933a977deeSAkihiko Odaki #define E1000_TDT_A(_n) (0x03818 + (0x100 * (_n)))
5943a977deeSAkihiko Odaki
5953a977deeSAkihiko Odaki /* TX Descriptor Control; RW */
5963a977deeSAkihiko Odaki #define E1000_TXDCTL(_n) (0x0E028 + (0x40 * (_n)))
5973a977deeSAkihiko Odaki #define E1000_TXDCTL_A(_n) (0x03828 + (0x100 * (_n)))
5983a977deeSAkihiko Odaki
5993a977deeSAkihiko Odaki /* TX Descriptor Completion Write–Back Address Low; RW */
6003a977deeSAkihiko Odaki #define E1000_TDWBAL(_n) (0x0E038 + (0x40 * (_n)))
6013a977deeSAkihiko Odaki #define E1000_TDWBAL_A(_n) (0x03838 + (0x100 * (_n)))
6023a977deeSAkihiko Odaki
6033a977deeSAkihiko Odaki /* TX Descriptor Completion Write–Back Address High; RW */
6043a977deeSAkihiko Odaki #define E1000_TDWBAH(_n) (0x0E03C + (0x40 * (_n)))
6053a977deeSAkihiko Odaki #define E1000_TDWBAH_A(_n) (0x0383C + (0x100 * (_n)))
6063a977deeSAkihiko Odaki
6073a977deeSAkihiko Odaki #define E1000_MTA_A 0x0200
6083a977deeSAkihiko Odaki
6093a977deeSAkihiko Odaki #define E1000_XDBAL_MASK (~(BIT(5) - 1)) /* TDBAL and RDBAL Registers Mask */
6103a977deeSAkihiko Odaki
6113a977deeSAkihiko Odaki #define E1000_ICR_MACSEC 0x00000020 /* MACSec */
6123a977deeSAkihiko Odaki #define E1000_ICR_RX0 0x00000040 /* Receiver Overrun */
6133a977deeSAkihiko Odaki #define E1000_ICR_GPI_SDP0 0x00000800 /* General Purpose, SDP0 pin */
6143a977deeSAkihiko Odaki #define E1000_ICR_GPI_SDP1 0x00001000 /* General Purpose, SDP1 pin */
6153a977deeSAkihiko Odaki #define E1000_ICR_GPI_SDP2 0x00002000 /* General Purpose, SDP2 pin */
6163a977deeSAkihiko Odaki #define E1000_ICR_GPI_SDP3 0x00004000 /* General Purpose, SDP3 pin */
6173a977deeSAkihiko Odaki #define E1000_ICR_PTRAP 0x00008000 /* Probe Trap */
6183a977deeSAkihiko Odaki #define E1000_ICR_MNG 0x00040000 /* Management Event */
6193a977deeSAkihiko Odaki #define E1000_ICR_OMED 0x00100000 /* Other Media Energy Detected */
6203a977deeSAkihiko Odaki #define E1000_ICR_FER 0x00400000 /* Fatal Error */
6213a977deeSAkihiko Odaki #define E1000_ICR_NFER 0x00800000 /* Non Fatal Error */
6223a977deeSAkihiko Odaki #define E1000_ICR_CSRTO 0x01000000 /* CSR access Time Out Indication */
6233a977deeSAkihiko Odaki #define E1000_ICR_SCE 0x02000000 /* Storm Control Event */
6243a977deeSAkihiko Odaki #define E1000_ICR_SW_WD 0x04000000 /* Software Watchdog */
6253a977deeSAkihiko Odaki
6263a977deeSAkihiko Odaki /* Extended Interrupts */
6273a977deeSAkihiko Odaki
6283a977deeSAkihiko Odaki #define E1000_EICR_MSIX_MASK 0x01FFFFFF /* Bits used in MSI-X mode */
6293a977deeSAkihiko Odaki #define E1000_EICR_LEGACY_MASK 0x4000FFFF /* Bits used in non MSI-X mode */
6303a977deeSAkihiko Odaki
6313a977deeSAkihiko Odaki /* Mirror VF Control (only RST bit); RW */
6323a977deeSAkihiko Odaki #define E1000_PVTCTRL(_n) (0x10000 + (_n) * 0x100)
6333a977deeSAkihiko Odaki
6343a977deeSAkihiko Odaki /* Mirror Good Packets Received Count; RO */
6353a977deeSAkihiko Odaki #define E1000_PVFGPRC(_n) (0x10010 + (_n) * 0x100)
6363a977deeSAkihiko Odaki
6373a977deeSAkihiko Odaki /* Mirror Good Packets Transmitted Count; RO */
6383a977deeSAkihiko Odaki #define E1000_PVFGPTC(_n) (0x10014 + (_n) * 0x100)
6393a977deeSAkihiko Odaki
6403a977deeSAkihiko Odaki /* Mirror Good Octets Received Count; RO */
6413a977deeSAkihiko Odaki #define E1000_PVFGORC(_n) (0x10018 + (_n) * 0x100)
6423a977deeSAkihiko Odaki
6433a977deeSAkihiko Odaki /* Mirror Extended Interrupt Cause Set; WO */
6443a977deeSAkihiko Odaki #define E1000_PVTEICS(_n) (0x10020 + (_n) * 0x100)
6453a977deeSAkihiko Odaki
6463a977deeSAkihiko Odaki /* Mirror Extended Interrupt Mask Set/Read; RW */
6473a977deeSAkihiko Odaki #define E1000_PVTEIMS(_n) (0x10024 + (_n) * 0x100)
6483a977deeSAkihiko Odaki
6493a977deeSAkihiko Odaki /* Mirror Extended Interrupt Mask Clear; WO */
6503a977deeSAkihiko Odaki #define E1000_PVTEIMC(_n) (0x10028 + (_n) * 0x100)
6513a977deeSAkihiko Odaki
6523a977deeSAkihiko Odaki /* Mirror Extended Interrupt Auto Clear; RW */
6533a977deeSAkihiko Odaki #define E1000_PVTEIAC(_n) (0x1002C + (_n) * 0x100)
6543a977deeSAkihiko Odaki
6553a977deeSAkihiko Odaki /* Mirror Extended Interrupt Auto Mask Enable; RW */
6563a977deeSAkihiko Odaki #define E1000_PVTEIAM(_n) (0x10030 + (_n) * 0x100)
6573a977deeSAkihiko Odaki
6583a977deeSAkihiko Odaki /* Mirror Good Octets Transmitted Count; RO */
6593a977deeSAkihiko Odaki #define E1000_PVFGOTC(_n) (0x10034 + (_n) * 0x100)
6603a977deeSAkihiko Odaki
6613a977deeSAkihiko Odaki /* Mirror Multicast Packets Received Count; RO */
6623a977deeSAkihiko Odaki #define E1000_PVFMPRC(_n) (0x1003C + (_n) * 0x100)
6633a977deeSAkihiko Odaki
6643a977deeSAkihiko Odaki /* Mirror Good RX Packets loopback Count; RO */
6653a977deeSAkihiko Odaki #define E1000_PVFGPRLBC(_n) (0x10040 + (_n) * 0x100)
6663a977deeSAkihiko Odaki
6673a977deeSAkihiko Odaki /* Mirror Good TX packets loopback Count; RO */
6683a977deeSAkihiko Odaki #define E1000_PVFGPTLBC(_n) (0x10044 + (_n) * 0x100)
6693a977deeSAkihiko Odaki
6703a977deeSAkihiko Odaki /* Mirror Good RX Octets loopback Count; RO */
6713a977deeSAkihiko Odaki #define E1000_PVFGORLBC(_n) (0x10048 + (_n) * 0x100)
6723a977deeSAkihiko Odaki
6733a977deeSAkihiko Odaki /* Mirror Good TX Octets loopback Count; RO */
6743a977deeSAkihiko Odaki #define E1000_PVFGOTLBC(_n) (0x10050 + (_n) * 0x100)
6753a977deeSAkihiko Odaki
6763a977deeSAkihiko Odaki /* Mirror Extended Interrupt Cause Set; RC/W1C */
6773a977deeSAkihiko Odaki #define E1000_PVTEICR(_n) (0x10080 + (_n) * 0x100)
6783a977deeSAkihiko Odaki
6793a977deeSAkihiko Odaki /*
6803a977deeSAkihiko Odaki * These are fake addresses that, according to the specification, the device
6813a977deeSAkihiko Odaki * is not using. They are used to distinguish between the PF and the VFs
6823a977deeSAkihiko Odaki * accessing their VTIVAR register (which is the same address, 0x1700)
6833a977deeSAkihiko Odaki */
6843a977deeSAkihiko Odaki #define E1000_VTIVAR 0x11700
6853a977deeSAkihiko Odaki #define E1000_VTIVAR_MISC 0x11720
6863a977deeSAkihiko Odaki
6873a977deeSAkihiko Odaki #define E1000_RSS_QUEUE(reta, hash) (E1000_RETA_VAL(reta, hash) & 0x0F)
6883a977deeSAkihiko Odaki
689abc9a29dSAkihiko Odaki #define E1000_MRQ_RSS_TYPE_IPV4UDP 7
690abc9a29dSAkihiko Odaki #define E1000_MRQ_RSS_TYPE_IPV6UDP 8
691abc9a29dSAkihiko Odaki
6923a977deeSAkihiko Odaki #define E1000_STATUS_IOV_MODE 0x00040000
6933a977deeSAkihiko Odaki
6943a977deeSAkihiko Odaki #define E1000_STATUS_NUM_VFS_SHIFT 14
6953a977deeSAkihiko Odaki
696ec82ad7cSTomasz Dzieciol #define E1000_ADVRXD_PKT_IP4 BIT(0)
697ec82ad7cSTomasz Dzieciol #define E1000_ADVRXD_PKT_IP6 BIT(2)
6981c4e67a5STomasz Dzieciol #define E1000_ADVRXD_PKT_IP6E BIT(3)
699ec82ad7cSTomasz Dzieciol #define E1000_ADVRXD_PKT_TCP BIT(4)
700ec82ad7cSTomasz Dzieciol #define E1000_ADVRXD_PKT_UDP BIT(5)
701ec82ad7cSTomasz Dzieciol #define E1000_ADVRXD_PKT_SCTP BIT(6)
702ed447c60SAkihiko Odaki
703560cf339STomasz Dzieciol #define IGB_MAX_PS_BUFFERS 2
704560cf339STomasz Dzieciol
705560cf339STomasz Dzieciol #define E1000_ADVRXD_HDR_LEN_OFFSET (21 - 16)
706560cf339STomasz Dzieciol #define E1000_ADVRXD_ADV_HDR_LEN_MASK ((BIT(10) - 1) << \
707560cf339STomasz Dzieciol E1000_ADVRXD_HDR_LEN_OFFSET)
708560cf339STomasz Dzieciol #define E1000_ADVRXD_HDR_SPH BIT(15)
709560cf339STomasz Dzieciol #define E1000_ADVRXD_ST_ERR_HBO_OFFSET BIT(3 + 20)
710560cf339STomasz Dzieciol
igb_ivar_entry_rx(uint8_t i)7113a977deeSAkihiko Odaki static inline uint8_t igb_ivar_entry_rx(uint8_t i)
7123a977deeSAkihiko Odaki {
7133a977deeSAkihiko Odaki return i < 8 ? i * 4 : (i - 8) * 4 + 2;
7143a977deeSAkihiko Odaki }
7153a977deeSAkihiko Odaki
igb_ivar_entry_tx(uint8_t i)7163a977deeSAkihiko Odaki static inline uint8_t igb_ivar_entry_tx(uint8_t i)
7173a977deeSAkihiko Odaki {
7183a977deeSAkihiko Odaki return i < 8 ? i * 4 + 1 : (i - 8) * 4 + 3;
7193a977deeSAkihiko Odaki }
7203a977deeSAkihiko Odaki
7213a977deeSAkihiko Odaki #endif
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