1fcbd8018SJean-Christophe Dubois /* 2fcbd8018SJean-Christophe Dubois * i.MX Fast Ethernet Controller emulation. 3fcbd8018SJean-Christophe Dubois * 4fcbd8018SJean-Christophe Dubois * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> 5fcbd8018SJean-Christophe Dubois * 6fcbd8018SJean-Christophe Dubois * Based on Coldfire Fast Ethernet Controller emulation. 7fcbd8018SJean-Christophe Dubois * 8fcbd8018SJean-Christophe Dubois * Copyright (c) 2007 CodeSourcery. 9fcbd8018SJean-Christophe Dubois * 10fcbd8018SJean-Christophe Dubois * This program is free software; you can redistribute it and/or modify it 11fcbd8018SJean-Christophe Dubois * under the terms of the GNU General Public License as published by the 12fcbd8018SJean-Christophe Dubois * Free Software Foundation; either version 2 of the License, or 13fcbd8018SJean-Christophe Dubois * (at your option) any later version. 14fcbd8018SJean-Christophe Dubois * 15fcbd8018SJean-Christophe Dubois * This program is distributed in the hope that it will be useful, but WITHOUT 16fcbd8018SJean-Christophe Dubois * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17fcbd8018SJean-Christophe Dubois * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18fcbd8018SJean-Christophe Dubois * for more details. 19fcbd8018SJean-Christophe Dubois * 20fcbd8018SJean-Christophe Dubois * You should have received a copy of the GNU General Public License along 21fcbd8018SJean-Christophe Dubois * with this program; if not, see <http://www.gnu.org/licenses/>. 22fcbd8018SJean-Christophe Dubois */ 23fcbd8018SJean-Christophe Dubois 248ef94f0bSPeter Maydell #include "qemu/osdep.h" 2564552b6bSMarkus Armbruster #include "hw/irq.h" 26fcbd8018SJean-Christophe Dubois #include "hw/net/imx_fec.h" 27*a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 28d6454270SMarkus Armbruster #include "migration/vmstate.h" 29fcbd8018SJean-Christophe Dubois #include "sysemu/dma.h" 3003dd024fSPaolo Bonzini #include "qemu/log.h" 310b8fa32fSMarkus Armbruster #include "qemu/module.h" 32a699b410SJean-Christophe Dubois #include "net/checksum.h" 33a699b410SJean-Christophe Dubois #include "net/eth.h" 34fcbd8018SJean-Christophe Dubois 35fcbd8018SJean-Christophe Dubois /* For crc32 */ 36fcbd8018SJean-Christophe Dubois #include <zlib.h> 37fcbd8018SJean-Christophe Dubois 38b72d8d25SJean-Christophe Dubois #ifndef DEBUG_IMX_FEC 39b72d8d25SJean-Christophe Dubois #define DEBUG_IMX_FEC 0 40fcbd8018SJean-Christophe Dubois #endif 41fcbd8018SJean-Christophe Dubois 42b72d8d25SJean-Christophe Dubois #define FEC_PRINTF(fmt, args...) \ 43b72d8d25SJean-Christophe Dubois do { \ 44b72d8d25SJean-Christophe Dubois if (DEBUG_IMX_FEC) { \ 45b72d8d25SJean-Christophe Dubois fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_FEC, \ 46b72d8d25SJean-Christophe Dubois __func__, ##args); \ 47b72d8d25SJean-Christophe Dubois } \ 48fcbd8018SJean-Christophe Dubois } while (0) 49b72d8d25SJean-Christophe Dubois 50b72d8d25SJean-Christophe Dubois #ifndef DEBUG_IMX_PHY 51b72d8d25SJean-Christophe Dubois #define DEBUG_IMX_PHY 0 52fcbd8018SJean-Christophe Dubois #endif 53fcbd8018SJean-Christophe Dubois 54b72d8d25SJean-Christophe Dubois #define PHY_PRINTF(fmt, args...) \ 55b72d8d25SJean-Christophe Dubois do { \ 56b72d8d25SJean-Christophe Dubois if (DEBUG_IMX_PHY) { \ 57b72d8d25SJean-Christophe Dubois fprintf(stderr, "[%s.phy]%s: " fmt , TYPE_IMX_FEC, \ 58b72d8d25SJean-Christophe Dubois __func__, ##args); \ 59b72d8d25SJean-Christophe Dubois } \ 60fcbd8018SJean-Christophe Dubois } while (0) 61fcbd8018SJean-Christophe Dubois 6281f17e0dSPrasad J Pandit #define IMX_MAX_DESC 1024 6381f17e0dSPrasad J Pandit 64a699b410SJean-Christophe Dubois static const char *imx_default_reg_name(IMXFECState *s, uint32_t index) 65db0de352SJean-Christophe Dubois { 66db0de352SJean-Christophe Dubois static char tmp[20]; 67a699b410SJean-Christophe Dubois sprintf(tmp, "index %d", index); 68a699b410SJean-Christophe Dubois return tmp; 69a699b410SJean-Christophe Dubois } 70db0de352SJean-Christophe Dubois 71a699b410SJean-Christophe Dubois static const char *imx_fec_reg_name(IMXFECState *s, uint32_t index) 72a699b410SJean-Christophe Dubois { 73a699b410SJean-Christophe Dubois switch (index) { 74a699b410SJean-Christophe Dubois case ENET_FRBR: 75a699b410SJean-Christophe Dubois return "FRBR"; 76a699b410SJean-Christophe Dubois case ENET_FRSR: 77a699b410SJean-Christophe Dubois return "FRSR"; 78a699b410SJean-Christophe Dubois case ENET_MIIGSK_CFGR: 79a699b410SJean-Christophe Dubois return "MIIGSK_CFGR"; 80a699b410SJean-Christophe Dubois case ENET_MIIGSK_ENR: 81a699b410SJean-Christophe Dubois return "MIIGSK_ENR"; 82a699b410SJean-Christophe Dubois default: 83a699b410SJean-Christophe Dubois return imx_default_reg_name(s, index); 84a699b410SJean-Christophe Dubois } 85a699b410SJean-Christophe Dubois } 86a699b410SJean-Christophe Dubois 87a699b410SJean-Christophe Dubois static const char *imx_enet_reg_name(IMXFECState *s, uint32_t index) 88a699b410SJean-Christophe Dubois { 89a699b410SJean-Christophe Dubois switch (index) { 90a699b410SJean-Christophe Dubois case ENET_RSFL: 91a699b410SJean-Christophe Dubois return "RSFL"; 92a699b410SJean-Christophe Dubois case ENET_RSEM: 93a699b410SJean-Christophe Dubois return "RSEM"; 94a699b410SJean-Christophe Dubois case ENET_RAEM: 95a699b410SJean-Christophe Dubois return "RAEM"; 96a699b410SJean-Christophe Dubois case ENET_RAFL: 97a699b410SJean-Christophe Dubois return "RAFL"; 98a699b410SJean-Christophe Dubois case ENET_TSEM: 99a699b410SJean-Christophe Dubois return "TSEM"; 100a699b410SJean-Christophe Dubois case ENET_TAEM: 101a699b410SJean-Christophe Dubois return "TAEM"; 102a699b410SJean-Christophe Dubois case ENET_TAFL: 103a699b410SJean-Christophe Dubois return "TAFL"; 104a699b410SJean-Christophe Dubois case ENET_TIPG: 105a699b410SJean-Christophe Dubois return "TIPG"; 106a699b410SJean-Christophe Dubois case ENET_FTRL: 107a699b410SJean-Christophe Dubois return "FTRL"; 108a699b410SJean-Christophe Dubois case ENET_TACC: 109a699b410SJean-Christophe Dubois return "TACC"; 110a699b410SJean-Christophe Dubois case ENET_RACC: 111a699b410SJean-Christophe Dubois return "RACC"; 112a699b410SJean-Christophe Dubois case ENET_ATCR: 113a699b410SJean-Christophe Dubois return "ATCR"; 114a699b410SJean-Christophe Dubois case ENET_ATVR: 115a699b410SJean-Christophe Dubois return "ATVR"; 116a699b410SJean-Christophe Dubois case ENET_ATOFF: 117a699b410SJean-Christophe Dubois return "ATOFF"; 118a699b410SJean-Christophe Dubois case ENET_ATPER: 119a699b410SJean-Christophe Dubois return "ATPER"; 120a699b410SJean-Christophe Dubois case ENET_ATCOR: 121a699b410SJean-Christophe Dubois return "ATCOR"; 122a699b410SJean-Christophe Dubois case ENET_ATINC: 123a699b410SJean-Christophe Dubois return "ATINC"; 124a699b410SJean-Christophe Dubois case ENET_ATSTMP: 125a699b410SJean-Christophe Dubois return "ATSTMP"; 126a699b410SJean-Christophe Dubois case ENET_TGSR: 127a699b410SJean-Christophe Dubois return "TGSR"; 128a699b410SJean-Christophe Dubois case ENET_TCSR0: 129a699b410SJean-Christophe Dubois return "TCSR0"; 130a699b410SJean-Christophe Dubois case ENET_TCCR0: 131a699b410SJean-Christophe Dubois return "TCCR0"; 132a699b410SJean-Christophe Dubois case ENET_TCSR1: 133a699b410SJean-Christophe Dubois return "TCSR1"; 134a699b410SJean-Christophe Dubois case ENET_TCCR1: 135a699b410SJean-Christophe Dubois return "TCCR1"; 136a699b410SJean-Christophe Dubois case ENET_TCSR2: 137a699b410SJean-Christophe Dubois return "TCSR2"; 138a699b410SJean-Christophe Dubois case ENET_TCCR2: 139a699b410SJean-Christophe Dubois return "TCCR2"; 140a699b410SJean-Christophe Dubois case ENET_TCSR3: 141a699b410SJean-Christophe Dubois return "TCSR3"; 142a699b410SJean-Christophe Dubois case ENET_TCCR3: 143a699b410SJean-Christophe Dubois return "TCCR3"; 144a699b410SJean-Christophe Dubois default: 145a699b410SJean-Christophe Dubois return imx_default_reg_name(s, index); 146a699b410SJean-Christophe Dubois } 147a699b410SJean-Christophe Dubois } 148a699b410SJean-Christophe Dubois 149a699b410SJean-Christophe Dubois static const char *imx_eth_reg_name(IMXFECState *s, uint32_t index) 150a699b410SJean-Christophe Dubois { 151db0de352SJean-Christophe Dubois switch (index) { 152db0de352SJean-Christophe Dubois case ENET_EIR: 153db0de352SJean-Christophe Dubois return "EIR"; 154db0de352SJean-Christophe Dubois case ENET_EIMR: 155db0de352SJean-Christophe Dubois return "EIMR"; 156db0de352SJean-Christophe Dubois case ENET_RDAR: 157db0de352SJean-Christophe Dubois return "RDAR"; 158db0de352SJean-Christophe Dubois case ENET_TDAR: 159db0de352SJean-Christophe Dubois return "TDAR"; 160db0de352SJean-Christophe Dubois case ENET_ECR: 161db0de352SJean-Christophe Dubois return "ECR"; 162db0de352SJean-Christophe Dubois case ENET_MMFR: 163db0de352SJean-Christophe Dubois return "MMFR"; 164db0de352SJean-Christophe Dubois case ENET_MSCR: 165db0de352SJean-Christophe Dubois return "MSCR"; 166db0de352SJean-Christophe Dubois case ENET_MIBC: 167db0de352SJean-Christophe Dubois return "MIBC"; 168db0de352SJean-Christophe Dubois case ENET_RCR: 169db0de352SJean-Christophe Dubois return "RCR"; 170db0de352SJean-Christophe Dubois case ENET_TCR: 171db0de352SJean-Christophe Dubois return "TCR"; 172db0de352SJean-Christophe Dubois case ENET_PALR: 173db0de352SJean-Christophe Dubois return "PALR"; 174db0de352SJean-Christophe Dubois case ENET_PAUR: 175db0de352SJean-Christophe Dubois return "PAUR"; 176db0de352SJean-Christophe Dubois case ENET_OPD: 177db0de352SJean-Christophe Dubois return "OPD"; 178db0de352SJean-Christophe Dubois case ENET_IAUR: 179db0de352SJean-Christophe Dubois return "IAUR"; 180db0de352SJean-Christophe Dubois case ENET_IALR: 181db0de352SJean-Christophe Dubois return "IALR"; 182db0de352SJean-Christophe Dubois case ENET_GAUR: 183db0de352SJean-Christophe Dubois return "GAUR"; 184db0de352SJean-Christophe Dubois case ENET_GALR: 185db0de352SJean-Christophe Dubois return "GALR"; 186db0de352SJean-Christophe Dubois case ENET_TFWR: 187db0de352SJean-Christophe Dubois return "TFWR"; 188db0de352SJean-Christophe Dubois case ENET_RDSR: 189db0de352SJean-Christophe Dubois return "RDSR"; 190db0de352SJean-Christophe Dubois case ENET_TDSR: 191db0de352SJean-Christophe Dubois return "TDSR"; 192db0de352SJean-Christophe Dubois case ENET_MRBR: 193db0de352SJean-Christophe Dubois return "MRBR"; 194db0de352SJean-Christophe Dubois default: 195a699b410SJean-Christophe Dubois if (s->is_fec) { 196a699b410SJean-Christophe Dubois return imx_fec_reg_name(s, index); 197a699b410SJean-Christophe Dubois } else { 198a699b410SJean-Christophe Dubois return imx_enet_reg_name(s, index); 199a699b410SJean-Christophe Dubois } 200db0de352SJean-Christophe Dubois } 201db0de352SJean-Christophe Dubois } 202db0de352SJean-Christophe Dubois 203f93f961cSAndrey Smirnov /* 204f93f961cSAndrey Smirnov * Versions of this device with more than one TX descriptor save the 205f93f961cSAndrey Smirnov * 2nd and 3rd descriptors in a subsection, to maintain migration 206f93f961cSAndrey Smirnov * compatibility with previous versions of the device that only 207f93f961cSAndrey Smirnov * supported a single descriptor. 208f93f961cSAndrey Smirnov */ 209f93f961cSAndrey Smirnov static bool imx_eth_is_multi_tx_ring(void *opaque) 210f93f961cSAndrey Smirnov { 211f93f961cSAndrey Smirnov IMXFECState *s = IMX_FEC(opaque); 212f93f961cSAndrey Smirnov 213f93f961cSAndrey Smirnov return s->tx_ring_num > 1; 214f93f961cSAndrey Smirnov } 215f93f961cSAndrey Smirnov 216f93f961cSAndrey Smirnov static const VMStateDescription vmstate_imx_eth_txdescs = { 217f93f961cSAndrey Smirnov .name = "imx.fec/txdescs", 218f93f961cSAndrey Smirnov .version_id = 1, 219f93f961cSAndrey Smirnov .minimum_version_id = 1, 220f93f961cSAndrey Smirnov .needed = imx_eth_is_multi_tx_ring, 221f93f961cSAndrey Smirnov .fields = (VMStateField[]) { 222f93f961cSAndrey Smirnov VMSTATE_UINT32(tx_descriptor[1], IMXFECState), 223f93f961cSAndrey Smirnov VMSTATE_UINT32(tx_descriptor[2], IMXFECState), 224f93f961cSAndrey Smirnov VMSTATE_END_OF_LIST() 225f93f961cSAndrey Smirnov } 226f93f961cSAndrey Smirnov }; 227f93f961cSAndrey Smirnov 228a699b410SJean-Christophe Dubois static const VMStateDescription vmstate_imx_eth = { 229fcbd8018SJean-Christophe Dubois .name = TYPE_IMX_FEC, 230db0de352SJean-Christophe Dubois .version_id = 2, 231db0de352SJean-Christophe Dubois .minimum_version_id = 2, 232fcbd8018SJean-Christophe Dubois .fields = (VMStateField[]) { 233db0de352SJean-Christophe Dubois VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), 234fcbd8018SJean-Christophe Dubois VMSTATE_UINT32(rx_descriptor, IMXFECState), 235f93f961cSAndrey Smirnov VMSTATE_UINT32(tx_descriptor[0], IMXFECState), 236fcbd8018SJean-Christophe Dubois VMSTATE_UINT32(phy_status, IMXFECState), 237fcbd8018SJean-Christophe Dubois VMSTATE_UINT32(phy_control, IMXFECState), 238fcbd8018SJean-Christophe Dubois VMSTATE_UINT32(phy_advertise, IMXFECState), 239fcbd8018SJean-Christophe Dubois VMSTATE_UINT32(phy_int, IMXFECState), 240fcbd8018SJean-Christophe Dubois VMSTATE_UINT32(phy_int_mask, IMXFECState), 241fcbd8018SJean-Christophe Dubois VMSTATE_END_OF_LIST() 242f93f961cSAndrey Smirnov }, 243f93f961cSAndrey Smirnov .subsections = (const VMStateDescription * []) { 244f93f961cSAndrey Smirnov &vmstate_imx_eth_txdescs, 245f93f961cSAndrey Smirnov NULL 246f93f961cSAndrey Smirnov }, 247fcbd8018SJean-Christophe Dubois }; 248fcbd8018SJean-Christophe Dubois 249fcbd8018SJean-Christophe Dubois #define PHY_INT_ENERGYON (1 << 7) 250fcbd8018SJean-Christophe Dubois #define PHY_INT_AUTONEG_COMPLETE (1 << 6) 251fcbd8018SJean-Christophe Dubois #define PHY_INT_FAULT (1 << 5) 252fcbd8018SJean-Christophe Dubois #define PHY_INT_DOWN (1 << 4) 253fcbd8018SJean-Christophe Dubois #define PHY_INT_AUTONEG_LP (1 << 3) 254fcbd8018SJean-Christophe Dubois #define PHY_INT_PARFAULT (1 << 2) 255fcbd8018SJean-Christophe Dubois #define PHY_INT_AUTONEG_PAGE (1 << 1) 256fcbd8018SJean-Christophe Dubois 257a699b410SJean-Christophe Dubois static void imx_eth_update(IMXFECState *s); 258fcbd8018SJean-Christophe Dubois 259fcbd8018SJean-Christophe Dubois /* 260fcbd8018SJean-Christophe Dubois * The MII phy could raise a GPIO to the processor which in turn 261fcbd8018SJean-Christophe Dubois * could be handled as an interrpt by the OS. 262fcbd8018SJean-Christophe Dubois * For now we don't handle any GPIO/interrupt line, so the OS will 263fcbd8018SJean-Christophe Dubois * have to poll for the PHY status. 264fcbd8018SJean-Christophe Dubois */ 265fcbd8018SJean-Christophe Dubois static void phy_update_irq(IMXFECState *s) 266fcbd8018SJean-Christophe Dubois { 267a699b410SJean-Christophe Dubois imx_eth_update(s); 268fcbd8018SJean-Christophe Dubois } 269fcbd8018SJean-Christophe Dubois 270fcbd8018SJean-Christophe Dubois static void phy_update_link(IMXFECState *s) 271fcbd8018SJean-Christophe Dubois { 272fcbd8018SJean-Christophe Dubois /* Autonegotiation status mirrors link status. */ 273fcbd8018SJean-Christophe Dubois if (qemu_get_queue(s->nic)->link_down) { 274fcbd8018SJean-Christophe Dubois PHY_PRINTF("link is down\n"); 275fcbd8018SJean-Christophe Dubois s->phy_status &= ~0x0024; 276fcbd8018SJean-Christophe Dubois s->phy_int |= PHY_INT_DOWN; 277fcbd8018SJean-Christophe Dubois } else { 278fcbd8018SJean-Christophe Dubois PHY_PRINTF("link is up\n"); 279fcbd8018SJean-Christophe Dubois s->phy_status |= 0x0024; 280fcbd8018SJean-Christophe Dubois s->phy_int |= PHY_INT_ENERGYON; 281fcbd8018SJean-Christophe Dubois s->phy_int |= PHY_INT_AUTONEG_COMPLETE; 282fcbd8018SJean-Christophe Dubois } 283fcbd8018SJean-Christophe Dubois phy_update_irq(s); 284fcbd8018SJean-Christophe Dubois } 285fcbd8018SJean-Christophe Dubois 286a699b410SJean-Christophe Dubois static void imx_eth_set_link(NetClientState *nc) 287fcbd8018SJean-Christophe Dubois { 288fcbd8018SJean-Christophe Dubois phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); 289fcbd8018SJean-Christophe Dubois } 290fcbd8018SJean-Christophe Dubois 291fcbd8018SJean-Christophe Dubois static void phy_reset(IMXFECState *s) 292fcbd8018SJean-Christophe Dubois { 293fcbd8018SJean-Christophe Dubois s->phy_status = 0x7809; 294fcbd8018SJean-Christophe Dubois s->phy_control = 0x3000; 295fcbd8018SJean-Christophe Dubois s->phy_advertise = 0x01e1; 296fcbd8018SJean-Christophe Dubois s->phy_int_mask = 0; 297fcbd8018SJean-Christophe Dubois s->phy_int = 0; 298fcbd8018SJean-Christophe Dubois phy_update_link(s); 299fcbd8018SJean-Christophe Dubois } 300fcbd8018SJean-Christophe Dubois 301fcbd8018SJean-Christophe Dubois static uint32_t do_phy_read(IMXFECState *s, int reg) 302fcbd8018SJean-Christophe Dubois { 303fcbd8018SJean-Christophe Dubois uint32_t val; 304fcbd8018SJean-Christophe Dubois 305fcbd8018SJean-Christophe Dubois if (reg > 31) { 306fcbd8018SJean-Christophe Dubois /* we only advertise one phy */ 307fcbd8018SJean-Christophe Dubois return 0; 308fcbd8018SJean-Christophe Dubois } 309fcbd8018SJean-Christophe Dubois 310fcbd8018SJean-Christophe Dubois switch (reg) { 311fcbd8018SJean-Christophe Dubois case 0: /* Basic Control */ 312fcbd8018SJean-Christophe Dubois val = s->phy_control; 313fcbd8018SJean-Christophe Dubois break; 314fcbd8018SJean-Christophe Dubois case 1: /* Basic Status */ 315fcbd8018SJean-Christophe Dubois val = s->phy_status; 316fcbd8018SJean-Christophe Dubois break; 317fcbd8018SJean-Christophe Dubois case 2: /* ID1 */ 318fcbd8018SJean-Christophe Dubois val = 0x0007; 319fcbd8018SJean-Christophe Dubois break; 320fcbd8018SJean-Christophe Dubois case 3: /* ID2 */ 321fcbd8018SJean-Christophe Dubois val = 0xc0d1; 322fcbd8018SJean-Christophe Dubois break; 323fcbd8018SJean-Christophe Dubois case 4: /* Auto-neg advertisement */ 324fcbd8018SJean-Christophe Dubois val = s->phy_advertise; 325fcbd8018SJean-Christophe Dubois break; 326fcbd8018SJean-Christophe Dubois case 5: /* Auto-neg Link Partner Ability */ 327fcbd8018SJean-Christophe Dubois val = 0x0f71; 328fcbd8018SJean-Christophe Dubois break; 329fcbd8018SJean-Christophe Dubois case 6: /* Auto-neg Expansion */ 330fcbd8018SJean-Christophe Dubois val = 1; 331fcbd8018SJean-Christophe Dubois break; 332fcbd8018SJean-Christophe Dubois case 29: /* Interrupt source. */ 333fcbd8018SJean-Christophe Dubois val = s->phy_int; 334fcbd8018SJean-Christophe Dubois s->phy_int = 0; 335fcbd8018SJean-Christophe Dubois phy_update_irq(s); 336fcbd8018SJean-Christophe Dubois break; 337fcbd8018SJean-Christophe Dubois case 30: /* Interrupt mask */ 338fcbd8018SJean-Christophe Dubois val = s->phy_int_mask; 339fcbd8018SJean-Christophe Dubois break; 340fcbd8018SJean-Christophe Dubois case 17: 341fcbd8018SJean-Christophe Dubois case 18: 342fcbd8018SJean-Christophe Dubois case 27: 343fcbd8018SJean-Christophe Dubois case 31: 344b72d8d25SJean-Christophe Dubois qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", 345fcbd8018SJean-Christophe Dubois TYPE_IMX_FEC, __func__, reg); 346fcbd8018SJean-Christophe Dubois val = 0; 347fcbd8018SJean-Christophe Dubois break; 348fcbd8018SJean-Christophe Dubois default: 349b72d8d25SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", 350fcbd8018SJean-Christophe Dubois TYPE_IMX_FEC, __func__, reg); 351fcbd8018SJean-Christophe Dubois val = 0; 352fcbd8018SJean-Christophe Dubois break; 353fcbd8018SJean-Christophe Dubois } 354fcbd8018SJean-Christophe Dubois 355fcbd8018SJean-Christophe Dubois PHY_PRINTF("read 0x%04x @ %d\n", val, reg); 356fcbd8018SJean-Christophe Dubois 357fcbd8018SJean-Christophe Dubois return val; 358fcbd8018SJean-Christophe Dubois } 359fcbd8018SJean-Christophe Dubois 360fcbd8018SJean-Christophe Dubois static void do_phy_write(IMXFECState *s, int reg, uint32_t val) 361fcbd8018SJean-Christophe Dubois { 362fcbd8018SJean-Christophe Dubois PHY_PRINTF("write 0x%04x @ %d\n", val, reg); 363fcbd8018SJean-Christophe Dubois 364fcbd8018SJean-Christophe Dubois if (reg > 31) { 365fcbd8018SJean-Christophe Dubois /* we only advertise one phy */ 366fcbd8018SJean-Christophe Dubois return; 367fcbd8018SJean-Christophe Dubois } 368fcbd8018SJean-Christophe Dubois 369fcbd8018SJean-Christophe Dubois switch (reg) { 370fcbd8018SJean-Christophe Dubois case 0: /* Basic Control */ 371fcbd8018SJean-Christophe Dubois if (val & 0x8000) { 372fcbd8018SJean-Christophe Dubois phy_reset(s); 373fcbd8018SJean-Christophe Dubois } else { 374fcbd8018SJean-Christophe Dubois s->phy_control = val & 0x7980; 375fcbd8018SJean-Christophe Dubois /* Complete autonegotiation immediately. */ 376fcbd8018SJean-Christophe Dubois if (val & 0x1000) { 377fcbd8018SJean-Christophe Dubois s->phy_status |= 0x0020; 378fcbd8018SJean-Christophe Dubois } 379fcbd8018SJean-Christophe Dubois } 380fcbd8018SJean-Christophe Dubois break; 381fcbd8018SJean-Christophe Dubois case 4: /* Auto-neg advertisement */ 382fcbd8018SJean-Christophe Dubois s->phy_advertise = (val & 0x2d7f) | 0x80; 383fcbd8018SJean-Christophe Dubois break; 384fcbd8018SJean-Christophe Dubois case 30: /* Interrupt mask */ 385fcbd8018SJean-Christophe Dubois s->phy_int_mask = val & 0xff; 386fcbd8018SJean-Christophe Dubois phy_update_irq(s); 387fcbd8018SJean-Christophe Dubois break; 388fcbd8018SJean-Christophe Dubois case 17: 389fcbd8018SJean-Christophe Dubois case 18: 390fcbd8018SJean-Christophe Dubois case 27: 391fcbd8018SJean-Christophe Dubois case 31: 392b72d8d25SJean-Christophe Dubois qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", 393fcbd8018SJean-Christophe Dubois TYPE_IMX_FEC, __func__, reg); 394fcbd8018SJean-Christophe Dubois break; 395fcbd8018SJean-Christophe Dubois default: 396b72d8d25SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", 397fcbd8018SJean-Christophe Dubois TYPE_IMX_FEC, __func__, reg); 398fcbd8018SJean-Christophe Dubois break; 399fcbd8018SJean-Christophe Dubois } 400fcbd8018SJean-Christophe Dubois } 401fcbd8018SJean-Christophe Dubois 402fcbd8018SJean-Christophe Dubois static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) 403fcbd8018SJean-Christophe Dubois { 404fcbd8018SJean-Christophe Dubois dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); 405fcbd8018SJean-Christophe Dubois } 406fcbd8018SJean-Christophe Dubois 407fcbd8018SJean-Christophe Dubois static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr) 408fcbd8018SJean-Christophe Dubois { 409fcbd8018SJean-Christophe Dubois dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); 410fcbd8018SJean-Christophe Dubois } 411fcbd8018SJean-Christophe Dubois 412a699b410SJean-Christophe Dubois static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_addr_t addr) 413fcbd8018SJean-Christophe Dubois { 414a699b410SJean-Christophe Dubois dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); 415a699b410SJean-Christophe Dubois } 416a699b410SJean-Christophe Dubois 417a699b410SJean-Christophe Dubois static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) 418a699b410SJean-Christophe Dubois { 419a699b410SJean-Christophe Dubois dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); 420a699b410SJean-Christophe Dubois } 421a699b410SJean-Christophe Dubois 422a699b410SJean-Christophe Dubois static void imx_eth_update(IMXFECState *s) 423a699b410SJean-Christophe Dubois { 4246461d7e2SGuenter Roeck /* 4256461d7e2SGuenter Roeck * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER 4266461d7e2SGuenter Roeck * interrupts swapped. This worked with older versions of Linux (4.14 4276461d7e2SGuenter Roeck * and older) since Linux associated both interrupt lines with Ethernet 4286461d7e2SGuenter Roeck * MAC interrupts. Specifically, 4296461d7e2SGuenter Roeck * - Linux 4.15 and later have separate interrupt handlers for the MAC and 4306461d7e2SGuenter Roeck * timer interrupts. Those versions of Linux fail with versions of QEMU 4316461d7e2SGuenter Roeck * with swapped interrupt assignments. 4326461d7e2SGuenter Roeck * - In linux 4.14, both interrupt lines were registered with the Ethernet 4336461d7e2SGuenter Roeck * MAC interrupt handler. As a result, all versions of qemu happen to 4346461d7e2SGuenter Roeck * work, though that is accidental. 4356461d7e2SGuenter Roeck * - In Linux 4.9 and older, the timer interrupt was registered directly 4366461d7e2SGuenter Roeck * with the Ethernet MAC interrupt handler. The MAC interrupt was 4376461d7e2SGuenter Roeck * redirected to a GPIO interrupt to work around erratum ERR006687. 4386461d7e2SGuenter Roeck * This was implemented using the SOC's IOMUX block. In qemu, this GPIO 4396461d7e2SGuenter Roeck * interrupt never fired since IOMUX is currently not supported in qemu. 4406461d7e2SGuenter Roeck * Linux instead received MAC interrupts on the timer interrupt. 4416461d7e2SGuenter Roeck * As a result, qemu versions with the swapped interrupt assignment work, 4426461d7e2SGuenter Roeck * albeit accidentally, but qemu versions with the correct interrupt 4436461d7e2SGuenter Roeck * assignment fail. 4446461d7e2SGuenter Roeck * 4456461d7e2SGuenter Roeck * To ensure that all versions of Linux work, generate ENET_INT_MAC 4466461d7e2SGuenter Roeck * interrrupts on both interrupt lines. This should be changed if and when 4476461d7e2SGuenter Roeck * qemu supports IOMUX. 4486461d7e2SGuenter Roeck */ 4496461d7e2SGuenter Roeck if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & 4506461d7e2SGuenter Roeck (ENET_INT_MAC | ENET_INT_TS_TIMER)) { 451a699b410SJean-Christophe Dubois qemu_set_irq(s->irq[1], 1); 452db0de352SJean-Christophe Dubois } else { 453a699b410SJean-Christophe Dubois qemu_set_irq(s->irq[1], 0); 454a699b410SJean-Christophe Dubois } 455a699b410SJean-Christophe Dubois 456a699b410SJean-Christophe Dubois if (s->regs[ENET_EIR] & s->regs[ENET_EIMR] & ENET_INT_MAC) { 457a699b410SJean-Christophe Dubois qemu_set_irq(s->irq[0], 1); 458a699b410SJean-Christophe Dubois } else { 459a699b410SJean-Christophe Dubois qemu_set_irq(s->irq[0], 0); 460fcbd8018SJean-Christophe Dubois } 461fcbd8018SJean-Christophe Dubois } 462fcbd8018SJean-Christophe Dubois 463fcbd8018SJean-Christophe Dubois static void imx_fec_do_tx(IMXFECState *s) 464fcbd8018SJean-Christophe Dubois { 46581f17e0dSPrasad J Pandit int frame_size = 0, descnt = 0; 4667bac20dcSAndrey Smirnov uint8_t *ptr = s->frame; 467f93f961cSAndrey Smirnov uint32_t addr = s->tx_descriptor[0]; 468fcbd8018SJean-Christophe Dubois 46981f17e0dSPrasad J Pandit while (descnt++ < IMX_MAX_DESC) { 470fcbd8018SJean-Christophe Dubois IMXFECBufDesc bd; 471fcbd8018SJean-Christophe Dubois int len; 472fcbd8018SJean-Christophe Dubois 473fcbd8018SJean-Christophe Dubois imx_fec_read_bd(&bd, addr); 474fcbd8018SJean-Christophe Dubois FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n", 475fcbd8018SJean-Christophe Dubois addr, bd.flags, bd.length, bd.data); 4761bb3c371SJean-Christophe Dubois if ((bd.flags & ENET_BD_R) == 0) { 477fcbd8018SJean-Christophe Dubois /* Run out of descriptors to transmit. */ 478a699b410SJean-Christophe Dubois FEC_PRINTF("tx_bd ran out of descriptors to transmit\n"); 479fcbd8018SJean-Christophe Dubois break; 480fcbd8018SJean-Christophe Dubois } 481fcbd8018SJean-Christophe Dubois len = bd.length; 4821bb3c371SJean-Christophe Dubois if (frame_size + len > ENET_MAX_FRAME_SIZE) { 4831bb3c371SJean-Christophe Dubois len = ENET_MAX_FRAME_SIZE - frame_size; 484db0de352SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_BABT; 485fcbd8018SJean-Christophe Dubois } 486fcbd8018SJean-Christophe Dubois dma_memory_read(&address_space_memory, bd.data, ptr, len); 487fcbd8018SJean-Christophe Dubois ptr += len; 488fcbd8018SJean-Christophe Dubois frame_size += len; 4891bb3c371SJean-Christophe Dubois if (bd.flags & ENET_BD_L) { 490fcbd8018SJean-Christophe Dubois /* Last buffer in frame. */ 4917bac20dcSAndrey Smirnov qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size); 4927bac20dcSAndrey Smirnov ptr = s->frame; 493fcbd8018SJean-Christophe Dubois frame_size = 0; 494db0de352SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_TXF; 495fcbd8018SJean-Christophe Dubois } 496db0de352SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_TXB; 4971bb3c371SJean-Christophe Dubois bd.flags &= ~ENET_BD_R; 498fcbd8018SJean-Christophe Dubois /* Write back the modified descriptor. */ 499fcbd8018SJean-Christophe Dubois imx_fec_write_bd(&bd, addr); 500fcbd8018SJean-Christophe Dubois /* Advance to the next descriptor. */ 5011bb3c371SJean-Christophe Dubois if ((bd.flags & ENET_BD_W) != 0) { 502db0de352SJean-Christophe Dubois addr = s->regs[ENET_TDSR]; 503fcbd8018SJean-Christophe Dubois } else { 504db0de352SJean-Christophe Dubois addr += sizeof(bd); 505fcbd8018SJean-Christophe Dubois } 506fcbd8018SJean-Christophe Dubois } 507fcbd8018SJean-Christophe Dubois 508f93f961cSAndrey Smirnov s->tx_descriptor[0] = addr; 509fcbd8018SJean-Christophe Dubois 510a699b410SJean-Christophe Dubois imx_eth_update(s); 511fcbd8018SJean-Christophe Dubois } 512fcbd8018SJean-Christophe Dubois 513f93f961cSAndrey Smirnov static void imx_enet_do_tx(IMXFECState *s, uint32_t index) 514a699b410SJean-Christophe Dubois { 51581f17e0dSPrasad J Pandit int frame_size = 0, descnt = 0; 516f93f961cSAndrey Smirnov 5177bac20dcSAndrey Smirnov uint8_t *ptr = s->frame; 518f93f961cSAndrey Smirnov uint32_t addr, int_txb, int_txf, tdsr; 519f93f961cSAndrey Smirnov size_t ring; 520f93f961cSAndrey Smirnov 521f93f961cSAndrey Smirnov switch (index) { 522f93f961cSAndrey Smirnov case ENET_TDAR: 523f93f961cSAndrey Smirnov ring = 0; 524f93f961cSAndrey Smirnov int_txb = ENET_INT_TXB; 525f93f961cSAndrey Smirnov int_txf = ENET_INT_TXF; 526f93f961cSAndrey Smirnov tdsr = ENET_TDSR; 527f93f961cSAndrey Smirnov break; 528f93f961cSAndrey Smirnov case ENET_TDAR1: 529f93f961cSAndrey Smirnov ring = 1; 530f93f961cSAndrey Smirnov int_txb = ENET_INT_TXB1; 531f93f961cSAndrey Smirnov int_txf = ENET_INT_TXF1; 532f93f961cSAndrey Smirnov tdsr = ENET_TDSR1; 533f93f961cSAndrey Smirnov break; 534f93f961cSAndrey Smirnov case ENET_TDAR2: 535f93f961cSAndrey Smirnov ring = 2; 536f93f961cSAndrey Smirnov int_txb = ENET_INT_TXB2; 537f93f961cSAndrey Smirnov int_txf = ENET_INT_TXF2; 538f93f961cSAndrey Smirnov tdsr = ENET_TDSR2; 539f93f961cSAndrey Smirnov break; 540f93f961cSAndrey Smirnov default: 541f93f961cSAndrey Smirnov qemu_log_mask(LOG_GUEST_ERROR, 542f93f961cSAndrey Smirnov "%s: bogus value for index %x\n", 543f93f961cSAndrey Smirnov __func__, index); 544f93f961cSAndrey Smirnov abort(); 545f93f961cSAndrey Smirnov break; 546f93f961cSAndrey Smirnov } 547f93f961cSAndrey Smirnov 548f93f961cSAndrey Smirnov addr = s->tx_descriptor[ring]; 549a699b410SJean-Christophe Dubois 55081f17e0dSPrasad J Pandit while (descnt++ < IMX_MAX_DESC) { 551a699b410SJean-Christophe Dubois IMXENETBufDesc bd; 552a699b410SJean-Christophe Dubois int len; 553a699b410SJean-Christophe Dubois 554a699b410SJean-Christophe Dubois imx_enet_read_bd(&bd, addr); 555a699b410SJean-Christophe Dubois FEC_PRINTF("tx_bd %x flags %04x len %d data %08x option %04x " 556a699b410SJean-Christophe Dubois "status %04x\n", addr, bd.flags, bd.length, bd.data, 557a699b410SJean-Christophe Dubois bd.option, bd.status); 558a699b410SJean-Christophe Dubois if ((bd.flags & ENET_BD_R) == 0) { 559a699b410SJean-Christophe Dubois /* Run out of descriptors to transmit. */ 560a699b410SJean-Christophe Dubois break; 561a699b410SJean-Christophe Dubois } 562a699b410SJean-Christophe Dubois len = bd.length; 563a699b410SJean-Christophe Dubois if (frame_size + len > ENET_MAX_FRAME_SIZE) { 564a699b410SJean-Christophe Dubois len = ENET_MAX_FRAME_SIZE - frame_size; 565a699b410SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_BABT; 566a699b410SJean-Christophe Dubois } 567a699b410SJean-Christophe Dubois dma_memory_read(&address_space_memory, bd.data, ptr, len); 568a699b410SJean-Christophe Dubois ptr += len; 569a699b410SJean-Christophe Dubois frame_size += len; 570a699b410SJean-Christophe Dubois if (bd.flags & ENET_BD_L) { 571a699b410SJean-Christophe Dubois if (bd.option & ENET_BD_PINS) { 5727bac20dcSAndrey Smirnov struct ip_header *ip_hd = PKT_GET_IP_HDR(s->frame); 573a699b410SJean-Christophe Dubois if (IP_HEADER_VERSION(ip_hd) == 4) { 5747bac20dcSAndrey Smirnov net_checksum_calculate(s->frame, frame_size); 575a699b410SJean-Christophe Dubois } 576a699b410SJean-Christophe Dubois } 577a699b410SJean-Christophe Dubois if (bd.option & ENET_BD_IINS) { 5787bac20dcSAndrey Smirnov struct ip_header *ip_hd = PKT_GET_IP_HDR(s->frame); 579a699b410SJean-Christophe Dubois /* We compute checksum only for IPv4 frames */ 580a699b410SJean-Christophe Dubois if (IP_HEADER_VERSION(ip_hd) == 4) { 581a699b410SJean-Christophe Dubois uint16_t csum; 582a699b410SJean-Christophe Dubois ip_hd->ip_sum = 0; 583a699b410SJean-Christophe Dubois csum = net_raw_checksum((uint8_t *)ip_hd, sizeof(*ip_hd)); 584a699b410SJean-Christophe Dubois ip_hd->ip_sum = cpu_to_be16(csum); 585a699b410SJean-Christophe Dubois } 586a699b410SJean-Christophe Dubois } 587a699b410SJean-Christophe Dubois /* Last buffer in frame. */ 5887bac20dcSAndrey Smirnov 58952cfd584SAndrey Smirnov qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size); 5907bac20dcSAndrey Smirnov ptr = s->frame; 5917bac20dcSAndrey Smirnov 592a699b410SJean-Christophe Dubois frame_size = 0; 593a699b410SJean-Christophe Dubois if (bd.option & ENET_BD_TX_INT) { 594f93f961cSAndrey Smirnov s->regs[ENET_EIR] |= int_txf; 595a699b410SJean-Christophe Dubois } 596a699b410SJean-Christophe Dubois } 597a699b410SJean-Christophe Dubois if (bd.option & ENET_BD_TX_INT) { 598f93f961cSAndrey Smirnov s->regs[ENET_EIR] |= int_txb; 599a699b410SJean-Christophe Dubois } 600a699b410SJean-Christophe Dubois bd.flags &= ~ENET_BD_R; 601a699b410SJean-Christophe Dubois /* Write back the modified descriptor. */ 602a699b410SJean-Christophe Dubois imx_enet_write_bd(&bd, addr); 603a699b410SJean-Christophe Dubois /* Advance to the next descriptor. */ 604a699b410SJean-Christophe Dubois if ((bd.flags & ENET_BD_W) != 0) { 605f93f961cSAndrey Smirnov addr = s->regs[tdsr]; 606a699b410SJean-Christophe Dubois } else { 607a699b410SJean-Christophe Dubois addr += sizeof(bd); 608a699b410SJean-Christophe Dubois } 609a699b410SJean-Christophe Dubois } 610a699b410SJean-Christophe Dubois 611f93f961cSAndrey Smirnov s->tx_descriptor[ring] = addr; 612a699b410SJean-Christophe Dubois 613a699b410SJean-Christophe Dubois imx_eth_update(s); 614a699b410SJean-Christophe Dubois } 615a699b410SJean-Christophe Dubois 616f93f961cSAndrey Smirnov static void imx_eth_do_tx(IMXFECState *s, uint32_t index) 617a699b410SJean-Christophe Dubois { 618a699b410SJean-Christophe Dubois if (!s->is_fec && (s->regs[ENET_ECR] & ENET_ECR_EN1588)) { 619f93f961cSAndrey Smirnov imx_enet_do_tx(s, index); 620a699b410SJean-Christophe Dubois } else { 621a699b410SJean-Christophe Dubois imx_fec_do_tx(s); 622a699b410SJean-Christophe Dubois } 623a699b410SJean-Christophe Dubois } 624a699b410SJean-Christophe Dubois 625b2b012afSAndrey Smirnov static void imx_eth_enable_rx(IMXFECState *s, bool flush) 626fcbd8018SJean-Christophe Dubois { 627fcbd8018SJean-Christophe Dubois IMXFECBufDesc bd; 628fcbd8018SJean-Christophe Dubois 629fcbd8018SJean-Christophe Dubois imx_fec_read_bd(&bd, s->rx_descriptor); 630fcbd8018SJean-Christophe Dubois 6311b58d58fSJean-Christophe Dubois s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0; 632fcbd8018SJean-Christophe Dubois 6331b58d58fSJean-Christophe Dubois if (!s->regs[ENET_RDAR]) { 634fcbd8018SJean-Christophe Dubois FEC_PRINTF("RX buffer full\n"); 635b2b012afSAndrey Smirnov } else if (flush) { 636fcbd8018SJean-Christophe Dubois qemu_flush_queued_packets(qemu_get_queue(s->nic)); 637fcbd8018SJean-Christophe Dubois } 638fcbd8018SJean-Christophe Dubois } 639fcbd8018SJean-Christophe Dubois 640a699b410SJean-Christophe Dubois static void imx_eth_reset(DeviceState *d) 641fcbd8018SJean-Christophe Dubois { 642fcbd8018SJean-Christophe Dubois IMXFECState *s = IMX_FEC(d); 643fcbd8018SJean-Christophe Dubois 644a699b410SJean-Christophe Dubois /* Reset the Device */ 645db0de352SJean-Christophe Dubois memset(s->regs, 0, sizeof(s->regs)); 646db0de352SJean-Christophe Dubois s->regs[ENET_ECR] = 0xf0000000; 647db0de352SJean-Christophe Dubois s->regs[ENET_MIBC] = 0xc0000000; 648db0de352SJean-Christophe Dubois s->regs[ENET_RCR] = 0x05ee0001; 649db0de352SJean-Christophe Dubois s->regs[ENET_OPD] = 0x00010000; 650db0de352SJean-Christophe Dubois 651db0de352SJean-Christophe Dubois s->regs[ENET_PALR] = (s->conf.macaddr.a[0] << 24) 652db0de352SJean-Christophe Dubois | (s->conf.macaddr.a[1] << 16) 653db0de352SJean-Christophe Dubois | (s->conf.macaddr.a[2] << 8) 654db0de352SJean-Christophe Dubois | s->conf.macaddr.a[3]; 655db0de352SJean-Christophe Dubois s->regs[ENET_PAUR] = (s->conf.macaddr.a[4] << 24) 656db0de352SJean-Christophe Dubois | (s->conf.macaddr.a[5] << 16) 657db0de352SJean-Christophe Dubois | 0x8808; 658db0de352SJean-Christophe Dubois 659a699b410SJean-Christophe Dubois if (s->is_fec) { 660db0de352SJean-Christophe Dubois s->regs[ENET_FRBR] = 0x00000600; 661db0de352SJean-Christophe Dubois s->regs[ENET_FRSR] = 0x00000500; 662db0de352SJean-Christophe Dubois s->regs[ENET_MIIGSK_ENR] = 0x00000006; 663a699b410SJean-Christophe Dubois } else { 664a699b410SJean-Christophe Dubois s->regs[ENET_RAEM] = 0x00000004; 665a699b410SJean-Christophe Dubois s->regs[ENET_RAFL] = 0x00000004; 666a699b410SJean-Christophe Dubois s->regs[ENET_TAEM] = 0x00000004; 667a699b410SJean-Christophe Dubois s->regs[ENET_TAFL] = 0x00000008; 668a699b410SJean-Christophe Dubois s->regs[ENET_TIPG] = 0x0000000c; 669a699b410SJean-Christophe Dubois s->regs[ENET_FTRL] = 0x000007ff; 670a699b410SJean-Christophe Dubois s->regs[ENET_ATPER] = 0x3b9aca00; 671a699b410SJean-Christophe Dubois } 672db0de352SJean-Christophe Dubois 673db0de352SJean-Christophe Dubois s->rx_descriptor = 0; 674f93f961cSAndrey Smirnov memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); 675fcbd8018SJean-Christophe Dubois 676fcbd8018SJean-Christophe Dubois /* We also reset the PHY */ 677fcbd8018SJean-Christophe Dubois phy_reset(s); 678fcbd8018SJean-Christophe Dubois } 679fcbd8018SJean-Christophe Dubois 680a699b410SJean-Christophe Dubois static uint32_t imx_default_read(IMXFECState *s, uint32_t index) 681a699b410SJean-Christophe Dubois { 682a699b410SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 683a699b410SJean-Christophe Dubois PRIx32 "\n", TYPE_IMX_FEC, __func__, index * 4); 684a699b410SJean-Christophe Dubois return 0; 685a699b410SJean-Christophe Dubois } 686a699b410SJean-Christophe Dubois 687a699b410SJean-Christophe Dubois static uint32_t imx_fec_read(IMXFECState *s, uint32_t index) 688a699b410SJean-Christophe Dubois { 689a699b410SJean-Christophe Dubois switch (index) { 690a699b410SJean-Christophe Dubois case ENET_FRBR: 691a699b410SJean-Christophe Dubois case ENET_FRSR: 692a699b410SJean-Christophe Dubois case ENET_MIIGSK_CFGR: 693a699b410SJean-Christophe Dubois case ENET_MIIGSK_ENR: 694a699b410SJean-Christophe Dubois return s->regs[index]; 695a699b410SJean-Christophe Dubois default: 696a699b410SJean-Christophe Dubois return imx_default_read(s, index); 697a699b410SJean-Christophe Dubois } 698a699b410SJean-Christophe Dubois } 699a699b410SJean-Christophe Dubois 700a699b410SJean-Christophe Dubois static uint32_t imx_enet_read(IMXFECState *s, uint32_t index) 701a699b410SJean-Christophe Dubois { 702a699b410SJean-Christophe Dubois switch (index) { 703a699b410SJean-Christophe Dubois case ENET_RSFL: 704a699b410SJean-Christophe Dubois case ENET_RSEM: 705a699b410SJean-Christophe Dubois case ENET_RAEM: 706a699b410SJean-Christophe Dubois case ENET_RAFL: 707a699b410SJean-Christophe Dubois case ENET_TSEM: 708a699b410SJean-Christophe Dubois case ENET_TAEM: 709a699b410SJean-Christophe Dubois case ENET_TAFL: 710a699b410SJean-Christophe Dubois case ENET_TIPG: 711a699b410SJean-Christophe Dubois case ENET_FTRL: 712a699b410SJean-Christophe Dubois case ENET_TACC: 713a699b410SJean-Christophe Dubois case ENET_RACC: 714a699b410SJean-Christophe Dubois case ENET_ATCR: 715a699b410SJean-Christophe Dubois case ENET_ATVR: 716a699b410SJean-Christophe Dubois case ENET_ATOFF: 717a699b410SJean-Christophe Dubois case ENET_ATPER: 718a699b410SJean-Christophe Dubois case ENET_ATCOR: 719a699b410SJean-Christophe Dubois case ENET_ATINC: 720a699b410SJean-Christophe Dubois case ENET_ATSTMP: 721a699b410SJean-Christophe Dubois case ENET_TGSR: 722a699b410SJean-Christophe Dubois case ENET_TCSR0: 723a699b410SJean-Christophe Dubois case ENET_TCCR0: 724a699b410SJean-Christophe Dubois case ENET_TCSR1: 725a699b410SJean-Christophe Dubois case ENET_TCCR1: 726a699b410SJean-Christophe Dubois case ENET_TCSR2: 727a699b410SJean-Christophe Dubois case ENET_TCCR2: 728a699b410SJean-Christophe Dubois case ENET_TCSR3: 729a699b410SJean-Christophe Dubois case ENET_TCCR3: 730a699b410SJean-Christophe Dubois return s->regs[index]; 731a699b410SJean-Christophe Dubois default: 732a699b410SJean-Christophe Dubois return imx_default_read(s, index); 733a699b410SJean-Christophe Dubois } 734a699b410SJean-Christophe Dubois } 735a699b410SJean-Christophe Dubois 736a699b410SJean-Christophe Dubois static uint64_t imx_eth_read(void *opaque, hwaddr offset, unsigned size) 737fcbd8018SJean-Christophe Dubois { 738db0de352SJean-Christophe Dubois uint32_t value = 0; 739fcbd8018SJean-Christophe Dubois IMXFECState *s = IMX_FEC(opaque); 740a699b410SJean-Christophe Dubois uint32_t index = offset >> 2; 741fcbd8018SJean-Christophe Dubois 742db0de352SJean-Christophe Dubois switch (index) { 743db0de352SJean-Christophe Dubois case ENET_EIR: 744db0de352SJean-Christophe Dubois case ENET_EIMR: 745db0de352SJean-Christophe Dubois case ENET_RDAR: 746db0de352SJean-Christophe Dubois case ENET_TDAR: 747db0de352SJean-Christophe Dubois case ENET_ECR: 748db0de352SJean-Christophe Dubois case ENET_MMFR: 749db0de352SJean-Christophe Dubois case ENET_MSCR: 750db0de352SJean-Christophe Dubois case ENET_MIBC: 751db0de352SJean-Christophe Dubois case ENET_RCR: 752db0de352SJean-Christophe Dubois case ENET_TCR: 753db0de352SJean-Christophe Dubois case ENET_PALR: 754db0de352SJean-Christophe Dubois case ENET_PAUR: 755db0de352SJean-Christophe Dubois case ENET_OPD: 756db0de352SJean-Christophe Dubois case ENET_IAUR: 757db0de352SJean-Christophe Dubois case ENET_IALR: 758db0de352SJean-Christophe Dubois case ENET_GAUR: 759db0de352SJean-Christophe Dubois case ENET_GALR: 760db0de352SJean-Christophe Dubois case ENET_TFWR: 761db0de352SJean-Christophe Dubois case ENET_RDSR: 762db0de352SJean-Christophe Dubois case ENET_TDSR: 763db0de352SJean-Christophe Dubois case ENET_MRBR: 764db0de352SJean-Christophe Dubois value = s->regs[index]; 765fcbd8018SJean-Christophe Dubois break; 766fcbd8018SJean-Christophe Dubois default: 767a699b410SJean-Christophe Dubois if (s->is_fec) { 768a699b410SJean-Christophe Dubois value = imx_fec_read(s, index); 769a699b410SJean-Christophe Dubois } else { 770a699b410SJean-Christophe Dubois value = imx_enet_read(s, index); 771a699b410SJean-Christophe Dubois } 772db0de352SJean-Christophe Dubois break; 773fcbd8018SJean-Christophe Dubois } 774db0de352SJean-Christophe Dubois 775a699b410SJean-Christophe Dubois FEC_PRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_eth_reg_name(s, index), 776db0de352SJean-Christophe Dubois value); 777db0de352SJean-Christophe Dubois 778db0de352SJean-Christophe Dubois return value; 779fcbd8018SJean-Christophe Dubois } 780fcbd8018SJean-Christophe Dubois 781a699b410SJean-Christophe Dubois static void imx_default_write(IMXFECState *s, uint32_t index, uint32_t value) 782a699b410SJean-Christophe Dubois { 783a699b410SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" 784a699b410SJean-Christophe Dubois PRIx32 "\n", TYPE_IMX_FEC, __func__, index * 4); 785a699b410SJean-Christophe Dubois return; 786a699b410SJean-Christophe Dubois } 787a699b410SJean-Christophe Dubois 788a699b410SJean-Christophe Dubois static void imx_fec_write(IMXFECState *s, uint32_t index, uint32_t value) 789a699b410SJean-Christophe Dubois { 790a699b410SJean-Christophe Dubois switch (index) { 791a699b410SJean-Christophe Dubois case ENET_FRBR: 792a699b410SJean-Christophe Dubois /* FRBR is read only */ 793a699b410SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Register FRBR is read only\n", 794a699b410SJean-Christophe Dubois TYPE_IMX_FEC, __func__); 795a699b410SJean-Christophe Dubois break; 796a699b410SJean-Christophe Dubois case ENET_FRSR: 797a699b410SJean-Christophe Dubois s->regs[index] = (value & 0x000003fc) | 0x00000400; 798a699b410SJean-Christophe Dubois break; 799a699b410SJean-Christophe Dubois case ENET_MIIGSK_CFGR: 800a699b410SJean-Christophe Dubois s->regs[index] = value & 0x00000053; 801a699b410SJean-Christophe Dubois break; 802a699b410SJean-Christophe Dubois case ENET_MIIGSK_ENR: 803a699b410SJean-Christophe Dubois s->regs[index] = (value & 0x00000002) ? 0x00000006 : 0; 804a699b410SJean-Christophe Dubois break; 805a699b410SJean-Christophe Dubois default: 806a699b410SJean-Christophe Dubois imx_default_write(s, index, value); 807a699b410SJean-Christophe Dubois break; 808a699b410SJean-Christophe Dubois } 809a699b410SJean-Christophe Dubois } 810a699b410SJean-Christophe Dubois 811a699b410SJean-Christophe Dubois static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value) 812a699b410SJean-Christophe Dubois { 813a699b410SJean-Christophe Dubois switch (index) { 814a699b410SJean-Christophe Dubois case ENET_RSFL: 815a699b410SJean-Christophe Dubois case ENET_RSEM: 816a699b410SJean-Christophe Dubois case ENET_RAEM: 817a699b410SJean-Christophe Dubois case ENET_RAFL: 818a699b410SJean-Christophe Dubois case ENET_TSEM: 819a699b410SJean-Christophe Dubois case ENET_TAEM: 820a699b410SJean-Christophe Dubois case ENET_TAFL: 821a699b410SJean-Christophe Dubois s->regs[index] = value & 0x000001ff; 822a699b410SJean-Christophe Dubois break; 823a699b410SJean-Christophe Dubois case ENET_TIPG: 824a699b410SJean-Christophe Dubois s->regs[index] = value & 0x0000001f; 825a699b410SJean-Christophe Dubois break; 826a699b410SJean-Christophe Dubois case ENET_FTRL: 827a699b410SJean-Christophe Dubois s->regs[index] = value & 0x00003fff; 828a699b410SJean-Christophe Dubois break; 829a699b410SJean-Christophe Dubois case ENET_TACC: 830a699b410SJean-Christophe Dubois s->regs[index] = value & 0x00000019; 831a699b410SJean-Christophe Dubois break; 832a699b410SJean-Christophe Dubois case ENET_RACC: 833a699b410SJean-Christophe Dubois s->regs[index] = value & 0x000000C7; 834a699b410SJean-Christophe Dubois break; 835a699b410SJean-Christophe Dubois case ENET_ATCR: 836a699b410SJean-Christophe Dubois s->regs[index] = value & 0x00002a9d; 837a699b410SJean-Christophe Dubois break; 838a699b410SJean-Christophe Dubois case ENET_ATVR: 839a699b410SJean-Christophe Dubois case ENET_ATOFF: 840a699b410SJean-Christophe Dubois case ENET_ATPER: 841a699b410SJean-Christophe Dubois s->regs[index] = value; 842a699b410SJean-Christophe Dubois break; 843a699b410SJean-Christophe Dubois case ENET_ATSTMP: 844a699b410SJean-Christophe Dubois /* ATSTMP is read only */ 845a699b410SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Register ATSTMP is read only\n", 846a699b410SJean-Christophe Dubois TYPE_IMX_FEC, __func__); 847a699b410SJean-Christophe Dubois break; 848a699b410SJean-Christophe Dubois case ENET_ATCOR: 849a699b410SJean-Christophe Dubois s->regs[index] = value & 0x7fffffff; 850a699b410SJean-Christophe Dubois break; 851a699b410SJean-Christophe Dubois case ENET_ATINC: 852a699b410SJean-Christophe Dubois s->regs[index] = value & 0x00007f7f; 853a699b410SJean-Christophe Dubois break; 854a699b410SJean-Christophe Dubois case ENET_TGSR: 855a699b410SJean-Christophe Dubois /* implement clear timer flag */ 856a699b410SJean-Christophe Dubois value = value & 0x0000000f; 857a699b410SJean-Christophe Dubois break; 858a699b410SJean-Christophe Dubois case ENET_TCSR0: 859a699b410SJean-Christophe Dubois case ENET_TCSR1: 860a699b410SJean-Christophe Dubois case ENET_TCSR2: 861a699b410SJean-Christophe Dubois case ENET_TCSR3: 862a699b410SJean-Christophe Dubois value = value & 0x000000fd; 863a699b410SJean-Christophe Dubois break; 864a699b410SJean-Christophe Dubois case ENET_TCCR0: 865a699b410SJean-Christophe Dubois case ENET_TCCR1: 866a699b410SJean-Christophe Dubois case ENET_TCCR2: 867a699b410SJean-Christophe Dubois case ENET_TCCR3: 868a699b410SJean-Christophe Dubois s->regs[index] = value; 869a699b410SJean-Christophe Dubois break; 870a699b410SJean-Christophe Dubois default: 871a699b410SJean-Christophe Dubois imx_default_write(s, index, value); 872a699b410SJean-Christophe Dubois break; 873a699b410SJean-Christophe Dubois } 874a699b410SJean-Christophe Dubois } 875a699b410SJean-Christophe Dubois 876a699b410SJean-Christophe Dubois static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, 877a699b410SJean-Christophe Dubois unsigned size) 878fcbd8018SJean-Christophe Dubois { 879fcbd8018SJean-Christophe Dubois IMXFECState *s = IMX_FEC(opaque); 880f93f961cSAndrey Smirnov const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s); 881a699b410SJean-Christophe Dubois uint32_t index = offset >> 2; 882fcbd8018SJean-Christophe Dubois 883a699b410SJean-Christophe Dubois FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_eth_reg_name(s, index), 884db0de352SJean-Christophe Dubois (uint32_t)value); 885fcbd8018SJean-Christophe Dubois 886db0de352SJean-Christophe Dubois switch (index) { 887db0de352SJean-Christophe Dubois case ENET_EIR: 888db0de352SJean-Christophe Dubois s->regs[index] &= ~value; 889fcbd8018SJean-Christophe Dubois break; 890db0de352SJean-Christophe Dubois case ENET_EIMR: 891db0de352SJean-Christophe Dubois s->regs[index] = value; 892fcbd8018SJean-Christophe Dubois break; 893db0de352SJean-Christophe Dubois case ENET_RDAR: 894db0de352SJean-Christophe Dubois if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { 895db0de352SJean-Christophe Dubois if (!s->regs[index]) { 896b2b012afSAndrey Smirnov imx_eth_enable_rx(s, true); 897fcbd8018SJean-Christophe Dubois } 898db0de352SJean-Christophe Dubois } else { 899db0de352SJean-Christophe Dubois s->regs[index] = 0; 900db0de352SJean-Christophe Dubois } 901fcbd8018SJean-Christophe Dubois break; 902f93f961cSAndrey Smirnov case ENET_TDAR1: /* FALLTHROUGH */ 903f93f961cSAndrey Smirnov case ENET_TDAR2: /* FALLTHROUGH */ 904f93f961cSAndrey Smirnov if (unlikely(single_tx_ring)) { 905f93f961cSAndrey Smirnov qemu_log_mask(LOG_GUEST_ERROR, 906f93f961cSAndrey Smirnov "[%s]%s: trying to access TDAR2 or TDAR1\n", 907f93f961cSAndrey Smirnov TYPE_IMX_FEC, __func__); 908f93f961cSAndrey Smirnov return; 909f93f961cSAndrey Smirnov } 910f93f961cSAndrey Smirnov case ENET_TDAR: /* FALLTHROUGH */ 911db0de352SJean-Christophe Dubois if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { 912db0de352SJean-Christophe Dubois s->regs[index] = ENET_TDAR_TDAR; 913f93f961cSAndrey Smirnov imx_eth_do_tx(s, index); 914fcbd8018SJean-Christophe Dubois } 915db0de352SJean-Christophe Dubois s->regs[index] = 0; 916fcbd8018SJean-Christophe Dubois break; 917db0de352SJean-Christophe Dubois case ENET_ECR: 9181bb3c371SJean-Christophe Dubois if (value & ENET_ECR_RESET) { 919a699b410SJean-Christophe Dubois return imx_eth_reset(DEVICE(s)); 920fcbd8018SJean-Christophe Dubois } 921db0de352SJean-Christophe Dubois s->regs[index] = value; 922db0de352SJean-Christophe Dubois if ((s->regs[index] & ENET_ECR_ETHEREN) == 0) { 923db0de352SJean-Christophe Dubois s->regs[ENET_RDAR] = 0; 924db0de352SJean-Christophe Dubois s->rx_descriptor = s->regs[ENET_RDSR]; 925db0de352SJean-Christophe Dubois s->regs[ENET_TDAR] = 0; 926f93f961cSAndrey Smirnov s->regs[ENET_TDAR1] = 0; 927f93f961cSAndrey Smirnov s->regs[ENET_TDAR2] = 0; 928f93f961cSAndrey Smirnov s->tx_descriptor[0] = s->regs[ENET_TDSR]; 929f93f961cSAndrey Smirnov s->tx_descriptor[1] = s->regs[ENET_TDSR1]; 930f93f961cSAndrey Smirnov s->tx_descriptor[2] = s->regs[ENET_TDSR2]; 931fcbd8018SJean-Christophe Dubois } 932fcbd8018SJean-Christophe Dubois break; 933db0de352SJean-Christophe Dubois case ENET_MMFR: 934db0de352SJean-Christophe Dubois s->regs[index] = value; 9354816dc16SJean-Christophe Dubois if (extract32(value, 29, 1)) { 936db0de352SJean-Christophe Dubois /* This is a read operation */ 937db0de352SJean-Christophe Dubois s->regs[ENET_MMFR] = deposit32(s->regs[ENET_MMFR], 0, 16, 938db0de352SJean-Christophe Dubois do_phy_read(s, 939db0de352SJean-Christophe Dubois extract32(value, 940db0de352SJean-Christophe Dubois 18, 10))); 9414816dc16SJean-Christophe Dubois } else { 942db0de352SJean-Christophe Dubois /* This a write operation */ 943b413643aSJean-Christophe Dubois do_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); 944fcbd8018SJean-Christophe Dubois } 945fcbd8018SJean-Christophe Dubois /* raise the interrupt as the PHY operation is done */ 946db0de352SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_MII; 947fcbd8018SJean-Christophe Dubois break; 948db0de352SJean-Christophe Dubois case ENET_MSCR: 949db0de352SJean-Christophe Dubois s->regs[index] = value & 0xfe; 950fcbd8018SJean-Christophe Dubois break; 951db0de352SJean-Christophe Dubois case ENET_MIBC: 952fcbd8018SJean-Christophe Dubois /* TODO: Implement MIB. */ 953db0de352SJean-Christophe Dubois s->regs[index] = (value & 0x80000000) ? 0xc0000000 : 0; 954fcbd8018SJean-Christophe Dubois break; 955db0de352SJean-Christophe Dubois case ENET_RCR: 956db0de352SJean-Christophe Dubois s->regs[index] = value & 0x07ff003f; 957fcbd8018SJean-Christophe Dubois /* TODO: Implement LOOP mode. */ 958fcbd8018SJean-Christophe Dubois break; 959db0de352SJean-Christophe Dubois case ENET_TCR: 960fcbd8018SJean-Christophe Dubois /* We transmit immediately, so raise GRA immediately. */ 961db0de352SJean-Christophe Dubois s->regs[index] = value; 962fcbd8018SJean-Christophe Dubois if (value & 1) { 963db0de352SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_GRA; 964fcbd8018SJean-Christophe Dubois } 965fcbd8018SJean-Christophe Dubois break; 966db0de352SJean-Christophe Dubois case ENET_PALR: 967db0de352SJean-Christophe Dubois s->regs[index] = value; 968fcbd8018SJean-Christophe Dubois s->conf.macaddr.a[0] = value >> 24; 969fcbd8018SJean-Christophe Dubois s->conf.macaddr.a[1] = value >> 16; 970fcbd8018SJean-Christophe Dubois s->conf.macaddr.a[2] = value >> 8; 971fcbd8018SJean-Christophe Dubois s->conf.macaddr.a[3] = value; 972fcbd8018SJean-Christophe Dubois break; 973db0de352SJean-Christophe Dubois case ENET_PAUR: 974db0de352SJean-Christophe Dubois s->regs[index] = (value | 0x0000ffff) & 0xffff8808; 975fcbd8018SJean-Christophe Dubois s->conf.macaddr.a[4] = value >> 24; 976fcbd8018SJean-Christophe Dubois s->conf.macaddr.a[5] = value >> 16; 977fcbd8018SJean-Christophe Dubois break; 978db0de352SJean-Christophe Dubois case ENET_OPD: 979db0de352SJean-Christophe Dubois s->regs[index] = (value & 0x0000ffff) | 0x00010000; 980fcbd8018SJean-Christophe Dubois break; 981db0de352SJean-Christophe Dubois case ENET_IAUR: 982db0de352SJean-Christophe Dubois case ENET_IALR: 983db0de352SJean-Christophe Dubois case ENET_GAUR: 984db0de352SJean-Christophe Dubois case ENET_GALR: 985fcbd8018SJean-Christophe Dubois /* TODO: implement MAC hash filtering. */ 986fcbd8018SJean-Christophe Dubois break; 987db0de352SJean-Christophe Dubois case ENET_TFWR: 988a699b410SJean-Christophe Dubois if (s->is_fec) { 989a699b410SJean-Christophe Dubois s->regs[index] = value & 0x3; 990a699b410SJean-Christophe Dubois } else { 991a699b410SJean-Christophe Dubois s->regs[index] = value & 0x13f; 992a699b410SJean-Christophe Dubois } 993fcbd8018SJean-Christophe Dubois break; 994db0de352SJean-Christophe Dubois case ENET_RDSR: 995a699b410SJean-Christophe Dubois if (s->is_fec) { 996db0de352SJean-Christophe Dubois s->regs[index] = value & ~3; 997a699b410SJean-Christophe Dubois } else { 998a699b410SJean-Christophe Dubois s->regs[index] = value & ~7; 999a699b410SJean-Christophe Dubois } 1000db0de352SJean-Christophe Dubois s->rx_descriptor = s->regs[index]; 1001fcbd8018SJean-Christophe Dubois break; 1002db0de352SJean-Christophe Dubois case ENET_TDSR: 1003a699b410SJean-Christophe Dubois if (s->is_fec) { 1004db0de352SJean-Christophe Dubois s->regs[index] = value & ~3; 1005a699b410SJean-Christophe Dubois } else { 1006a699b410SJean-Christophe Dubois s->regs[index] = value & ~7; 1007a699b410SJean-Christophe Dubois } 1008f93f961cSAndrey Smirnov s->tx_descriptor[0] = s->regs[index]; 1009f93f961cSAndrey Smirnov break; 1010f93f961cSAndrey Smirnov case ENET_TDSR1: 1011f93f961cSAndrey Smirnov if (unlikely(single_tx_ring)) { 1012f93f961cSAndrey Smirnov qemu_log_mask(LOG_GUEST_ERROR, 1013f93f961cSAndrey Smirnov "[%s]%s: trying to access TDSR1\n", 1014f93f961cSAndrey Smirnov TYPE_IMX_FEC, __func__); 1015f93f961cSAndrey Smirnov return; 1016f93f961cSAndrey Smirnov } 1017f93f961cSAndrey Smirnov 1018f93f961cSAndrey Smirnov s->regs[index] = value & ~7; 1019f93f961cSAndrey Smirnov s->tx_descriptor[1] = s->regs[index]; 1020f93f961cSAndrey Smirnov break; 1021f93f961cSAndrey Smirnov case ENET_TDSR2: 1022f93f961cSAndrey Smirnov if (unlikely(single_tx_ring)) { 1023f93f961cSAndrey Smirnov qemu_log_mask(LOG_GUEST_ERROR, 1024f93f961cSAndrey Smirnov "[%s]%s: trying to access TDSR2\n", 1025f93f961cSAndrey Smirnov TYPE_IMX_FEC, __func__); 1026f93f961cSAndrey Smirnov return; 1027f93f961cSAndrey Smirnov } 1028f93f961cSAndrey Smirnov 1029f93f961cSAndrey Smirnov s->regs[index] = value & ~7; 1030f93f961cSAndrey Smirnov s->tx_descriptor[2] = s->regs[index]; 1031fcbd8018SJean-Christophe Dubois break; 1032db0de352SJean-Christophe Dubois case ENET_MRBR: 1033a699b410SJean-Christophe Dubois s->regs[index] = value & 0x00003ff0; 1034fcbd8018SJean-Christophe Dubois break; 1035fcbd8018SJean-Christophe Dubois default: 1036a699b410SJean-Christophe Dubois if (s->is_fec) { 1037a699b410SJean-Christophe Dubois imx_fec_write(s, index, value); 1038a699b410SJean-Christophe Dubois } else { 1039a699b410SJean-Christophe Dubois imx_enet_write(s, index, value); 1040a699b410SJean-Christophe Dubois } 1041a699b410SJean-Christophe Dubois return; 1042fcbd8018SJean-Christophe Dubois } 1043fcbd8018SJean-Christophe Dubois 1044a699b410SJean-Christophe Dubois imx_eth_update(s); 1045fcbd8018SJean-Christophe Dubois } 1046fcbd8018SJean-Christophe Dubois 1047a699b410SJean-Christophe Dubois static int imx_eth_can_receive(NetClientState *nc) 1048fcbd8018SJean-Christophe Dubois { 1049fcbd8018SJean-Christophe Dubois IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1050fcbd8018SJean-Christophe Dubois 1051a699b410SJean-Christophe Dubois FEC_PRINTF("\n"); 1052a699b410SJean-Christophe Dubois 1053b2b012afSAndrey Smirnov return !!s->regs[ENET_RDAR]; 1054fcbd8018SJean-Christophe Dubois } 1055fcbd8018SJean-Christophe Dubois 1056fcbd8018SJean-Christophe Dubois static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf, 1057fcbd8018SJean-Christophe Dubois size_t len) 1058fcbd8018SJean-Christophe Dubois { 1059fcbd8018SJean-Christophe Dubois IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1060fcbd8018SJean-Christophe Dubois IMXFECBufDesc bd; 1061fcbd8018SJean-Christophe Dubois uint32_t flags = 0; 1062fcbd8018SJean-Christophe Dubois uint32_t addr; 1063fcbd8018SJean-Christophe Dubois uint32_t crc; 1064fcbd8018SJean-Christophe Dubois uint32_t buf_addr; 1065fcbd8018SJean-Christophe Dubois uint8_t *crc_ptr; 1066fcbd8018SJean-Christophe Dubois unsigned int buf_len; 1067fcbd8018SJean-Christophe Dubois size_t size = len; 1068fcbd8018SJean-Christophe Dubois 1069fcbd8018SJean-Christophe Dubois FEC_PRINTF("len %d\n", (int)size); 1070fcbd8018SJean-Christophe Dubois 1071db0de352SJean-Christophe Dubois if (!s->regs[ENET_RDAR]) { 1072b72d8d25SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", 1073fcbd8018SJean-Christophe Dubois TYPE_IMX_FEC, __func__); 1074fcbd8018SJean-Christophe Dubois return 0; 1075fcbd8018SJean-Christophe Dubois } 1076fcbd8018SJean-Christophe Dubois 1077fcbd8018SJean-Christophe Dubois /* 4 bytes for the CRC. */ 1078fcbd8018SJean-Christophe Dubois size += 4; 1079fcbd8018SJean-Christophe Dubois crc = cpu_to_be32(crc32(~0, buf, size)); 1080fcbd8018SJean-Christophe Dubois crc_ptr = (uint8_t *) &crc; 1081fcbd8018SJean-Christophe Dubois 1082a699b410SJean-Christophe Dubois /* Huge frames are truncated. */ 10831bb3c371SJean-Christophe Dubois if (size > ENET_MAX_FRAME_SIZE) { 10841bb3c371SJean-Christophe Dubois size = ENET_MAX_FRAME_SIZE; 10851bb3c371SJean-Christophe Dubois flags |= ENET_BD_TR | ENET_BD_LG; 1086fcbd8018SJean-Christophe Dubois } 1087fcbd8018SJean-Christophe Dubois 1088fcbd8018SJean-Christophe Dubois /* Frames larger than the user limit just set error flags. */ 1089db0de352SJean-Christophe Dubois if (size > (s->regs[ENET_RCR] >> 16)) { 10901bb3c371SJean-Christophe Dubois flags |= ENET_BD_LG; 1091fcbd8018SJean-Christophe Dubois } 1092fcbd8018SJean-Christophe Dubois 1093fcbd8018SJean-Christophe Dubois addr = s->rx_descriptor; 1094fcbd8018SJean-Christophe Dubois while (size > 0) { 1095fcbd8018SJean-Christophe Dubois imx_fec_read_bd(&bd, addr); 10961bb3c371SJean-Christophe Dubois if ((bd.flags & ENET_BD_E) == 0) { 1097fcbd8018SJean-Christophe Dubois /* No descriptors available. Bail out. */ 1098fcbd8018SJean-Christophe Dubois /* 1099fcbd8018SJean-Christophe Dubois * FIXME: This is wrong. We should probably either 1100fcbd8018SJean-Christophe Dubois * save the remainder for when more RX buffers are 1101fcbd8018SJean-Christophe Dubois * available, or flag an error. 1102fcbd8018SJean-Christophe Dubois */ 1103b72d8d25SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Lost end of frame\n", 1104fcbd8018SJean-Christophe Dubois TYPE_IMX_FEC, __func__); 1105fcbd8018SJean-Christophe Dubois break; 1106fcbd8018SJean-Christophe Dubois } 1107db0de352SJean-Christophe Dubois buf_len = (size <= s->regs[ENET_MRBR]) ? size : s->regs[ENET_MRBR]; 1108fcbd8018SJean-Christophe Dubois bd.length = buf_len; 1109fcbd8018SJean-Christophe Dubois size -= buf_len; 1110b72d8d25SJean-Christophe Dubois 1111b72d8d25SJean-Christophe Dubois FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length); 1112b72d8d25SJean-Christophe Dubois 1113fcbd8018SJean-Christophe Dubois /* The last 4 bytes are the CRC. */ 1114fcbd8018SJean-Christophe Dubois if (size < 4) { 1115fcbd8018SJean-Christophe Dubois buf_len += size - 4; 1116fcbd8018SJean-Christophe Dubois } 1117fcbd8018SJean-Christophe Dubois buf_addr = bd.data; 1118fcbd8018SJean-Christophe Dubois dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); 1119fcbd8018SJean-Christophe Dubois buf += buf_len; 1120fcbd8018SJean-Christophe Dubois if (size < 4) { 1121fcbd8018SJean-Christophe Dubois dma_memory_write(&address_space_memory, buf_addr + buf_len, 1122fcbd8018SJean-Christophe Dubois crc_ptr, 4 - size); 1123fcbd8018SJean-Christophe Dubois crc_ptr += 4 - size; 1124fcbd8018SJean-Christophe Dubois } 11251bb3c371SJean-Christophe Dubois bd.flags &= ~ENET_BD_E; 1126fcbd8018SJean-Christophe Dubois if (size == 0) { 1127fcbd8018SJean-Christophe Dubois /* Last buffer in frame. */ 11281bb3c371SJean-Christophe Dubois bd.flags |= flags | ENET_BD_L; 1129fcbd8018SJean-Christophe Dubois FEC_PRINTF("rx frame flags %04x\n", bd.flags); 1130db0de352SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_RXF; 1131fcbd8018SJean-Christophe Dubois } else { 1132db0de352SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_RXB; 1133fcbd8018SJean-Christophe Dubois } 1134fcbd8018SJean-Christophe Dubois imx_fec_write_bd(&bd, addr); 1135fcbd8018SJean-Christophe Dubois /* Advance to the next descriptor. */ 11361bb3c371SJean-Christophe Dubois if ((bd.flags & ENET_BD_W) != 0) { 1137db0de352SJean-Christophe Dubois addr = s->regs[ENET_RDSR]; 1138fcbd8018SJean-Christophe Dubois } else { 1139db0de352SJean-Christophe Dubois addr += sizeof(bd); 1140fcbd8018SJean-Christophe Dubois } 1141fcbd8018SJean-Christophe Dubois } 1142fcbd8018SJean-Christophe Dubois s->rx_descriptor = addr; 1143b2b012afSAndrey Smirnov imx_eth_enable_rx(s, false); 1144a699b410SJean-Christophe Dubois imx_eth_update(s); 1145fcbd8018SJean-Christophe Dubois return len; 1146fcbd8018SJean-Christophe Dubois } 1147fcbd8018SJean-Christophe Dubois 1148a699b410SJean-Christophe Dubois static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, 1149a699b410SJean-Christophe Dubois size_t len) 1150a699b410SJean-Christophe Dubois { 1151a699b410SJean-Christophe Dubois IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1152a699b410SJean-Christophe Dubois IMXENETBufDesc bd; 1153a699b410SJean-Christophe Dubois uint32_t flags = 0; 1154a699b410SJean-Christophe Dubois uint32_t addr; 1155a699b410SJean-Christophe Dubois uint32_t crc; 1156a699b410SJean-Christophe Dubois uint32_t buf_addr; 1157a699b410SJean-Christophe Dubois uint8_t *crc_ptr; 1158a699b410SJean-Christophe Dubois unsigned int buf_len; 1159a699b410SJean-Christophe Dubois size_t size = len; 1160ebdd8cddSAndrey Smirnov bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; 1161a699b410SJean-Christophe Dubois 1162a699b410SJean-Christophe Dubois FEC_PRINTF("len %d\n", (int)size); 1163a699b410SJean-Christophe Dubois 1164a699b410SJean-Christophe Dubois if (!s->regs[ENET_RDAR]) { 1165a699b410SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n", 1166a699b410SJean-Christophe Dubois TYPE_IMX_FEC, __func__); 1167a699b410SJean-Christophe Dubois return 0; 1168a699b410SJean-Christophe Dubois } 1169a699b410SJean-Christophe Dubois 1170a699b410SJean-Christophe Dubois /* 4 bytes for the CRC. */ 1171a699b410SJean-Christophe Dubois size += 4; 1172a699b410SJean-Christophe Dubois crc = cpu_to_be32(crc32(~0, buf, size)); 1173a699b410SJean-Christophe Dubois crc_ptr = (uint8_t *) &crc; 1174a699b410SJean-Christophe Dubois 1175ebdd8cddSAndrey Smirnov if (shift16) { 1176ebdd8cddSAndrey Smirnov size += 2; 1177ebdd8cddSAndrey Smirnov } 1178ebdd8cddSAndrey Smirnov 1179894d74ccSAndrey Smirnov /* Huge frames are truncated. */ 1180ff9a7feeSAndrey Smirnov if (size > s->regs[ENET_FTRL]) { 1181ff9a7feeSAndrey Smirnov size = s->regs[ENET_FTRL]; 1182a699b410SJean-Christophe Dubois flags |= ENET_BD_TR | ENET_BD_LG; 1183a699b410SJean-Christophe Dubois } 1184a699b410SJean-Christophe Dubois 1185a699b410SJean-Christophe Dubois /* Frames larger than the user limit just set error flags. */ 1186a699b410SJean-Christophe Dubois if (size > (s->regs[ENET_RCR] >> 16)) { 1187a699b410SJean-Christophe Dubois flags |= ENET_BD_LG; 1188a699b410SJean-Christophe Dubois } 1189a699b410SJean-Christophe Dubois 1190a699b410SJean-Christophe Dubois addr = s->rx_descriptor; 1191a699b410SJean-Christophe Dubois while (size > 0) { 1192a699b410SJean-Christophe Dubois imx_enet_read_bd(&bd, addr); 1193a699b410SJean-Christophe Dubois if ((bd.flags & ENET_BD_E) == 0) { 1194a699b410SJean-Christophe Dubois /* No descriptors available. Bail out. */ 1195a699b410SJean-Christophe Dubois /* 1196a699b410SJean-Christophe Dubois * FIXME: This is wrong. We should probably either 1197a699b410SJean-Christophe Dubois * save the remainder for when more RX buffers are 1198a699b410SJean-Christophe Dubois * available, or flag an error. 1199a699b410SJean-Christophe Dubois */ 1200a699b410SJean-Christophe Dubois qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Lost end of frame\n", 1201a699b410SJean-Christophe Dubois TYPE_IMX_FEC, __func__); 1202a699b410SJean-Christophe Dubois break; 1203a699b410SJean-Christophe Dubois } 12044c5e7a6cSAndrey Smirnov buf_len = MIN(size, s->regs[ENET_MRBR]); 1205a699b410SJean-Christophe Dubois bd.length = buf_len; 1206a699b410SJean-Christophe Dubois size -= buf_len; 1207a699b410SJean-Christophe Dubois 1208a699b410SJean-Christophe Dubois FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length); 1209a699b410SJean-Christophe Dubois 1210a699b410SJean-Christophe Dubois /* The last 4 bytes are the CRC. */ 1211a699b410SJean-Christophe Dubois if (size < 4) { 1212a699b410SJean-Christophe Dubois buf_len += size - 4; 1213a699b410SJean-Christophe Dubois } 1214a699b410SJean-Christophe Dubois buf_addr = bd.data; 1215ebdd8cddSAndrey Smirnov 1216ebdd8cddSAndrey Smirnov if (shift16) { 1217ebdd8cddSAndrey Smirnov /* 1218ebdd8cddSAndrey Smirnov * If SHIFT16 bit of ENETx_RACC register is set we need to 1219ebdd8cddSAndrey Smirnov * align the payload to 4-byte boundary. 1220ebdd8cddSAndrey Smirnov */ 1221ebdd8cddSAndrey Smirnov const uint8_t zeros[2] = { 0 }; 1222ebdd8cddSAndrey Smirnov 1223ebdd8cddSAndrey Smirnov dma_memory_write(&address_space_memory, buf_addr, 1224ebdd8cddSAndrey Smirnov zeros, sizeof(zeros)); 1225ebdd8cddSAndrey Smirnov 1226ebdd8cddSAndrey Smirnov buf_addr += sizeof(zeros); 1227ebdd8cddSAndrey Smirnov buf_len -= sizeof(zeros); 1228ebdd8cddSAndrey Smirnov 1229ebdd8cddSAndrey Smirnov /* We only do this once per Ethernet frame */ 1230ebdd8cddSAndrey Smirnov shift16 = false; 1231ebdd8cddSAndrey Smirnov } 1232ebdd8cddSAndrey Smirnov 1233a699b410SJean-Christophe Dubois dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); 1234a699b410SJean-Christophe Dubois buf += buf_len; 1235a699b410SJean-Christophe Dubois if (size < 4) { 1236a699b410SJean-Christophe Dubois dma_memory_write(&address_space_memory, buf_addr + buf_len, 1237a699b410SJean-Christophe Dubois crc_ptr, 4 - size); 1238a699b410SJean-Christophe Dubois crc_ptr += 4 - size; 1239a699b410SJean-Christophe Dubois } 1240a699b410SJean-Christophe Dubois bd.flags &= ~ENET_BD_E; 1241a699b410SJean-Christophe Dubois if (size == 0) { 1242a699b410SJean-Christophe Dubois /* Last buffer in frame. */ 1243a699b410SJean-Christophe Dubois bd.flags |= flags | ENET_BD_L; 1244a699b410SJean-Christophe Dubois FEC_PRINTF("rx frame flags %04x\n", bd.flags); 1245a699b410SJean-Christophe Dubois if (bd.option & ENET_BD_RX_INT) { 1246a699b410SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_RXF; 1247a699b410SJean-Christophe Dubois } 1248a699b410SJean-Christophe Dubois } else { 1249a699b410SJean-Christophe Dubois if (bd.option & ENET_BD_RX_INT) { 1250a699b410SJean-Christophe Dubois s->regs[ENET_EIR] |= ENET_INT_RXB; 1251a699b410SJean-Christophe Dubois } 1252a699b410SJean-Christophe Dubois } 1253a699b410SJean-Christophe Dubois imx_enet_write_bd(&bd, addr); 1254a699b410SJean-Christophe Dubois /* Advance to the next descriptor. */ 1255a699b410SJean-Christophe Dubois if ((bd.flags & ENET_BD_W) != 0) { 1256a699b410SJean-Christophe Dubois addr = s->regs[ENET_RDSR]; 1257a699b410SJean-Christophe Dubois } else { 1258a699b410SJean-Christophe Dubois addr += sizeof(bd); 1259a699b410SJean-Christophe Dubois } 1260a699b410SJean-Christophe Dubois } 1261a699b410SJean-Christophe Dubois s->rx_descriptor = addr; 1262b2b012afSAndrey Smirnov imx_eth_enable_rx(s, false); 1263a699b410SJean-Christophe Dubois imx_eth_update(s); 1264a699b410SJean-Christophe Dubois return len; 1265a699b410SJean-Christophe Dubois } 1266a699b410SJean-Christophe Dubois 1267a699b410SJean-Christophe Dubois static ssize_t imx_eth_receive(NetClientState *nc, const uint8_t *buf, 1268a699b410SJean-Christophe Dubois size_t len) 1269a699b410SJean-Christophe Dubois { 1270a699b410SJean-Christophe Dubois IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1271a699b410SJean-Christophe Dubois 1272a699b410SJean-Christophe Dubois if (!s->is_fec && (s->regs[ENET_ECR] & ENET_ECR_EN1588)) { 1273a699b410SJean-Christophe Dubois return imx_enet_receive(nc, buf, len); 1274a699b410SJean-Christophe Dubois } else { 1275a699b410SJean-Christophe Dubois return imx_fec_receive(nc, buf, len); 1276a699b410SJean-Christophe Dubois } 1277a699b410SJean-Christophe Dubois } 1278a699b410SJean-Christophe Dubois 1279a699b410SJean-Christophe Dubois static const MemoryRegionOps imx_eth_ops = { 1280a699b410SJean-Christophe Dubois .read = imx_eth_read, 1281a699b410SJean-Christophe Dubois .write = imx_eth_write, 1282fcbd8018SJean-Christophe Dubois .valid.min_access_size = 4, 1283fcbd8018SJean-Christophe Dubois .valid.max_access_size = 4, 1284fcbd8018SJean-Christophe Dubois .endianness = DEVICE_NATIVE_ENDIAN, 1285fcbd8018SJean-Christophe Dubois }; 1286fcbd8018SJean-Christophe Dubois 1287a699b410SJean-Christophe Dubois static void imx_eth_cleanup(NetClientState *nc) 1288fcbd8018SJean-Christophe Dubois { 1289fcbd8018SJean-Christophe Dubois IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc)); 1290fcbd8018SJean-Christophe Dubois 1291fcbd8018SJean-Christophe Dubois s->nic = NULL; 1292fcbd8018SJean-Christophe Dubois } 1293fcbd8018SJean-Christophe Dubois 1294a699b410SJean-Christophe Dubois static NetClientInfo imx_eth_net_info = { 1295f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 1296fcbd8018SJean-Christophe Dubois .size = sizeof(NICState), 1297a699b410SJean-Christophe Dubois .can_receive = imx_eth_can_receive, 1298a699b410SJean-Christophe Dubois .receive = imx_eth_receive, 1299a699b410SJean-Christophe Dubois .cleanup = imx_eth_cleanup, 1300a699b410SJean-Christophe Dubois .link_status_changed = imx_eth_set_link, 1301fcbd8018SJean-Christophe Dubois }; 1302fcbd8018SJean-Christophe Dubois 1303fcbd8018SJean-Christophe Dubois 1304a699b410SJean-Christophe Dubois static void imx_eth_realize(DeviceState *dev, Error **errp) 1305fcbd8018SJean-Christophe Dubois { 1306fcbd8018SJean-Christophe Dubois IMXFECState *s = IMX_FEC(dev); 1307fcbd8018SJean-Christophe Dubois SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1308fcbd8018SJean-Christophe Dubois 1309a699b410SJean-Christophe Dubois memory_region_init_io(&s->iomem, OBJECT(dev), &imx_eth_ops, s, 1310831858adSAndrey Smirnov TYPE_IMX_FEC, FSL_IMX25_FEC_SIZE); 1311fcbd8018SJean-Christophe Dubois sysbus_init_mmio(sbd, &s->iomem); 1312a699b410SJean-Christophe Dubois sysbus_init_irq(sbd, &s->irq[0]); 1313a699b410SJean-Christophe Dubois sysbus_init_irq(sbd, &s->irq[1]); 1314a699b410SJean-Christophe Dubois 1315fcbd8018SJean-Christophe Dubois qemu_macaddr_default_if_unset(&s->conf.macaddr); 1316fcbd8018SJean-Christophe Dubois 1317a699b410SJean-Christophe Dubois s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf, 1318a699b410SJean-Christophe Dubois object_get_typename(OBJECT(dev)), 1319a699b410SJean-Christophe Dubois DEVICE(dev)->id, s); 1320a699b410SJean-Christophe Dubois 1321fcbd8018SJean-Christophe Dubois qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 1322fcbd8018SJean-Christophe Dubois } 1323fcbd8018SJean-Christophe Dubois 1324a699b410SJean-Christophe Dubois static Property imx_eth_properties[] = { 1325fcbd8018SJean-Christophe Dubois DEFINE_NIC_PROPERTIES(IMXFECState, conf), 1326f93f961cSAndrey Smirnov DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1), 1327fcbd8018SJean-Christophe Dubois DEFINE_PROP_END_OF_LIST(), 1328fcbd8018SJean-Christophe Dubois }; 1329fcbd8018SJean-Christophe Dubois 1330a699b410SJean-Christophe Dubois static void imx_eth_class_init(ObjectClass *klass, void *data) 1331fcbd8018SJean-Christophe Dubois { 1332fcbd8018SJean-Christophe Dubois DeviceClass *dc = DEVICE_CLASS(klass); 1333fcbd8018SJean-Christophe Dubois 1334a699b410SJean-Christophe Dubois dc->vmsd = &vmstate_imx_eth; 1335a699b410SJean-Christophe Dubois dc->reset = imx_eth_reset; 1336a699b410SJean-Christophe Dubois dc->props = imx_eth_properties; 1337a699b410SJean-Christophe Dubois dc->realize = imx_eth_realize; 1338a699b410SJean-Christophe Dubois dc->desc = "i.MX FEC/ENET Ethernet Controller"; 1339a699b410SJean-Christophe Dubois } 1340a699b410SJean-Christophe Dubois 1341a699b410SJean-Christophe Dubois static void imx_fec_init(Object *obj) 1342a699b410SJean-Christophe Dubois { 1343a699b410SJean-Christophe Dubois IMXFECState *s = IMX_FEC(obj); 1344a699b410SJean-Christophe Dubois 1345a699b410SJean-Christophe Dubois s->is_fec = true; 1346a699b410SJean-Christophe Dubois } 1347a699b410SJean-Christophe Dubois 1348a699b410SJean-Christophe Dubois static void imx_enet_init(Object *obj) 1349a699b410SJean-Christophe Dubois { 1350a699b410SJean-Christophe Dubois IMXFECState *s = IMX_FEC(obj); 1351a699b410SJean-Christophe Dubois 1352a699b410SJean-Christophe Dubois s->is_fec = false; 1353fcbd8018SJean-Christophe Dubois } 1354fcbd8018SJean-Christophe Dubois 1355fcbd8018SJean-Christophe Dubois static const TypeInfo imx_fec_info = { 1356fcbd8018SJean-Christophe Dubois .name = TYPE_IMX_FEC, 1357fcbd8018SJean-Christophe Dubois .parent = TYPE_SYS_BUS_DEVICE, 1358fcbd8018SJean-Christophe Dubois .instance_size = sizeof(IMXFECState), 1359a699b410SJean-Christophe Dubois .instance_init = imx_fec_init, 1360a699b410SJean-Christophe Dubois .class_init = imx_eth_class_init, 1361fcbd8018SJean-Christophe Dubois }; 1362fcbd8018SJean-Christophe Dubois 1363a699b410SJean-Christophe Dubois static const TypeInfo imx_enet_info = { 1364a699b410SJean-Christophe Dubois .name = TYPE_IMX_ENET, 1365a699b410SJean-Christophe Dubois .parent = TYPE_IMX_FEC, 1366a699b410SJean-Christophe Dubois .instance_init = imx_enet_init, 1367a699b410SJean-Christophe Dubois }; 1368a699b410SJean-Christophe Dubois 1369a699b410SJean-Christophe Dubois static void imx_eth_register_types(void) 1370fcbd8018SJean-Christophe Dubois { 1371fcbd8018SJean-Christophe Dubois type_register_static(&imx_fec_info); 1372a699b410SJean-Christophe Dubois type_register_static(&imx_enet_info); 1373fcbd8018SJean-Christophe Dubois } 1374fcbd8018SJean-Christophe Dubois 1375a699b410SJean-Christophe Dubois type_init(imx_eth_register_types) 1376