149ab747fSPaolo Bonzini /* 249ab747fSPaolo Bonzini * QEMU AMD PC-Net II (Am79C970A) PCI emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2004 Antony T Curtis 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 2549ab747fSPaolo Bonzini /* This software was written to be compatible with the specification: 2649ab747fSPaolo Bonzini * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet 2749ab747fSPaolo Bonzini * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 2849ab747fSPaolo Bonzini */ 2949ab747fSPaolo Bonzini 3049ab747fSPaolo Bonzini #include "hw/pci/pci.h" 3149ab747fSPaolo Bonzini #include "net/net.h" 3249ab747fSPaolo Bonzini #include "hw/loader.h" 3349ab747fSPaolo Bonzini #include "qemu/timer.h" 3449ab747fSPaolo Bonzini #include "sysemu/dma.h" 3549ab747fSPaolo Bonzini 3647b43a1fSPaolo Bonzini #include "pcnet.h" 3749ab747fSPaolo Bonzini 3849ab747fSPaolo Bonzini //#define PCNET_DEBUG 3949ab747fSPaolo Bonzini //#define PCNET_DEBUG_IO 4049ab747fSPaolo Bonzini //#define PCNET_DEBUG_BCR 4149ab747fSPaolo Bonzini //#define PCNET_DEBUG_CSR 4249ab747fSPaolo Bonzini //#define PCNET_DEBUG_RMD 4349ab747fSPaolo Bonzini //#define PCNET_DEBUG_TMD 4449ab747fSPaolo Bonzini //#define PCNET_DEBUG_MATCH 4549ab747fSPaolo Bonzini 461f8c7946SPeter Crosthwaite #define TYPE_PCI_PCNET "pcnet" 471f8c7946SPeter Crosthwaite 481f8c7946SPeter Crosthwaite #define PCI_PCNET(obj) \ 491f8c7946SPeter Crosthwaite OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET) 5049ab747fSPaolo Bonzini 5149ab747fSPaolo Bonzini typedef struct { 521f8c7946SPeter Crosthwaite /*< private >*/ 531f8c7946SPeter Crosthwaite PCIDevice parent_obj; 541f8c7946SPeter Crosthwaite /*< public >*/ 551f8c7946SPeter Crosthwaite 5649ab747fSPaolo Bonzini PCNetState state; 5749ab747fSPaolo Bonzini MemoryRegion io_bar; 5849ab747fSPaolo Bonzini } PCIPCNetState; 5949ab747fSPaolo Bonzini 6049ab747fSPaolo Bonzini static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) 6149ab747fSPaolo Bonzini { 6249ab747fSPaolo Bonzini PCNetState *s = opaque; 6349ab747fSPaolo Bonzini #ifdef PCNET_DEBUG 6449ab747fSPaolo Bonzini printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val); 6549ab747fSPaolo Bonzini #endif 6649ab747fSPaolo Bonzini if (BCR_APROMWE(s)) { 6749ab747fSPaolo Bonzini s->prom[addr & 15] = val; 6849ab747fSPaolo Bonzini } 6949ab747fSPaolo Bonzini } 7049ab747fSPaolo Bonzini 7149ab747fSPaolo Bonzini static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr) 7249ab747fSPaolo Bonzini { 7349ab747fSPaolo Bonzini PCNetState *s = opaque; 7449ab747fSPaolo Bonzini uint32_t val = s->prom[addr & 15]; 7549ab747fSPaolo Bonzini #ifdef PCNET_DEBUG 7649ab747fSPaolo Bonzini printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val); 7749ab747fSPaolo Bonzini #endif 7849ab747fSPaolo Bonzini return val; 7949ab747fSPaolo Bonzini } 8049ab747fSPaolo Bonzini 8149ab747fSPaolo Bonzini static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr, 8249ab747fSPaolo Bonzini unsigned size) 8349ab747fSPaolo Bonzini { 8449ab747fSPaolo Bonzini PCNetState *d = opaque; 8549ab747fSPaolo Bonzini 8649ab747fSPaolo Bonzini if (addr < 0x10) { 8749ab747fSPaolo Bonzini if (!BCR_DWIO(d) && size == 1) { 8849ab747fSPaolo Bonzini return pcnet_aprom_readb(d, addr); 8949ab747fSPaolo Bonzini } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 9049ab747fSPaolo Bonzini return pcnet_aprom_readb(d, addr) | 9149ab747fSPaolo Bonzini (pcnet_aprom_readb(d, addr + 1) << 8); 9249ab747fSPaolo Bonzini } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 9349ab747fSPaolo Bonzini return pcnet_aprom_readb(d, addr) | 9449ab747fSPaolo Bonzini (pcnet_aprom_readb(d, addr + 1) << 8) | 9549ab747fSPaolo Bonzini (pcnet_aprom_readb(d, addr + 2) << 16) | 9649ab747fSPaolo Bonzini (pcnet_aprom_readb(d, addr + 3) << 24); 9749ab747fSPaolo Bonzini } 9849ab747fSPaolo Bonzini } else { 9949ab747fSPaolo Bonzini if (size == 2) { 10049ab747fSPaolo Bonzini return pcnet_ioport_readw(d, addr); 10149ab747fSPaolo Bonzini } else if (size == 4) { 10249ab747fSPaolo Bonzini return pcnet_ioport_readl(d, addr); 10349ab747fSPaolo Bonzini } 10449ab747fSPaolo Bonzini } 10549ab747fSPaolo Bonzini return ((uint64_t)1 << (size * 8)) - 1; 10649ab747fSPaolo Bonzini } 10749ab747fSPaolo Bonzini 10849ab747fSPaolo Bonzini static void pcnet_ioport_write(void *opaque, hwaddr addr, 10949ab747fSPaolo Bonzini uint64_t data, unsigned size) 11049ab747fSPaolo Bonzini { 11149ab747fSPaolo Bonzini PCNetState *d = opaque; 11249ab747fSPaolo Bonzini 11349ab747fSPaolo Bonzini if (addr < 0x10) { 11449ab747fSPaolo Bonzini if (!BCR_DWIO(d) && size == 1) { 11549ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr, data); 11649ab747fSPaolo Bonzini } else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) { 11749ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr, data & 0xff); 11849ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr + 1, data >> 8); 11949ab747fSPaolo Bonzini } else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) { 12049ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr, data & 0xff); 12149ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff); 12249ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff); 12349ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr + 3, data >> 24); 12449ab747fSPaolo Bonzini } 12549ab747fSPaolo Bonzini } else { 12649ab747fSPaolo Bonzini if (size == 2) { 12749ab747fSPaolo Bonzini pcnet_ioport_writew(d, addr, data); 12849ab747fSPaolo Bonzini } else if (size == 4) { 12949ab747fSPaolo Bonzini pcnet_ioport_writel(d, addr, data); 13049ab747fSPaolo Bonzini } 13149ab747fSPaolo Bonzini } 13249ab747fSPaolo Bonzini } 13349ab747fSPaolo Bonzini 13449ab747fSPaolo Bonzini static const MemoryRegionOps pcnet_io_ops = { 13549ab747fSPaolo Bonzini .read = pcnet_ioport_read, 13649ab747fSPaolo Bonzini .write = pcnet_ioport_write, 13749ab747fSPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 13849ab747fSPaolo Bonzini }; 13949ab747fSPaolo Bonzini 14049ab747fSPaolo Bonzini static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) 14149ab747fSPaolo Bonzini { 14249ab747fSPaolo Bonzini PCNetState *d = opaque; 14349ab747fSPaolo Bonzini #ifdef PCNET_DEBUG_IO 14449ab747fSPaolo Bonzini printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr, 14549ab747fSPaolo Bonzini val); 14649ab747fSPaolo Bonzini #endif 14749ab747fSPaolo Bonzini if (!(addr & 0x10)) 14849ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr & 0x0f, val); 14949ab747fSPaolo Bonzini } 15049ab747fSPaolo Bonzini 15149ab747fSPaolo Bonzini static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr) 15249ab747fSPaolo Bonzini { 15349ab747fSPaolo Bonzini PCNetState *d = opaque; 15449ab747fSPaolo Bonzini uint32_t val = -1; 15549ab747fSPaolo Bonzini if (!(addr & 0x10)) 15649ab747fSPaolo Bonzini val = pcnet_aprom_readb(d, addr & 0x0f); 15749ab747fSPaolo Bonzini #ifdef PCNET_DEBUG_IO 15849ab747fSPaolo Bonzini printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, 15949ab747fSPaolo Bonzini val & 0xff); 16049ab747fSPaolo Bonzini #endif 16149ab747fSPaolo Bonzini return val; 16249ab747fSPaolo Bonzini } 16349ab747fSPaolo Bonzini 16449ab747fSPaolo Bonzini static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val) 16549ab747fSPaolo Bonzini { 16649ab747fSPaolo Bonzini PCNetState *d = opaque; 16749ab747fSPaolo Bonzini #ifdef PCNET_DEBUG_IO 16849ab747fSPaolo Bonzini printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, 16949ab747fSPaolo Bonzini val); 17049ab747fSPaolo Bonzini #endif 17149ab747fSPaolo Bonzini if (addr & 0x10) 17249ab747fSPaolo Bonzini pcnet_ioport_writew(d, addr & 0x0f, val); 17349ab747fSPaolo Bonzini else { 17449ab747fSPaolo Bonzini addr &= 0x0f; 17549ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr, val & 0xff); 17649ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); 17749ab747fSPaolo Bonzini } 17849ab747fSPaolo Bonzini } 17949ab747fSPaolo Bonzini 18049ab747fSPaolo Bonzini static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr) 18149ab747fSPaolo Bonzini { 18249ab747fSPaolo Bonzini PCNetState *d = opaque; 18349ab747fSPaolo Bonzini uint32_t val = -1; 18449ab747fSPaolo Bonzini if (addr & 0x10) 18549ab747fSPaolo Bonzini val = pcnet_ioport_readw(d, addr & 0x0f); 18649ab747fSPaolo Bonzini else { 18749ab747fSPaolo Bonzini addr &= 0x0f; 18849ab747fSPaolo Bonzini val = pcnet_aprom_readb(d, addr+1); 18949ab747fSPaolo Bonzini val <<= 8; 19049ab747fSPaolo Bonzini val |= pcnet_aprom_readb(d, addr); 19149ab747fSPaolo Bonzini } 19249ab747fSPaolo Bonzini #ifdef PCNET_DEBUG_IO 19349ab747fSPaolo Bonzini printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr, 19449ab747fSPaolo Bonzini val & 0xffff); 19549ab747fSPaolo Bonzini #endif 19649ab747fSPaolo Bonzini return val; 19749ab747fSPaolo Bonzini } 19849ab747fSPaolo Bonzini 19949ab747fSPaolo Bonzini static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val) 20049ab747fSPaolo Bonzini { 20149ab747fSPaolo Bonzini PCNetState *d = opaque; 20249ab747fSPaolo Bonzini #ifdef PCNET_DEBUG_IO 20349ab747fSPaolo Bonzini printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr, 20449ab747fSPaolo Bonzini val); 20549ab747fSPaolo Bonzini #endif 20649ab747fSPaolo Bonzini if (addr & 0x10) 20749ab747fSPaolo Bonzini pcnet_ioport_writel(d, addr & 0x0f, val); 20849ab747fSPaolo Bonzini else { 20949ab747fSPaolo Bonzini addr &= 0x0f; 21049ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr, val & 0xff); 21149ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8); 21249ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16); 21349ab747fSPaolo Bonzini pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24); 21449ab747fSPaolo Bonzini } 21549ab747fSPaolo Bonzini } 21649ab747fSPaolo Bonzini 21749ab747fSPaolo Bonzini static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr) 21849ab747fSPaolo Bonzini { 21949ab747fSPaolo Bonzini PCNetState *d = opaque; 22049ab747fSPaolo Bonzini uint32_t val; 22149ab747fSPaolo Bonzini if (addr & 0x10) 22249ab747fSPaolo Bonzini val = pcnet_ioport_readl(d, addr & 0x0f); 22349ab747fSPaolo Bonzini else { 22449ab747fSPaolo Bonzini addr &= 0x0f; 22549ab747fSPaolo Bonzini val = pcnet_aprom_readb(d, addr+3); 22649ab747fSPaolo Bonzini val <<= 8; 22749ab747fSPaolo Bonzini val |= pcnet_aprom_readb(d, addr+2); 22849ab747fSPaolo Bonzini val <<= 8; 22949ab747fSPaolo Bonzini val |= pcnet_aprom_readb(d, addr+1); 23049ab747fSPaolo Bonzini val <<= 8; 23149ab747fSPaolo Bonzini val |= pcnet_aprom_readb(d, addr); 23249ab747fSPaolo Bonzini } 23349ab747fSPaolo Bonzini #ifdef PCNET_DEBUG_IO 23449ab747fSPaolo Bonzini printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, 23549ab747fSPaolo Bonzini val); 23649ab747fSPaolo Bonzini #endif 23749ab747fSPaolo Bonzini return val; 23849ab747fSPaolo Bonzini } 23949ab747fSPaolo Bonzini 24049ab747fSPaolo Bonzini static const VMStateDescription vmstate_pci_pcnet = { 24149ab747fSPaolo Bonzini .name = "pcnet", 24249ab747fSPaolo Bonzini .version_id = 3, 24349ab747fSPaolo Bonzini .minimum_version_id = 2, 24449ab747fSPaolo Bonzini .minimum_version_id_old = 2, 24549ab747fSPaolo Bonzini .fields = (VMStateField []) { 2461f8c7946SPeter Crosthwaite VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState), 24749ab747fSPaolo Bonzini VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState), 24849ab747fSPaolo Bonzini VMSTATE_END_OF_LIST() 24949ab747fSPaolo Bonzini } 25049ab747fSPaolo Bonzini }; 25149ab747fSPaolo Bonzini 25249ab747fSPaolo Bonzini /* PCI interface */ 25349ab747fSPaolo Bonzini 25449ab747fSPaolo Bonzini static const MemoryRegionOps pcnet_mmio_ops = { 25549ab747fSPaolo Bonzini .old_mmio = { 25649ab747fSPaolo Bonzini .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl }, 25749ab747fSPaolo Bonzini .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel }, 25849ab747fSPaolo Bonzini }, 25949ab747fSPaolo Bonzini .endianness = DEVICE_NATIVE_ENDIAN, 26049ab747fSPaolo Bonzini }; 26149ab747fSPaolo Bonzini 26249ab747fSPaolo Bonzini static void pci_physical_memory_write(void *dma_opaque, hwaddr addr, 26349ab747fSPaolo Bonzini uint8_t *buf, int len, int do_bswap) 26449ab747fSPaolo Bonzini { 26549ab747fSPaolo Bonzini pci_dma_write(dma_opaque, addr, buf, len); 26649ab747fSPaolo Bonzini } 26749ab747fSPaolo Bonzini 26849ab747fSPaolo Bonzini static void pci_physical_memory_read(void *dma_opaque, hwaddr addr, 26949ab747fSPaolo Bonzini uint8_t *buf, int len, int do_bswap) 27049ab747fSPaolo Bonzini { 27149ab747fSPaolo Bonzini pci_dma_read(dma_opaque, addr, buf, len); 27249ab747fSPaolo Bonzini } 27349ab747fSPaolo Bonzini 27449ab747fSPaolo Bonzini static void pci_pcnet_cleanup(NetClientState *nc) 27549ab747fSPaolo Bonzini { 27649ab747fSPaolo Bonzini PCNetState *d = qemu_get_nic_opaque(nc); 27749ab747fSPaolo Bonzini 27849ab747fSPaolo Bonzini pcnet_common_cleanup(d); 27949ab747fSPaolo Bonzini } 28049ab747fSPaolo Bonzini 28149ab747fSPaolo Bonzini static void pci_pcnet_uninit(PCIDevice *dev) 28249ab747fSPaolo Bonzini { 2831f8c7946SPeter Crosthwaite PCIPCNetState *d = PCI_PCNET(dev); 28449ab747fSPaolo Bonzini 28549ab747fSPaolo Bonzini memory_region_destroy(&d->state.mmio); 28649ab747fSPaolo Bonzini memory_region_destroy(&d->io_bar); 287*bc72ad67SAlex Bligh timer_del(d->state.poll_timer); 288*bc72ad67SAlex Bligh timer_free(d->state.poll_timer); 28949ab747fSPaolo Bonzini qemu_del_nic(d->state.nic); 29049ab747fSPaolo Bonzini } 29149ab747fSPaolo Bonzini 29249ab747fSPaolo Bonzini static NetClientInfo net_pci_pcnet_info = { 29349ab747fSPaolo Bonzini .type = NET_CLIENT_OPTIONS_KIND_NIC, 29449ab747fSPaolo Bonzini .size = sizeof(NICState), 29549ab747fSPaolo Bonzini .can_receive = pcnet_can_receive, 29649ab747fSPaolo Bonzini .receive = pcnet_receive, 29749ab747fSPaolo Bonzini .link_status_changed = pcnet_set_link_status, 29849ab747fSPaolo Bonzini .cleanup = pci_pcnet_cleanup, 29949ab747fSPaolo Bonzini }; 30049ab747fSPaolo Bonzini 30149ab747fSPaolo Bonzini static int pci_pcnet_init(PCIDevice *pci_dev) 30249ab747fSPaolo Bonzini { 3031f8c7946SPeter Crosthwaite PCIPCNetState *d = PCI_PCNET(pci_dev); 30449ab747fSPaolo Bonzini PCNetState *s = &d->state; 30549ab747fSPaolo Bonzini uint8_t *pci_conf; 30649ab747fSPaolo Bonzini 30749ab747fSPaolo Bonzini #if 0 30849ab747fSPaolo Bonzini printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n", 30949ab747fSPaolo Bonzini sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD)); 31049ab747fSPaolo Bonzini #endif 31149ab747fSPaolo Bonzini 31249ab747fSPaolo Bonzini pci_conf = pci_dev->config; 31349ab747fSPaolo Bonzini 31449ab747fSPaolo Bonzini pci_set_word(pci_conf + PCI_STATUS, 31549ab747fSPaolo Bonzini PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 31649ab747fSPaolo Bonzini 31749ab747fSPaolo Bonzini pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0); 31849ab747fSPaolo Bonzini pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0); 31949ab747fSPaolo Bonzini 32049ab747fSPaolo Bonzini pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 32149ab747fSPaolo Bonzini pci_conf[PCI_MIN_GNT] = 0x06; 32249ab747fSPaolo Bonzini pci_conf[PCI_MAX_LAT] = 0xff; 32349ab747fSPaolo Bonzini 32449ab747fSPaolo Bonzini /* Handler for memory-mapped I/O */ 325eedfac6fSPaolo Bonzini memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s, 326eedfac6fSPaolo Bonzini "pcnet-mmio", PCNET_PNPMMIO_SIZE); 32749ab747fSPaolo Bonzini 328eedfac6fSPaolo Bonzini memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io", 32949ab747fSPaolo Bonzini PCNET_IOPORT_SIZE); 33049ab747fSPaolo Bonzini pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar); 33149ab747fSPaolo Bonzini 33249ab747fSPaolo Bonzini pci_register_bar(pci_dev, 1, 0, &s->mmio); 33349ab747fSPaolo Bonzini 33449ab747fSPaolo Bonzini s->irq = pci_dev->irq[0]; 33549ab747fSPaolo Bonzini s->phys_mem_read = pci_physical_memory_read; 33649ab747fSPaolo Bonzini s->phys_mem_write = pci_physical_memory_write; 33749ab747fSPaolo Bonzini s->dma_opaque = pci_dev; 33849ab747fSPaolo Bonzini 3391f8c7946SPeter Crosthwaite return pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info); 34049ab747fSPaolo Bonzini } 34149ab747fSPaolo Bonzini 34249ab747fSPaolo Bonzini static void pci_reset(DeviceState *dev) 34349ab747fSPaolo Bonzini { 3441f8c7946SPeter Crosthwaite PCIPCNetState *d = PCI_PCNET(dev); 34549ab747fSPaolo Bonzini 34649ab747fSPaolo Bonzini pcnet_h_reset(&d->state); 34749ab747fSPaolo Bonzini } 34849ab747fSPaolo Bonzini 34949ab747fSPaolo Bonzini static Property pcnet_properties[] = { 35049ab747fSPaolo Bonzini DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf), 35149ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 35249ab747fSPaolo Bonzini }; 35349ab747fSPaolo Bonzini 35449ab747fSPaolo Bonzini static void pcnet_class_init(ObjectClass *klass, void *data) 35549ab747fSPaolo Bonzini { 35649ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 35749ab747fSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 35849ab747fSPaolo Bonzini 35949ab747fSPaolo Bonzini k->init = pci_pcnet_init; 36049ab747fSPaolo Bonzini k->exit = pci_pcnet_uninit; 36149ab747fSPaolo Bonzini k->romfile = "efi-pcnet.rom", 36249ab747fSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_AMD; 36349ab747fSPaolo Bonzini k->device_id = PCI_DEVICE_ID_AMD_LANCE; 36449ab747fSPaolo Bonzini k->revision = 0x10; 36549ab747fSPaolo Bonzini k->class_id = PCI_CLASS_NETWORK_ETHERNET; 36649ab747fSPaolo Bonzini dc->reset = pci_reset; 36749ab747fSPaolo Bonzini dc->vmsd = &vmstate_pci_pcnet; 36849ab747fSPaolo Bonzini dc->props = pcnet_properties; 369125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 37049ab747fSPaolo Bonzini } 37149ab747fSPaolo Bonzini 37249ab747fSPaolo Bonzini static const TypeInfo pcnet_info = { 3731f8c7946SPeter Crosthwaite .name = TYPE_PCI_PCNET, 37449ab747fSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 37549ab747fSPaolo Bonzini .instance_size = sizeof(PCIPCNetState), 37649ab747fSPaolo Bonzini .class_init = pcnet_class_init, 37749ab747fSPaolo Bonzini }; 37849ab747fSPaolo Bonzini 37949ab747fSPaolo Bonzini static void pci_pcnet_register_types(void) 38049ab747fSPaolo Bonzini { 38149ab747fSPaolo Bonzini type_register_static(&pcnet_info); 38249ab747fSPaolo Bonzini } 38349ab747fSPaolo Bonzini 38449ab747fSPaolo Bonzini type_init(pci_pcnet_register_types) 385