1315a1350SMichael S. Tsirkin /*
2315a1350SMichael S. Tsirkin * pcie_aer.c
3315a1350SMichael S. Tsirkin *
4315a1350SMichael S. Tsirkin * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5315a1350SMichael S. Tsirkin * VA Linux Systems Japan K.K.
6315a1350SMichael S. Tsirkin *
7315a1350SMichael S. Tsirkin * This program is free software; you can redistribute it and/or modify
8315a1350SMichael S. Tsirkin * it under the terms of the GNU General Public License as published by
9315a1350SMichael S. Tsirkin * the Free Software Foundation; either version 2 of the License, or
10315a1350SMichael S. Tsirkin * (at your option) any later version.
11315a1350SMichael S. Tsirkin *
12315a1350SMichael S. Tsirkin * This program is distributed in the hope that it will be useful,
13315a1350SMichael S. Tsirkin * but WITHOUT ANY WARRANTY; without even the implied warranty of
14315a1350SMichael S. Tsirkin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15315a1350SMichael S. Tsirkin * GNU General Public License for more details.
16315a1350SMichael S. Tsirkin *
17315a1350SMichael S. Tsirkin * You should have received a copy of the GNU General Public License along
18315a1350SMichael S. Tsirkin * with this program; if not, see <http://www.gnu.org/licenses/>.
19315a1350SMichael S. Tsirkin */
20315a1350SMichael S. Tsirkin
2197d5408fSPeter Maydell #include "qemu/osdep.h"
22d6454270SMarkus Armbruster #include "migration/vmstate.h"
23c759b24fSMichael S. Tsirkin #include "hw/pci/pci_bridge.h"
24c759b24fSMichael S. Tsirkin #include "hw/pci/pcie.h"
25c759b24fSMichael S. Tsirkin #include "hw/pci/msix.h"
26c759b24fSMichael S. Tsirkin #include "hw/pci/msi.h"
2706aac7bdSMichael S. Tsirkin #include "hw/pci/pci_bus.h"
28c759b24fSMichael S. Tsirkin #include "hw/pci/pcie_regs.h"
29d0e67298SMarkus Armbruster #include "pci-internal.h"
30315a1350SMichael S. Tsirkin
31315a1350SMichael S. Tsirkin //#define DEBUG_PCIE
32315a1350SMichael S. Tsirkin #ifdef DEBUG_PCIE
33315a1350SMichael S. Tsirkin # define PCIE_DPRINTF(fmt, ...) \
34315a1350SMichael S. Tsirkin fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
35315a1350SMichael S. Tsirkin #else
36315a1350SMichael S. Tsirkin # define PCIE_DPRINTF(fmt, ...) do {} while (0)
37315a1350SMichael S. Tsirkin #endif
38315a1350SMichael S. Tsirkin #define PCIE_DEV_PRINTF(dev, fmt, ...) \
39315a1350SMichael S. Tsirkin PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
40315a1350SMichael S. Tsirkin
41315a1350SMichael S. Tsirkin #define PCI_ERR_SRC_COR_OFFS 0
42315a1350SMichael S. Tsirkin #define PCI_ERR_SRC_UNCOR_OFFS 2
43315a1350SMichael S. Tsirkin
44315a1350SMichael S. Tsirkin /* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */
pcie_aer_uncor_default_severity(uint32_t status)45315a1350SMichael S. Tsirkin static uint32_t pcie_aer_uncor_default_severity(uint32_t status)
46315a1350SMichael S. Tsirkin {
47315a1350SMichael S. Tsirkin switch (status) {
48315a1350SMichael S. Tsirkin case PCI_ERR_UNC_INTN:
49315a1350SMichael S. Tsirkin case PCI_ERR_UNC_DLP:
50315a1350SMichael S. Tsirkin case PCI_ERR_UNC_SDN:
51315a1350SMichael S. Tsirkin case PCI_ERR_UNC_RX_OVER:
52315a1350SMichael S. Tsirkin case PCI_ERR_UNC_FCP:
53315a1350SMichael S. Tsirkin case PCI_ERR_UNC_MALF_TLP:
54315a1350SMichael S. Tsirkin return PCI_ERR_ROOT_CMD_FATAL_EN;
55315a1350SMichael S. Tsirkin case PCI_ERR_UNC_POISON_TLP:
56315a1350SMichael S. Tsirkin case PCI_ERR_UNC_ECRC:
57315a1350SMichael S. Tsirkin case PCI_ERR_UNC_UNSUP:
58315a1350SMichael S. Tsirkin case PCI_ERR_UNC_COMP_TIME:
59315a1350SMichael S. Tsirkin case PCI_ERR_UNC_COMP_ABORT:
60315a1350SMichael S. Tsirkin case PCI_ERR_UNC_UNX_COMP:
61315a1350SMichael S. Tsirkin case PCI_ERR_UNC_ACSV:
62315a1350SMichael S. Tsirkin case PCI_ERR_UNC_MCBTLP:
63315a1350SMichael S. Tsirkin case PCI_ERR_UNC_ATOP_EBLOCKED:
64315a1350SMichael S. Tsirkin case PCI_ERR_UNC_TLP_PRF_BLOCKED:
65315a1350SMichael S. Tsirkin return PCI_ERR_ROOT_CMD_NONFATAL_EN;
66315a1350SMichael S. Tsirkin default:
67315a1350SMichael S. Tsirkin abort();
68315a1350SMichael S. Tsirkin break;
69315a1350SMichael S. Tsirkin }
70315a1350SMichael S. Tsirkin return PCI_ERR_ROOT_CMD_FATAL_EN;
71315a1350SMichael S. Tsirkin }
72315a1350SMichael S. Tsirkin
aer_log_add_err(PCIEAERLog * aer_log,const PCIEAERErr * err)73315a1350SMichael S. Tsirkin static int aer_log_add_err(PCIEAERLog *aer_log, const PCIEAERErr *err)
74315a1350SMichael S. Tsirkin {
75315a1350SMichael S. Tsirkin if (aer_log->log_num == aer_log->log_max) {
76315a1350SMichael S. Tsirkin return -1;
77315a1350SMichael S. Tsirkin }
78315a1350SMichael S. Tsirkin memcpy(&aer_log->log[aer_log->log_num], err, sizeof *err);
79315a1350SMichael S. Tsirkin aer_log->log_num++;
80315a1350SMichael S. Tsirkin return 0;
81315a1350SMichael S. Tsirkin }
82315a1350SMichael S. Tsirkin
aer_log_del_err(PCIEAERLog * aer_log,PCIEAERErr * err)83315a1350SMichael S. Tsirkin static void aer_log_del_err(PCIEAERLog *aer_log, PCIEAERErr *err)
84315a1350SMichael S. Tsirkin {
85315a1350SMichael S. Tsirkin assert(aer_log->log_num);
86315a1350SMichael S. Tsirkin *err = aer_log->log[0];
87315a1350SMichael S. Tsirkin aer_log->log_num--;
88315a1350SMichael S. Tsirkin memmove(&aer_log->log[0], &aer_log->log[1],
89315a1350SMichael S. Tsirkin aer_log->log_num * sizeof *err);
90315a1350SMichael S. Tsirkin }
91315a1350SMichael S. Tsirkin
aer_log_clear_all_err(PCIEAERLog * aer_log)92315a1350SMichael S. Tsirkin static void aer_log_clear_all_err(PCIEAERLog *aer_log)
93315a1350SMichael S. Tsirkin {
94315a1350SMichael S. Tsirkin aer_log->log_num = 0;
95315a1350SMichael S. Tsirkin }
96315a1350SMichael S. Tsirkin
pcie_aer_init(PCIDevice * dev,uint8_t cap_ver,uint16_t offset,uint16_t size,Error ** errp)97f18c697bSDou Liyang int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
98f18c697bSDou Liyang uint16_t size, Error **errp)
99315a1350SMichael S. Tsirkin {
100f18c697bSDou Liyang pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver,
1018d86ada2SChen Fan offset, size);
10233848ceeSCao jin dev->exp.aer_cap = offset;
103315a1350SMichael S. Tsirkin
10433848ceeSCao jin /* clip down the value to avoid unreasonable memory usage */
105315a1350SMichael S. Tsirkin if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
10633848ceeSCao jin error_setg(errp, "Invalid aer_log_max %d. The max number of aer log "
10733848ceeSCao jin "is %d", dev->exp.aer_log.log_max, PCIE_AER_LOG_MAX_LIMIT);
108315a1350SMichael S. Tsirkin return -EINVAL;
109315a1350SMichael S. Tsirkin }
110315a1350SMichael S. Tsirkin dev->exp.aer_log.log = g_malloc0(sizeof dev->exp.aer_log.log[0] *
111315a1350SMichael S. Tsirkin dev->exp.aer_log.log_max);
112315a1350SMichael S. Tsirkin
113315a1350SMichael S. Tsirkin pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
114315a1350SMichael S. Tsirkin PCI_ERR_UNC_SUPPORTED);
1155ed3dabeSLeonardo Bras
1165ed3dabeSLeonardo Bras if (dev->cap_present & QEMU_PCIE_ERR_UNC_MASK) {
117010746aeSJonathan Cameron pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK,
118010746aeSJonathan Cameron PCI_ERR_UNC_MASK_DEFAULT);
119010746aeSJonathan Cameron pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK,
120010746aeSJonathan Cameron PCI_ERR_UNC_SUPPORTED);
1215ed3dabeSLeonardo Bras }
122315a1350SMichael S. Tsirkin
123315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
124315a1350SMichael S. Tsirkin PCI_ERR_UNC_SEVERITY_DEFAULT);
125315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER,
126315a1350SMichael S. Tsirkin PCI_ERR_UNC_SUPPORTED);
127315a1350SMichael S. Tsirkin
128315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS,
129310e91f7SChen Fan PCI_ERR_COR_SUPPORTED);
130315a1350SMichael S. Tsirkin
131315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_COR_MASK,
132315a1350SMichael S. Tsirkin PCI_ERR_COR_MASK_DEFAULT);
133315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK,
134315a1350SMichael S. Tsirkin PCI_ERR_COR_SUPPORTED);
135315a1350SMichael S. Tsirkin
136315a1350SMichael S. Tsirkin /* capabilities and control. multiple header logging is supported */
137315a1350SMichael S. Tsirkin if (dev->exp.aer_log.log_max > 0) {
138315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_CAP,
139315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC |
140315a1350SMichael S. Tsirkin PCI_ERR_CAP_MHRC);
141315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
142315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE |
143315a1350SMichael S. Tsirkin PCI_ERR_CAP_MHRE);
144315a1350SMichael S. Tsirkin } else {
145315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_CAP,
146315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC);
147315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
148315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
149315a1350SMichael S. Tsirkin }
150315a1350SMichael S. Tsirkin
151315a1350SMichael S. Tsirkin switch (pcie_cap_get_type(dev)) {
152315a1350SMichael S. Tsirkin case PCI_EXP_TYPE_ROOT_PORT:
153315a1350SMichael S. Tsirkin /* this case will be set by pcie_aer_root_init() */
154315a1350SMichael S. Tsirkin /* fallthrough */
155315a1350SMichael S. Tsirkin case PCI_EXP_TYPE_DOWNSTREAM:
156315a1350SMichael S. Tsirkin case PCI_EXP_TYPE_UPSTREAM:
157315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL,
158315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_SERR);
159315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS,
160315a1350SMichael S. Tsirkin PCI_SEC_STATUS_RCV_SYSTEM_ERROR);
161315a1350SMichael S. Tsirkin break;
162315a1350SMichael S. Tsirkin default:
163315a1350SMichael S. Tsirkin /* nothing */
164315a1350SMichael S. Tsirkin break;
165315a1350SMichael S. Tsirkin }
166315a1350SMichael S. Tsirkin return 0;
167315a1350SMichael S. Tsirkin }
168315a1350SMichael S. Tsirkin
pcie_aer_exit(PCIDevice * dev)169315a1350SMichael S. Tsirkin void pcie_aer_exit(PCIDevice *dev)
170315a1350SMichael S. Tsirkin {
171315a1350SMichael S. Tsirkin g_free(dev->exp.aer_log.log);
172315a1350SMichael S. Tsirkin }
173315a1350SMichael S. Tsirkin
pcie_aer_update_uncor_status(PCIDevice * dev)174315a1350SMichael S. Tsirkin static void pcie_aer_update_uncor_status(PCIDevice *dev)
175315a1350SMichael S. Tsirkin {
176315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
177315a1350SMichael S. Tsirkin PCIEAERLog *aer_log = &dev->exp.aer_log;
178315a1350SMichael S. Tsirkin
179315a1350SMichael S. Tsirkin uint16_t i;
180315a1350SMichael S. Tsirkin for (i = 0; i < aer_log->log_num; i++) {
181315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(aer_cap + PCI_ERR_UNCOR_STATUS,
182315a1350SMichael S. Tsirkin dev->exp.aer_log.log[i].status);
183315a1350SMichael S. Tsirkin }
184315a1350SMichael S. Tsirkin }
185315a1350SMichael S. Tsirkin
186315a1350SMichael S. Tsirkin /*
187315a1350SMichael S. Tsirkin * return value:
188315a1350SMichael S. Tsirkin * true: error message needs to be sent up
189315a1350SMichael S. Tsirkin * false: error message is masked
190315a1350SMichael S. Tsirkin *
191315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control
192315a1350SMichael S. Tsirkin * Figure 6-3
193315a1350SMichael S. Tsirkin * all pci express devices part
194315a1350SMichael S. Tsirkin */
195315a1350SMichael S. Tsirkin static bool
pcie_aer_msg_alldev(PCIDevice * dev,const PCIEAERMsg * msg)196315a1350SMichael S. Tsirkin pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
197315a1350SMichael S. Tsirkin {
1989a6ef182SJonathan Cameron uint16_t devctl = pci_get_word(dev->config + dev->exp.exp_cap +
1999a6ef182SJonathan Cameron PCI_EXP_DEVCTL);
200315a1350SMichael S. Tsirkin if (!(pcie_aer_msg_is_uncor(msg) &&
2019a6ef182SJonathan Cameron (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR)) &&
2029a6ef182SJonathan Cameron !((msg->severity == PCI_ERR_ROOT_CMD_NONFATAL_EN) &&
2039a6ef182SJonathan Cameron (devctl & PCI_EXP_DEVCTL_NFERE)) &&
2049a6ef182SJonathan Cameron !((msg->severity == PCI_ERR_ROOT_CMD_COR_EN) &&
2059a6ef182SJonathan Cameron (devctl & PCI_EXP_DEVCTL_CERE)) &&
2069a6ef182SJonathan Cameron !((msg->severity == PCI_ERR_ROOT_CMD_FATAL_EN) &&
2079a6ef182SJonathan Cameron (devctl & PCI_EXP_DEVCTL_FERE))) {
208315a1350SMichael S. Tsirkin return false;
209315a1350SMichael S. Tsirkin }
210315a1350SMichael S. Tsirkin
211315a1350SMichael S. Tsirkin /* Signaled System Error
212315a1350SMichael S. Tsirkin *
213315a1350SMichael S. Tsirkin * 7.5.1.1 Command register
214315a1350SMichael S. Tsirkin * Bit 8 SERR# Enable
215315a1350SMichael S. Tsirkin *
216315a1350SMichael S. Tsirkin * When Set, this bit enables reporting of Non-fatal and Fatal
217315a1350SMichael S. Tsirkin * errors detected by the Function to the Root Complex. Note that
218315a1350SMichael S. Tsirkin * errors are reported if enabled either through this bit or through
219315a1350SMichael S. Tsirkin * the PCI Express specific bits in the Device Control register (see
220315a1350SMichael S. Tsirkin * Section 7.8.4).
221315a1350SMichael S. Tsirkin */
222315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->config + PCI_STATUS,
223315a1350SMichael S. Tsirkin PCI_STATUS_SIG_SYSTEM_ERROR);
224315a1350SMichael S. Tsirkin
225315a1350SMichael S. Tsirkin if (!(msg->severity &
226315a1350SMichael S. Tsirkin pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL))) {
227315a1350SMichael S. Tsirkin return false;
228315a1350SMichael S. Tsirkin }
229315a1350SMichael S. Tsirkin
230315a1350SMichael S. Tsirkin /* send up error message */
231315a1350SMichael S. Tsirkin return true;
232315a1350SMichael S. Tsirkin }
233315a1350SMichael S. Tsirkin
234315a1350SMichael S. Tsirkin /*
235315a1350SMichael S. Tsirkin * return value:
236315a1350SMichael S. Tsirkin * true: error message is sent up
237315a1350SMichael S. Tsirkin * false: error message is masked
238315a1350SMichael S. Tsirkin *
239315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control
240315a1350SMichael S. Tsirkin * Figure 6-3
241315a1350SMichael S. Tsirkin * virtual pci bridge part
242315a1350SMichael S. Tsirkin */
pcie_aer_msg_vbridge(PCIDevice * dev,const PCIEAERMsg * msg)243315a1350SMichael S. Tsirkin static bool pcie_aer_msg_vbridge(PCIDevice *dev, const PCIEAERMsg *msg)
244315a1350SMichael S. Tsirkin {
245315a1350SMichael S. Tsirkin uint16_t bridge_control = pci_get_word(dev->config + PCI_BRIDGE_CONTROL);
246315a1350SMichael S. Tsirkin
247315a1350SMichael S. Tsirkin if (pcie_aer_msg_is_uncor(msg)) {
248315a1350SMichael S. Tsirkin /* Received System Error */
249315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->config + PCI_SEC_STATUS,
250315a1350SMichael S. Tsirkin PCI_SEC_STATUS_RCV_SYSTEM_ERROR);
251315a1350SMichael S. Tsirkin }
252315a1350SMichael S. Tsirkin
253315a1350SMichael S. Tsirkin if (!(bridge_control & PCI_BRIDGE_CTL_SERR)) {
254315a1350SMichael S. Tsirkin return false;
255315a1350SMichael S. Tsirkin }
256315a1350SMichael S. Tsirkin return true;
257315a1350SMichael S. Tsirkin }
258315a1350SMichael S. Tsirkin
pcie_aer_root_set_vector(PCIDevice * dev,unsigned int vector)259315a1350SMichael S. Tsirkin void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector)
260315a1350SMichael S. Tsirkin {
261315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
262315a1350SMichael S. Tsirkin assert(vector < PCI_ERR_ROOT_IRQ_MAX);
263315a1350SMichael S. Tsirkin pci_long_test_and_clear_mask(aer_cap + PCI_ERR_ROOT_STATUS,
264315a1350SMichael S. Tsirkin PCI_ERR_ROOT_IRQ);
265315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(aer_cap + PCI_ERR_ROOT_STATUS,
266315a1350SMichael S. Tsirkin vector << PCI_ERR_ROOT_IRQ_SHIFT);
267315a1350SMichael S. Tsirkin }
268315a1350SMichael S. Tsirkin
pcie_aer_root_get_vector(PCIDevice * dev)269315a1350SMichael S. Tsirkin static unsigned int pcie_aer_root_get_vector(PCIDevice *dev)
270315a1350SMichael S. Tsirkin {
271315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
272315a1350SMichael S. Tsirkin uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
273315a1350SMichael S. Tsirkin return (root_status & PCI_ERR_ROOT_IRQ) >> PCI_ERR_ROOT_IRQ_SHIFT;
274315a1350SMichael S. Tsirkin }
275315a1350SMichael S. Tsirkin
276315a1350SMichael S. Tsirkin /* Given a status register, get corresponding bits in the command register */
pcie_aer_status_to_cmd(uint32_t status)277315a1350SMichael S. Tsirkin static uint32_t pcie_aer_status_to_cmd(uint32_t status)
278315a1350SMichael S. Tsirkin {
279315a1350SMichael S. Tsirkin uint32_t cmd = 0;
280315a1350SMichael S. Tsirkin if (status & PCI_ERR_ROOT_COR_RCV) {
281315a1350SMichael S. Tsirkin cmd |= PCI_ERR_ROOT_CMD_COR_EN;
282315a1350SMichael S. Tsirkin }
283315a1350SMichael S. Tsirkin if (status & PCI_ERR_ROOT_NONFATAL_RCV) {
284315a1350SMichael S. Tsirkin cmd |= PCI_ERR_ROOT_CMD_NONFATAL_EN;
285315a1350SMichael S. Tsirkin }
286315a1350SMichael S. Tsirkin if (status & PCI_ERR_ROOT_FATAL_RCV) {
287315a1350SMichael S. Tsirkin cmd |= PCI_ERR_ROOT_CMD_FATAL_EN;
288315a1350SMichael S. Tsirkin }
289315a1350SMichael S. Tsirkin return cmd;
290315a1350SMichael S. Tsirkin }
291315a1350SMichael S. Tsirkin
pcie_aer_root_notify(PCIDevice * dev)292315a1350SMichael S. Tsirkin static void pcie_aer_root_notify(PCIDevice *dev)
293315a1350SMichael S. Tsirkin {
294315a1350SMichael S. Tsirkin if (msix_enabled(dev)) {
295315a1350SMichael S. Tsirkin msix_notify(dev, pcie_aer_root_get_vector(dev));
296315a1350SMichael S. Tsirkin } else if (msi_enabled(dev)) {
297315a1350SMichael S. Tsirkin msi_notify(dev, pcie_aer_root_get_vector(dev));
2982e865671SFrederic Barrat } else if (pci_intx(dev) != -1) {
2995a03e708SMarcel Apfelbaum pci_irq_assert(dev);
300315a1350SMichael S. Tsirkin }
301315a1350SMichael S. Tsirkin }
302315a1350SMichael S. Tsirkin
303315a1350SMichael S. Tsirkin /*
304315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control
305315a1350SMichael S. Tsirkin * Figure 6-3
306315a1350SMichael S. Tsirkin * root port part
307315a1350SMichael S. Tsirkin */
pcie_aer_msg_root_port(PCIDevice * dev,const PCIEAERMsg * msg)308315a1350SMichael S. Tsirkin static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
309315a1350SMichael S. Tsirkin {
310315a1350SMichael S. Tsirkin uint16_t cmd;
311315a1350SMichael S. Tsirkin uint8_t *aer_cap;
312315a1350SMichael S. Tsirkin uint32_t root_cmd;
313315a1350SMichael S. Tsirkin uint32_t root_status, prev_status;
314315a1350SMichael S. Tsirkin
315315a1350SMichael S. Tsirkin cmd = pci_get_word(dev->config + PCI_COMMAND);
316315a1350SMichael S. Tsirkin aer_cap = dev->config + dev->exp.aer_cap;
317315a1350SMichael S. Tsirkin root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
318315a1350SMichael S. Tsirkin prev_status = root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
319315a1350SMichael S. Tsirkin
320315a1350SMichael S. Tsirkin if (cmd & PCI_COMMAND_SERR) {
321315a1350SMichael S. Tsirkin /* System Error.
322315a1350SMichael S. Tsirkin *
323315a1350SMichael S. Tsirkin * The way to report System Error is platform specific and
324315a1350SMichael S. Tsirkin * it isn't implemented in qemu right now.
325315a1350SMichael S. Tsirkin * So just discard the error for now.
326315a1350SMichael S. Tsirkin * OS which cares of aer would receive errors via
327f1c0cff8SMichael Tokarev * native aer mechanisms, so this wouldn't matter.
328315a1350SMichael S. Tsirkin */
329315a1350SMichael S. Tsirkin }
330315a1350SMichael S. Tsirkin
331118d4ed0SDr. David Alan Gilbert /* Error Message Received: Root Error Status register */
332315a1350SMichael S. Tsirkin switch (msg->severity) {
333315a1350SMichael S. Tsirkin case PCI_ERR_ROOT_CMD_COR_EN:
334315a1350SMichael S. Tsirkin if (root_status & PCI_ERR_ROOT_COR_RCV) {
335315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
336315a1350SMichael S. Tsirkin } else {
337315a1350SMichael S. Tsirkin pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC + PCI_ERR_SRC_COR_OFFS,
338315a1350SMichael S. Tsirkin msg->source_id);
339315a1350SMichael S. Tsirkin }
340315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_COR_RCV;
341315a1350SMichael S. Tsirkin break;
342315a1350SMichael S. Tsirkin case PCI_ERR_ROOT_CMD_NONFATAL_EN:
343315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
344315a1350SMichael S. Tsirkin break;
345315a1350SMichael S. Tsirkin case PCI_ERR_ROOT_CMD_FATAL_EN:
346315a1350SMichael S. Tsirkin if (!(root_status & PCI_ERR_ROOT_UNCOR_RCV)) {
347315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_FIRST_FATAL;
348315a1350SMichael S. Tsirkin }
349315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_FATAL_RCV;
350315a1350SMichael S. Tsirkin break;
351315a1350SMichael S. Tsirkin default:
352315a1350SMichael S. Tsirkin abort();
353315a1350SMichael S. Tsirkin break;
354315a1350SMichael S. Tsirkin }
355315a1350SMichael S. Tsirkin if (pcie_aer_msg_is_uncor(msg)) {
356315a1350SMichael S. Tsirkin if (root_status & PCI_ERR_ROOT_UNCOR_RCV) {
357315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
358315a1350SMichael S. Tsirkin } else {
359315a1350SMichael S. Tsirkin pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC +
360315a1350SMichael S. Tsirkin PCI_ERR_SRC_UNCOR_OFFS, msg->source_id);
361315a1350SMichael S. Tsirkin }
362315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_UNCOR_RCV;
363315a1350SMichael S. Tsirkin }
364315a1350SMichael S. Tsirkin pci_set_long(aer_cap + PCI_ERR_ROOT_STATUS, root_status);
365315a1350SMichael S. Tsirkin
366315a1350SMichael S. Tsirkin /* 6.2.4.1.2 Interrupt Generation */
367315a1350SMichael S. Tsirkin /* All the above did was set some bits in the status register.
368315a1350SMichael S. Tsirkin * Specifically these that match message severity.
369315a1350SMichael S. Tsirkin * The below code relies on this fact. */
370315a1350SMichael S. Tsirkin if (!(root_cmd & msg->severity) ||
371315a1350SMichael S. Tsirkin (pcie_aer_status_to_cmd(prev_status) & root_cmd)) {
372315a1350SMichael S. Tsirkin /* Condition is not being set or was already true so nothing to do. */
373315a1350SMichael S. Tsirkin return;
374315a1350SMichael S. Tsirkin }
375315a1350SMichael S. Tsirkin
376315a1350SMichael S. Tsirkin pcie_aer_root_notify(dev);
377315a1350SMichael S. Tsirkin }
378315a1350SMichael S. Tsirkin
379315a1350SMichael S. Tsirkin /*
380315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control Figure 6-3
381315a1350SMichael S. Tsirkin *
382315a1350SMichael S. Tsirkin * Walk up the bus tree from the device, propagate the error message.
383315a1350SMichael S. Tsirkin */
pcie_aer_msg(PCIDevice * dev,const PCIEAERMsg * msg)3848f16de18SEric Blake static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg)
385315a1350SMichael S. Tsirkin {
386315a1350SMichael S. Tsirkin uint8_t type;
387315a1350SMichael S. Tsirkin
388315a1350SMichael S. Tsirkin while (dev) {
389315a1350SMichael S. Tsirkin if (!pci_is_express(dev)) {
390315a1350SMichael S. Tsirkin /* just ignore it */
391315a1350SMichael S. Tsirkin /* TODO: Shouldn't we set PCI_STATUS_SIG_SYSTEM_ERROR?
392315a1350SMichael S. Tsirkin * Consider e.g. a PCI bridge above a PCI Express device. */
393315a1350SMichael S. Tsirkin return;
394315a1350SMichael S. Tsirkin }
395315a1350SMichael S. Tsirkin
396315a1350SMichael S. Tsirkin type = pcie_cap_get_type(dev);
397315a1350SMichael S. Tsirkin if ((type == PCI_EXP_TYPE_ROOT_PORT ||
398315a1350SMichael S. Tsirkin type == PCI_EXP_TYPE_UPSTREAM ||
399315a1350SMichael S. Tsirkin type == PCI_EXP_TYPE_DOWNSTREAM) &&
400315a1350SMichael S. Tsirkin !pcie_aer_msg_vbridge(dev, msg)) {
401315a1350SMichael S. Tsirkin return;
402315a1350SMichael S. Tsirkin }
403315a1350SMichael S. Tsirkin if (!pcie_aer_msg_alldev(dev, msg)) {
404315a1350SMichael S. Tsirkin return;
405315a1350SMichael S. Tsirkin }
406315a1350SMichael S. Tsirkin if (type == PCI_EXP_TYPE_ROOT_PORT) {
407315a1350SMichael S. Tsirkin pcie_aer_msg_root_port(dev, msg);
408315a1350SMichael S. Tsirkin /* Root port can notify system itself,
409315a1350SMichael S. Tsirkin or send the error message to root complex event collector. */
410315a1350SMichael S. Tsirkin /*
411315a1350SMichael S. Tsirkin * if root port is associated with an event collector,
412315a1350SMichael S. Tsirkin * return the root complex event collector here.
413315a1350SMichael S. Tsirkin * For now root complex event collector isn't supported.
414315a1350SMichael S. Tsirkin */
415315a1350SMichael S. Tsirkin return;
416315a1350SMichael S. Tsirkin }
417fd56e061SDavid Gibson dev = pci_bridge_get_device(pci_get_bus(dev));
418315a1350SMichael S. Tsirkin }
419315a1350SMichael S. Tsirkin }
420315a1350SMichael S. Tsirkin
pcie_aer_update_log(PCIDevice * dev,const PCIEAERErr * err)421315a1350SMichael S. Tsirkin static void pcie_aer_update_log(PCIDevice *dev, const PCIEAERErr *err)
422315a1350SMichael S. Tsirkin {
423315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
424786a4ea8SStefan Hajnoczi uint8_t first_bit = ctz32(err->status);
425315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
426315a1350SMichael S. Tsirkin int i;
427315a1350SMichael S. Tsirkin
428315a1350SMichael S. Tsirkin assert(err->status);
429315a1350SMichael S. Tsirkin assert(!(err->status & (err->status - 1)));
430315a1350SMichael S. Tsirkin
431315a1350SMichael S. Tsirkin errcap &= ~(PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP);
432315a1350SMichael S. Tsirkin errcap |= PCI_ERR_CAP_FEP(first_bit);
433315a1350SMichael S. Tsirkin
434315a1350SMichael S. Tsirkin if (err->flags & PCIE_AER_ERR_HEADER_VALID) {
435315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(err->header); ++i) {
436315a1350SMichael S. Tsirkin /* 7.10.8 Header Log Register */
437315a1350SMichael S. Tsirkin uint8_t *header_log =
438315a1350SMichael S. Tsirkin aer_cap + PCI_ERR_HEADER_LOG + i * sizeof err->header[0];
4396bd194abSPeter Maydell stl_be_p(header_log, err->header[i]);
440315a1350SMichael S. Tsirkin }
441315a1350SMichael S. Tsirkin } else {
442315a1350SMichael S. Tsirkin assert(!(err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT));
443315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
444315a1350SMichael S. Tsirkin }
445315a1350SMichael S. Tsirkin
446315a1350SMichael S. Tsirkin if ((err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT) &&
44777a3c1d7SChen Fan (pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP2) &
448315a1350SMichael S. Tsirkin PCI_EXP_DEVCAP2_EETLPP)) {
449315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) {
450315a1350SMichael S. Tsirkin /* 7.10.12 tlp prefix log register */
451315a1350SMichael S. Tsirkin uint8_t *prefix_log =
452315a1350SMichael S. Tsirkin aer_cap + PCI_ERR_TLP_PREFIX_LOG + i * sizeof err->prefix[0];
4536bd194abSPeter Maydell stl_be_p(prefix_log, err->prefix[i]);
454315a1350SMichael S. Tsirkin }
455315a1350SMichael S. Tsirkin errcap |= PCI_ERR_CAP_TLP;
456315a1350SMichael S. Tsirkin } else {
457315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0,
458315a1350SMichael S. Tsirkin PCI_ERR_TLP_PREFIX_LOG_SIZE);
459315a1350SMichael S. Tsirkin }
460315a1350SMichael S. Tsirkin pci_set_long(aer_cap + PCI_ERR_CAP, errcap);
461315a1350SMichael S. Tsirkin }
462315a1350SMichael S. Tsirkin
pcie_aer_clear_log(PCIDevice * dev)463315a1350SMichael S. Tsirkin static void pcie_aer_clear_log(PCIDevice *dev)
464315a1350SMichael S. Tsirkin {
465315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
466315a1350SMichael S. Tsirkin
467315a1350SMichael S. Tsirkin pci_long_test_and_clear_mask(aer_cap + PCI_ERR_CAP,
468315a1350SMichael S. Tsirkin PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP);
469315a1350SMichael S. Tsirkin
470315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
471315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, PCI_ERR_TLP_PREFIX_LOG_SIZE);
472315a1350SMichael S. Tsirkin }
473315a1350SMichael S. Tsirkin
pcie_aer_clear_error(PCIDevice * dev)474315a1350SMichael S. Tsirkin static void pcie_aer_clear_error(PCIDevice *dev)
475315a1350SMichael S. Tsirkin {
476315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
477315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
478315a1350SMichael S. Tsirkin PCIEAERLog *aer_log = &dev->exp.aer_log;
479315a1350SMichael S. Tsirkin PCIEAERErr err;
480315a1350SMichael S. Tsirkin
481315a1350SMichael S. Tsirkin if (!(errcap & PCI_ERR_CAP_MHRE) || !aer_log->log_num) {
482315a1350SMichael S. Tsirkin pcie_aer_clear_log(dev);
483315a1350SMichael S. Tsirkin return;
484315a1350SMichael S. Tsirkin }
485315a1350SMichael S. Tsirkin
486315a1350SMichael S. Tsirkin /*
487315a1350SMichael S. Tsirkin * If more errors are queued, set corresponding bits in uncorrectable
488315a1350SMichael S. Tsirkin * error status.
489315a1350SMichael S. Tsirkin * We emulate uncorrectable error status register as W1CS.
490315a1350SMichael S. Tsirkin * So set bit in uncorrectable error status here again for multiple
491315a1350SMichael S. Tsirkin * error recording support.
492315a1350SMichael S. Tsirkin *
493315a1350SMichael S. Tsirkin * 6.2.4.2 Multiple Error Handling(Advanced Error Reporting Capability)
494315a1350SMichael S. Tsirkin */
495315a1350SMichael S. Tsirkin pcie_aer_update_uncor_status(dev);
496315a1350SMichael S. Tsirkin
497315a1350SMichael S. Tsirkin aer_log_del_err(aer_log, &err);
498315a1350SMichael S. Tsirkin pcie_aer_update_log(dev, &err);
499315a1350SMichael S. Tsirkin }
500315a1350SMichael S. Tsirkin
pcie_aer_record_error(PCIDevice * dev,const PCIEAERErr * err)501315a1350SMichael S. Tsirkin static int pcie_aer_record_error(PCIDevice *dev,
502315a1350SMichael S. Tsirkin const PCIEAERErr *err)
503315a1350SMichael S. Tsirkin {
504315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
505315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
506315a1350SMichael S. Tsirkin int fep = PCI_ERR_CAP_FEP(errcap);
507315a1350SMichael S. Tsirkin
508315a1350SMichael S. Tsirkin assert(err->status);
509315a1350SMichael S. Tsirkin assert(!(err->status & (err->status - 1)));
510315a1350SMichael S. Tsirkin
511315a1350SMichael S. Tsirkin if (errcap & PCI_ERR_CAP_MHRE &&
512315a1350SMichael S. Tsirkin (pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) {
513315a1350SMichael S. Tsirkin /* Not first error. queue error */
514315a1350SMichael S. Tsirkin if (aer_log_add_err(&dev->exp.aer_log, err) < 0) {
515315a1350SMichael S. Tsirkin /* overflow */
516315a1350SMichael S. Tsirkin return -1;
517315a1350SMichael S. Tsirkin }
518315a1350SMichael S. Tsirkin return 0;
519315a1350SMichael S. Tsirkin }
520315a1350SMichael S. Tsirkin
521315a1350SMichael S. Tsirkin pcie_aer_update_log(dev, err);
522315a1350SMichael S. Tsirkin return 0;
523315a1350SMichael S. Tsirkin }
524315a1350SMichael S. Tsirkin
525315a1350SMichael S. Tsirkin typedef struct PCIEAERInject {
526315a1350SMichael S. Tsirkin PCIDevice *dev;
527315a1350SMichael S. Tsirkin uint8_t *aer_cap;
528315a1350SMichael S. Tsirkin const PCIEAERErr *err;
529315a1350SMichael S. Tsirkin uint16_t devctl;
530315a1350SMichael S. Tsirkin uint16_t devsta;
531315a1350SMichael S. Tsirkin uint32_t error_status;
532315a1350SMichael S. Tsirkin bool unsupported_request;
533315a1350SMichael S. Tsirkin bool log_overflow;
534315a1350SMichael S. Tsirkin PCIEAERMsg msg;
535315a1350SMichael S. Tsirkin } PCIEAERInject;
536315a1350SMichael S. Tsirkin
pcie_aer_inject_cor_error(PCIEAERInject * inj,uint32_t uncor_status,bool is_advisory_nonfatal)537315a1350SMichael S. Tsirkin static bool pcie_aer_inject_cor_error(PCIEAERInject *inj,
538315a1350SMichael S. Tsirkin uint32_t uncor_status,
539315a1350SMichael S. Tsirkin bool is_advisory_nonfatal)
540315a1350SMichael S. Tsirkin {
541315a1350SMichael S. Tsirkin PCIDevice *dev = inj->dev;
542315a1350SMichael S. Tsirkin
543315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_CED;
544315a1350SMichael S. Tsirkin if (inj->unsupported_request) {
545315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_URD;
546315a1350SMichael S. Tsirkin }
547315a1350SMichael S. Tsirkin pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta);
548315a1350SMichael S. Tsirkin
549315a1350SMichael S. Tsirkin if (inj->aer_cap) {
550315a1350SMichael S. Tsirkin uint32_t mask;
551315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_COR_STATUS,
552315a1350SMichael S. Tsirkin inj->error_status);
553315a1350SMichael S. Tsirkin mask = pci_get_long(inj->aer_cap + PCI_ERR_COR_MASK);
554315a1350SMichael S. Tsirkin if (mask & inj->error_status) {
555315a1350SMichael S. Tsirkin return false;
556315a1350SMichael S. Tsirkin }
557315a1350SMichael S. Tsirkin if (is_advisory_nonfatal) {
558315a1350SMichael S. Tsirkin uint32_t uncor_mask =
559315a1350SMichael S. Tsirkin pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK);
560315a1350SMichael S. Tsirkin if (!(uncor_mask & uncor_status)) {
561315a1350SMichael S. Tsirkin inj->log_overflow = !!pcie_aer_record_error(dev, inj->err);
562315a1350SMichael S. Tsirkin }
563315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
564315a1350SMichael S. Tsirkin uncor_status);
565315a1350SMichael S. Tsirkin }
566315a1350SMichael S. Tsirkin }
567315a1350SMichael S. Tsirkin
568315a1350SMichael S. Tsirkin if (inj->unsupported_request && !(inj->devctl & PCI_EXP_DEVCTL_URRE)) {
569315a1350SMichael S. Tsirkin return false;
570315a1350SMichael S. Tsirkin }
571315a1350SMichael S. Tsirkin if (!(inj->devctl & PCI_EXP_DEVCTL_CERE)) {
572315a1350SMichael S. Tsirkin return false;
573315a1350SMichael S. Tsirkin }
574315a1350SMichael S. Tsirkin
575315a1350SMichael S. Tsirkin inj->msg.severity = PCI_ERR_ROOT_CMD_COR_EN;
576315a1350SMichael S. Tsirkin return true;
577315a1350SMichael S. Tsirkin }
578315a1350SMichael S. Tsirkin
pcie_aer_inject_uncor_error(PCIEAERInject * inj,bool is_fatal)579315a1350SMichael S. Tsirkin static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal)
580315a1350SMichael S. Tsirkin {
581315a1350SMichael S. Tsirkin PCIDevice *dev = inj->dev;
582315a1350SMichael S. Tsirkin uint16_t cmd;
583315a1350SMichael S. Tsirkin
584315a1350SMichael S. Tsirkin if (is_fatal) {
585315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_FED;
586315a1350SMichael S. Tsirkin } else {
587315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_NFED;
588315a1350SMichael S. Tsirkin }
589315a1350SMichael S. Tsirkin if (inj->unsupported_request) {
590315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_URD;
591315a1350SMichael S. Tsirkin }
592315a1350SMichael S. Tsirkin pci_set_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta);
593315a1350SMichael S. Tsirkin
594315a1350SMichael S. Tsirkin if (inj->aer_cap) {
595315a1350SMichael S. Tsirkin uint32_t mask = pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK);
596315a1350SMichael S. Tsirkin if (mask & inj->error_status) {
597315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
598315a1350SMichael S. Tsirkin inj->error_status);
599315a1350SMichael S. Tsirkin return false;
600315a1350SMichael S. Tsirkin }
601315a1350SMichael S. Tsirkin
602315a1350SMichael S. Tsirkin inj->log_overflow = !!pcie_aer_record_error(dev, inj->err);
603315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
604315a1350SMichael S. Tsirkin inj->error_status);
605315a1350SMichael S. Tsirkin }
606315a1350SMichael S. Tsirkin
607315a1350SMichael S. Tsirkin cmd = pci_get_word(dev->config + PCI_COMMAND);
608315a1350SMichael S. Tsirkin if (inj->unsupported_request &&
609315a1350SMichael S. Tsirkin !(inj->devctl & PCI_EXP_DEVCTL_URRE) && !(cmd & PCI_COMMAND_SERR)) {
610315a1350SMichael S. Tsirkin return false;
611315a1350SMichael S. Tsirkin }
612315a1350SMichael S. Tsirkin if (is_fatal) {
613315a1350SMichael S. Tsirkin if (!((cmd & PCI_COMMAND_SERR) ||
614315a1350SMichael S. Tsirkin (inj->devctl & PCI_EXP_DEVCTL_FERE))) {
615315a1350SMichael S. Tsirkin return false;
616315a1350SMichael S. Tsirkin }
617315a1350SMichael S. Tsirkin inj->msg.severity = PCI_ERR_ROOT_CMD_FATAL_EN;
618315a1350SMichael S. Tsirkin } else {
619315a1350SMichael S. Tsirkin if (!((cmd & PCI_COMMAND_SERR) ||
620315a1350SMichael S. Tsirkin (inj->devctl & PCI_EXP_DEVCTL_NFERE))) {
621315a1350SMichael S. Tsirkin return false;
622315a1350SMichael S. Tsirkin }
623315a1350SMichael S. Tsirkin inj->msg.severity = PCI_ERR_ROOT_CMD_NONFATAL_EN;
624315a1350SMichael S. Tsirkin }
625315a1350SMichael S. Tsirkin return true;
626315a1350SMichael S. Tsirkin }
627315a1350SMichael S. Tsirkin
628315a1350SMichael S. Tsirkin /*
629315a1350SMichael S. Tsirkin * non-Function specific error must be recorded in all functions.
630315a1350SMichael S. Tsirkin * It is the responsibility of the caller of this function.
631315a1350SMichael S. Tsirkin * It is also caller's responsibility to determine which function should
632b01738c2SChen Fan * report the error.
633315a1350SMichael S. Tsirkin *
634315a1350SMichael S. Tsirkin * 6.2.4 Error Logging
635b01738c2SChen Fan * 6.2.5 Sequence of Device Error Signaling and Logging Operations
636ce394947SMichael S. Tsirkin * Figure 6-2: Flowchart Showing Sequence of Device Error Signaling and Logging
637315a1350SMichael S. Tsirkin * Operations
638315a1350SMichael S. Tsirkin */
pcie_aer_inject_error(PCIDevice * dev,const PCIEAERErr * err)639d0e67298SMarkus Armbruster int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err)
640315a1350SMichael S. Tsirkin {
641315a1350SMichael S. Tsirkin uint8_t *aer_cap = NULL;
642315a1350SMichael S. Tsirkin uint16_t devctl = 0;
643315a1350SMichael S. Tsirkin uint16_t devsta = 0;
644315a1350SMichael S. Tsirkin uint32_t error_status = err->status;
645315a1350SMichael S. Tsirkin PCIEAERInject inj;
646315a1350SMichael S. Tsirkin
647315a1350SMichael S. Tsirkin if (!pci_is_express(dev)) {
648315a1350SMichael S. Tsirkin return -ENOSYS;
649315a1350SMichael S. Tsirkin }
650315a1350SMichael S. Tsirkin
651315a1350SMichael S. Tsirkin if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
652315a1350SMichael S. Tsirkin error_status &= PCI_ERR_COR_SUPPORTED;
653315a1350SMichael S. Tsirkin } else {
654315a1350SMichael S. Tsirkin error_status &= PCI_ERR_UNC_SUPPORTED;
655315a1350SMichael S. Tsirkin }
656315a1350SMichael S. Tsirkin
657315a1350SMichael S. Tsirkin /* invalid status bit. one and only one bit must be set */
658315a1350SMichael S. Tsirkin if (!error_status || (error_status & (error_status - 1))) {
659315a1350SMichael S. Tsirkin return -EINVAL;
660315a1350SMichael S. Tsirkin }
661315a1350SMichael S. Tsirkin
662315a1350SMichael S. Tsirkin if (dev->exp.aer_cap) {
663315a1350SMichael S. Tsirkin uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
664315a1350SMichael S. Tsirkin aer_cap = dev->config + dev->exp.aer_cap;
665315a1350SMichael S. Tsirkin devctl = pci_get_long(exp_cap + PCI_EXP_DEVCTL);
666315a1350SMichael S. Tsirkin devsta = pci_get_long(exp_cap + PCI_EXP_DEVSTA);
667315a1350SMichael S. Tsirkin }
668315a1350SMichael S. Tsirkin
669315a1350SMichael S. Tsirkin inj.dev = dev;
670315a1350SMichael S. Tsirkin inj.aer_cap = aer_cap;
671315a1350SMichael S. Tsirkin inj.err = err;
672315a1350SMichael S. Tsirkin inj.devctl = devctl;
673315a1350SMichael S. Tsirkin inj.devsta = devsta;
674315a1350SMichael S. Tsirkin inj.error_status = error_status;
675315a1350SMichael S. Tsirkin inj.unsupported_request = !(err->flags & PCIE_AER_ERR_IS_CORRECTABLE) &&
676315a1350SMichael S. Tsirkin err->status == PCI_ERR_UNC_UNSUP;
677315a1350SMichael S. Tsirkin inj.log_overflow = false;
678315a1350SMichael S. Tsirkin
679315a1350SMichael S. Tsirkin if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
680315a1350SMichael S. Tsirkin if (!pcie_aer_inject_cor_error(&inj, 0, false)) {
681315a1350SMichael S. Tsirkin return 0;
682315a1350SMichael S. Tsirkin }
683315a1350SMichael S. Tsirkin } else {
684315a1350SMichael S. Tsirkin bool is_fatal =
685315a1350SMichael S. Tsirkin pcie_aer_uncor_default_severity(error_status) ==
686315a1350SMichael S. Tsirkin PCI_ERR_ROOT_CMD_FATAL_EN;
687315a1350SMichael S. Tsirkin if (aer_cap) {
688315a1350SMichael S. Tsirkin is_fatal =
689315a1350SMichael S. Tsirkin error_status & pci_get_long(aer_cap + PCI_ERR_UNCOR_SEVER);
690315a1350SMichael S. Tsirkin }
691315a1350SMichael S. Tsirkin if (!is_fatal && (err->flags & PCIE_AER_ERR_MAYBE_ADVISORY)) {
692315a1350SMichael S. Tsirkin inj.error_status = PCI_ERR_COR_ADV_NONFATAL;
693315a1350SMichael S. Tsirkin if (!pcie_aer_inject_cor_error(&inj, error_status, true)) {
694315a1350SMichael S. Tsirkin return 0;
695315a1350SMichael S. Tsirkin }
696315a1350SMichael S. Tsirkin } else {
697315a1350SMichael S. Tsirkin if (!pcie_aer_inject_uncor_error(&inj, is_fatal)) {
698315a1350SMichael S. Tsirkin return 0;
699315a1350SMichael S. Tsirkin }
700315a1350SMichael S. Tsirkin }
701315a1350SMichael S. Tsirkin }
702315a1350SMichael S. Tsirkin
703315a1350SMichael S. Tsirkin /* send up error message */
704315a1350SMichael S. Tsirkin inj.msg.source_id = err->source_id;
705315a1350SMichael S. Tsirkin pcie_aer_msg(dev, &inj.msg);
706315a1350SMichael S. Tsirkin
707315a1350SMichael S. Tsirkin if (inj.log_overflow) {
708315a1350SMichael S. Tsirkin PCIEAERErr header_log_overflow = {
709315a1350SMichael S. Tsirkin .status = PCI_ERR_COR_HL_OVERFLOW,
710315a1350SMichael S. Tsirkin .flags = PCIE_AER_ERR_IS_CORRECTABLE,
711315a1350SMichael S. Tsirkin };
712315a1350SMichael S. Tsirkin int ret = pcie_aer_inject_error(dev, &header_log_overflow);
713315a1350SMichael S. Tsirkin assert(!ret);
714315a1350SMichael S. Tsirkin }
715315a1350SMichael S. Tsirkin return 0;
716315a1350SMichael S. Tsirkin }
717315a1350SMichael S. Tsirkin
pcie_aer_write_config(PCIDevice * dev,uint32_t addr,uint32_t val,int len)718315a1350SMichael S. Tsirkin void pcie_aer_write_config(PCIDevice *dev,
719315a1350SMichael S. Tsirkin uint32_t addr, uint32_t val, int len)
720315a1350SMichael S. Tsirkin {
721315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
722315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
723315a1350SMichael S. Tsirkin uint32_t first_error = 1U << PCI_ERR_CAP_FEP(errcap);
724315a1350SMichael S. Tsirkin uint32_t uncorsta = pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS);
725315a1350SMichael S. Tsirkin
726315a1350SMichael S. Tsirkin /* uncorrectable error */
727315a1350SMichael S. Tsirkin if (!(uncorsta & first_error)) {
728315a1350SMichael S. Tsirkin /* the bit that corresponds to the first error is cleared */
729315a1350SMichael S. Tsirkin pcie_aer_clear_error(dev);
730315a1350SMichael S. Tsirkin } else if (errcap & PCI_ERR_CAP_MHRE) {
731315a1350SMichael S. Tsirkin /* When PCI_ERR_CAP_MHRE is enabled and the first error isn't cleared
732315a1350SMichael S. Tsirkin * nothing should happen. So we have to revert the modification to
733315a1350SMichael S. Tsirkin * the register.
734315a1350SMichael S. Tsirkin */
735315a1350SMichael S. Tsirkin pcie_aer_update_uncor_status(dev);
736315a1350SMichael S. Tsirkin } else {
737315a1350SMichael S. Tsirkin /* capability & control
738315a1350SMichael S. Tsirkin * PCI_ERR_CAP_MHRE might be cleared, so clear of header log.
739315a1350SMichael S. Tsirkin */
740315a1350SMichael S. Tsirkin aer_log_clear_all_err(&dev->exp.aer_log);
741315a1350SMichael S. Tsirkin }
742315a1350SMichael S. Tsirkin }
743315a1350SMichael S. Tsirkin
pcie_aer_root_init(PCIDevice * dev)744315a1350SMichael S. Tsirkin void pcie_aer_root_init(PCIDevice *dev)
745315a1350SMichael S. Tsirkin {
746315a1350SMichael S. Tsirkin uint16_t pos = dev->exp.aer_cap;
747315a1350SMichael S. Tsirkin
748315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND,
749315a1350SMichael S. Tsirkin PCI_ERR_ROOT_CMD_EN_MASK);
750315a1350SMichael S. Tsirkin pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS,
751315a1350SMichael S. Tsirkin PCI_ERR_ROOT_STATUS_REPORT_MASK);
752315a1350SMichael S. Tsirkin /* PCI_ERR_ROOT_IRQ is RO but devices change it using a
753315a1350SMichael S. Tsirkin * device-specific method.
754315a1350SMichael S. Tsirkin */
755315a1350SMichael S. Tsirkin pci_set_long(dev->cmask + pos + PCI_ERR_ROOT_STATUS,
756315a1350SMichael S. Tsirkin ~PCI_ERR_ROOT_IRQ);
757315a1350SMichael S. Tsirkin }
758315a1350SMichael S. Tsirkin
pcie_aer_root_reset(PCIDevice * dev)759315a1350SMichael S. Tsirkin void pcie_aer_root_reset(PCIDevice *dev)
760315a1350SMichael S. Tsirkin {
761315a1350SMichael S. Tsirkin uint8_t* aer_cap = dev->config + dev->exp.aer_cap;
762315a1350SMichael S. Tsirkin
763315a1350SMichael S. Tsirkin pci_set_long(aer_cap + PCI_ERR_ROOT_COMMAND, 0);
764315a1350SMichael S. Tsirkin
765315a1350SMichael S. Tsirkin /*
766315a1350SMichael S. Tsirkin * Advanced Error Interrupt Message Number in Root Error Status Register
767315a1350SMichael S. Tsirkin * must be updated by chip dependent code because it's chip dependent
768315a1350SMichael S. Tsirkin * which number is used.
769315a1350SMichael S. Tsirkin */
770315a1350SMichael S. Tsirkin }
771315a1350SMichael S. Tsirkin
pcie_aer_root_write_config(PCIDevice * dev,uint32_t addr,uint32_t val,int len,uint32_t root_cmd_prev)772315a1350SMichael S. Tsirkin void pcie_aer_root_write_config(PCIDevice *dev,
773315a1350SMichael S. Tsirkin uint32_t addr, uint32_t val, int len,
774315a1350SMichael S. Tsirkin uint32_t root_cmd_prev)
775315a1350SMichael S. Tsirkin {
776315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
777315a1350SMichael S. Tsirkin uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
778315a1350SMichael S. Tsirkin uint32_t enabled_cmd = pcie_aer_status_to_cmd(root_status);
779315a1350SMichael S. Tsirkin uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
780315a1350SMichael S. Tsirkin /* 6.2.4.1.2 Interrupt Generation */
781315a1350SMichael S. Tsirkin if (!msix_enabled(dev) && !msi_enabled(dev)) {
78220766514SFrederic Barrat if (pci_intx(dev) != -1) {
7835a03e708SMarcel Apfelbaum pci_set_irq(dev, !!(root_cmd & enabled_cmd));
78420766514SFrederic Barrat }
785315a1350SMichael S. Tsirkin return;
786315a1350SMichael S. Tsirkin }
787315a1350SMichael S. Tsirkin
788315a1350SMichael S. Tsirkin if ((root_cmd_prev & enabled_cmd) || !(root_cmd & enabled_cmd)) {
789315a1350SMichael S. Tsirkin /* Send MSI on transition from false to true. */
790315a1350SMichael S. Tsirkin return;
791315a1350SMichael S. Tsirkin }
792315a1350SMichael S. Tsirkin
793315a1350SMichael S. Tsirkin pcie_aer_root_notify(dev);
794315a1350SMichael S. Tsirkin }
795315a1350SMichael S. Tsirkin
796315a1350SMichael S. Tsirkin static const VMStateDescription vmstate_pcie_aer_err = {
797315a1350SMichael S. Tsirkin .name = "PCIE_AER_ERROR",
798315a1350SMichael S. Tsirkin .version_id = 1,
799315a1350SMichael S. Tsirkin .minimum_version_id = 1,
800*8e5e0890SRichard Henderson .fields = (const VMStateField[]) {
801315a1350SMichael S. Tsirkin VMSTATE_UINT32(status, PCIEAERErr),
802315a1350SMichael S. Tsirkin VMSTATE_UINT16(source_id, PCIEAERErr),
803315a1350SMichael S. Tsirkin VMSTATE_UINT16(flags, PCIEAERErr),
804315a1350SMichael S. Tsirkin VMSTATE_UINT32_ARRAY(header, PCIEAERErr, 4),
805315a1350SMichael S. Tsirkin VMSTATE_UINT32_ARRAY(prefix, PCIEAERErr, 4),
806315a1350SMichael S. Tsirkin VMSTATE_END_OF_LIST()
807315a1350SMichael S. Tsirkin }
808315a1350SMichael S. Tsirkin };
809315a1350SMichael S. Tsirkin
pcie_aer_state_log_num_valid(void * opaque,int version_id)8105f691ff9SMichael S. Tsirkin static bool pcie_aer_state_log_num_valid(void *opaque, int version_id)
8115f691ff9SMichael S. Tsirkin {
8125f691ff9SMichael S. Tsirkin PCIEAERLog *s = opaque;
8135f691ff9SMichael S. Tsirkin
8145f691ff9SMichael S. Tsirkin return s->log_num <= s->log_max;
8155f691ff9SMichael S. Tsirkin }
8165f691ff9SMichael S. Tsirkin
817315a1350SMichael S. Tsirkin const VMStateDescription vmstate_pcie_aer_log = {
818315a1350SMichael S. Tsirkin .name = "PCIE_AER_ERROR_LOG",
819315a1350SMichael S. Tsirkin .version_id = 1,
820315a1350SMichael S. Tsirkin .minimum_version_id = 1,
821*8e5e0890SRichard Henderson .fields = (const VMStateField[]) {
822315a1350SMichael S. Tsirkin VMSTATE_UINT16(log_num, PCIEAERLog),
823d2164ad3SHalil Pasic VMSTATE_UINT16_EQUAL(log_max, PCIEAERLog, NULL),
8245f691ff9SMichael S. Tsirkin VMSTATE_VALIDATE("log_num <= log_max", pcie_aer_state_log_num_valid),
825315a1350SMichael S. Tsirkin VMSTATE_STRUCT_VARRAY_POINTER_UINT16(log, PCIEAERLog, log_num,
826315a1350SMichael S. Tsirkin vmstate_pcie_aer_err, PCIEAERErr),
827315a1350SMichael S. Tsirkin VMSTATE_END_OF_LIST()
828315a1350SMichael S. Tsirkin }
829315a1350SMichael S. Tsirkin };
830315a1350SMichael S. Tsirkin
831315a1350SMichael S. Tsirkin typedef struct PCIEAERErrorName {
832315a1350SMichael S. Tsirkin const char *name;
833315a1350SMichael S. Tsirkin uint32_t val;
834315a1350SMichael S. Tsirkin bool correctable;
835315a1350SMichael S. Tsirkin } PCIEAERErrorName;
836315a1350SMichael S. Tsirkin
837315a1350SMichael S. Tsirkin /*
838315a1350SMichael S. Tsirkin * AER error name -> value conversion table
839315a1350SMichael S. Tsirkin * This naming scheme is same to linux aer-injection tool.
840315a1350SMichael S. Tsirkin */
841315a1350SMichael S. Tsirkin static const struct PCIEAERErrorName pcie_aer_error_list[] = {
842315a1350SMichael S. Tsirkin {
843315a1350SMichael S. Tsirkin .name = "DLP",
844315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_DLP,
845315a1350SMichael S. Tsirkin .correctable = false,
846315a1350SMichael S. Tsirkin }, {
847315a1350SMichael S. Tsirkin .name = "SDN",
848315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_SDN,
849315a1350SMichael S. Tsirkin .correctable = false,
850315a1350SMichael S. Tsirkin }, {
851315a1350SMichael S. Tsirkin .name = "POISON_TLP",
852315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_POISON_TLP,
853315a1350SMichael S. Tsirkin .correctable = false,
854315a1350SMichael S. Tsirkin }, {
855315a1350SMichael S. Tsirkin .name = "FCP",
856315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_FCP,
857315a1350SMichael S. Tsirkin .correctable = false,
858315a1350SMichael S. Tsirkin }, {
859315a1350SMichael S. Tsirkin .name = "COMP_TIME",
860315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_COMP_TIME,
861315a1350SMichael S. Tsirkin .correctable = false,
862315a1350SMichael S. Tsirkin }, {
863315a1350SMichael S. Tsirkin .name = "COMP_ABORT",
864315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_COMP_ABORT,
865315a1350SMichael S. Tsirkin .correctable = false,
866315a1350SMichael S. Tsirkin }, {
867315a1350SMichael S. Tsirkin .name = "UNX_COMP",
868315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_UNX_COMP,
869315a1350SMichael S. Tsirkin .correctable = false,
870315a1350SMichael S. Tsirkin }, {
871315a1350SMichael S. Tsirkin .name = "RX_OVER",
872315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_RX_OVER,
873315a1350SMichael S. Tsirkin .correctable = false,
874315a1350SMichael S. Tsirkin }, {
875315a1350SMichael S. Tsirkin .name = "MALF_TLP",
876315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_MALF_TLP,
877315a1350SMichael S. Tsirkin .correctable = false,
878315a1350SMichael S. Tsirkin }, {
879315a1350SMichael S. Tsirkin .name = "ECRC",
880315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_ECRC,
881315a1350SMichael S. Tsirkin .correctable = false,
882315a1350SMichael S. Tsirkin }, {
883315a1350SMichael S. Tsirkin .name = "UNSUP",
884315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_UNSUP,
885315a1350SMichael S. Tsirkin .correctable = false,
886315a1350SMichael S. Tsirkin }, {
887315a1350SMichael S. Tsirkin .name = "ACSV",
888315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_ACSV,
889315a1350SMichael S. Tsirkin .correctable = false,
890315a1350SMichael S. Tsirkin }, {
891315a1350SMichael S. Tsirkin .name = "INTN",
892315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_INTN,
893315a1350SMichael S. Tsirkin .correctable = false,
894315a1350SMichael S. Tsirkin }, {
895315a1350SMichael S. Tsirkin .name = "MCBTLP",
896315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_MCBTLP,
897315a1350SMichael S. Tsirkin .correctable = false,
898315a1350SMichael S. Tsirkin }, {
899315a1350SMichael S. Tsirkin .name = "ATOP_EBLOCKED",
900315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_ATOP_EBLOCKED,
901315a1350SMichael S. Tsirkin .correctable = false,
902315a1350SMichael S. Tsirkin }, {
903315a1350SMichael S. Tsirkin .name = "TLP_PRF_BLOCKED",
904315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_TLP_PRF_BLOCKED,
905315a1350SMichael S. Tsirkin .correctable = false,
906315a1350SMichael S. Tsirkin }, {
907315a1350SMichael S. Tsirkin .name = "RCVR",
908315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_RCVR,
909315a1350SMichael S. Tsirkin .correctable = true,
910315a1350SMichael S. Tsirkin }, {
911315a1350SMichael S. Tsirkin .name = "BAD_TLP",
912315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_BAD_TLP,
913315a1350SMichael S. Tsirkin .correctable = true,
914315a1350SMichael S. Tsirkin }, {
915315a1350SMichael S. Tsirkin .name = "BAD_DLLP",
916315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_BAD_DLLP,
917315a1350SMichael S. Tsirkin .correctable = true,
918315a1350SMichael S. Tsirkin }, {
919315a1350SMichael S. Tsirkin .name = "REP_ROLL",
920315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_REP_ROLL,
921315a1350SMichael S. Tsirkin .correctable = true,
922315a1350SMichael S. Tsirkin }, {
923315a1350SMichael S. Tsirkin .name = "REP_TIMER",
924315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_REP_TIMER,
925315a1350SMichael S. Tsirkin .correctable = true,
926315a1350SMichael S. Tsirkin }, {
927315a1350SMichael S. Tsirkin .name = "ADV_NONFATAL",
928315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_ADV_NONFATAL,
929315a1350SMichael S. Tsirkin .correctable = true,
930315a1350SMichael S. Tsirkin }, {
931315a1350SMichael S. Tsirkin .name = "INTERNAL",
932315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_INTERNAL,
933315a1350SMichael S. Tsirkin .correctable = true,
934315a1350SMichael S. Tsirkin }, {
935315a1350SMichael S. Tsirkin .name = "HL_OVERFLOW",
936315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_HL_OVERFLOW,
937315a1350SMichael S. Tsirkin .correctable = true,
938315a1350SMichael S. Tsirkin },
939315a1350SMichael S. Tsirkin };
940315a1350SMichael S. Tsirkin
pcie_aer_parse_error_string(const char * error_name,uint32_t * status,bool * correctable)941d0e67298SMarkus Armbruster int pcie_aer_parse_error_string(const char *error_name,
942315a1350SMichael S. Tsirkin uint32_t *status, bool *correctable)
943315a1350SMichael S. Tsirkin {
944315a1350SMichael S. Tsirkin int i;
945315a1350SMichael S. Tsirkin
946315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(pcie_aer_error_list); i++) {
947315a1350SMichael S. Tsirkin const PCIEAERErrorName *e = &pcie_aer_error_list[i];
948315a1350SMichael S. Tsirkin if (strcmp(error_name, e->name)) {
949315a1350SMichael S. Tsirkin continue;
950315a1350SMichael S. Tsirkin }
951315a1350SMichael S. Tsirkin
952315a1350SMichael S. Tsirkin *status = e->val;
953315a1350SMichael S. Tsirkin *correctable = e->correctable;
954315a1350SMichael S. Tsirkin return 0;
955315a1350SMichael S. Tsirkin }
956315a1350SMichael S. Tsirkin return -EINVAL;
957315a1350SMichael S. Tsirkin }
958