1315a1350SMichael S. Tsirkin /* 2315a1350SMichael S. Tsirkin * pcie_aer.c 3315a1350SMichael S. Tsirkin * 4315a1350SMichael S. Tsirkin * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5315a1350SMichael S. Tsirkin * VA Linux Systems Japan K.K. 6315a1350SMichael S. Tsirkin * 7315a1350SMichael S. Tsirkin * This program is free software; you can redistribute it and/or modify 8315a1350SMichael S. Tsirkin * it under the terms of the GNU General Public License as published by 9315a1350SMichael S. Tsirkin * the Free Software Foundation; either version 2 of the License, or 10315a1350SMichael S. Tsirkin * (at your option) any later version. 11315a1350SMichael S. Tsirkin * 12315a1350SMichael S. Tsirkin * This program is distributed in the hope that it will be useful, 13315a1350SMichael S. Tsirkin * but WITHOUT ANY WARRANTY; without even the implied warranty of 14315a1350SMichael S. Tsirkin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15315a1350SMichael S. Tsirkin * GNU General Public License for more details. 16315a1350SMichael S. Tsirkin * 17315a1350SMichael S. Tsirkin * You should have received a copy of the GNU General Public License along 18315a1350SMichael S. Tsirkin * with this program; if not, see <http://www.gnu.org/licenses/>. 19315a1350SMichael S. Tsirkin */ 20315a1350SMichael S. Tsirkin 21315a1350SMichael S. Tsirkin #include "sysemu.h" 22315a1350SMichael S. Tsirkin #include "qemu-objects.h" 23315a1350SMichael S. Tsirkin #include "monitor.h" 24c759b24fSMichael S. Tsirkin #include "hw/pci/pci_bridge.h" 25c759b24fSMichael S. Tsirkin #include "hw/pci/pcie.h" 26c759b24fSMichael S. Tsirkin #include "hw/pci/msix.h" 27c759b24fSMichael S. Tsirkin #include "hw/pci/msi.h" 28*06aac7bdSMichael S. Tsirkin #include "hw/pci/pci_bus.h" 29c759b24fSMichael S. Tsirkin #include "hw/pci/pcie_regs.h" 30315a1350SMichael S. Tsirkin 31315a1350SMichael S. Tsirkin //#define DEBUG_PCIE 32315a1350SMichael S. Tsirkin #ifdef DEBUG_PCIE 33315a1350SMichael S. Tsirkin # define PCIE_DPRINTF(fmt, ...) \ 34315a1350SMichael S. Tsirkin fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 35315a1350SMichael S. Tsirkin #else 36315a1350SMichael S. Tsirkin # define PCIE_DPRINTF(fmt, ...) do {} while (0) 37315a1350SMichael S. Tsirkin #endif 38315a1350SMichael S. Tsirkin #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 39315a1350SMichael S. Tsirkin PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 40315a1350SMichael S. Tsirkin 41315a1350SMichael S. Tsirkin #define PCI_ERR_SRC_COR_OFFS 0 42315a1350SMichael S. Tsirkin #define PCI_ERR_SRC_UNCOR_OFFS 2 43315a1350SMichael S. Tsirkin 44315a1350SMichael S. Tsirkin /* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */ 45315a1350SMichael S. Tsirkin static uint32_t pcie_aer_uncor_default_severity(uint32_t status) 46315a1350SMichael S. Tsirkin { 47315a1350SMichael S. Tsirkin switch (status) { 48315a1350SMichael S. Tsirkin case PCI_ERR_UNC_INTN: 49315a1350SMichael S. Tsirkin case PCI_ERR_UNC_DLP: 50315a1350SMichael S. Tsirkin case PCI_ERR_UNC_SDN: 51315a1350SMichael S. Tsirkin case PCI_ERR_UNC_RX_OVER: 52315a1350SMichael S. Tsirkin case PCI_ERR_UNC_FCP: 53315a1350SMichael S. Tsirkin case PCI_ERR_UNC_MALF_TLP: 54315a1350SMichael S. Tsirkin return PCI_ERR_ROOT_CMD_FATAL_EN; 55315a1350SMichael S. Tsirkin case PCI_ERR_UNC_POISON_TLP: 56315a1350SMichael S. Tsirkin case PCI_ERR_UNC_ECRC: 57315a1350SMichael S. Tsirkin case PCI_ERR_UNC_UNSUP: 58315a1350SMichael S. Tsirkin case PCI_ERR_UNC_COMP_TIME: 59315a1350SMichael S. Tsirkin case PCI_ERR_UNC_COMP_ABORT: 60315a1350SMichael S. Tsirkin case PCI_ERR_UNC_UNX_COMP: 61315a1350SMichael S. Tsirkin case PCI_ERR_UNC_ACSV: 62315a1350SMichael S. Tsirkin case PCI_ERR_UNC_MCBTLP: 63315a1350SMichael S. Tsirkin case PCI_ERR_UNC_ATOP_EBLOCKED: 64315a1350SMichael S. Tsirkin case PCI_ERR_UNC_TLP_PRF_BLOCKED: 65315a1350SMichael S. Tsirkin return PCI_ERR_ROOT_CMD_NONFATAL_EN; 66315a1350SMichael S. Tsirkin default: 67315a1350SMichael S. Tsirkin abort(); 68315a1350SMichael S. Tsirkin break; 69315a1350SMichael S. Tsirkin } 70315a1350SMichael S. Tsirkin return PCI_ERR_ROOT_CMD_FATAL_EN; 71315a1350SMichael S. Tsirkin } 72315a1350SMichael S. Tsirkin 73315a1350SMichael S. Tsirkin static int aer_log_add_err(PCIEAERLog *aer_log, const PCIEAERErr *err) 74315a1350SMichael S. Tsirkin { 75315a1350SMichael S. Tsirkin if (aer_log->log_num == aer_log->log_max) { 76315a1350SMichael S. Tsirkin return -1; 77315a1350SMichael S. Tsirkin } 78315a1350SMichael S. Tsirkin memcpy(&aer_log->log[aer_log->log_num], err, sizeof *err); 79315a1350SMichael S. Tsirkin aer_log->log_num++; 80315a1350SMichael S. Tsirkin return 0; 81315a1350SMichael S. Tsirkin } 82315a1350SMichael S. Tsirkin 83315a1350SMichael S. Tsirkin static void aer_log_del_err(PCIEAERLog *aer_log, PCIEAERErr *err) 84315a1350SMichael S. Tsirkin { 85315a1350SMichael S. Tsirkin assert(aer_log->log_num); 86315a1350SMichael S. Tsirkin *err = aer_log->log[0]; 87315a1350SMichael S. Tsirkin aer_log->log_num--; 88315a1350SMichael S. Tsirkin memmove(&aer_log->log[0], &aer_log->log[1], 89315a1350SMichael S. Tsirkin aer_log->log_num * sizeof *err); 90315a1350SMichael S. Tsirkin } 91315a1350SMichael S. Tsirkin 92315a1350SMichael S. Tsirkin static void aer_log_clear_all_err(PCIEAERLog *aer_log) 93315a1350SMichael S. Tsirkin { 94315a1350SMichael S. Tsirkin aer_log->log_num = 0; 95315a1350SMichael S. Tsirkin } 96315a1350SMichael S. Tsirkin 97315a1350SMichael S. Tsirkin int pcie_aer_init(PCIDevice *dev, uint16_t offset) 98315a1350SMichael S. Tsirkin { 99315a1350SMichael S. Tsirkin PCIExpressDevice *exp; 100315a1350SMichael S. Tsirkin 101315a1350SMichael S. Tsirkin pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER, 102315a1350SMichael S. Tsirkin offset, PCI_ERR_SIZEOF); 103315a1350SMichael S. Tsirkin exp = &dev->exp; 104315a1350SMichael S. Tsirkin exp->aer_cap = offset; 105315a1350SMichael S. Tsirkin 106315a1350SMichael S. Tsirkin /* log_max is property */ 107315a1350SMichael S. Tsirkin if (dev->exp.aer_log.log_max == PCIE_AER_LOG_MAX_UNSET) { 108315a1350SMichael S. Tsirkin dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT; 109315a1350SMichael S. Tsirkin } 110315a1350SMichael S. Tsirkin /* clip down the value to avoid unreasobale memory usage */ 111315a1350SMichael S. Tsirkin if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) { 112315a1350SMichael S. Tsirkin return -EINVAL; 113315a1350SMichael S. Tsirkin } 114315a1350SMichael S. Tsirkin dev->exp.aer_log.log = g_malloc0(sizeof dev->exp.aer_log.log[0] * 115315a1350SMichael S. Tsirkin dev->exp.aer_log.log_max); 116315a1350SMichael S. Tsirkin 117315a1350SMichael S. Tsirkin pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, 118315a1350SMichael S. Tsirkin PCI_ERR_UNC_SUPPORTED); 119315a1350SMichael S. Tsirkin 120315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, 121315a1350SMichael S. Tsirkin PCI_ERR_UNC_SEVERITY_DEFAULT); 122315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER, 123315a1350SMichael S. Tsirkin PCI_ERR_UNC_SUPPORTED); 124315a1350SMichael S. Tsirkin 125315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS, 126315a1350SMichael S. Tsirkin PCI_ERR_COR_STATUS); 127315a1350SMichael S. Tsirkin 128315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_COR_MASK, 129315a1350SMichael S. Tsirkin PCI_ERR_COR_MASK_DEFAULT); 130315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK, 131315a1350SMichael S. Tsirkin PCI_ERR_COR_SUPPORTED); 132315a1350SMichael S. Tsirkin 133315a1350SMichael S. Tsirkin /* capabilities and control. multiple header logging is supported */ 134315a1350SMichael S. Tsirkin if (dev->exp.aer_log.log_max > 0) { 135315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_CAP, 136315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC | 137315a1350SMichael S. Tsirkin PCI_ERR_CAP_MHRC); 138315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_CAP, 139315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE | 140315a1350SMichael S. Tsirkin PCI_ERR_CAP_MHRE); 141315a1350SMichael S. Tsirkin } else { 142315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_CAP, 143315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC); 144315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_CAP, 145315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 146315a1350SMichael S. Tsirkin } 147315a1350SMichael S. Tsirkin 148315a1350SMichael S. Tsirkin switch (pcie_cap_get_type(dev)) { 149315a1350SMichael S. Tsirkin case PCI_EXP_TYPE_ROOT_PORT: 150315a1350SMichael S. Tsirkin /* this case will be set by pcie_aer_root_init() */ 151315a1350SMichael S. Tsirkin /* fallthrough */ 152315a1350SMichael S. Tsirkin case PCI_EXP_TYPE_DOWNSTREAM: 153315a1350SMichael S. Tsirkin case PCI_EXP_TYPE_UPSTREAM: 154315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL, 155315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_SERR); 156315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS, 157315a1350SMichael S. Tsirkin PCI_SEC_STATUS_RCV_SYSTEM_ERROR); 158315a1350SMichael S. Tsirkin break; 159315a1350SMichael S. Tsirkin default: 160315a1350SMichael S. Tsirkin /* nothing */ 161315a1350SMichael S. Tsirkin break; 162315a1350SMichael S. Tsirkin } 163315a1350SMichael S. Tsirkin return 0; 164315a1350SMichael S. Tsirkin } 165315a1350SMichael S. Tsirkin 166315a1350SMichael S. Tsirkin void pcie_aer_exit(PCIDevice *dev) 167315a1350SMichael S. Tsirkin { 168315a1350SMichael S. Tsirkin g_free(dev->exp.aer_log.log); 169315a1350SMichael S. Tsirkin } 170315a1350SMichael S. Tsirkin 171315a1350SMichael S. Tsirkin static void pcie_aer_update_uncor_status(PCIDevice *dev) 172315a1350SMichael S. Tsirkin { 173315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 174315a1350SMichael S. Tsirkin PCIEAERLog *aer_log = &dev->exp.aer_log; 175315a1350SMichael S. Tsirkin 176315a1350SMichael S. Tsirkin uint16_t i; 177315a1350SMichael S. Tsirkin for (i = 0; i < aer_log->log_num; i++) { 178315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(aer_cap + PCI_ERR_UNCOR_STATUS, 179315a1350SMichael S. Tsirkin dev->exp.aer_log.log[i].status); 180315a1350SMichael S. Tsirkin } 181315a1350SMichael S. Tsirkin } 182315a1350SMichael S. Tsirkin 183315a1350SMichael S. Tsirkin /* 184315a1350SMichael S. Tsirkin * return value: 185315a1350SMichael S. Tsirkin * true: error message needs to be sent up 186315a1350SMichael S. Tsirkin * false: error message is masked 187315a1350SMichael S. Tsirkin * 188315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control 189315a1350SMichael S. Tsirkin * Figure 6-3 190315a1350SMichael S. Tsirkin * all pci express devices part 191315a1350SMichael S. Tsirkin */ 192315a1350SMichael S. Tsirkin static bool 193315a1350SMichael S. Tsirkin pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg) 194315a1350SMichael S. Tsirkin { 195315a1350SMichael S. Tsirkin if (!(pcie_aer_msg_is_uncor(msg) && 196315a1350SMichael S. Tsirkin (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) { 197315a1350SMichael S. Tsirkin return false; 198315a1350SMichael S. Tsirkin } 199315a1350SMichael S. Tsirkin 200315a1350SMichael S. Tsirkin /* Signaled System Error 201315a1350SMichael S. Tsirkin * 202315a1350SMichael S. Tsirkin * 7.5.1.1 Command register 203315a1350SMichael S. Tsirkin * Bit 8 SERR# Enable 204315a1350SMichael S. Tsirkin * 205315a1350SMichael S. Tsirkin * When Set, this bit enables reporting of Non-fatal and Fatal 206315a1350SMichael S. Tsirkin * errors detected by the Function to the Root Complex. Note that 207315a1350SMichael S. Tsirkin * errors are reported if enabled either through this bit or through 208315a1350SMichael S. Tsirkin * the PCI Express specific bits in the Device Control register (see 209315a1350SMichael S. Tsirkin * Section 7.8.4). 210315a1350SMichael S. Tsirkin */ 211315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->config + PCI_STATUS, 212315a1350SMichael S. Tsirkin PCI_STATUS_SIG_SYSTEM_ERROR); 213315a1350SMichael S. Tsirkin 214315a1350SMichael S. Tsirkin if (!(msg->severity & 215315a1350SMichael S. Tsirkin pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL))) { 216315a1350SMichael S. Tsirkin return false; 217315a1350SMichael S. Tsirkin } 218315a1350SMichael S. Tsirkin 219315a1350SMichael S. Tsirkin /* send up error message */ 220315a1350SMichael S. Tsirkin return true; 221315a1350SMichael S. Tsirkin } 222315a1350SMichael S. Tsirkin 223315a1350SMichael S. Tsirkin /* 224315a1350SMichael S. Tsirkin * return value: 225315a1350SMichael S. Tsirkin * true: error message is sent up 226315a1350SMichael S. Tsirkin * false: error message is masked 227315a1350SMichael S. Tsirkin * 228315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control 229315a1350SMichael S. Tsirkin * Figure 6-3 230315a1350SMichael S. Tsirkin * virtual pci bridge part 231315a1350SMichael S. Tsirkin */ 232315a1350SMichael S. Tsirkin static bool pcie_aer_msg_vbridge(PCIDevice *dev, const PCIEAERMsg *msg) 233315a1350SMichael S. Tsirkin { 234315a1350SMichael S. Tsirkin uint16_t bridge_control = pci_get_word(dev->config + PCI_BRIDGE_CONTROL); 235315a1350SMichael S. Tsirkin 236315a1350SMichael S. Tsirkin if (pcie_aer_msg_is_uncor(msg)) { 237315a1350SMichael S. Tsirkin /* Received System Error */ 238315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->config + PCI_SEC_STATUS, 239315a1350SMichael S. Tsirkin PCI_SEC_STATUS_RCV_SYSTEM_ERROR); 240315a1350SMichael S. Tsirkin } 241315a1350SMichael S. Tsirkin 242315a1350SMichael S. Tsirkin if (!(bridge_control & PCI_BRIDGE_CTL_SERR)) { 243315a1350SMichael S. Tsirkin return false; 244315a1350SMichael S. Tsirkin } 245315a1350SMichael S. Tsirkin return true; 246315a1350SMichael S. Tsirkin } 247315a1350SMichael S. Tsirkin 248315a1350SMichael S. Tsirkin void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector) 249315a1350SMichael S. Tsirkin { 250315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 251315a1350SMichael S. Tsirkin assert(vector < PCI_ERR_ROOT_IRQ_MAX); 252315a1350SMichael S. Tsirkin pci_long_test_and_clear_mask(aer_cap + PCI_ERR_ROOT_STATUS, 253315a1350SMichael S. Tsirkin PCI_ERR_ROOT_IRQ); 254315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(aer_cap + PCI_ERR_ROOT_STATUS, 255315a1350SMichael S. Tsirkin vector << PCI_ERR_ROOT_IRQ_SHIFT); 256315a1350SMichael S. Tsirkin } 257315a1350SMichael S. Tsirkin 258315a1350SMichael S. Tsirkin static unsigned int pcie_aer_root_get_vector(PCIDevice *dev) 259315a1350SMichael S. Tsirkin { 260315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 261315a1350SMichael S. Tsirkin uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); 262315a1350SMichael S. Tsirkin return (root_status & PCI_ERR_ROOT_IRQ) >> PCI_ERR_ROOT_IRQ_SHIFT; 263315a1350SMichael S. Tsirkin } 264315a1350SMichael S. Tsirkin 265315a1350SMichael S. Tsirkin /* Given a status register, get corresponding bits in the command register */ 266315a1350SMichael S. Tsirkin static uint32_t pcie_aer_status_to_cmd(uint32_t status) 267315a1350SMichael S. Tsirkin { 268315a1350SMichael S. Tsirkin uint32_t cmd = 0; 269315a1350SMichael S. Tsirkin if (status & PCI_ERR_ROOT_COR_RCV) { 270315a1350SMichael S. Tsirkin cmd |= PCI_ERR_ROOT_CMD_COR_EN; 271315a1350SMichael S. Tsirkin } 272315a1350SMichael S. Tsirkin if (status & PCI_ERR_ROOT_NONFATAL_RCV) { 273315a1350SMichael S. Tsirkin cmd |= PCI_ERR_ROOT_CMD_NONFATAL_EN; 274315a1350SMichael S. Tsirkin } 275315a1350SMichael S. Tsirkin if (status & PCI_ERR_ROOT_FATAL_RCV) { 276315a1350SMichael S. Tsirkin cmd |= PCI_ERR_ROOT_CMD_FATAL_EN; 277315a1350SMichael S. Tsirkin } 278315a1350SMichael S. Tsirkin return cmd; 279315a1350SMichael S. Tsirkin } 280315a1350SMichael S. Tsirkin 281315a1350SMichael S. Tsirkin static void pcie_aer_root_notify(PCIDevice *dev) 282315a1350SMichael S. Tsirkin { 283315a1350SMichael S. Tsirkin if (msix_enabled(dev)) { 284315a1350SMichael S. Tsirkin msix_notify(dev, pcie_aer_root_get_vector(dev)); 285315a1350SMichael S. Tsirkin } else if (msi_enabled(dev)) { 286315a1350SMichael S. Tsirkin msi_notify(dev, pcie_aer_root_get_vector(dev)); 287315a1350SMichael S. Tsirkin } else { 288315a1350SMichael S. Tsirkin qemu_set_irq(dev->irq[dev->exp.aer_intx], 1); 289315a1350SMichael S. Tsirkin } 290315a1350SMichael S. Tsirkin } 291315a1350SMichael S. Tsirkin 292315a1350SMichael S. Tsirkin /* 293315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control 294315a1350SMichael S. Tsirkin * Figure 6-3 295315a1350SMichael S. Tsirkin * root port part 296315a1350SMichael S. Tsirkin */ 297315a1350SMichael S. Tsirkin static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg) 298315a1350SMichael S. Tsirkin { 299315a1350SMichael S. Tsirkin uint16_t cmd; 300315a1350SMichael S. Tsirkin uint8_t *aer_cap; 301315a1350SMichael S. Tsirkin uint32_t root_cmd; 302315a1350SMichael S. Tsirkin uint32_t root_status, prev_status; 303315a1350SMichael S. Tsirkin 304315a1350SMichael S. Tsirkin cmd = pci_get_word(dev->config + PCI_COMMAND); 305315a1350SMichael S. Tsirkin aer_cap = dev->config + dev->exp.aer_cap; 306315a1350SMichael S. Tsirkin root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); 307315a1350SMichael S. Tsirkin prev_status = root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); 308315a1350SMichael S. Tsirkin 309315a1350SMichael S. Tsirkin if (cmd & PCI_COMMAND_SERR) { 310315a1350SMichael S. Tsirkin /* System Error. 311315a1350SMichael S. Tsirkin * 312315a1350SMichael S. Tsirkin * The way to report System Error is platform specific and 313315a1350SMichael S. Tsirkin * it isn't implemented in qemu right now. 314315a1350SMichael S. Tsirkin * So just discard the error for now. 315315a1350SMichael S. Tsirkin * OS which cares of aer would receive errors via 316315a1350SMichael S. Tsirkin * native aer mechanims, so this wouldn't matter. 317315a1350SMichael S. Tsirkin */ 318315a1350SMichael S. Tsirkin } 319315a1350SMichael S. Tsirkin 320315a1350SMichael S. Tsirkin /* Errro Message Received: Root Error Status register */ 321315a1350SMichael S. Tsirkin switch (msg->severity) { 322315a1350SMichael S. Tsirkin case PCI_ERR_ROOT_CMD_COR_EN: 323315a1350SMichael S. Tsirkin if (root_status & PCI_ERR_ROOT_COR_RCV) { 324315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_MULTI_COR_RCV; 325315a1350SMichael S. Tsirkin } else { 326315a1350SMichael S. Tsirkin pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC + PCI_ERR_SRC_COR_OFFS, 327315a1350SMichael S. Tsirkin msg->source_id); 328315a1350SMichael S. Tsirkin } 329315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_COR_RCV; 330315a1350SMichael S. Tsirkin break; 331315a1350SMichael S. Tsirkin case PCI_ERR_ROOT_CMD_NONFATAL_EN: 332315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_NONFATAL_RCV; 333315a1350SMichael S. Tsirkin break; 334315a1350SMichael S. Tsirkin case PCI_ERR_ROOT_CMD_FATAL_EN: 335315a1350SMichael S. Tsirkin if (!(root_status & PCI_ERR_ROOT_UNCOR_RCV)) { 336315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_FIRST_FATAL; 337315a1350SMichael S. Tsirkin } 338315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_FATAL_RCV; 339315a1350SMichael S. Tsirkin break; 340315a1350SMichael S. Tsirkin default: 341315a1350SMichael S. Tsirkin abort(); 342315a1350SMichael S. Tsirkin break; 343315a1350SMichael S. Tsirkin } 344315a1350SMichael S. Tsirkin if (pcie_aer_msg_is_uncor(msg)) { 345315a1350SMichael S. Tsirkin if (root_status & PCI_ERR_ROOT_UNCOR_RCV) { 346315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV; 347315a1350SMichael S. Tsirkin } else { 348315a1350SMichael S. Tsirkin pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC + 349315a1350SMichael S. Tsirkin PCI_ERR_SRC_UNCOR_OFFS, msg->source_id); 350315a1350SMichael S. Tsirkin } 351315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_UNCOR_RCV; 352315a1350SMichael S. Tsirkin } 353315a1350SMichael S. Tsirkin pci_set_long(aer_cap + PCI_ERR_ROOT_STATUS, root_status); 354315a1350SMichael S. Tsirkin 355315a1350SMichael S. Tsirkin /* 6.2.4.1.2 Interrupt Generation */ 356315a1350SMichael S. Tsirkin /* All the above did was set some bits in the status register. 357315a1350SMichael S. Tsirkin * Specifically these that match message severity. 358315a1350SMichael S. Tsirkin * The below code relies on this fact. */ 359315a1350SMichael S. Tsirkin if (!(root_cmd & msg->severity) || 360315a1350SMichael S. Tsirkin (pcie_aer_status_to_cmd(prev_status) & root_cmd)) { 361315a1350SMichael S. Tsirkin /* Condition is not being set or was already true so nothing to do. */ 362315a1350SMichael S. Tsirkin return; 363315a1350SMichael S. Tsirkin } 364315a1350SMichael S. Tsirkin 365315a1350SMichael S. Tsirkin pcie_aer_root_notify(dev); 366315a1350SMichael S. Tsirkin } 367315a1350SMichael S. Tsirkin 368315a1350SMichael S. Tsirkin /* 369315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control Figure 6-3 370315a1350SMichael S. Tsirkin * 371315a1350SMichael S. Tsirkin * Walk up the bus tree from the device, propagate the error message. 372315a1350SMichael S. Tsirkin */ 373315a1350SMichael S. Tsirkin static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg) 374315a1350SMichael S. Tsirkin { 375315a1350SMichael S. Tsirkin uint8_t type; 376315a1350SMichael S. Tsirkin 377315a1350SMichael S. Tsirkin while (dev) { 378315a1350SMichael S. Tsirkin if (!pci_is_express(dev)) { 379315a1350SMichael S. Tsirkin /* just ignore it */ 380315a1350SMichael S. Tsirkin /* TODO: Shouldn't we set PCI_STATUS_SIG_SYSTEM_ERROR? 381315a1350SMichael S. Tsirkin * Consider e.g. a PCI bridge above a PCI Express device. */ 382315a1350SMichael S. Tsirkin return; 383315a1350SMichael S. Tsirkin } 384315a1350SMichael S. Tsirkin 385315a1350SMichael S. Tsirkin type = pcie_cap_get_type(dev); 386315a1350SMichael S. Tsirkin if ((type == PCI_EXP_TYPE_ROOT_PORT || 387315a1350SMichael S. Tsirkin type == PCI_EXP_TYPE_UPSTREAM || 388315a1350SMichael S. Tsirkin type == PCI_EXP_TYPE_DOWNSTREAM) && 389315a1350SMichael S. Tsirkin !pcie_aer_msg_vbridge(dev, msg)) { 390315a1350SMichael S. Tsirkin return; 391315a1350SMichael S. Tsirkin } 392315a1350SMichael S. Tsirkin if (!pcie_aer_msg_alldev(dev, msg)) { 393315a1350SMichael S. Tsirkin return; 394315a1350SMichael S. Tsirkin } 395315a1350SMichael S. Tsirkin if (type == PCI_EXP_TYPE_ROOT_PORT) { 396315a1350SMichael S. Tsirkin pcie_aer_msg_root_port(dev, msg); 397315a1350SMichael S. Tsirkin /* Root port can notify system itself, 398315a1350SMichael S. Tsirkin or send the error message to root complex event collector. */ 399315a1350SMichael S. Tsirkin /* 400315a1350SMichael S. Tsirkin * if root port is associated with an event collector, 401315a1350SMichael S. Tsirkin * return the root complex event collector here. 402315a1350SMichael S. Tsirkin * For now root complex event collector isn't supported. 403315a1350SMichael S. Tsirkin */ 404315a1350SMichael S. Tsirkin return; 405315a1350SMichael S. Tsirkin } 406315a1350SMichael S. Tsirkin dev = pci_bridge_get_device(dev->bus); 407315a1350SMichael S. Tsirkin } 408315a1350SMichael S. Tsirkin } 409315a1350SMichael S. Tsirkin 410315a1350SMichael S. Tsirkin static void pcie_aer_update_log(PCIDevice *dev, const PCIEAERErr *err) 411315a1350SMichael S. Tsirkin { 412315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 413315a1350SMichael S. Tsirkin uint8_t first_bit = ffs(err->status) - 1; 414315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); 415315a1350SMichael S. Tsirkin int i; 416315a1350SMichael S. Tsirkin 417315a1350SMichael S. Tsirkin assert(err->status); 418315a1350SMichael S. Tsirkin assert(!(err->status & (err->status - 1))); 419315a1350SMichael S. Tsirkin 420315a1350SMichael S. Tsirkin errcap &= ~(PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP); 421315a1350SMichael S. Tsirkin errcap |= PCI_ERR_CAP_FEP(first_bit); 422315a1350SMichael S. Tsirkin 423315a1350SMichael S. Tsirkin if (err->flags & PCIE_AER_ERR_HEADER_VALID) { 424315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(err->header); ++i) { 425315a1350SMichael S. Tsirkin /* 7.10.8 Header Log Register */ 426315a1350SMichael S. Tsirkin uint8_t *header_log = 427315a1350SMichael S. Tsirkin aer_cap + PCI_ERR_HEADER_LOG + i * sizeof err->header[0]; 428315a1350SMichael S. Tsirkin cpu_to_be32wu((uint32_t*)header_log, err->header[i]); 429315a1350SMichael S. Tsirkin } 430315a1350SMichael S. Tsirkin } else { 431315a1350SMichael S. Tsirkin assert(!(err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT)); 432315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE); 433315a1350SMichael S. Tsirkin } 434315a1350SMichael S. Tsirkin 435315a1350SMichael S. Tsirkin if ((err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT) && 436315a1350SMichael S. Tsirkin (pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) & 437315a1350SMichael S. Tsirkin PCI_EXP_DEVCAP2_EETLPP)) { 438315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) { 439315a1350SMichael S. Tsirkin /* 7.10.12 tlp prefix log register */ 440315a1350SMichael S. Tsirkin uint8_t *prefix_log = 441315a1350SMichael S. Tsirkin aer_cap + PCI_ERR_TLP_PREFIX_LOG + i * sizeof err->prefix[0]; 442315a1350SMichael S. Tsirkin cpu_to_be32wu((uint32_t*)prefix_log, err->prefix[i]); 443315a1350SMichael S. Tsirkin } 444315a1350SMichael S. Tsirkin errcap |= PCI_ERR_CAP_TLP; 445315a1350SMichael S. Tsirkin } else { 446315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, 447315a1350SMichael S. Tsirkin PCI_ERR_TLP_PREFIX_LOG_SIZE); 448315a1350SMichael S. Tsirkin } 449315a1350SMichael S. Tsirkin pci_set_long(aer_cap + PCI_ERR_CAP, errcap); 450315a1350SMichael S. Tsirkin } 451315a1350SMichael S. Tsirkin 452315a1350SMichael S. Tsirkin static void pcie_aer_clear_log(PCIDevice *dev) 453315a1350SMichael S. Tsirkin { 454315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 455315a1350SMichael S. Tsirkin 456315a1350SMichael S. Tsirkin pci_long_test_and_clear_mask(aer_cap + PCI_ERR_CAP, 457315a1350SMichael S. Tsirkin PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP); 458315a1350SMichael S. Tsirkin 459315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE); 460315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, PCI_ERR_TLP_PREFIX_LOG_SIZE); 461315a1350SMichael S. Tsirkin } 462315a1350SMichael S. Tsirkin 463315a1350SMichael S. Tsirkin static void pcie_aer_clear_error(PCIDevice *dev) 464315a1350SMichael S. Tsirkin { 465315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 466315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); 467315a1350SMichael S. Tsirkin PCIEAERLog *aer_log = &dev->exp.aer_log; 468315a1350SMichael S. Tsirkin PCIEAERErr err; 469315a1350SMichael S. Tsirkin 470315a1350SMichael S. Tsirkin if (!(errcap & PCI_ERR_CAP_MHRE) || !aer_log->log_num) { 471315a1350SMichael S. Tsirkin pcie_aer_clear_log(dev); 472315a1350SMichael S. Tsirkin return; 473315a1350SMichael S. Tsirkin } 474315a1350SMichael S. Tsirkin 475315a1350SMichael S. Tsirkin /* 476315a1350SMichael S. Tsirkin * If more errors are queued, set corresponding bits in uncorrectable 477315a1350SMichael S. Tsirkin * error status. 478315a1350SMichael S. Tsirkin * We emulate uncorrectable error status register as W1CS. 479315a1350SMichael S. Tsirkin * So set bit in uncorrectable error status here again for multiple 480315a1350SMichael S. Tsirkin * error recording support. 481315a1350SMichael S. Tsirkin * 482315a1350SMichael S. Tsirkin * 6.2.4.2 Multiple Error Handling(Advanced Error Reporting Capability) 483315a1350SMichael S. Tsirkin */ 484315a1350SMichael S. Tsirkin pcie_aer_update_uncor_status(dev); 485315a1350SMichael S. Tsirkin 486315a1350SMichael S. Tsirkin aer_log_del_err(aer_log, &err); 487315a1350SMichael S. Tsirkin pcie_aer_update_log(dev, &err); 488315a1350SMichael S. Tsirkin } 489315a1350SMichael S. Tsirkin 490315a1350SMichael S. Tsirkin static int pcie_aer_record_error(PCIDevice *dev, 491315a1350SMichael S. Tsirkin const PCIEAERErr *err) 492315a1350SMichael S. Tsirkin { 493315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 494315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); 495315a1350SMichael S. Tsirkin int fep = PCI_ERR_CAP_FEP(errcap); 496315a1350SMichael S. Tsirkin 497315a1350SMichael S. Tsirkin assert(err->status); 498315a1350SMichael S. Tsirkin assert(!(err->status & (err->status - 1))); 499315a1350SMichael S. Tsirkin 500315a1350SMichael S. Tsirkin if (errcap & PCI_ERR_CAP_MHRE && 501315a1350SMichael S. Tsirkin (pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) { 502315a1350SMichael S. Tsirkin /* Not first error. queue error */ 503315a1350SMichael S. Tsirkin if (aer_log_add_err(&dev->exp.aer_log, err) < 0) { 504315a1350SMichael S. Tsirkin /* overflow */ 505315a1350SMichael S. Tsirkin return -1; 506315a1350SMichael S. Tsirkin } 507315a1350SMichael S. Tsirkin return 0; 508315a1350SMichael S. Tsirkin } 509315a1350SMichael S. Tsirkin 510315a1350SMichael S. Tsirkin pcie_aer_update_log(dev, err); 511315a1350SMichael S. Tsirkin return 0; 512315a1350SMichael S. Tsirkin } 513315a1350SMichael S. Tsirkin 514315a1350SMichael S. Tsirkin typedef struct PCIEAERInject { 515315a1350SMichael S. Tsirkin PCIDevice *dev; 516315a1350SMichael S. Tsirkin uint8_t *aer_cap; 517315a1350SMichael S. Tsirkin const PCIEAERErr *err; 518315a1350SMichael S. Tsirkin uint16_t devctl; 519315a1350SMichael S. Tsirkin uint16_t devsta; 520315a1350SMichael S. Tsirkin uint32_t error_status; 521315a1350SMichael S. Tsirkin bool unsupported_request; 522315a1350SMichael S. Tsirkin bool log_overflow; 523315a1350SMichael S. Tsirkin PCIEAERMsg msg; 524315a1350SMichael S. Tsirkin } PCIEAERInject; 525315a1350SMichael S. Tsirkin 526315a1350SMichael S. Tsirkin static bool pcie_aer_inject_cor_error(PCIEAERInject *inj, 527315a1350SMichael S. Tsirkin uint32_t uncor_status, 528315a1350SMichael S. Tsirkin bool is_advisory_nonfatal) 529315a1350SMichael S. Tsirkin { 530315a1350SMichael S. Tsirkin PCIDevice *dev = inj->dev; 531315a1350SMichael S. Tsirkin 532315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_CED; 533315a1350SMichael S. Tsirkin if (inj->unsupported_request) { 534315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_URD; 535315a1350SMichael S. Tsirkin } 536315a1350SMichael S. Tsirkin pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta); 537315a1350SMichael S. Tsirkin 538315a1350SMichael S. Tsirkin if (inj->aer_cap) { 539315a1350SMichael S. Tsirkin uint32_t mask; 540315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_COR_STATUS, 541315a1350SMichael S. Tsirkin inj->error_status); 542315a1350SMichael S. Tsirkin mask = pci_get_long(inj->aer_cap + PCI_ERR_COR_MASK); 543315a1350SMichael S. Tsirkin if (mask & inj->error_status) { 544315a1350SMichael S. Tsirkin return false; 545315a1350SMichael S. Tsirkin } 546315a1350SMichael S. Tsirkin if (is_advisory_nonfatal) { 547315a1350SMichael S. Tsirkin uint32_t uncor_mask = 548315a1350SMichael S. Tsirkin pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK); 549315a1350SMichael S. Tsirkin if (!(uncor_mask & uncor_status)) { 550315a1350SMichael S. Tsirkin inj->log_overflow = !!pcie_aer_record_error(dev, inj->err); 551315a1350SMichael S. Tsirkin } 552315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, 553315a1350SMichael S. Tsirkin uncor_status); 554315a1350SMichael S. Tsirkin } 555315a1350SMichael S. Tsirkin } 556315a1350SMichael S. Tsirkin 557315a1350SMichael S. Tsirkin if (inj->unsupported_request && !(inj->devctl & PCI_EXP_DEVCTL_URRE)) { 558315a1350SMichael S. Tsirkin return false; 559315a1350SMichael S. Tsirkin } 560315a1350SMichael S. Tsirkin if (!(inj->devctl & PCI_EXP_DEVCTL_CERE)) { 561315a1350SMichael S. Tsirkin return false; 562315a1350SMichael S. Tsirkin } 563315a1350SMichael S. Tsirkin 564315a1350SMichael S. Tsirkin inj->msg.severity = PCI_ERR_ROOT_CMD_COR_EN; 565315a1350SMichael S. Tsirkin return true; 566315a1350SMichael S. Tsirkin } 567315a1350SMichael S. Tsirkin 568315a1350SMichael S. Tsirkin static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal) 569315a1350SMichael S. Tsirkin { 570315a1350SMichael S. Tsirkin PCIDevice *dev = inj->dev; 571315a1350SMichael S. Tsirkin uint16_t cmd; 572315a1350SMichael S. Tsirkin 573315a1350SMichael S. Tsirkin if (is_fatal) { 574315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_FED; 575315a1350SMichael S. Tsirkin } else { 576315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_NFED; 577315a1350SMichael S. Tsirkin } 578315a1350SMichael S. Tsirkin if (inj->unsupported_request) { 579315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_URD; 580315a1350SMichael S. Tsirkin } 581315a1350SMichael S. Tsirkin pci_set_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta); 582315a1350SMichael S. Tsirkin 583315a1350SMichael S. Tsirkin if (inj->aer_cap) { 584315a1350SMichael S. Tsirkin uint32_t mask = pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK); 585315a1350SMichael S. Tsirkin if (mask & inj->error_status) { 586315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, 587315a1350SMichael S. Tsirkin inj->error_status); 588315a1350SMichael S. Tsirkin return false; 589315a1350SMichael S. Tsirkin } 590315a1350SMichael S. Tsirkin 591315a1350SMichael S. Tsirkin inj->log_overflow = !!pcie_aer_record_error(dev, inj->err); 592315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, 593315a1350SMichael S. Tsirkin inj->error_status); 594315a1350SMichael S. Tsirkin } 595315a1350SMichael S. Tsirkin 596315a1350SMichael S. Tsirkin cmd = pci_get_word(dev->config + PCI_COMMAND); 597315a1350SMichael S. Tsirkin if (inj->unsupported_request && 598315a1350SMichael S. Tsirkin !(inj->devctl & PCI_EXP_DEVCTL_URRE) && !(cmd & PCI_COMMAND_SERR)) { 599315a1350SMichael S. Tsirkin return false; 600315a1350SMichael S. Tsirkin } 601315a1350SMichael S. Tsirkin if (is_fatal) { 602315a1350SMichael S. Tsirkin if (!((cmd & PCI_COMMAND_SERR) || 603315a1350SMichael S. Tsirkin (inj->devctl & PCI_EXP_DEVCTL_FERE))) { 604315a1350SMichael S. Tsirkin return false; 605315a1350SMichael S. Tsirkin } 606315a1350SMichael S. Tsirkin inj->msg.severity = PCI_ERR_ROOT_CMD_FATAL_EN; 607315a1350SMichael S. Tsirkin } else { 608315a1350SMichael S. Tsirkin if (!((cmd & PCI_COMMAND_SERR) || 609315a1350SMichael S. Tsirkin (inj->devctl & PCI_EXP_DEVCTL_NFERE))) { 610315a1350SMichael S. Tsirkin return false; 611315a1350SMichael S. Tsirkin } 612315a1350SMichael S. Tsirkin inj->msg.severity = PCI_ERR_ROOT_CMD_NONFATAL_EN; 613315a1350SMichael S. Tsirkin } 614315a1350SMichael S. Tsirkin return true; 615315a1350SMichael S. Tsirkin } 616315a1350SMichael S. Tsirkin 617315a1350SMichael S. Tsirkin /* 618315a1350SMichael S. Tsirkin * non-Function specific error must be recorded in all functions. 619315a1350SMichael S. Tsirkin * It is the responsibility of the caller of this function. 620315a1350SMichael S. Tsirkin * It is also caller's responsibility to determine which function should 621315a1350SMichael S. Tsirkin * report the rerror. 622315a1350SMichael S. Tsirkin * 623315a1350SMichael S. Tsirkin * 6.2.4 Error Logging 624315a1350SMichael S. Tsirkin * 6.2.5 Sqeunce of Device Error Signaling and Logging Operations 625315a1350SMichael S. Tsirkin * table 6-2: Flowchard Showing Sequence of Device Error Signaling and Logging 626315a1350SMichael S. Tsirkin * Operations 627315a1350SMichael S. Tsirkin */ 628315a1350SMichael S. Tsirkin int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err) 629315a1350SMichael S. Tsirkin { 630315a1350SMichael S. Tsirkin uint8_t *aer_cap = NULL; 631315a1350SMichael S. Tsirkin uint16_t devctl = 0; 632315a1350SMichael S. Tsirkin uint16_t devsta = 0; 633315a1350SMichael S. Tsirkin uint32_t error_status = err->status; 634315a1350SMichael S. Tsirkin PCIEAERInject inj; 635315a1350SMichael S. Tsirkin 636315a1350SMichael S. Tsirkin if (!pci_is_express(dev)) { 637315a1350SMichael S. Tsirkin return -ENOSYS; 638315a1350SMichael S. Tsirkin } 639315a1350SMichael S. Tsirkin 640315a1350SMichael S. Tsirkin if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) { 641315a1350SMichael S. Tsirkin error_status &= PCI_ERR_COR_SUPPORTED; 642315a1350SMichael S. Tsirkin } else { 643315a1350SMichael S. Tsirkin error_status &= PCI_ERR_UNC_SUPPORTED; 644315a1350SMichael S. Tsirkin } 645315a1350SMichael S. Tsirkin 646315a1350SMichael S. Tsirkin /* invalid status bit. one and only one bit must be set */ 647315a1350SMichael S. Tsirkin if (!error_status || (error_status & (error_status - 1))) { 648315a1350SMichael S. Tsirkin return -EINVAL; 649315a1350SMichael S. Tsirkin } 650315a1350SMichael S. Tsirkin 651315a1350SMichael S. Tsirkin if (dev->exp.aer_cap) { 652315a1350SMichael S. Tsirkin uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 653315a1350SMichael S. Tsirkin aer_cap = dev->config + dev->exp.aer_cap; 654315a1350SMichael S. Tsirkin devctl = pci_get_long(exp_cap + PCI_EXP_DEVCTL); 655315a1350SMichael S. Tsirkin devsta = pci_get_long(exp_cap + PCI_EXP_DEVSTA); 656315a1350SMichael S. Tsirkin } 657315a1350SMichael S. Tsirkin 658315a1350SMichael S. Tsirkin inj.dev = dev; 659315a1350SMichael S. Tsirkin inj.aer_cap = aer_cap; 660315a1350SMichael S. Tsirkin inj.err = err; 661315a1350SMichael S. Tsirkin inj.devctl = devctl; 662315a1350SMichael S. Tsirkin inj.devsta = devsta; 663315a1350SMichael S. Tsirkin inj.error_status = error_status; 664315a1350SMichael S. Tsirkin inj.unsupported_request = !(err->flags & PCIE_AER_ERR_IS_CORRECTABLE) && 665315a1350SMichael S. Tsirkin err->status == PCI_ERR_UNC_UNSUP; 666315a1350SMichael S. Tsirkin inj.log_overflow = false; 667315a1350SMichael S. Tsirkin 668315a1350SMichael S. Tsirkin if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) { 669315a1350SMichael S. Tsirkin if (!pcie_aer_inject_cor_error(&inj, 0, false)) { 670315a1350SMichael S. Tsirkin return 0; 671315a1350SMichael S. Tsirkin } 672315a1350SMichael S. Tsirkin } else { 673315a1350SMichael S. Tsirkin bool is_fatal = 674315a1350SMichael S. Tsirkin pcie_aer_uncor_default_severity(error_status) == 675315a1350SMichael S. Tsirkin PCI_ERR_ROOT_CMD_FATAL_EN; 676315a1350SMichael S. Tsirkin if (aer_cap) { 677315a1350SMichael S. Tsirkin is_fatal = 678315a1350SMichael S. Tsirkin error_status & pci_get_long(aer_cap + PCI_ERR_UNCOR_SEVER); 679315a1350SMichael S. Tsirkin } 680315a1350SMichael S. Tsirkin if (!is_fatal && (err->flags & PCIE_AER_ERR_MAYBE_ADVISORY)) { 681315a1350SMichael S. Tsirkin inj.error_status = PCI_ERR_COR_ADV_NONFATAL; 682315a1350SMichael S. Tsirkin if (!pcie_aer_inject_cor_error(&inj, error_status, true)) { 683315a1350SMichael S. Tsirkin return 0; 684315a1350SMichael S. Tsirkin } 685315a1350SMichael S. Tsirkin } else { 686315a1350SMichael S. Tsirkin if (!pcie_aer_inject_uncor_error(&inj, is_fatal)) { 687315a1350SMichael S. Tsirkin return 0; 688315a1350SMichael S. Tsirkin } 689315a1350SMichael S. Tsirkin } 690315a1350SMichael S. Tsirkin } 691315a1350SMichael S. Tsirkin 692315a1350SMichael S. Tsirkin /* send up error message */ 693315a1350SMichael S. Tsirkin inj.msg.source_id = err->source_id; 694315a1350SMichael S. Tsirkin pcie_aer_msg(dev, &inj.msg); 695315a1350SMichael S. Tsirkin 696315a1350SMichael S. Tsirkin if (inj.log_overflow) { 697315a1350SMichael S. Tsirkin PCIEAERErr header_log_overflow = { 698315a1350SMichael S. Tsirkin .status = PCI_ERR_COR_HL_OVERFLOW, 699315a1350SMichael S. Tsirkin .flags = PCIE_AER_ERR_IS_CORRECTABLE, 700315a1350SMichael S. Tsirkin }; 701315a1350SMichael S. Tsirkin int ret = pcie_aer_inject_error(dev, &header_log_overflow); 702315a1350SMichael S. Tsirkin assert(!ret); 703315a1350SMichael S. Tsirkin } 704315a1350SMichael S. Tsirkin return 0; 705315a1350SMichael S. Tsirkin } 706315a1350SMichael S. Tsirkin 707315a1350SMichael S. Tsirkin void pcie_aer_write_config(PCIDevice *dev, 708315a1350SMichael S. Tsirkin uint32_t addr, uint32_t val, int len) 709315a1350SMichael S. Tsirkin { 710315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 711315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); 712315a1350SMichael S. Tsirkin uint32_t first_error = 1U << PCI_ERR_CAP_FEP(errcap); 713315a1350SMichael S. Tsirkin uint32_t uncorsta = pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS); 714315a1350SMichael S. Tsirkin 715315a1350SMichael S. Tsirkin /* uncorrectable error */ 716315a1350SMichael S. Tsirkin if (!(uncorsta & first_error)) { 717315a1350SMichael S. Tsirkin /* the bit that corresponds to the first error is cleared */ 718315a1350SMichael S. Tsirkin pcie_aer_clear_error(dev); 719315a1350SMichael S. Tsirkin } else if (errcap & PCI_ERR_CAP_MHRE) { 720315a1350SMichael S. Tsirkin /* When PCI_ERR_CAP_MHRE is enabled and the first error isn't cleared 721315a1350SMichael S. Tsirkin * nothing should happen. So we have to revert the modification to 722315a1350SMichael S. Tsirkin * the register. 723315a1350SMichael S. Tsirkin */ 724315a1350SMichael S. Tsirkin pcie_aer_update_uncor_status(dev); 725315a1350SMichael S. Tsirkin } else { 726315a1350SMichael S. Tsirkin /* capability & control 727315a1350SMichael S. Tsirkin * PCI_ERR_CAP_MHRE might be cleared, so clear of header log. 728315a1350SMichael S. Tsirkin */ 729315a1350SMichael S. Tsirkin aer_log_clear_all_err(&dev->exp.aer_log); 730315a1350SMichael S. Tsirkin } 731315a1350SMichael S. Tsirkin } 732315a1350SMichael S. Tsirkin 733315a1350SMichael S. Tsirkin void pcie_aer_root_init(PCIDevice *dev) 734315a1350SMichael S. Tsirkin { 735315a1350SMichael S. Tsirkin uint16_t pos = dev->exp.aer_cap; 736315a1350SMichael S. Tsirkin 737315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND, 738315a1350SMichael S. Tsirkin PCI_ERR_ROOT_CMD_EN_MASK); 739315a1350SMichael S. Tsirkin pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS, 740315a1350SMichael S. Tsirkin PCI_ERR_ROOT_STATUS_REPORT_MASK); 741315a1350SMichael S. Tsirkin /* PCI_ERR_ROOT_IRQ is RO but devices change it using a 742315a1350SMichael S. Tsirkin * device-specific method. 743315a1350SMichael S. Tsirkin */ 744315a1350SMichael S. Tsirkin pci_set_long(dev->cmask + pos + PCI_ERR_ROOT_STATUS, 745315a1350SMichael S. Tsirkin ~PCI_ERR_ROOT_IRQ); 746315a1350SMichael S. Tsirkin } 747315a1350SMichael S. Tsirkin 748315a1350SMichael S. Tsirkin void pcie_aer_root_reset(PCIDevice *dev) 749315a1350SMichael S. Tsirkin { 750315a1350SMichael S. Tsirkin uint8_t* aer_cap = dev->config + dev->exp.aer_cap; 751315a1350SMichael S. Tsirkin 752315a1350SMichael S. Tsirkin pci_set_long(aer_cap + PCI_ERR_ROOT_COMMAND, 0); 753315a1350SMichael S. Tsirkin 754315a1350SMichael S. Tsirkin /* 755315a1350SMichael S. Tsirkin * Advanced Error Interrupt Message Number in Root Error Status Register 756315a1350SMichael S. Tsirkin * must be updated by chip dependent code because it's chip dependent 757315a1350SMichael S. Tsirkin * which number is used. 758315a1350SMichael S. Tsirkin */ 759315a1350SMichael S. Tsirkin } 760315a1350SMichael S. Tsirkin 761315a1350SMichael S. Tsirkin void pcie_aer_root_write_config(PCIDevice *dev, 762315a1350SMichael S. Tsirkin uint32_t addr, uint32_t val, int len, 763315a1350SMichael S. Tsirkin uint32_t root_cmd_prev) 764315a1350SMichael S. Tsirkin { 765315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 766315a1350SMichael S. Tsirkin uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); 767315a1350SMichael S. Tsirkin uint32_t enabled_cmd = pcie_aer_status_to_cmd(root_status); 768315a1350SMichael S. Tsirkin uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); 769315a1350SMichael S. Tsirkin /* 6.2.4.1.2 Interrupt Generation */ 770315a1350SMichael S. Tsirkin if (!msix_enabled(dev) && !msi_enabled(dev)) { 771315a1350SMichael S. Tsirkin qemu_set_irq(dev->irq[dev->exp.aer_intx], !!(root_cmd & enabled_cmd)); 772315a1350SMichael S. Tsirkin return; 773315a1350SMichael S. Tsirkin } 774315a1350SMichael S. Tsirkin 775315a1350SMichael S. Tsirkin if ((root_cmd_prev & enabled_cmd) || !(root_cmd & enabled_cmd)) { 776315a1350SMichael S. Tsirkin /* Send MSI on transition from false to true. */ 777315a1350SMichael S. Tsirkin return; 778315a1350SMichael S. Tsirkin } 779315a1350SMichael S. Tsirkin 780315a1350SMichael S. Tsirkin pcie_aer_root_notify(dev); 781315a1350SMichael S. Tsirkin } 782315a1350SMichael S. Tsirkin 783315a1350SMichael S. Tsirkin static const VMStateDescription vmstate_pcie_aer_err = { 784315a1350SMichael S. Tsirkin .name = "PCIE_AER_ERROR", 785315a1350SMichael S. Tsirkin .version_id = 1, 786315a1350SMichael S. Tsirkin .minimum_version_id = 1, 787315a1350SMichael S. Tsirkin .minimum_version_id_old = 1, 788315a1350SMichael S. Tsirkin .fields = (VMStateField[]) { 789315a1350SMichael S. Tsirkin VMSTATE_UINT32(status, PCIEAERErr), 790315a1350SMichael S. Tsirkin VMSTATE_UINT16(source_id, PCIEAERErr), 791315a1350SMichael S. Tsirkin VMSTATE_UINT16(flags, PCIEAERErr), 792315a1350SMichael S. Tsirkin VMSTATE_UINT32_ARRAY(header, PCIEAERErr, 4), 793315a1350SMichael S. Tsirkin VMSTATE_UINT32_ARRAY(prefix, PCIEAERErr, 4), 794315a1350SMichael S. Tsirkin VMSTATE_END_OF_LIST() 795315a1350SMichael S. Tsirkin } 796315a1350SMichael S. Tsirkin }; 797315a1350SMichael S. Tsirkin 798315a1350SMichael S. Tsirkin const VMStateDescription vmstate_pcie_aer_log = { 799315a1350SMichael S. Tsirkin .name = "PCIE_AER_ERROR_LOG", 800315a1350SMichael S. Tsirkin .version_id = 1, 801315a1350SMichael S. Tsirkin .minimum_version_id = 1, 802315a1350SMichael S. Tsirkin .minimum_version_id_old = 1, 803315a1350SMichael S. Tsirkin .fields = (VMStateField[]) { 804315a1350SMichael S. Tsirkin VMSTATE_UINT16(log_num, PCIEAERLog), 805315a1350SMichael S. Tsirkin VMSTATE_UINT16(log_max, PCIEAERLog), 806315a1350SMichael S. Tsirkin VMSTATE_STRUCT_VARRAY_POINTER_UINT16(log, PCIEAERLog, log_num, 807315a1350SMichael S. Tsirkin vmstate_pcie_aer_err, PCIEAERErr), 808315a1350SMichael S. Tsirkin VMSTATE_END_OF_LIST() 809315a1350SMichael S. Tsirkin } 810315a1350SMichael S. Tsirkin }; 811315a1350SMichael S. Tsirkin 812315a1350SMichael S. Tsirkin void pcie_aer_inject_error_print(Monitor *mon, const QObject *data) 813315a1350SMichael S. Tsirkin { 814315a1350SMichael S. Tsirkin QDict *qdict; 815315a1350SMichael S. Tsirkin int devfn; 816315a1350SMichael S. Tsirkin assert(qobject_type(data) == QTYPE_QDICT); 817315a1350SMichael S. Tsirkin qdict = qobject_to_qdict(data); 818315a1350SMichael S. Tsirkin 819315a1350SMichael S. Tsirkin devfn = (int)qdict_get_int(qdict, "devfn"); 820315a1350SMichael S. Tsirkin monitor_printf(mon, "OK id: %s domain: %x, bus: %x devfn: %x.%x\n", 821315a1350SMichael S. Tsirkin qdict_get_str(qdict, "id"), 822315a1350SMichael S. Tsirkin (int) qdict_get_int(qdict, "domain"), 823315a1350SMichael S. Tsirkin (int) qdict_get_int(qdict, "bus"), 824315a1350SMichael S. Tsirkin PCI_SLOT(devfn), PCI_FUNC(devfn)); 825315a1350SMichael S. Tsirkin } 826315a1350SMichael S. Tsirkin 827315a1350SMichael S. Tsirkin typedef struct PCIEAERErrorName { 828315a1350SMichael S. Tsirkin const char *name; 829315a1350SMichael S. Tsirkin uint32_t val; 830315a1350SMichael S. Tsirkin bool correctable; 831315a1350SMichael S. Tsirkin } PCIEAERErrorName; 832315a1350SMichael S. Tsirkin 833315a1350SMichael S. Tsirkin /* 834315a1350SMichael S. Tsirkin * AER error name -> value conversion table 835315a1350SMichael S. Tsirkin * This naming scheme is same to linux aer-injection tool. 836315a1350SMichael S. Tsirkin */ 837315a1350SMichael S. Tsirkin static const struct PCIEAERErrorName pcie_aer_error_list[] = { 838315a1350SMichael S. Tsirkin { 839315a1350SMichael S. Tsirkin .name = "TRAIN", 840315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_TRAIN, 841315a1350SMichael S. Tsirkin .correctable = false, 842315a1350SMichael S. Tsirkin }, { 843315a1350SMichael S. Tsirkin .name = "DLP", 844315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_DLP, 845315a1350SMichael S. Tsirkin .correctable = false, 846315a1350SMichael S. Tsirkin }, { 847315a1350SMichael S. Tsirkin .name = "SDN", 848315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_SDN, 849315a1350SMichael S. Tsirkin .correctable = false, 850315a1350SMichael S. Tsirkin }, { 851315a1350SMichael S. Tsirkin .name = "POISON_TLP", 852315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_POISON_TLP, 853315a1350SMichael S. Tsirkin .correctable = false, 854315a1350SMichael S. Tsirkin }, { 855315a1350SMichael S. Tsirkin .name = "FCP", 856315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_FCP, 857315a1350SMichael S. Tsirkin .correctable = false, 858315a1350SMichael S. Tsirkin }, { 859315a1350SMichael S. Tsirkin .name = "COMP_TIME", 860315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_COMP_TIME, 861315a1350SMichael S. Tsirkin .correctable = false, 862315a1350SMichael S. Tsirkin }, { 863315a1350SMichael S. Tsirkin .name = "COMP_ABORT", 864315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_COMP_ABORT, 865315a1350SMichael S. Tsirkin .correctable = false, 866315a1350SMichael S. Tsirkin }, { 867315a1350SMichael S. Tsirkin .name = "UNX_COMP", 868315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_UNX_COMP, 869315a1350SMichael S. Tsirkin .correctable = false, 870315a1350SMichael S. Tsirkin }, { 871315a1350SMichael S. Tsirkin .name = "RX_OVER", 872315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_RX_OVER, 873315a1350SMichael S. Tsirkin .correctable = false, 874315a1350SMichael S. Tsirkin }, { 875315a1350SMichael S. Tsirkin .name = "MALF_TLP", 876315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_MALF_TLP, 877315a1350SMichael S. Tsirkin .correctable = false, 878315a1350SMichael S. Tsirkin }, { 879315a1350SMichael S. Tsirkin .name = "ECRC", 880315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_ECRC, 881315a1350SMichael S. Tsirkin .correctable = false, 882315a1350SMichael S. Tsirkin }, { 883315a1350SMichael S. Tsirkin .name = "UNSUP", 884315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_UNSUP, 885315a1350SMichael S. Tsirkin .correctable = false, 886315a1350SMichael S. Tsirkin }, { 887315a1350SMichael S. Tsirkin .name = "ACSV", 888315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_ACSV, 889315a1350SMichael S. Tsirkin .correctable = false, 890315a1350SMichael S. Tsirkin }, { 891315a1350SMichael S. Tsirkin .name = "INTN", 892315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_INTN, 893315a1350SMichael S. Tsirkin .correctable = false, 894315a1350SMichael S. Tsirkin }, { 895315a1350SMichael S. Tsirkin .name = "MCBTLP", 896315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_MCBTLP, 897315a1350SMichael S. Tsirkin .correctable = false, 898315a1350SMichael S. Tsirkin }, { 899315a1350SMichael S. Tsirkin .name = "ATOP_EBLOCKED", 900315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_ATOP_EBLOCKED, 901315a1350SMichael S. Tsirkin .correctable = false, 902315a1350SMichael S. Tsirkin }, { 903315a1350SMichael S. Tsirkin .name = "TLP_PRF_BLOCKED", 904315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_TLP_PRF_BLOCKED, 905315a1350SMichael S. Tsirkin .correctable = false, 906315a1350SMichael S. Tsirkin }, { 907315a1350SMichael S. Tsirkin .name = "RCVR", 908315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_RCVR, 909315a1350SMichael S. Tsirkin .correctable = true, 910315a1350SMichael S. Tsirkin }, { 911315a1350SMichael S. Tsirkin .name = "BAD_TLP", 912315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_BAD_TLP, 913315a1350SMichael S. Tsirkin .correctable = true, 914315a1350SMichael S. Tsirkin }, { 915315a1350SMichael S. Tsirkin .name = "BAD_DLLP", 916315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_BAD_DLLP, 917315a1350SMichael S. Tsirkin .correctable = true, 918315a1350SMichael S. Tsirkin }, { 919315a1350SMichael S. Tsirkin .name = "REP_ROLL", 920315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_REP_ROLL, 921315a1350SMichael S. Tsirkin .correctable = true, 922315a1350SMichael S. Tsirkin }, { 923315a1350SMichael S. Tsirkin .name = "REP_TIMER", 924315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_REP_TIMER, 925315a1350SMichael S. Tsirkin .correctable = true, 926315a1350SMichael S. Tsirkin }, { 927315a1350SMichael S. Tsirkin .name = "ADV_NONFATAL", 928315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_ADV_NONFATAL, 929315a1350SMichael S. Tsirkin .correctable = true, 930315a1350SMichael S. Tsirkin }, { 931315a1350SMichael S. Tsirkin .name = "INTERNAL", 932315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_INTERNAL, 933315a1350SMichael S. Tsirkin .correctable = true, 934315a1350SMichael S. Tsirkin }, { 935315a1350SMichael S. Tsirkin .name = "HL_OVERFLOW", 936315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_HL_OVERFLOW, 937315a1350SMichael S. Tsirkin .correctable = true, 938315a1350SMichael S. Tsirkin }, 939315a1350SMichael S. Tsirkin }; 940315a1350SMichael S. Tsirkin 941315a1350SMichael S. Tsirkin static int pcie_aer_parse_error_string(const char *error_name, 942315a1350SMichael S. Tsirkin uint32_t *status, bool *correctable) 943315a1350SMichael S. Tsirkin { 944315a1350SMichael S. Tsirkin int i; 945315a1350SMichael S. Tsirkin 946315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(pcie_aer_error_list); i++) { 947315a1350SMichael S. Tsirkin const PCIEAERErrorName *e = &pcie_aer_error_list[i]; 948315a1350SMichael S. Tsirkin if (strcmp(error_name, e->name)) { 949315a1350SMichael S. Tsirkin continue; 950315a1350SMichael S. Tsirkin } 951315a1350SMichael S. Tsirkin 952315a1350SMichael S. Tsirkin *status = e->val; 953315a1350SMichael S. Tsirkin *correctable = e->correctable; 954315a1350SMichael S. Tsirkin return 0; 955315a1350SMichael S. Tsirkin } 956315a1350SMichael S. Tsirkin return -EINVAL; 957315a1350SMichael S. Tsirkin } 958315a1350SMichael S. Tsirkin 959315a1350SMichael S. Tsirkin int do_pcie_aer_inject_error(Monitor *mon, 960315a1350SMichael S. Tsirkin const QDict *qdict, QObject **ret_data) 961315a1350SMichael S. Tsirkin { 962315a1350SMichael S. Tsirkin const char *id = qdict_get_str(qdict, "id"); 963315a1350SMichael S. Tsirkin const char *error_name; 964315a1350SMichael S. Tsirkin uint32_t error_status; 965315a1350SMichael S. Tsirkin bool correctable; 966315a1350SMichael S. Tsirkin PCIDevice *dev; 967315a1350SMichael S. Tsirkin PCIEAERErr err; 968315a1350SMichael S. Tsirkin int ret; 969315a1350SMichael S. Tsirkin 970315a1350SMichael S. Tsirkin ret = pci_qdev_find_device(id, &dev); 971315a1350SMichael S. Tsirkin if (ret < 0) { 972315a1350SMichael S. Tsirkin monitor_printf(mon, 973315a1350SMichael S. Tsirkin "id or pci device path is invalid or device not " 974315a1350SMichael S. Tsirkin "found. %s\n", id); 975315a1350SMichael S. Tsirkin return ret; 976315a1350SMichael S. Tsirkin } 977315a1350SMichael S. Tsirkin if (!pci_is_express(dev)) { 978315a1350SMichael S. Tsirkin monitor_printf(mon, "the device doesn't support pci express. %s\n", 979315a1350SMichael S. Tsirkin id); 980315a1350SMichael S. Tsirkin return -ENOSYS; 981315a1350SMichael S. Tsirkin } 982315a1350SMichael S. Tsirkin 983315a1350SMichael S. Tsirkin error_name = qdict_get_str(qdict, "error_status"); 984315a1350SMichael S. Tsirkin if (pcie_aer_parse_error_string(error_name, &error_status, &correctable)) { 985315a1350SMichael S. Tsirkin char *e = NULL; 986315a1350SMichael S. Tsirkin error_status = strtoul(error_name, &e, 0); 987315a1350SMichael S. Tsirkin correctable = qdict_get_try_bool(qdict, "correctable", 0); 988315a1350SMichael S. Tsirkin if (!e || *e != '\0') { 989315a1350SMichael S. Tsirkin monitor_printf(mon, "invalid error status value. \"%s\"", 990315a1350SMichael S. Tsirkin error_name); 991315a1350SMichael S. Tsirkin return -EINVAL; 992315a1350SMichael S. Tsirkin } 993315a1350SMichael S. Tsirkin } 994315a1350SMichael S. Tsirkin err.status = error_status; 995315a1350SMichael S. Tsirkin err.source_id = (pci_bus_num(dev->bus) << 8) | dev->devfn; 996315a1350SMichael S. Tsirkin 997315a1350SMichael S. Tsirkin err.flags = 0; 998315a1350SMichael S. Tsirkin if (correctable) { 999315a1350SMichael S. Tsirkin err.flags |= PCIE_AER_ERR_IS_CORRECTABLE; 1000315a1350SMichael S. Tsirkin } 1001315a1350SMichael S. Tsirkin if (qdict_get_try_bool(qdict, "advisory_non_fatal", 0)) { 1002315a1350SMichael S. Tsirkin err.flags |= PCIE_AER_ERR_MAYBE_ADVISORY; 1003315a1350SMichael S. Tsirkin } 1004315a1350SMichael S. Tsirkin if (qdict_haskey(qdict, "header0")) { 1005315a1350SMichael S. Tsirkin err.flags |= PCIE_AER_ERR_HEADER_VALID; 1006315a1350SMichael S. Tsirkin } 1007315a1350SMichael S. Tsirkin if (qdict_haskey(qdict, "prefix0")) { 1008315a1350SMichael S. Tsirkin err.flags |= PCIE_AER_ERR_TLP_PREFIX_PRESENT; 1009315a1350SMichael S. Tsirkin } 1010315a1350SMichael S. Tsirkin 1011315a1350SMichael S. Tsirkin err.header[0] = qdict_get_try_int(qdict, "header0", 0); 1012315a1350SMichael S. Tsirkin err.header[1] = qdict_get_try_int(qdict, "header1", 0); 1013315a1350SMichael S. Tsirkin err.header[2] = qdict_get_try_int(qdict, "header2", 0); 1014315a1350SMichael S. Tsirkin err.header[3] = qdict_get_try_int(qdict, "header3", 0); 1015315a1350SMichael S. Tsirkin 1016315a1350SMichael S. Tsirkin err.prefix[0] = qdict_get_try_int(qdict, "prefix0", 0); 1017315a1350SMichael S. Tsirkin err.prefix[1] = qdict_get_try_int(qdict, "prefix1", 0); 1018315a1350SMichael S. Tsirkin err.prefix[2] = qdict_get_try_int(qdict, "prefix2", 0); 1019315a1350SMichael S. Tsirkin err.prefix[3] = qdict_get_try_int(qdict, "prefix3", 0); 1020315a1350SMichael S. Tsirkin 1021315a1350SMichael S. Tsirkin ret = pcie_aer_inject_error(dev, &err); 1022315a1350SMichael S. Tsirkin *ret_data = qobject_from_jsonf("{'id': %s, " 1023315a1350SMichael S. Tsirkin "'domain': %d, 'bus': %d, 'devfn': %d, " 1024315a1350SMichael S. Tsirkin "'ret': %d}", 1025315a1350SMichael S. Tsirkin id, 1026315a1350SMichael S. Tsirkin pci_find_domain(dev->bus), 1027315a1350SMichael S. Tsirkin pci_bus_num(dev->bus), dev->devfn, 1028315a1350SMichael S. Tsirkin ret); 1029315a1350SMichael S. Tsirkin assert(*ret_data); 1030315a1350SMichael S. Tsirkin 1031315a1350SMichael S. Tsirkin return 0; 1032315a1350SMichael S. Tsirkin } 1033