1315a1350SMichael S. Tsirkin /* 2315a1350SMichael S. Tsirkin * pcie_aer.c 3315a1350SMichael S. Tsirkin * 4315a1350SMichael S. Tsirkin * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5315a1350SMichael S. Tsirkin * VA Linux Systems Japan K.K. 6315a1350SMichael S. Tsirkin * 7315a1350SMichael S. Tsirkin * This program is free software; you can redistribute it and/or modify 8315a1350SMichael S. Tsirkin * it under the terms of the GNU General Public License as published by 9315a1350SMichael S. Tsirkin * the Free Software Foundation; either version 2 of the License, or 10315a1350SMichael S. Tsirkin * (at your option) any later version. 11315a1350SMichael S. Tsirkin * 12315a1350SMichael S. Tsirkin * This program is distributed in the hope that it will be useful, 13315a1350SMichael S. Tsirkin * but WITHOUT ANY WARRANTY; without even the implied warranty of 14315a1350SMichael S. Tsirkin * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15315a1350SMichael S. Tsirkin * GNU General Public License for more details. 16315a1350SMichael S. Tsirkin * 17315a1350SMichael S. Tsirkin * You should have received a copy of the GNU General Public License along 18315a1350SMichael S. Tsirkin * with this program; if not, see <http://www.gnu.org/licenses/>. 19315a1350SMichael S. Tsirkin */ 20315a1350SMichael S. Tsirkin 2197d5408fSPeter Maydell #include "qemu/osdep.h" 22d6454270SMarkus Armbruster #include "migration/vmstate.h" 23c759b24fSMichael S. Tsirkin #include "hw/pci/pci_bridge.h" 24c759b24fSMichael S. Tsirkin #include "hw/pci/pcie.h" 25c759b24fSMichael S. Tsirkin #include "hw/pci/msix.h" 26c759b24fSMichael S. Tsirkin #include "hw/pci/msi.h" 2706aac7bdSMichael S. Tsirkin #include "hw/pci/pci_bus.h" 28c759b24fSMichael S. Tsirkin #include "hw/pci/pcie_regs.h" 29d0e67298SMarkus Armbruster #include "pci-internal.h" 30315a1350SMichael S. Tsirkin 31315a1350SMichael S. Tsirkin //#define DEBUG_PCIE 32315a1350SMichael S. Tsirkin #ifdef DEBUG_PCIE 33315a1350SMichael S. Tsirkin # define PCIE_DPRINTF(fmt, ...) \ 34315a1350SMichael S. Tsirkin fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__) 35315a1350SMichael S. Tsirkin #else 36315a1350SMichael S. Tsirkin # define PCIE_DPRINTF(fmt, ...) do {} while (0) 37315a1350SMichael S. Tsirkin #endif 38315a1350SMichael S. Tsirkin #define PCIE_DEV_PRINTF(dev, fmt, ...) \ 39315a1350SMichael S. Tsirkin PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__) 40315a1350SMichael S. Tsirkin 41315a1350SMichael S. Tsirkin #define PCI_ERR_SRC_COR_OFFS 0 42315a1350SMichael S. Tsirkin #define PCI_ERR_SRC_UNCOR_OFFS 2 43315a1350SMichael S. Tsirkin 44315a1350SMichael S. Tsirkin /* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */ 45315a1350SMichael S. Tsirkin static uint32_t pcie_aer_uncor_default_severity(uint32_t status) 46315a1350SMichael S. Tsirkin { 47315a1350SMichael S. Tsirkin switch (status) { 48315a1350SMichael S. Tsirkin case PCI_ERR_UNC_INTN: 49315a1350SMichael S. Tsirkin case PCI_ERR_UNC_DLP: 50315a1350SMichael S. Tsirkin case PCI_ERR_UNC_SDN: 51315a1350SMichael S. Tsirkin case PCI_ERR_UNC_RX_OVER: 52315a1350SMichael S. Tsirkin case PCI_ERR_UNC_FCP: 53315a1350SMichael S. Tsirkin case PCI_ERR_UNC_MALF_TLP: 54315a1350SMichael S. Tsirkin return PCI_ERR_ROOT_CMD_FATAL_EN; 55315a1350SMichael S. Tsirkin case PCI_ERR_UNC_POISON_TLP: 56315a1350SMichael S. Tsirkin case PCI_ERR_UNC_ECRC: 57315a1350SMichael S. Tsirkin case PCI_ERR_UNC_UNSUP: 58315a1350SMichael S. Tsirkin case PCI_ERR_UNC_COMP_TIME: 59315a1350SMichael S. Tsirkin case PCI_ERR_UNC_COMP_ABORT: 60315a1350SMichael S. Tsirkin case PCI_ERR_UNC_UNX_COMP: 61315a1350SMichael S. Tsirkin case PCI_ERR_UNC_ACSV: 62315a1350SMichael S. Tsirkin case PCI_ERR_UNC_MCBTLP: 63315a1350SMichael S. Tsirkin case PCI_ERR_UNC_ATOP_EBLOCKED: 64315a1350SMichael S. Tsirkin case PCI_ERR_UNC_TLP_PRF_BLOCKED: 65315a1350SMichael S. Tsirkin return PCI_ERR_ROOT_CMD_NONFATAL_EN; 66315a1350SMichael S. Tsirkin default: 67315a1350SMichael S. Tsirkin abort(); 68315a1350SMichael S. Tsirkin break; 69315a1350SMichael S. Tsirkin } 70315a1350SMichael S. Tsirkin return PCI_ERR_ROOT_CMD_FATAL_EN; 71315a1350SMichael S. Tsirkin } 72315a1350SMichael S. Tsirkin 73315a1350SMichael S. Tsirkin static int aer_log_add_err(PCIEAERLog *aer_log, const PCIEAERErr *err) 74315a1350SMichael S. Tsirkin { 75315a1350SMichael S. Tsirkin if (aer_log->log_num == aer_log->log_max) { 76315a1350SMichael S. Tsirkin return -1; 77315a1350SMichael S. Tsirkin } 78315a1350SMichael S. Tsirkin memcpy(&aer_log->log[aer_log->log_num], err, sizeof *err); 79315a1350SMichael S. Tsirkin aer_log->log_num++; 80315a1350SMichael S. Tsirkin return 0; 81315a1350SMichael S. Tsirkin } 82315a1350SMichael S. Tsirkin 83315a1350SMichael S. Tsirkin static void aer_log_del_err(PCIEAERLog *aer_log, PCIEAERErr *err) 84315a1350SMichael S. Tsirkin { 85315a1350SMichael S. Tsirkin assert(aer_log->log_num); 86315a1350SMichael S. Tsirkin *err = aer_log->log[0]; 87315a1350SMichael S. Tsirkin aer_log->log_num--; 88315a1350SMichael S. Tsirkin memmove(&aer_log->log[0], &aer_log->log[1], 89315a1350SMichael S. Tsirkin aer_log->log_num * sizeof *err); 90315a1350SMichael S. Tsirkin } 91315a1350SMichael S. Tsirkin 92315a1350SMichael S. Tsirkin static void aer_log_clear_all_err(PCIEAERLog *aer_log) 93315a1350SMichael S. Tsirkin { 94315a1350SMichael S. Tsirkin aer_log->log_num = 0; 95315a1350SMichael S. Tsirkin } 96315a1350SMichael S. Tsirkin 97f18c697bSDou Liyang int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, 98f18c697bSDou Liyang uint16_t size, Error **errp) 99315a1350SMichael S. Tsirkin { 100f18c697bSDou Liyang pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver, 1018d86ada2SChen Fan offset, size); 10233848ceeSCao jin dev->exp.aer_cap = offset; 103315a1350SMichael S. Tsirkin 10433848ceeSCao jin /* clip down the value to avoid unreasonable memory usage */ 105315a1350SMichael S. Tsirkin if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) { 10633848ceeSCao jin error_setg(errp, "Invalid aer_log_max %d. The max number of aer log " 10733848ceeSCao jin "is %d", dev->exp.aer_log.log_max, PCIE_AER_LOG_MAX_LIMIT); 108315a1350SMichael S. Tsirkin return -EINVAL; 109315a1350SMichael S. Tsirkin } 110315a1350SMichael S. Tsirkin dev->exp.aer_log.log = g_malloc0(sizeof dev->exp.aer_log.log[0] * 111315a1350SMichael S. Tsirkin dev->exp.aer_log.log_max); 112315a1350SMichael S. Tsirkin 113315a1350SMichael S. Tsirkin pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, 114315a1350SMichael S. Tsirkin PCI_ERR_UNC_SUPPORTED); 115315a1350SMichael S. Tsirkin 116315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, 117315a1350SMichael S. Tsirkin PCI_ERR_UNC_SEVERITY_DEFAULT); 118315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER, 119315a1350SMichael S. Tsirkin PCI_ERR_UNC_SUPPORTED); 120315a1350SMichael S. Tsirkin 121315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS, 122310e91f7SChen Fan PCI_ERR_COR_SUPPORTED); 123315a1350SMichael S. Tsirkin 124315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_COR_MASK, 125315a1350SMichael S. Tsirkin PCI_ERR_COR_MASK_DEFAULT); 126315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK, 127315a1350SMichael S. Tsirkin PCI_ERR_COR_SUPPORTED); 128315a1350SMichael S. Tsirkin 129315a1350SMichael S. Tsirkin /* capabilities and control. multiple header logging is supported */ 130315a1350SMichael S. Tsirkin if (dev->exp.aer_log.log_max > 0) { 131315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_CAP, 132315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC | 133315a1350SMichael S. Tsirkin PCI_ERR_CAP_MHRC); 134315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_CAP, 135315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE | 136315a1350SMichael S. Tsirkin PCI_ERR_CAP_MHRE); 137315a1350SMichael S. Tsirkin } else { 138315a1350SMichael S. Tsirkin pci_set_long(dev->config + offset + PCI_ERR_CAP, 139315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC); 140315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + offset + PCI_ERR_CAP, 141315a1350SMichael S. Tsirkin PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 142315a1350SMichael S. Tsirkin } 143315a1350SMichael S. Tsirkin 144315a1350SMichael S. Tsirkin switch (pcie_cap_get_type(dev)) { 145315a1350SMichael S. Tsirkin case PCI_EXP_TYPE_ROOT_PORT: 146315a1350SMichael S. Tsirkin /* this case will be set by pcie_aer_root_init() */ 147315a1350SMichael S. Tsirkin /* fallthrough */ 148315a1350SMichael S. Tsirkin case PCI_EXP_TYPE_DOWNSTREAM: 149315a1350SMichael S. Tsirkin case PCI_EXP_TYPE_UPSTREAM: 150315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL, 151315a1350SMichael S. Tsirkin PCI_BRIDGE_CTL_SERR); 152315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS, 153315a1350SMichael S. Tsirkin PCI_SEC_STATUS_RCV_SYSTEM_ERROR); 154315a1350SMichael S. Tsirkin break; 155315a1350SMichael S. Tsirkin default: 156315a1350SMichael S. Tsirkin /* nothing */ 157315a1350SMichael S. Tsirkin break; 158315a1350SMichael S. Tsirkin } 159315a1350SMichael S. Tsirkin return 0; 160315a1350SMichael S. Tsirkin } 161315a1350SMichael S. Tsirkin 162315a1350SMichael S. Tsirkin void pcie_aer_exit(PCIDevice *dev) 163315a1350SMichael S. Tsirkin { 164315a1350SMichael S. Tsirkin g_free(dev->exp.aer_log.log); 165315a1350SMichael S. Tsirkin } 166315a1350SMichael S. Tsirkin 167315a1350SMichael S. Tsirkin static void pcie_aer_update_uncor_status(PCIDevice *dev) 168315a1350SMichael S. Tsirkin { 169315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 170315a1350SMichael S. Tsirkin PCIEAERLog *aer_log = &dev->exp.aer_log; 171315a1350SMichael S. Tsirkin 172315a1350SMichael S. Tsirkin uint16_t i; 173315a1350SMichael S. Tsirkin for (i = 0; i < aer_log->log_num; i++) { 174315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(aer_cap + PCI_ERR_UNCOR_STATUS, 175315a1350SMichael S. Tsirkin dev->exp.aer_log.log[i].status); 176315a1350SMichael S. Tsirkin } 177315a1350SMichael S. Tsirkin } 178315a1350SMichael S. Tsirkin 179315a1350SMichael S. Tsirkin /* 180315a1350SMichael S. Tsirkin * return value: 181315a1350SMichael S. Tsirkin * true: error message needs to be sent up 182315a1350SMichael S. Tsirkin * false: error message is masked 183315a1350SMichael S. Tsirkin * 184315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control 185315a1350SMichael S. Tsirkin * Figure 6-3 186315a1350SMichael S. Tsirkin * all pci express devices part 187315a1350SMichael S. Tsirkin */ 188315a1350SMichael S. Tsirkin static bool 189315a1350SMichael S. Tsirkin pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg) 190315a1350SMichael S. Tsirkin { 191315a1350SMichael S. Tsirkin if (!(pcie_aer_msg_is_uncor(msg) && 192315a1350SMichael S. Tsirkin (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) { 193315a1350SMichael S. Tsirkin return false; 194315a1350SMichael S. Tsirkin } 195315a1350SMichael S. Tsirkin 196315a1350SMichael S. Tsirkin /* Signaled System Error 197315a1350SMichael S. Tsirkin * 198315a1350SMichael S. Tsirkin * 7.5.1.1 Command register 199315a1350SMichael S. Tsirkin * Bit 8 SERR# Enable 200315a1350SMichael S. Tsirkin * 201315a1350SMichael S. Tsirkin * When Set, this bit enables reporting of Non-fatal and Fatal 202315a1350SMichael S. Tsirkin * errors detected by the Function to the Root Complex. Note that 203315a1350SMichael S. Tsirkin * errors are reported if enabled either through this bit or through 204315a1350SMichael S. Tsirkin * the PCI Express specific bits in the Device Control register (see 205315a1350SMichael S. Tsirkin * Section 7.8.4). 206315a1350SMichael S. Tsirkin */ 207315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->config + PCI_STATUS, 208315a1350SMichael S. Tsirkin PCI_STATUS_SIG_SYSTEM_ERROR); 209315a1350SMichael S. Tsirkin 210315a1350SMichael S. Tsirkin if (!(msg->severity & 211315a1350SMichael S. Tsirkin pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL))) { 212315a1350SMichael S. Tsirkin return false; 213315a1350SMichael S. Tsirkin } 214315a1350SMichael S. Tsirkin 215315a1350SMichael S. Tsirkin /* send up error message */ 216315a1350SMichael S. Tsirkin return true; 217315a1350SMichael S. Tsirkin } 218315a1350SMichael S. Tsirkin 219315a1350SMichael S. Tsirkin /* 220315a1350SMichael S. Tsirkin * return value: 221315a1350SMichael S. Tsirkin * true: error message is sent up 222315a1350SMichael S. Tsirkin * false: error message is masked 223315a1350SMichael S. Tsirkin * 224315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control 225315a1350SMichael S. Tsirkin * Figure 6-3 226315a1350SMichael S. Tsirkin * virtual pci bridge part 227315a1350SMichael S. Tsirkin */ 228315a1350SMichael S. Tsirkin static bool pcie_aer_msg_vbridge(PCIDevice *dev, const PCIEAERMsg *msg) 229315a1350SMichael S. Tsirkin { 230315a1350SMichael S. Tsirkin uint16_t bridge_control = pci_get_word(dev->config + PCI_BRIDGE_CONTROL); 231315a1350SMichael S. Tsirkin 232315a1350SMichael S. Tsirkin if (pcie_aer_msg_is_uncor(msg)) { 233315a1350SMichael S. Tsirkin /* Received System Error */ 234315a1350SMichael S. Tsirkin pci_word_test_and_set_mask(dev->config + PCI_SEC_STATUS, 235315a1350SMichael S. Tsirkin PCI_SEC_STATUS_RCV_SYSTEM_ERROR); 236315a1350SMichael S. Tsirkin } 237315a1350SMichael S. Tsirkin 238315a1350SMichael S. Tsirkin if (!(bridge_control & PCI_BRIDGE_CTL_SERR)) { 239315a1350SMichael S. Tsirkin return false; 240315a1350SMichael S. Tsirkin } 241315a1350SMichael S. Tsirkin return true; 242315a1350SMichael S. Tsirkin } 243315a1350SMichael S. Tsirkin 244315a1350SMichael S. Tsirkin void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector) 245315a1350SMichael S. Tsirkin { 246315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 247315a1350SMichael S. Tsirkin assert(vector < PCI_ERR_ROOT_IRQ_MAX); 248315a1350SMichael S. Tsirkin pci_long_test_and_clear_mask(aer_cap + PCI_ERR_ROOT_STATUS, 249315a1350SMichael S. Tsirkin PCI_ERR_ROOT_IRQ); 250315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(aer_cap + PCI_ERR_ROOT_STATUS, 251315a1350SMichael S. Tsirkin vector << PCI_ERR_ROOT_IRQ_SHIFT); 252315a1350SMichael S. Tsirkin } 253315a1350SMichael S. Tsirkin 254315a1350SMichael S. Tsirkin static unsigned int pcie_aer_root_get_vector(PCIDevice *dev) 255315a1350SMichael S. Tsirkin { 256315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 257315a1350SMichael S. Tsirkin uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); 258315a1350SMichael S. Tsirkin return (root_status & PCI_ERR_ROOT_IRQ) >> PCI_ERR_ROOT_IRQ_SHIFT; 259315a1350SMichael S. Tsirkin } 260315a1350SMichael S. Tsirkin 261315a1350SMichael S. Tsirkin /* Given a status register, get corresponding bits in the command register */ 262315a1350SMichael S. Tsirkin static uint32_t pcie_aer_status_to_cmd(uint32_t status) 263315a1350SMichael S. Tsirkin { 264315a1350SMichael S. Tsirkin uint32_t cmd = 0; 265315a1350SMichael S. Tsirkin if (status & PCI_ERR_ROOT_COR_RCV) { 266315a1350SMichael S. Tsirkin cmd |= PCI_ERR_ROOT_CMD_COR_EN; 267315a1350SMichael S. Tsirkin } 268315a1350SMichael S. Tsirkin if (status & PCI_ERR_ROOT_NONFATAL_RCV) { 269315a1350SMichael S. Tsirkin cmd |= PCI_ERR_ROOT_CMD_NONFATAL_EN; 270315a1350SMichael S. Tsirkin } 271315a1350SMichael S. Tsirkin if (status & PCI_ERR_ROOT_FATAL_RCV) { 272315a1350SMichael S. Tsirkin cmd |= PCI_ERR_ROOT_CMD_FATAL_EN; 273315a1350SMichael S. Tsirkin } 274315a1350SMichael S. Tsirkin return cmd; 275315a1350SMichael S. Tsirkin } 276315a1350SMichael S. Tsirkin 277315a1350SMichael S. Tsirkin static void pcie_aer_root_notify(PCIDevice *dev) 278315a1350SMichael S. Tsirkin { 279315a1350SMichael S. Tsirkin if (msix_enabled(dev)) { 280315a1350SMichael S. Tsirkin msix_notify(dev, pcie_aer_root_get_vector(dev)); 281315a1350SMichael S. Tsirkin } else if (msi_enabled(dev)) { 282315a1350SMichael S. Tsirkin msi_notify(dev, pcie_aer_root_get_vector(dev)); 2832e865671SFrederic Barrat } else if (pci_intx(dev) != -1) { 2845a03e708SMarcel Apfelbaum pci_irq_assert(dev); 285315a1350SMichael S. Tsirkin } 286315a1350SMichael S. Tsirkin } 287315a1350SMichael S. Tsirkin 288315a1350SMichael S. Tsirkin /* 289315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control 290315a1350SMichael S. Tsirkin * Figure 6-3 291315a1350SMichael S. Tsirkin * root port part 292315a1350SMichael S. Tsirkin */ 293315a1350SMichael S. Tsirkin static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg) 294315a1350SMichael S. Tsirkin { 295315a1350SMichael S. Tsirkin uint16_t cmd; 296315a1350SMichael S. Tsirkin uint8_t *aer_cap; 297315a1350SMichael S. Tsirkin uint32_t root_cmd; 298315a1350SMichael S. Tsirkin uint32_t root_status, prev_status; 299315a1350SMichael S. Tsirkin 300315a1350SMichael S. Tsirkin cmd = pci_get_word(dev->config + PCI_COMMAND); 301315a1350SMichael S. Tsirkin aer_cap = dev->config + dev->exp.aer_cap; 302315a1350SMichael S. Tsirkin root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); 303315a1350SMichael S. Tsirkin prev_status = root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); 304315a1350SMichael S. Tsirkin 305315a1350SMichael S. Tsirkin if (cmd & PCI_COMMAND_SERR) { 306315a1350SMichael S. Tsirkin /* System Error. 307315a1350SMichael S. Tsirkin * 308315a1350SMichael S. Tsirkin * The way to report System Error is platform specific and 309315a1350SMichael S. Tsirkin * it isn't implemented in qemu right now. 310315a1350SMichael S. Tsirkin * So just discard the error for now. 311315a1350SMichael S. Tsirkin * OS which cares of aer would receive errors via 312315a1350SMichael S. Tsirkin * native aer mechanims, so this wouldn't matter. 313315a1350SMichael S. Tsirkin */ 314315a1350SMichael S. Tsirkin } 315315a1350SMichael S. Tsirkin 316118d4ed0SDr. David Alan Gilbert /* Error Message Received: Root Error Status register */ 317315a1350SMichael S. Tsirkin switch (msg->severity) { 318315a1350SMichael S. Tsirkin case PCI_ERR_ROOT_CMD_COR_EN: 319315a1350SMichael S. Tsirkin if (root_status & PCI_ERR_ROOT_COR_RCV) { 320315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_MULTI_COR_RCV; 321315a1350SMichael S. Tsirkin } else { 322315a1350SMichael S. Tsirkin pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC + PCI_ERR_SRC_COR_OFFS, 323315a1350SMichael S. Tsirkin msg->source_id); 324315a1350SMichael S. Tsirkin } 325315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_COR_RCV; 326315a1350SMichael S. Tsirkin break; 327315a1350SMichael S. Tsirkin case PCI_ERR_ROOT_CMD_NONFATAL_EN: 328315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_NONFATAL_RCV; 329315a1350SMichael S. Tsirkin break; 330315a1350SMichael S. Tsirkin case PCI_ERR_ROOT_CMD_FATAL_EN: 331315a1350SMichael S. Tsirkin if (!(root_status & PCI_ERR_ROOT_UNCOR_RCV)) { 332315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_FIRST_FATAL; 333315a1350SMichael S. Tsirkin } 334315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_FATAL_RCV; 335315a1350SMichael S. Tsirkin break; 336315a1350SMichael S. Tsirkin default: 337315a1350SMichael S. Tsirkin abort(); 338315a1350SMichael S. Tsirkin break; 339315a1350SMichael S. Tsirkin } 340315a1350SMichael S. Tsirkin if (pcie_aer_msg_is_uncor(msg)) { 341315a1350SMichael S. Tsirkin if (root_status & PCI_ERR_ROOT_UNCOR_RCV) { 342315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV; 343315a1350SMichael S. Tsirkin } else { 344315a1350SMichael S. Tsirkin pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC + 345315a1350SMichael S. Tsirkin PCI_ERR_SRC_UNCOR_OFFS, msg->source_id); 346315a1350SMichael S. Tsirkin } 347315a1350SMichael S. Tsirkin root_status |= PCI_ERR_ROOT_UNCOR_RCV; 348315a1350SMichael S. Tsirkin } 349315a1350SMichael S. Tsirkin pci_set_long(aer_cap + PCI_ERR_ROOT_STATUS, root_status); 350315a1350SMichael S. Tsirkin 351315a1350SMichael S. Tsirkin /* 6.2.4.1.2 Interrupt Generation */ 352315a1350SMichael S. Tsirkin /* All the above did was set some bits in the status register. 353315a1350SMichael S. Tsirkin * Specifically these that match message severity. 354315a1350SMichael S. Tsirkin * The below code relies on this fact. */ 355315a1350SMichael S. Tsirkin if (!(root_cmd & msg->severity) || 356315a1350SMichael S. Tsirkin (pcie_aer_status_to_cmd(prev_status) & root_cmd)) { 357315a1350SMichael S. Tsirkin /* Condition is not being set or was already true so nothing to do. */ 358315a1350SMichael S. Tsirkin return; 359315a1350SMichael S. Tsirkin } 360315a1350SMichael S. Tsirkin 361315a1350SMichael S. Tsirkin pcie_aer_root_notify(dev); 362315a1350SMichael S. Tsirkin } 363315a1350SMichael S. Tsirkin 364315a1350SMichael S. Tsirkin /* 365315a1350SMichael S. Tsirkin * 6.2.6 Error Message Control Figure 6-3 366315a1350SMichael S. Tsirkin * 367315a1350SMichael S. Tsirkin * Walk up the bus tree from the device, propagate the error message. 368315a1350SMichael S. Tsirkin */ 3698f16de18SEric Blake static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg) 370315a1350SMichael S. Tsirkin { 371315a1350SMichael S. Tsirkin uint8_t type; 372315a1350SMichael S. Tsirkin 373315a1350SMichael S. Tsirkin while (dev) { 374315a1350SMichael S. Tsirkin if (!pci_is_express(dev)) { 375315a1350SMichael S. Tsirkin /* just ignore it */ 376315a1350SMichael S. Tsirkin /* TODO: Shouldn't we set PCI_STATUS_SIG_SYSTEM_ERROR? 377315a1350SMichael S. Tsirkin * Consider e.g. a PCI bridge above a PCI Express device. */ 378315a1350SMichael S. Tsirkin return; 379315a1350SMichael S. Tsirkin } 380315a1350SMichael S. Tsirkin 381315a1350SMichael S. Tsirkin type = pcie_cap_get_type(dev); 382315a1350SMichael S. Tsirkin if ((type == PCI_EXP_TYPE_ROOT_PORT || 383315a1350SMichael S. Tsirkin type == PCI_EXP_TYPE_UPSTREAM || 384315a1350SMichael S. Tsirkin type == PCI_EXP_TYPE_DOWNSTREAM) && 385315a1350SMichael S. Tsirkin !pcie_aer_msg_vbridge(dev, msg)) { 386315a1350SMichael S. Tsirkin return; 387315a1350SMichael S. Tsirkin } 388315a1350SMichael S. Tsirkin if (!pcie_aer_msg_alldev(dev, msg)) { 389315a1350SMichael S. Tsirkin return; 390315a1350SMichael S. Tsirkin } 391315a1350SMichael S. Tsirkin if (type == PCI_EXP_TYPE_ROOT_PORT) { 392315a1350SMichael S. Tsirkin pcie_aer_msg_root_port(dev, msg); 393315a1350SMichael S. Tsirkin /* Root port can notify system itself, 394315a1350SMichael S. Tsirkin or send the error message to root complex event collector. */ 395315a1350SMichael S. Tsirkin /* 396315a1350SMichael S. Tsirkin * if root port is associated with an event collector, 397315a1350SMichael S. Tsirkin * return the root complex event collector here. 398315a1350SMichael S. Tsirkin * For now root complex event collector isn't supported. 399315a1350SMichael S. Tsirkin */ 400315a1350SMichael S. Tsirkin return; 401315a1350SMichael S. Tsirkin } 402fd56e061SDavid Gibson dev = pci_bridge_get_device(pci_get_bus(dev)); 403315a1350SMichael S. Tsirkin } 404315a1350SMichael S. Tsirkin } 405315a1350SMichael S. Tsirkin 406315a1350SMichael S. Tsirkin static void pcie_aer_update_log(PCIDevice *dev, const PCIEAERErr *err) 407315a1350SMichael S. Tsirkin { 408315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 409786a4ea8SStefan Hajnoczi uint8_t first_bit = ctz32(err->status); 410315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); 411315a1350SMichael S. Tsirkin int i; 412315a1350SMichael S. Tsirkin 413315a1350SMichael S. Tsirkin assert(err->status); 414315a1350SMichael S. Tsirkin assert(!(err->status & (err->status - 1))); 415315a1350SMichael S. Tsirkin 416315a1350SMichael S. Tsirkin errcap &= ~(PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP); 417315a1350SMichael S. Tsirkin errcap |= PCI_ERR_CAP_FEP(first_bit); 418315a1350SMichael S. Tsirkin 419315a1350SMichael S. Tsirkin if (err->flags & PCIE_AER_ERR_HEADER_VALID) { 420315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(err->header); ++i) { 421315a1350SMichael S. Tsirkin /* 7.10.8 Header Log Register */ 422315a1350SMichael S. Tsirkin uint8_t *header_log = 423315a1350SMichael S. Tsirkin aer_cap + PCI_ERR_HEADER_LOG + i * sizeof err->header[0]; 4246bd194abSPeter Maydell stl_be_p(header_log, err->header[i]); 425315a1350SMichael S. Tsirkin } 426315a1350SMichael S. Tsirkin } else { 427315a1350SMichael S. Tsirkin assert(!(err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT)); 428315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE); 429315a1350SMichael S. Tsirkin } 430315a1350SMichael S. Tsirkin 431315a1350SMichael S. Tsirkin if ((err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT) && 43277a3c1d7SChen Fan (pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP2) & 433315a1350SMichael S. Tsirkin PCI_EXP_DEVCAP2_EETLPP)) { 434315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) { 435315a1350SMichael S. Tsirkin /* 7.10.12 tlp prefix log register */ 436315a1350SMichael S. Tsirkin uint8_t *prefix_log = 437315a1350SMichael S. Tsirkin aer_cap + PCI_ERR_TLP_PREFIX_LOG + i * sizeof err->prefix[0]; 4386bd194abSPeter Maydell stl_be_p(prefix_log, err->prefix[i]); 439315a1350SMichael S. Tsirkin } 440315a1350SMichael S. Tsirkin errcap |= PCI_ERR_CAP_TLP; 441315a1350SMichael S. Tsirkin } else { 442315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, 443315a1350SMichael S. Tsirkin PCI_ERR_TLP_PREFIX_LOG_SIZE); 444315a1350SMichael S. Tsirkin } 445315a1350SMichael S. Tsirkin pci_set_long(aer_cap + PCI_ERR_CAP, errcap); 446315a1350SMichael S. Tsirkin } 447315a1350SMichael S. Tsirkin 448315a1350SMichael S. Tsirkin static void pcie_aer_clear_log(PCIDevice *dev) 449315a1350SMichael S. Tsirkin { 450315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 451315a1350SMichael S. Tsirkin 452315a1350SMichael S. Tsirkin pci_long_test_and_clear_mask(aer_cap + PCI_ERR_CAP, 453315a1350SMichael S. Tsirkin PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP); 454315a1350SMichael S. Tsirkin 455315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE); 456315a1350SMichael S. Tsirkin memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, PCI_ERR_TLP_PREFIX_LOG_SIZE); 457315a1350SMichael S. Tsirkin } 458315a1350SMichael S. Tsirkin 459315a1350SMichael S. Tsirkin static void pcie_aer_clear_error(PCIDevice *dev) 460315a1350SMichael S. Tsirkin { 461315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 462315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); 463315a1350SMichael S. Tsirkin PCIEAERLog *aer_log = &dev->exp.aer_log; 464315a1350SMichael S. Tsirkin PCIEAERErr err; 465315a1350SMichael S. Tsirkin 466315a1350SMichael S. Tsirkin if (!(errcap & PCI_ERR_CAP_MHRE) || !aer_log->log_num) { 467315a1350SMichael S. Tsirkin pcie_aer_clear_log(dev); 468315a1350SMichael S. Tsirkin return; 469315a1350SMichael S. Tsirkin } 470315a1350SMichael S. Tsirkin 471315a1350SMichael S. Tsirkin /* 472315a1350SMichael S. Tsirkin * If more errors are queued, set corresponding bits in uncorrectable 473315a1350SMichael S. Tsirkin * error status. 474315a1350SMichael S. Tsirkin * We emulate uncorrectable error status register as W1CS. 475315a1350SMichael S. Tsirkin * So set bit in uncorrectable error status here again for multiple 476315a1350SMichael S. Tsirkin * error recording support. 477315a1350SMichael S. Tsirkin * 478315a1350SMichael S. Tsirkin * 6.2.4.2 Multiple Error Handling(Advanced Error Reporting Capability) 479315a1350SMichael S. Tsirkin */ 480315a1350SMichael S. Tsirkin pcie_aer_update_uncor_status(dev); 481315a1350SMichael S. Tsirkin 482315a1350SMichael S. Tsirkin aer_log_del_err(aer_log, &err); 483315a1350SMichael S. Tsirkin pcie_aer_update_log(dev, &err); 484315a1350SMichael S. Tsirkin } 485315a1350SMichael S. Tsirkin 486315a1350SMichael S. Tsirkin static int pcie_aer_record_error(PCIDevice *dev, 487315a1350SMichael S. Tsirkin const PCIEAERErr *err) 488315a1350SMichael S. Tsirkin { 489315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 490315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); 491315a1350SMichael S. Tsirkin int fep = PCI_ERR_CAP_FEP(errcap); 492315a1350SMichael S. Tsirkin 493315a1350SMichael S. Tsirkin assert(err->status); 494315a1350SMichael S. Tsirkin assert(!(err->status & (err->status - 1))); 495315a1350SMichael S. Tsirkin 496315a1350SMichael S. Tsirkin if (errcap & PCI_ERR_CAP_MHRE && 497315a1350SMichael S. Tsirkin (pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) { 498315a1350SMichael S. Tsirkin /* Not first error. queue error */ 499315a1350SMichael S. Tsirkin if (aer_log_add_err(&dev->exp.aer_log, err) < 0) { 500315a1350SMichael S. Tsirkin /* overflow */ 501315a1350SMichael S. Tsirkin return -1; 502315a1350SMichael S. Tsirkin } 503315a1350SMichael S. Tsirkin return 0; 504315a1350SMichael S. Tsirkin } 505315a1350SMichael S. Tsirkin 506315a1350SMichael S. Tsirkin pcie_aer_update_log(dev, err); 507315a1350SMichael S. Tsirkin return 0; 508315a1350SMichael S. Tsirkin } 509315a1350SMichael S. Tsirkin 510315a1350SMichael S. Tsirkin typedef struct PCIEAERInject { 511315a1350SMichael S. Tsirkin PCIDevice *dev; 512315a1350SMichael S. Tsirkin uint8_t *aer_cap; 513315a1350SMichael S. Tsirkin const PCIEAERErr *err; 514315a1350SMichael S. Tsirkin uint16_t devctl; 515315a1350SMichael S. Tsirkin uint16_t devsta; 516315a1350SMichael S. Tsirkin uint32_t error_status; 517315a1350SMichael S. Tsirkin bool unsupported_request; 518315a1350SMichael S. Tsirkin bool log_overflow; 519315a1350SMichael S. Tsirkin PCIEAERMsg msg; 520315a1350SMichael S. Tsirkin } PCIEAERInject; 521315a1350SMichael S. Tsirkin 522315a1350SMichael S. Tsirkin static bool pcie_aer_inject_cor_error(PCIEAERInject *inj, 523315a1350SMichael S. Tsirkin uint32_t uncor_status, 524315a1350SMichael S. Tsirkin bool is_advisory_nonfatal) 525315a1350SMichael S. Tsirkin { 526315a1350SMichael S. Tsirkin PCIDevice *dev = inj->dev; 527315a1350SMichael S. Tsirkin 528315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_CED; 529315a1350SMichael S. Tsirkin if (inj->unsupported_request) { 530315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_URD; 531315a1350SMichael S. Tsirkin } 532315a1350SMichael S. Tsirkin pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta); 533315a1350SMichael S. Tsirkin 534315a1350SMichael S. Tsirkin if (inj->aer_cap) { 535315a1350SMichael S. Tsirkin uint32_t mask; 536315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_COR_STATUS, 537315a1350SMichael S. Tsirkin inj->error_status); 538315a1350SMichael S. Tsirkin mask = pci_get_long(inj->aer_cap + PCI_ERR_COR_MASK); 539315a1350SMichael S. Tsirkin if (mask & inj->error_status) { 540315a1350SMichael S. Tsirkin return false; 541315a1350SMichael S. Tsirkin } 542315a1350SMichael S. Tsirkin if (is_advisory_nonfatal) { 543315a1350SMichael S. Tsirkin uint32_t uncor_mask = 544315a1350SMichael S. Tsirkin pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK); 545315a1350SMichael S. Tsirkin if (!(uncor_mask & uncor_status)) { 546315a1350SMichael S. Tsirkin inj->log_overflow = !!pcie_aer_record_error(dev, inj->err); 547315a1350SMichael S. Tsirkin } 548315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, 549315a1350SMichael S. Tsirkin uncor_status); 550315a1350SMichael S. Tsirkin } 551315a1350SMichael S. Tsirkin } 552315a1350SMichael S. Tsirkin 553315a1350SMichael S. Tsirkin if (inj->unsupported_request && !(inj->devctl & PCI_EXP_DEVCTL_URRE)) { 554315a1350SMichael S. Tsirkin return false; 555315a1350SMichael S. Tsirkin } 556315a1350SMichael S. Tsirkin if (!(inj->devctl & PCI_EXP_DEVCTL_CERE)) { 557315a1350SMichael S. Tsirkin return false; 558315a1350SMichael S. Tsirkin } 559315a1350SMichael S. Tsirkin 560315a1350SMichael S. Tsirkin inj->msg.severity = PCI_ERR_ROOT_CMD_COR_EN; 561315a1350SMichael S. Tsirkin return true; 562315a1350SMichael S. Tsirkin } 563315a1350SMichael S. Tsirkin 564315a1350SMichael S. Tsirkin static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal) 565315a1350SMichael S. Tsirkin { 566315a1350SMichael S. Tsirkin PCIDevice *dev = inj->dev; 567315a1350SMichael S. Tsirkin uint16_t cmd; 568315a1350SMichael S. Tsirkin 569315a1350SMichael S. Tsirkin if (is_fatal) { 570315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_FED; 571315a1350SMichael S. Tsirkin } else { 572315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_NFED; 573315a1350SMichael S. Tsirkin } 574315a1350SMichael S. Tsirkin if (inj->unsupported_request) { 575315a1350SMichael S. Tsirkin inj->devsta |= PCI_EXP_DEVSTA_URD; 576315a1350SMichael S. Tsirkin } 577315a1350SMichael S. Tsirkin pci_set_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta); 578315a1350SMichael S. Tsirkin 579315a1350SMichael S. Tsirkin if (inj->aer_cap) { 580315a1350SMichael S. Tsirkin uint32_t mask = pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK); 581315a1350SMichael S. Tsirkin if (mask & inj->error_status) { 582315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, 583315a1350SMichael S. Tsirkin inj->error_status); 584315a1350SMichael S. Tsirkin return false; 585315a1350SMichael S. Tsirkin } 586315a1350SMichael S. Tsirkin 587315a1350SMichael S. Tsirkin inj->log_overflow = !!pcie_aer_record_error(dev, inj->err); 588315a1350SMichael S. Tsirkin pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS, 589315a1350SMichael S. Tsirkin inj->error_status); 590315a1350SMichael S. Tsirkin } 591315a1350SMichael S. Tsirkin 592315a1350SMichael S. Tsirkin cmd = pci_get_word(dev->config + PCI_COMMAND); 593315a1350SMichael S. Tsirkin if (inj->unsupported_request && 594315a1350SMichael S. Tsirkin !(inj->devctl & PCI_EXP_DEVCTL_URRE) && !(cmd & PCI_COMMAND_SERR)) { 595315a1350SMichael S. Tsirkin return false; 596315a1350SMichael S. Tsirkin } 597315a1350SMichael S. Tsirkin if (is_fatal) { 598315a1350SMichael S. Tsirkin if (!((cmd & PCI_COMMAND_SERR) || 599315a1350SMichael S. Tsirkin (inj->devctl & PCI_EXP_DEVCTL_FERE))) { 600315a1350SMichael S. Tsirkin return false; 601315a1350SMichael S. Tsirkin } 602315a1350SMichael S. Tsirkin inj->msg.severity = PCI_ERR_ROOT_CMD_FATAL_EN; 603315a1350SMichael S. Tsirkin } else { 604315a1350SMichael S. Tsirkin if (!((cmd & PCI_COMMAND_SERR) || 605315a1350SMichael S. Tsirkin (inj->devctl & PCI_EXP_DEVCTL_NFERE))) { 606315a1350SMichael S. Tsirkin return false; 607315a1350SMichael S. Tsirkin } 608315a1350SMichael S. Tsirkin inj->msg.severity = PCI_ERR_ROOT_CMD_NONFATAL_EN; 609315a1350SMichael S. Tsirkin } 610315a1350SMichael S. Tsirkin return true; 611315a1350SMichael S. Tsirkin } 612315a1350SMichael S. Tsirkin 613315a1350SMichael S. Tsirkin /* 614315a1350SMichael S. Tsirkin * non-Function specific error must be recorded in all functions. 615315a1350SMichael S. Tsirkin * It is the responsibility of the caller of this function. 616315a1350SMichael S. Tsirkin * It is also caller's responsibility to determine which function should 617b01738c2SChen Fan * report the error. 618315a1350SMichael S. Tsirkin * 619315a1350SMichael S. Tsirkin * 6.2.4 Error Logging 620b01738c2SChen Fan * 6.2.5 Sequence of Device Error Signaling and Logging Operations 621ce394947SMichael S. Tsirkin * Figure 6-2: Flowchart Showing Sequence of Device Error Signaling and Logging 622315a1350SMichael S. Tsirkin * Operations 623315a1350SMichael S. Tsirkin */ 624d0e67298SMarkus Armbruster int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err) 625315a1350SMichael S. Tsirkin { 626315a1350SMichael S. Tsirkin uint8_t *aer_cap = NULL; 627315a1350SMichael S. Tsirkin uint16_t devctl = 0; 628315a1350SMichael S. Tsirkin uint16_t devsta = 0; 629315a1350SMichael S. Tsirkin uint32_t error_status = err->status; 630315a1350SMichael S. Tsirkin PCIEAERInject inj; 631315a1350SMichael S. Tsirkin 632315a1350SMichael S. Tsirkin if (!pci_is_express(dev)) { 633315a1350SMichael S. Tsirkin return -ENOSYS; 634315a1350SMichael S. Tsirkin } 635315a1350SMichael S. Tsirkin 636315a1350SMichael S. Tsirkin if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) { 637315a1350SMichael S. Tsirkin error_status &= PCI_ERR_COR_SUPPORTED; 638315a1350SMichael S. Tsirkin } else { 639315a1350SMichael S. Tsirkin error_status &= PCI_ERR_UNC_SUPPORTED; 640315a1350SMichael S. Tsirkin } 641315a1350SMichael S. Tsirkin 642315a1350SMichael S. Tsirkin /* invalid status bit. one and only one bit must be set */ 643315a1350SMichael S. Tsirkin if (!error_status || (error_status & (error_status - 1))) { 644315a1350SMichael S. Tsirkin return -EINVAL; 645315a1350SMichael S. Tsirkin } 646315a1350SMichael S. Tsirkin 647315a1350SMichael S. Tsirkin if (dev->exp.aer_cap) { 648315a1350SMichael S. Tsirkin uint8_t *exp_cap = dev->config + dev->exp.exp_cap; 649315a1350SMichael S. Tsirkin aer_cap = dev->config + dev->exp.aer_cap; 650315a1350SMichael S. Tsirkin devctl = pci_get_long(exp_cap + PCI_EXP_DEVCTL); 651315a1350SMichael S. Tsirkin devsta = pci_get_long(exp_cap + PCI_EXP_DEVSTA); 652315a1350SMichael S. Tsirkin } 653315a1350SMichael S. Tsirkin 654315a1350SMichael S. Tsirkin inj.dev = dev; 655315a1350SMichael S. Tsirkin inj.aer_cap = aer_cap; 656315a1350SMichael S. Tsirkin inj.err = err; 657315a1350SMichael S. Tsirkin inj.devctl = devctl; 658315a1350SMichael S. Tsirkin inj.devsta = devsta; 659315a1350SMichael S. Tsirkin inj.error_status = error_status; 660315a1350SMichael S. Tsirkin inj.unsupported_request = !(err->flags & PCIE_AER_ERR_IS_CORRECTABLE) && 661315a1350SMichael S. Tsirkin err->status == PCI_ERR_UNC_UNSUP; 662315a1350SMichael S. Tsirkin inj.log_overflow = false; 663315a1350SMichael S. Tsirkin 664315a1350SMichael S. Tsirkin if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) { 665315a1350SMichael S. Tsirkin if (!pcie_aer_inject_cor_error(&inj, 0, false)) { 666315a1350SMichael S. Tsirkin return 0; 667315a1350SMichael S. Tsirkin } 668315a1350SMichael S. Tsirkin } else { 669315a1350SMichael S. Tsirkin bool is_fatal = 670315a1350SMichael S. Tsirkin pcie_aer_uncor_default_severity(error_status) == 671315a1350SMichael S. Tsirkin PCI_ERR_ROOT_CMD_FATAL_EN; 672315a1350SMichael S. Tsirkin if (aer_cap) { 673315a1350SMichael S. Tsirkin is_fatal = 674315a1350SMichael S. Tsirkin error_status & pci_get_long(aer_cap + PCI_ERR_UNCOR_SEVER); 675315a1350SMichael S. Tsirkin } 676315a1350SMichael S. Tsirkin if (!is_fatal && (err->flags & PCIE_AER_ERR_MAYBE_ADVISORY)) { 677315a1350SMichael S. Tsirkin inj.error_status = PCI_ERR_COR_ADV_NONFATAL; 678315a1350SMichael S. Tsirkin if (!pcie_aer_inject_cor_error(&inj, error_status, true)) { 679315a1350SMichael S. Tsirkin return 0; 680315a1350SMichael S. Tsirkin } 681315a1350SMichael S. Tsirkin } else { 682315a1350SMichael S. Tsirkin if (!pcie_aer_inject_uncor_error(&inj, is_fatal)) { 683315a1350SMichael S. Tsirkin return 0; 684315a1350SMichael S. Tsirkin } 685315a1350SMichael S. Tsirkin } 686315a1350SMichael S. Tsirkin } 687315a1350SMichael S. Tsirkin 688315a1350SMichael S. Tsirkin /* send up error message */ 689315a1350SMichael S. Tsirkin inj.msg.source_id = err->source_id; 690315a1350SMichael S. Tsirkin pcie_aer_msg(dev, &inj.msg); 691315a1350SMichael S. Tsirkin 692315a1350SMichael S. Tsirkin if (inj.log_overflow) { 693315a1350SMichael S. Tsirkin PCIEAERErr header_log_overflow = { 694315a1350SMichael S. Tsirkin .status = PCI_ERR_COR_HL_OVERFLOW, 695315a1350SMichael S. Tsirkin .flags = PCIE_AER_ERR_IS_CORRECTABLE, 696315a1350SMichael S. Tsirkin }; 697315a1350SMichael S. Tsirkin int ret = pcie_aer_inject_error(dev, &header_log_overflow); 698315a1350SMichael S. Tsirkin assert(!ret); 699315a1350SMichael S. Tsirkin } 700315a1350SMichael S. Tsirkin return 0; 701315a1350SMichael S. Tsirkin } 702315a1350SMichael S. Tsirkin 703315a1350SMichael S. Tsirkin void pcie_aer_write_config(PCIDevice *dev, 704315a1350SMichael S. Tsirkin uint32_t addr, uint32_t val, int len) 705315a1350SMichael S. Tsirkin { 706315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 707315a1350SMichael S. Tsirkin uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP); 708315a1350SMichael S. Tsirkin uint32_t first_error = 1U << PCI_ERR_CAP_FEP(errcap); 709315a1350SMichael S. Tsirkin uint32_t uncorsta = pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS); 710315a1350SMichael S. Tsirkin 711315a1350SMichael S. Tsirkin /* uncorrectable error */ 712315a1350SMichael S. Tsirkin if (!(uncorsta & first_error)) { 713315a1350SMichael S. Tsirkin /* the bit that corresponds to the first error is cleared */ 714315a1350SMichael S. Tsirkin pcie_aer_clear_error(dev); 715315a1350SMichael S. Tsirkin } else if (errcap & PCI_ERR_CAP_MHRE) { 716315a1350SMichael S. Tsirkin /* When PCI_ERR_CAP_MHRE is enabled and the first error isn't cleared 717315a1350SMichael S. Tsirkin * nothing should happen. So we have to revert the modification to 718315a1350SMichael S. Tsirkin * the register. 719315a1350SMichael S. Tsirkin */ 720315a1350SMichael S. Tsirkin pcie_aer_update_uncor_status(dev); 721315a1350SMichael S. Tsirkin } else { 722315a1350SMichael S. Tsirkin /* capability & control 723315a1350SMichael S. Tsirkin * PCI_ERR_CAP_MHRE might be cleared, so clear of header log. 724315a1350SMichael S. Tsirkin */ 725315a1350SMichael S. Tsirkin aer_log_clear_all_err(&dev->exp.aer_log); 726315a1350SMichael S. Tsirkin } 727315a1350SMichael S. Tsirkin } 728315a1350SMichael S. Tsirkin 729315a1350SMichael S. Tsirkin void pcie_aer_root_init(PCIDevice *dev) 730315a1350SMichael S. Tsirkin { 731315a1350SMichael S. Tsirkin uint16_t pos = dev->exp.aer_cap; 732315a1350SMichael S. Tsirkin 733315a1350SMichael S. Tsirkin pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND, 734315a1350SMichael S. Tsirkin PCI_ERR_ROOT_CMD_EN_MASK); 735315a1350SMichael S. Tsirkin pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS, 736315a1350SMichael S. Tsirkin PCI_ERR_ROOT_STATUS_REPORT_MASK); 737315a1350SMichael S. Tsirkin /* PCI_ERR_ROOT_IRQ is RO but devices change it using a 738315a1350SMichael S. Tsirkin * device-specific method. 739315a1350SMichael S. Tsirkin */ 740315a1350SMichael S. Tsirkin pci_set_long(dev->cmask + pos + PCI_ERR_ROOT_STATUS, 741315a1350SMichael S. Tsirkin ~PCI_ERR_ROOT_IRQ); 742315a1350SMichael S. Tsirkin } 743315a1350SMichael S. Tsirkin 744315a1350SMichael S. Tsirkin void pcie_aer_root_reset(PCIDevice *dev) 745315a1350SMichael S. Tsirkin { 746315a1350SMichael S. Tsirkin uint8_t* aer_cap = dev->config + dev->exp.aer_cap; 747315a1350SMichael S. Tsirkin 748315a1350SMichael S. Tsirkin pci_set_long(aer_cap + PCI_ERR_ROOT_COMMAND, 0); 749315a1350SMichael S. Tsirkin 750315a1350SMichael S. Tsirkin /* 751315a1350SMichael S. Tsirkin * Advanced Error Interrupt Message Number in Root Error Status Register 752315a1350SMichael S. Tsirkin * must be updated by chip dependent code because it's chip dependent 753315a1350SMichael S. Tsirkin * which number is used. 754315a1350SMichael S. Tsirkin */ 755315a1350SMichael S. Tsirkin } 756315a1350SMichael S. Tsirkin 757315a1350SMichael S. Tsirkin void pcie_aer_root_write_config(PCIDevice *dev, 758315a1350SMichael S. Tsirkin uint32_t addr, uint32_t val, int len, 759315a1350SMichael S. Tsirkin uint32_t root_cmd_prev) 760315a1350SMichael S. Tsirkin { 761315a1350SMichael S. Tsirkin uint8_t *aer_cap = dev->config + dev->exp.aer_cap; 762315a1350SMichael S. Tsirkin uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS); 763315a1350SMichael S. Tsirkin uint32_t enabled_cmd = pcie_aer_status_to_cmd(root_status); 764315a1350SMichael S. Tsirkin uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND); 765315a1350SMichael S. Tsirkin /* 6.2.4.1.2 Interrupt Generation */ 766315a1350SMichael S. Tsirkin if (!msix_enabled(dev) && !msi_enabled(dev)) { 76720766514SFrederic Barrat if (pci_intx(dev) != -1) { 7685a03e708SMarcel Apfelbaum pci_set_irq(dev, !!(root_cmd & enabled_cmd)); 76920766514SFrederic Barrat } 770315a1350SMichael S. Tsirkin return; 771315a1350SMichael S. Tsirkin } 772315a1350SMichael S. Tsirkin 773315a1350SMichael S. Tsirkin if ((root_cmd_prev & enabled_cmd) || !(root_cmd & enabled_cmd)) { 774315a1350SMichael S. Tsirkin /* Send MSI on transition from false to true. */ 775315a1350SMichael S. Tsirkin return; 776315a1350SMichael S. Tsirkin } 777315a1350SMichael S. Tsirkin 778315a1350SMichael S. Tsirkin pcie_aer_root_notify(dev); 779315a1350SMichael S. Tsirkin } 780315a1350SMichael S. Tsirkin 781315a1350SMichael S. Tsirkin static const VMStateDescription vmstate_pcie_aer_err = { 782315a1350SMichael S. Tsirkin .name = "PCIE_AER_ERROR", 783315a1350SMichael S. Tsirkin .version_id = 1, 784315a1350SMichael S. Tsirkin .minimum_version_id = 1, 785315a1350SMichael S. Tsirkin .fields = (VMStateField[]) { 786315a1350SMichael S. Tsirkin VMSTATE_UINT32(status, PCIEAERErr), 787315a1350SMichael S. Tsirkin VMSTATE_UINT16(source_id, PCIEAERErr), 788315a1350SMichael S. Tsirkin VMSTATE_UINT16(flags, PCIEAERErr), 789315a1350SMichael S. Tsirkin VMSTATE_UINT32_ARRAY(header, PCIEAERErr, 4), 790315a1350SMichael S. Tsirkin VMSTATE_UINT32_ARRAY(prefix, PCIEAERErr, 4), 791315a1350SMichael S. Tsirkin VMSTATE_END_OF_LIST() 792315a1350SMichael S. Tsirkin } 793315a1350SMichael S. Tsirkin }; 794315a1350SMichael S. Tsirkin 7955f691ff9SMichael S. Tsirkin static bool pcie_aer_state_log_num_valid(void *opaque, int version_id) 7965f691ff9SMichael S. Tsirkin { 7975f691ff9SMichael S. Tsirkin PCIEAERLog *s = opaque; 7985f691ff9SMichael S. Tsirkin 7995f691ff9SMichael S. Tsirkin return s->log_num <= s->log_max; 8005f691ff9SMichael S. Tsirkin } 8015f691ff9SMichael S. Tsirkin 802315a1350SMichael S. Tsirkin const VMStateDescription vmstate_pcie_aer_log = { 803315a1350SMichael S. Tsirkin .name = "PCIE_AER_ERROR_LOG", 804315a1350SMichael S. Tsirkin .version_id = 1, 805315a1350SMichael S. Tsirkin .minimum_version_id = 1, 806315a1350SMichael S. Tsirkin .fields = (VMStateField[]) { 807315a1350SMichael S. Tsirkin VMSTATE_UINT16(log_num, PCIEAERLog), 808d2164ad3SHalil Pasic VMSTATE_UINT16_EQUAL(log_max, PCIEAERLog, NULL), 8095f691ff9SMichael S. Tsirkin VMSTATE_VALIDATE("log_num <= log_max", pcie_aer_state_log_num_valid), 810315a1350SMichael S. Tsirkin VMSTATE_STRUCT_VARRAY_POINTER_UINT16(log, PCIEAERLog, log_num, 811315a1350SMichael S. Tsirkin vmstate_pcie_aer_err, PCIEAERErr), 812315a1350SMichael S. Tsirkin VMSTATE_END_OF_LIST() 813315a1350SMichael S. Tsirkin } 814315a1350SMichael S. Tsirkin }; 815315a1350SMichael S. Tsirkin 816315a1350SMichael S. Tsirkin typedef struct PCIEAERErrorName { 817315a1350SMichael S. Tsirkin const char *name; 818315a1350SMichael S. Tsirkin uint32_t val; 819315a1350SMichael S. Tsirkin bool correctable; 820315a1350SMichael S. Tsirkin } PCIEAERErrorName; 821315a1350SMichael S. Tsirkin 822315a1350SMichael S. Tsirkin /* 823315a1350SMichael S. Tsirkin * AER error name -> value conversion table 824315a1350SMichael S. Tsirkin * This naming scheme is same to linux aer-injection tool. 825315a1350SMichael S. Tsirkin */ 826315a1350SMichael S. Tsirkin static const struct PCIEAERErrorName pcie_aer_error_list[] = { 827315a1350SMichael S. Tsirkin { 828315a1350SMichael S. Tsirkin .name = "DLP", 829315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_DLP, 830315a1350SMichael S. Tsirkin .correctable = false, 831315a1350SMichael S. Tsirkin }, { 832315a1350SMichael S. Tsirkin .name = "SDN", 833315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_SDN, 834315a1350SMichael S. Tsirkin .correctable = false, 835315a1350SMichael S. Tsirkin }, { 836315a1350SMichael S. Tsirkin .name = "POISON_TLP", 837315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_POISON_TLP, 838315a1350SMichael S. Tsirkin .correctable = false, 839315a1350SMichael S. Tsirkin }, { 840315a1350SMichael S. Tsirkin .name = "FCP", 841315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_FCP, 842315a1350SMichael S. Tsirkin .correctable = false, 843315a1350SMichael S. Tsirkin }, { 844315a1350SMichael S. Tsirkin .name = "COMP_TIME", 845315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_COMP_TIME, 846315a1350SMichael S. Tsirkin .correctable = false, 847315a1350SMichael S. Tsirkin }, { 848315a1350SMichael S. Tsirkin .name = "COMP_ABORT", 849315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_COMP_ABORT, 850315a1350SMichael S. Tsirkin .correctable = false, 851315a1350SMichael S. Tsirkin }, { 852315a1350SMichael S. Tsirkin .name = "UNX_COMP", 853315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_UNX_COMP, 854315a1350SMichael S. Tsirkin .correctable = false, 855315a1350SMichael S. Tsirkin }, { 856315a1350SMichael S. Tsirkin .name = "RX_OVER", 857315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_RX_OVER, 858315a1350SMichael S. Tsirkin .correctable = false, 859315a1350SMichael S. Tsirkin }, { 860315a1350SMichael S. Tsirkin .name = "MALF_TLP", 861315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_MALF_TLP, 862315a1350SMichael S. Tsirkin .correctable = false, 863315a1350SMichael S. Tsirkin }, { 864315a1350SMichael S. Tsirkin .name = "ECRC", 865315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_ECRC, 866315a1350SMichael S. Tsirkin .correctable = false, 867315a1350SMichael S. Tsirkin }, { 868315a1350SMichael S. Tsirkin .name = "UNSUP", 869315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_UNSUP, 870315a1350SMichael S. Tsirkin .correctable = false, 871315a1350SMichael S. Tsirkin }, { 872315a1350SMichael S. Tsirkin .name = "ACSV", 873315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_ACSV, 874315a1350SMichael S. Tsirkin .correctable = false, 875315a1350SMichael S. Tsirkin }, { 876315a1350SMichael S. Tsirkin .name = "INTN", 877315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_INTN, 878315a1350SMichael S. Tsirkin .correctable = false, 879315a1350SMichael S. Tsirkin }, { 880315a1350SMichael S. Tsirkin .name = "MCBTLP", 881315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_MCBTLP, 882315a1350SMichael S. Tsirkin .correctable = false, 883315a1350SMichael S. Tsirkin }, { 884315a1350SMichael S. Tsirkin .name = "ATOP_EBLOCKED", 885315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_ATOP_EBLOCKED, 886315a1350SMichael S. Tsirkin .correctable = false, 887315a1350SMichael S. Tsirkin }, { 888315a1350SMichael S. Tsirkin .name = "TLP_PRF_BLOCKED", 889315a1350SMichael S. Tsirkin .val = PCI_ERR_UNC_TLP_PRF_BLOCKED, 890315a1350SMichael S. Tsirkin .correctable = false, 891315a1350SMichael S. Tsirkin }, { 892315a1350SMichael S. Tsirkin .name = "RCVR", 893315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_RCVR, 894315a1350SMichael S. Tsirkin .correctable = true, 895315a1350SMichael S. Tsirkin }, { 896315a1350SMichael S. Tsirkin .name = "BAD_TLP", 897315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_BAD_TLP, 898315a1350SMichael S. Tsirkin .correctable = true, 899315a1350SMichael S. Tsirkin }, { 900315a1350SMichael S. Tsirkin .name = "BAD_DLLP", 901315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_BAD_DLLP, 902315a1350SMichael S. Tsirkin .correctable = true, 903315a1350SMichael S. Tsirkin }, { 904315a1350SMichael S. Tsirkin .name = "REP_ROLL", 905315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_REP_ROLL, 906315a1350SMichael S. Tsirkin .correctable = true, 907315a1350SMichael S. Tsirkin }, { 908315a1350SMichael S. Tsirkin .name = "REP_TIMER", 909315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_REP_TIMER, 910315a1350SMichael S. Tsirkin .correctable = true, 911315a1350SMichael S. Tsirkin }, { 912315a1350SMichael S. Tsirkin .name = "ADV_NONFATAL", 913315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_ADV_NONFATAL, 914315a1350SMichael S. Tsirkin .correctable = true, 915315a1350SMichael S. Tsirkin }, { 916315a1350SMichael S. Tsirkin .name = "INTERNAL", 917315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_INTERNAL, 918315a1350SMichael S. Tsirkin .correctable = true, 919315a1350SMichael S. Tsirkin }, { 920315a1350SMichael S. Tsirkin .name = "HL_OVERFLOW", 921315a1350SMichael S. Tsirkin .val = PCI_ERR_COR_HL_OVERFLOW, 922315a1350SMichael S. Tsirkin .correctable = true, 923315a1350SMichael S. Tsirkin }, 924315a1350SMichael S. Tsirkin }; 925315a1350SMichael S. Tsirkin 926d0e67298SMarkus Armbruster int pcie_aer_parse_error_string(const char *error_name, 927315a1350SMichael S. Tsirkin uint32_t *status, bool *correctable) 928315a1350SMichael S. Tsirkin { 929315a1350SMichael S. Tsirkin int i; 930315a1350SMichael S. Tsirkin 931315a1350SMichael S. Tsirkin for (i = 0; i < ARRAY_SIZE(pcie_aer_error_list); i++) { 932315a1350SMichael S. Tsirkin const PCIEAERErrorName *e = &pcie_aer_error_list[i]; 933315a1350SMichael S. Tsirkin if (strcmp(error_name, e->name)) { 934315a1350SMichael S. Tsirkin continue; 935315a1350SMichael S. Tsirkin } 936315a1350SMichael S. Tsirkin 937315a1350SMichael S. Tsirkin *status = e->val; 938315a1350SMichael S. Tsirkin *correctable = e->correctable; 939315a1350SMichael S. Tsirkin return 0; 940315a1350SMichael S. Tsirkin } 941315a1350SMichael S. Tsirkin return -EINVAL; 942315a1350SMichael S. Tsirkin } 943