1 /* 2 * QEMU PowerPC Booke hardware System Emulator 3 * 4 * Copyright (c) 2011 AdaCore 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/ppc.h" 26 #include "qemu/timer.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/nvram.h" 29 #include "qemu/log.h" 30 #include "hw/loader.h" 31 32 33 /* Timer Control Register */ 34 35 #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */ 36 #define TCR_WP_MASK (0x3 << TCR_WP_SHIFT) 37 #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */ 38 #define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT) 39 #define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */ 40 #define TCR_DIE (1 << 26) /* Decrementer Interrupt Enable */ 41 #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */ 42 #define TCR_FP_MASK (0x3 << TCR_FP_SHIFT) 43 #define TCR_FIE (1 << 23) /* Fixed-Interval Timer Interrupt Enable */ 44 #define TCR_ARE (1 << 22) /* Auto-Reload Enable */ 45 46 /* Timer Control Register (e500 specific fields) */ 47 48 #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */ 49 #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT) 50 #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */ 51 #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT) 52 53 /* Timer Status Register */ 54 55 #define TSR_FIS (1 << 26) /* Fixed-Interval Timer Interrupt Status */ 56 #define TSR_DIS (1 << 27) /* Decrementer Interrupt Status */ 57 #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */ 58 #define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT) 59 #define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */ 60 #define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */ 61 62 typedef struct booke_timer_t booke_timer_t; 63 struct booke_timer_t { 64 65 uint64_t fit_next; 66 struct QEMUTimer *fit_timer; 67 68 uint64_t wdt_next; 69 struct QEMUTimer *wdt_timer; 70 71 uint32_t flags; 72 }; 73 74 static void booke_update_irq(PowerPCCPU *cpu) 75 { 76 CPUPPCState *env = &cpu->env; 77 78 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 79 (env->spr[SPR_BOOKE_TSR] & TSR_DIS 80 && env->spr[SPR_BOOKE_TCR] & TCR_DIE)); 81 82 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 83 (env->spr[SPR_BOOKE_TSR] & TSR_WIS 84 && env->spr[SPR_BOOKE_TCR] & TCR_WIE)); 85 86 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 87 (env->spr[SPR_BOOKE_TSR] & TSR_FIS 88 && env->spr[SPR_BOOKE_TCR] & TCR_FIE)); 89 } 90 91 /* Return the location of the bit of time base at which the FIT will raise an 92 interrupt */ 93 static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env) 94 { 95 uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT; 96 97 if (tb_env->flags & PPC_TIMER_E500) { 98 /* e500 Fixed-interval timer period extension */ 99 uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK) 100 >> TCR_E500_FPEXT_SHIFT; 101 fp = 63 - (fp | fpext << 2); 102 } else { 103 fp = env->fit_period[fp]; 104 } 105 106 return fp; 107 } 108 109 /* Return the location of the bit of time base at which the WDT will raise an 110 interrupt */ 111 static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env) 112 { 113 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT; 114 115 if (tb_env->flags & PPC_TIMER_E500) { 116 /* e500 Watchdog timer period extension */ 117 uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK) 118 >> TCR_E500_WPEXT_SHIFT; 119 wp = 63 - (wp | wpext << 2); 120 } else { 121 wp = env->wdt_period[wp]; 122 } 123 124 return wp; 125 } 126 127 static void booke_update_fixed_timer(CPUPPCState *env, 128 uint8_t target_bit, 129 uint64_t *next, 130 struct QEMUTimer *timer) 131 { 132 ppc_tb_t *tb_env = env->tb_env; 133 uint64_t lapse; 134 uint64_t tb; 135 uint64_t period = 1 << (target_bit + 1); 136 uint64_t now; 137 138 now = qemu_get_clock_ns(vm_clock); 139 tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset); 140 141 lapse = period - ((tb - (1 << target_bit)) & (period - 1)); 142 143 *next = now + muldiv64(lapse, get_ticks_per_sec(), tb_env->tb_freq); 144 145 /* XXX: If expire time is now. We can't run the callback because we don't 146 * have access to it. So we just set the timer one nanosecond later. 147 */ 148 149 if (*next == now) { 150 (*next)++; 151 } 152 153 qemu_mod_timer(timer, *next); 154 } 155 156 static void booke_decr_cb(void *opaque) 157 { 158 PowerPCCPU *cpu = opaque; 159 CPUPPCState *env = &cpu->env; 160 161 env->spr[SPR_BOOKE_TSR] |= TSR_DIS; 162 booke_update_irq(cpu); 163 164 if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) { 165 /* Auto Reload */ 166 cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]); 167 } 168 } 169 170 static void booke_fit_cb(void *opaque) 171 { 172 PowerPCCPU *cpu = opaque; 173 CPUPPCState *env = &cpu->env; 174 ppc_tb_t *tb_env; 175 booke_timer_t *booke_timer; 176 177 tb_env = env->tb_env; 178 booke_timer = tb_env->opaque; 179 env->spr[SPR_BOOKE_TSR] |= TSR_FIS; 180 181 booke_update_irq(cpu); 182 183 booke_update_fixed_timer(env, 184 booke_get_fit_target(env, tb_env), 185 &booke_timer->fit_next, 186 booke_timer->fit_timer); 187 } 188 189 static void booke_wdt_cb(void *opaque) 190 { 191 PowerPCCPU *cpu = opaque; 192 CPUPPCState *env = &cpu->env; 193 ppc_tb_t *tb_env; 194 booke_timer_t *booke_timer; 195 196 tb_env = env->tb_env; 197 booke_timer = tb_env->opaque; 198 199 /* TODO: There's lots of complicated stuff to do here */ 200 201 booke_update_irq(cpu); 202 203 booke_update_fixed_timer(env, 204 booke_get_wdt_target(env, tb_env), 205 &booke_timer->wdt_next, 206 booke_timer->wdt_timer); 207 } 208 209 void store_booke_tsr(CPUPPCState *env, target_ulong val) 210 { 211 PowerPCCPU *cpu = ppc_env_get_cpu(env); 212 213 env->spr[SPR_BOOKE_TSR] &= ~val; 214 booke_update_irq(cpu); 215 } 216 217 void store_booke_tcr(CPUPPCState *env, target_ulong val) 218 { 219 PowerPCCPU *cpu = ppc_env_get_cpu(env); 220 ppc_tb_t *tb_env = env->tb_env; 221 booke_timer_t *booke_timer = tb_env->opaque; 222 223 tb_env = env->tb_env; 224 env->spr[SPR_BOOKE_TCR] = val; 225 226 booke_update_irq(cpu); 227 228 booke_update_fixed_timer(env, 229 booke_get_fit_target(env, tb_env), 230 &booke_timer->fit_next, 231 booke_timer->fit_timer); 232 233 booke_update_fixed_timer(env, 234 booke_get_wdt_target(env, tb_env), 235 &booke_timer->wdt_next, 236 booke_timer->wdt_timer); 237 238 } 239 240 static void ppc_booke_timer_reset_handle(void *opaque) 241 { 242 PowerPCCPU *cpu = opaque; 243 CPUPPCState *env = &cpu->env; 244 245 env->spr[SPR_BOOKE_TSR] = 0; 246 env->spr[SPR_BOOKE_TCR] = 0; 247 248 booke_update_irq(cpu); 249 } 250 251 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags) 252 { 253 ppc_tb_t *tb_env; 254 booke_timer_t *booke_timer; 255 256 tb_env = g_malloc0(sizeof(ppc_tb_t)); 257 booke_timer = g_malloc0(sizeof(booke_timer_t)); 258 259 cpu->env.tb_env = tb_env; 260 tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; 261 262 tb_env->tb_freq = freq; 263 tb_env->decr_freq = freq; 264 tb_env->opaque = booke_timer; 265 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &booke_decr_cb, cpu); 266 267 booke_timer->fit_timer = 268 qemu_new_timer_ns(vm_clock, &booke_fit_cb, cpu); 269 booke_timer->wdt_timer = 270 qemu_new_timer_ns(vm_clock, &booke_wdt_cb, cpu); 271 272 qemu_register_reset(ppc_booke_timer_reset_handle, cpu); 273 } 274