19f811207SElena Ufimtseva /* 29f811207SElena Ufimtseva * Copyright © 2018, 2021 Oracle and/or its affiliates. 39f811207SElena Ufimtseva * 49f811207SElena Ufimtseva * This work is licensed under the terms of the GNU GPL, version 2 or later. 59f811207SElena Ufimtseva * See the COPYING file in the top-level directory. 69f811207SElena Ufimtseva * 79f811207SElena Ufimtseva */ 89f811207SElena Ufimtseva 99f811207SElena Ufimtseva #include "qemu/osdep.h" 109f811207SElena Ufimtseva #include "qemu-common.h" 119f811207SElena Ufimtseva 129f811207SElena Ufimtseva #include "hw/remote/proxy.h" 139f811207SElena Ufimtseva #include "hw/pci/pci.h" 149f811207SElena Ufimtseva #include "qapi/error.h" 159f811207SElena Ufimtseva #include "io/channel-util.h" 169f811207SElena Ufimtseva #include "hw/qdev-properties.h" 179f811207SElena Ufimtseva #include "monitor/monitor.h" 189f811207SElena Ufimtseva #include "migration/blocker.h" 199f811207SElena Ufimtseva #include "qemu/sockets.h" 2011ab8725SElena Ufimtseva #include "hw/remote/mpqemu-link.h" 2111ab8725SElena Ufimtseva #include "qemu/error-report.h" 22c746b74aSJagannathan Raman #include "hw/remote/proxy-memory-listener.h" 23c746b74aSJagannathan Raman #include "qom/object.h" 24bd36adb8SJagannathan Raman #include "qemu/event_notifier.h" 25bd36adb8SJagannathan Raman #include "sysemu/kvm.h" 26bd36adb8SJagannathan Raman #include "util/event_notifier-posix.c" 27bd36adb8SJagannathan Raman 281bec145cSJagannathan Raman static void probe_pci_info(PCIDevice *dev, Error **errp); 29b6cc02d9SElena Ufimtseva static void proxy_device_reset(DeviceState *dev); 301bec145cSJagannathan Raman 31bd36adb8SJagannathan Raman static void proxy_intx_update(PCIDevice *pci_dev) 32bd36adb8SJagannathan Raman { 33bd36adb8SJagannathan Raman PCIProxyDev *dev = PCI_PROXY_DEV(pci_dev); 34bd36adb8SJagannathan Raman PCIINTxRoute route; 35bd36adb8SJagannathan Raman int pin = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 36bd36adb8SJagannathan Raman 37bd36adb8SJagannathan Raman if (dev->virq != -1) { 38bd36adb8SJagannathan Raman kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq); 39bd36adb8SJagannathan Raman dev->virq = -1; 40bd36adb8SJagannathan Raman } 41bd36adb8SJagannathan Raman 42bd36adb8SJagannathan Raman route = pci_device_route_intx_to_irq(pci_dev, pin); 43bd36adb8SJagannathan Raman 44bd36adb8SJagannathan Raman dev->virq = route.irq; 45bd36adb8SJagannathan Raman 46bd36adb8SJagannathan Raman if (dev->virq != -1) { 47bd36adb8SJagannathan Raman kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &dev->intr, 48bd36adb8SJagannathan Raman &dev->resample, dev->virq); 49bd36adb8SJagannathan Raman } 50bd36adb8SJagannathan Raman } 51bd36adb8SJagannathan Raman 52bd36adb8SJagannathan Raman static void setup_irqfd(PCIProxyDev *dev) 53bd36adb8SJagannathan Raman { 54bd36adb8SJagannathan Raman PCIDevice *pci_dev = PCI_DEVICE(dev); 55bd36adb8SJagannathan Raman MPQemuMsg msg; 56bd36adb8SJagannathan Raman Error *local_err = NULL; 57bd36adb8SJagannathan Raman 58bd36adb8SJagannathan Raman event_notifier_init(&dev->intr, 0); 59bd36adb8SJagannathan Raman event_notifier_init(&dev->resample, 0); 60bd36adb8SJagannathan Raman 61bd36adb8SJagannathan Raman memset(&msg, 0, sizeof(MPQemuMsg)); 62bd36adb8SJagannathan Raman msg.cmd = MPQEMU_CMD_SET_IRQFD; 63bd36adb8SJagannathan Raman msg.num_fds = 2; 64bd36adb8SJagannathan Raman msg.fds[0] = event_notifier_get_fd(&dev->intr); 65bd36adb8SJagannathan Raman msg.fds[1] = event_notifier_get_fd(&dev->resample); 66bd36adb8SJagannathan Raman msg.size = 0; 67bd36adb8SJagannathan Raman 68bd36adb8SJagannathan Raman if (!mpqemu_msg_send(&msg, dev->ioc, &local_err)) { 69bd36adb8SJagannathan Raman error_report_err(local_err); 70bd36adb8SJagannathan Raman } 71bd36adb8SJagannathan Raman 72bd36adb8SJagannathan Raman dev->virq = -1; 73bd36adb8SJagannathan Raman 74bd36adb8SJagannathan Raman proxy_intx_update(pci_dev); 75bd36adb8SJagannathan Raman 76bd36adb8SJagannathan Raman pci_device_set_intx_routing_notifier(pci_dev, proxy_intx_update); 77bd36adb8SJagannathan Raman } 789f811207SElena Ufimtseva 799f811207SElena Ufimtseva static void pci_proxy_dev_realize(PCIDevice *device, Error **errp) 809f811207SElena Ufimtseva { 819f811207SElena Ufimtseva ERRP_GUARD(); 829f811207SElena Ufimtseva PCIProxyDev *dev = PCI_PROXY_DEV(device); 831bec145cSJagannathan Raman uint8_t *pci_conf = device->config; 849f811207SElena Ufimtseva int fd; 859f811207SElena Ufimtseva 869f811207SElena Ufimtseva if (!dev->fd) { 879f811207SElena Ufimtseva error_setg(errp, "fd parameter not specified for %s", 889f811207SElena Ufimtseva DEVICE(device)->id); 899f811207SElena Ufimtseva return; 909f811207SElena Ufimtseva } 919f811207SElena Ufimtseva 929f811207SElena Ufimtseva fd = monitor_fd_param(monitor_cur(), dev->fd, errp); 939f811207SElena Ufimtseva if (fd == -1) { 949f811207SElena Ufimtseva error_prepend(errp, "proxy: unable to parse fd %s: ", dev->fd); 959f811207SElena Ufimtseva return; 969f811207SElena Ufimtseva } 979f811207SElena Ufimtseva 989f811207SElena Ufimtseva if (!fd_is_socket(fd)) { 999f811207SElena Ufimtseva error_setg(errp, "proxy: fd %d is not a socket", fd); 1009f811207SElena Ufimtseva close(fd); 1019f811207SElena Ufimtseva return; 1029f811207SElena Ufimtseva } 1039f811207SElena Ufimtseva 1049f811207SElena Ufimtseva dev->ioc = qio_channel_new_fd(fd, errp); 1059f811207SElena Ufimtseva 1069f811207SElena Ufimtseva error_setg(&dev->migration_blocker, "%s does not support migration", 1079f811207SElena Ufimtseva TYPE_PCI_PROXY_DEV); 1089f811207SElena Ufimtseva migrate_add_blocker(dev->migration_blocker, errp); 1099f811207SElena Ufimtseva 1109f811207SElena Ufimtseva qemu_mutex_init(&dev->io_mutex); 1119f811207SElena Ufimtseva qio_channel_set_blocking(dev->ioc, true, NULL); 112c746b74aSJagannathan Raman 1131bec145cSJagannathan Raman pci_conf[PCI_LATENCY_TIMER] = 0xff; 1141bec145cSJagannathan Raman pci_conf[PCI_INTERRUPT_PIN] = 0x01; 1151bec145cSJagannathan Raman 116c746b74aSJagannathan Raman proxy_memory_listener_configure(&dev->proxy_listener, dev->ioc); 117bd36adb8SJagannathan Raman 118bd36adb8SJagannathan Raman setup_irqfd(dev); 1191bec145cSJagannathan Raman 1201bec145cSJagannathan Raman probe_pci_info(PCI_DEVICE(dev), errp); 1219f811207SElena Ufimtseva } 1229f811207SElena Ufimtseva 1239f811207SElena Ufimtseva static void pci_proxy_dev_exit(PCIDevice *pdev) 1249f811207SElena Ufimtseva { 1259f811207SElena Ufimtseva PCIProxyDev *dev = PCI_PROXY_DEV(pdev); 1269f811207SElena Ufimtseva 1279f811207SElena Ufimtseva if (dev->ioc) { 1289f811207SElena Ufimtseva qio_channel_close(dev->ioc, NULL); 1299f811207SElena Ufimtseva } 1309f811207SElena Ufimtseva 1319f811207SElena Ufimtseva migrate_del_blocker(dev->migration_blocker); 1329f811207SElena Ufimtseva 1339f811207SElena Ufimtseva error_free(dev->migration_blocker); 134c746b74aSJagannathan Raman 135c746b74aSJagannathan Raman proxy_memory_listener_deconfigure(&dev->proxy_listener); 136bd36adb8SJagannathan Raman 137bd36adb8SJagannathan Raman event_notifier_cleanup(&dev->intr); 138bd36adb8SJagannathan Raman event_notifier_cleanup(&dev->resample); 1399f811207SElena Ufimtseva } 1409f811207SElena Ufimtseva 14111ab8725SElena Ufimtseva static void config_op_send(PCIProxyDev *pdev, uint32_t addr, uint32_t *val, 14211ab8725SElena Ufimtseva int len, unsigned int op) 14311ab8725SElena Ufimtseva { 14411ab8725SElena Ufimtseva MPQemuMsg msg = { 0 }; 14511ab8725SElena Ufimtseva uint64_t ret = -EINVAL; 14611ab8725SElena Ufimtseva Error *local_err = NULL; 14711ab8725SElena Ufimtseva 14811ab8725SElena Ufimtseva msg.cmd = op; 14911ab8725SElena Ufimtseva msg.data.pci_conf_data.addr = addr; 15011ab8725SElena Ufimtseva msg.data.pci_conf_data.val = (op == MPQEMU_CMD_PCI_CFGWRITE) ? *val : 0; 15111ab8725SElena Ufimtseva msg.data.pci_conf_data.len = len; 15211ab8725SElena Ufimtseva msg.size = sizeof(PciConfDataMsg); 15311ab8725SElena Ufimtseva 15411ab8725SElena Ufimtseva ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); 15511ab8725SElena Ufimtseva if (local_err) { 15611ab8725SElena Ufimtseva error_report_err(local_err); 15711ab8725SElena Ufimtseva } 15811ab8725SElena Ufimtseva 15911ab8725SElena Ufimtseva if (ret == UINT64_MAX) { 16011ab8725SElena Ufimtseva error_report("Failed to perform PCI config %s operation", 16111ab8725SElena Ufimtseva (op == MPQEMU_CMD_PCI_CFGREAD) ? "READ" : "WRITE"); 16211ab8725SElena Ufimtseva } 16311ab8725SElena Ufimtseva 16411ab8725SElena Ufimtseva if (op == MPQEMU_CMD_PCI_CFGREAD) { 16511ab8725SElena Ufimtseva *val = (uint32_t)ret; 16611ab8725SElena Ufimtseva } 16711ab8725SElena Ufimtseva } 16811ab8725SElena Ufimtseva 16911ab8725SElena Ufimtseva static uint32_t pci_proxy_read_config(PCIDevice *d, uint32_t addr, int len) 17011ab8725SElena Ufimtseva { 17111ab8725SElena Ufimtseva uint32_t val; 17211ab8725SElena Ufimtseva 17311ab8725SElena Ufimtseva config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGREAD); 17411ab8725SElena Ufimtseva 17511ab8725SElena Ufimtseva return val; 17611ab8725SElena Ufimtseva } 17711ab8725SElena Ufimtseva 17811ab8725SElena Ufimtseva static void pci_proxy_write_config(PCIDevice *d, uint32_t addr, uint32_t val, 17911ab8725SElena Ufimtseva int len) 18011ab8725SElena Ufimtseva { 18111ab8725SElena Ufimtseva /* 18211ab8725SElena Ufimtseva * Some of the functions access the copy of remote device's PCI config 18311ab8725SElena Ufimtseva * space which is cached in the proxy device. Therefore, maintain 18411ab8725SElena Ufimtseva * it updated. 18511ab8725SElena Ufimtseva */ 18611ab8725SElena Ufimtseva pci_default_write_config(d, addr, val, len); 18711ab8725SElena Ufimtseva 18811ab8725SElena Ufimtseva config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGWRITE); 18911ab8725SElena Ufimtseva } 19011ab8725SElena Ufimtseva 1919f811207SElena Ufimtseva static Property proxy_properties[] = { 1929f811207SElena Ufimtseva DEFINE_PROP_STRING("fd", PCIProxyDev, fd), 1939f811207SElena Ufimtseva DEFINE_PROP_END_OF_LIST(), 1949f811207SElena Ufimtseva }; 1959f811207SElena Ufimtseva 1969f811207SElena Ufimtseva static void pci_proxy_dev_class_init(ObjectClass *klass, void *data) 1979f811207SElena Ufimtseva { 1989f811207SElena Ufimtseva DeviceClass *dc = DEVICE_CLASS(klass); 1999f811207SElena Ufimtseva PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2009f811207SElena Ufimtseva 2019f811207SElena Ufimtseva k->realize = pci_proxy_dev_realize; 2029f811207SElena Ufimtseva k->exit = pci_proxy_dev_exit; 20311ab8725SElena Ufimtseva k->config_read = pci_proxy_read_config; 20411ab8725SElena Ufimtseva k->config_write = pci_proxy_write_config; 20511ab8725SElena Ufimtseva 206b6cc02d9SElena Ufimtseva dc->reset = proxy_device_reset; 207b6cc02d9SElena Ufimtseva 2089f811207SElena Ufimtseva device_class_set_props(dc, proxy_properties); 2099f811207SElena Ufimtseva } 2109f811207SElena Ufimtseva 2119f811207SElena Ufimtseva static const TypeInfo pci_proxy_dev_type_info = { 2129f811207SElena Ufimtseva .name = TYPE_PCI_PROXY_DEV, 2139f811207SElena Ufimtseva .parent = TYPE_PCI_DEVICE, 2149f811207SElena Ufimtseva .instance_size = sizeof(PCIProxyDev), 2159f811207SElena Ufimtseva .class_init = pci_proxy_dev_class_init, 2169f811207SElena Ufimtseva .interfaces = (InterfaceInfo[]) { 2179f811207SElena Ufimtseva { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 2189f811207SElena Ufimtseva { }, 2199f811207SElena Ufimtseva }, 2209f811207SElena Ufimtseva }; 2219f811207SElena Ufimtseva 2229f811207SElena Ufimtseva static void pci_proxy_dev_register_types(void) 2239f811207SElena Ufimtseva { 2249f811207SElena Ufimtseva type_register_static(&pci_proxy_dev_type_info); 2259f811207SElena Ufimtseva } 2269f811207SElena Ufimtseva 2279f811207SElena Ufimtseva type_init(pci_proxy_dev_register_types) 2287ee3f823SJagannathan Raman 2297ee3f823SJagannathan Raman static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr, 2307ee3f823SJagannathan Raman bool write, hwaddr addr, uint64_t *val, 2317ee3f823SJagannathan Raman unsigned size, bool memory) 2327ee3f823SJagannathan Raman { 2337ee3f823SJagannathan Raman MPQemuMsg msg = { 0 }; 2347ee3f823SJagannathan Raman long ret = -EINVAL; 2357ee3f823SJagannathan Raman Error *local_err = NULL; 2367ee3f823SJagannathan Raman 2377ee3f823SJagannathan Raman msg.size = sizeof(BarAccessMsg); 2387ee3f823SJagannathan Raman msg.data.bar_access.addr = mr->addr + addr; 2397ee3f823SJagannathan Raman msg.data.bar_access.size = size; 2407ee3f823SJagannathan Raman msg.data.bar_access.memory = memory; 2417ee3f823SJagannathan Raman 2427ee3f823SJagannathan Raman if (write) { 2437ee3f823SJagannathan Raman msg.cmd = MPQEMU_CMD_BAR_WRITE; 2447ee3f823SJagannathan Raman msg.data.bar_access.val = *val; 2457ee3f823SJagannathan Raman } else { 2467ee3f823SJagannathan Raman msg.cmd = MPQEMU_CMD_BAR_READ; 2477ee3f823SJagannathan Raman } 2487ee3f823SJagannathan Raman 2497ee3f823SJagannathan Raman ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); 2507ee3f823SJagannathan Raman if (local_err) { 2517ee3f823SJagannathan Raman error_report_err(local_err); 2527ee3f823SJagannathan Raman } 2537ee3f823SJagannathan Raman 2547ee3f823SJagannathan Raman if (!write) { 2557ee3f823SJagannathan Raman *val = ret; 2567ee3f823SJagannathan Raman } 2577ee3f823SJagannathan Raman } 2587ee3f823SJagannathan Raman 2597ee3f823SJagannathan Raman static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val, 2607ee3f823SJagannathan Raman unsigned size) 2617ee3f823SJagannathan Raman { 2627ee3f823SJagannathan Raman ProxyMemoryRegion *pmr = opaque; 2637ee3f823SJagannathan Raman 2647ee3f823SJagannathan Raman send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size, 2657ee3f823SJagannathan Raman pmr->memory); 2667ee3f823SJagannathan Raman } 2677ee3f823SJagannathan Raman 2687ee3f823SJagannathan Raman static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size) 2697ee3f823SJagannathan Raman { 2707ee3f823SJagannathan Raman ProxyMemoryRegion *pmr = opaque; 2717ee3f823SJagannathan Raman uint64_t val; 2727ee3f823SJagannathan Raman 2737ee3f823SJagannathan Raman send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size, 2747ee3f823SJagannathan Raman pmr->memory); 2757ee3f823SJagannathan Raman 2767ee3f823SJagannathan Raman return val; 2777ee3f823SJagannathan Raman } 2787ee3f823SJagannathan Raman 2797ee3f823SJagannathan Raman const MemoryRegionOps proxy_mr_ops = { 2807ee3f823SJagannathan Raman .read = proxy_bar_read, 2817ee3f823SJagannathan Raman .write = proxy_bar_write, 2827ee3f823SJagannathan Raman .endianness = DEVICE_NATIVE_ENDIAN, 2837ee3f823SJagannathan Raman .impl = { 2847ee3f823SJagannathan Raman .min_access_size = 1, 2857ee3f823SJagannathan Raman .max_access_size = 8, 2867ee3f823SJagannathan Raman }, 2877ee3f823SJagannathan Raman }; 2881bec145cSJagannathan Raman 2891bec145cSJagannathan Raman static void probe_pci_info(PCIDevice *dev, Error **errp) 2901bec145cSJagannathan Raman { 2911bec145cSJagannathan Raman PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2921bec145cSJagannathan Raman uint32_t orig_val, new_val, base_class, val; 2931bec145cSJagannathan Raman PCIProxyDev *pdev = PCI_PROXY_DEV(dev); 2941bec145cSJagannathan Raman DeviceClass *dc = DEVICE_CLASS(pc); 2951bec145cSJagannathan Raman uint8_t type; 2961bec145cSJagannathan Raman int i, size; 2971bec145cSJagannathan Raman 2981bec145cSJagannathan Raman config_op_send(pdev, PCI_VENDOR_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 2991bec145cSJagannathan Raman pc->vendor_id = (uint16_t)val; 3001bec145cSJagannathan Raman 3011bec145cSJagannathan Raman config_op_send(pdev, PCI_DEVICE_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 3021bec145cSJagannathan Raman pc->device_id = (uint16_t)val; 3031bec145cSJagannathan Raman 3041bec145cSJagannathan Raman config_op_send(pdev, PCI_CLASS_DEVICE, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 3051bec145cSJagannathan Raman pc->class_id = (uint16_t)val; 3061bec145cSJagannathan Raman 3071bec145cSJagannathan Raman config_op_send(pdev, PCI_SUBSYSTEM_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 3081bec145cSJagannathan Raman pc->subsystem_id = (uint16_t)val; 3091bec145cSJagannathan Raman 3101bec145cSJagannathan Raman base_class = pc->class_id >> 4; 3111bec145cSJagannathan Raman switch (base_class) { 3121bec145cSJagannathan Raman case PCI_BASE_CLASS_BRIDGE: 3131bec145cSJagannathan Raman set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 3141bec145cSJagannathan Raman break; 3151bec145cSJagannathan Raman case PCI_BASE_CLASS_STORAGE: 3161bec145cSJagannathan Raman set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 3171bec145cSJagannathan Raman break; 3181bec145cSJagannathan Raman case PCI_BASE_CLASS_NETWORK: 3191bec145cSJagannathan Raman set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 3201bec145cSJagannathan Raman break; 3211bec145cSJagannathan Raman case PCI_BASE_CLASS_INPUT: 3221bec145cSJagannathan Raman set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 3231bec145cSJagannathan Raman break; 3241bec145cSJagannathan Raman case PCI_BASE_CLASS_DISPLAY: 3251bec145cSJagannathan Raman set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 3261bec145cSJagannathan Raman break; 3271bec145cSJagannathan Raman case PCI_BASE_CLASS_PROCESSOR: 3281bec145cSJagannathan Raman set_bit(DEVICE_CATEGORY_CPU, dc->categories); 3291bec145cSJagannathan Raman break; 3301bec145cSJagannathan Raman default: 3311bec145cSJagannathan Raman set_bit(DEVICE_CATEGORY_MISC, dc->categories); 3321bec145cSJagannathan Raman break; 3331bec145cSJagannathan Raman } 3341bec145cSJagannathan Raman 3351bec145cSJagannathan Raman for (i = 0; i < PCI_NUM_REGIONS; i++) { 3361bec145cSJagannathan Raman config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4, 3371bec145cSJagannathan Raman MPQEMU_CMD_PCI_CFGREAD); 3381bec145cSJagannathan Raman new_val = 0xffffffff; 3391bec145cSJagannathan Raman config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, 3401bec145cSJagannathan Raman MPQEMU_CMD_PCI_CFGWRITE); 3411bec145cSJagannathan Raman config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, 3421bec145cSJagannathan Raman MPQEMU_CMD_PCI_CFGREAD); 3431bec145cSJagannathan Raman size = (~(new_val & 0xFFFFFFF0)) + 1; 3441bec145cSJagannathan Raman config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4, 3451bec145cSJagannathan Raman MPQEMU_CMD_PCI_CFGWRITE); 3461bec145cSJagannathan Raman type = (new_val & 0x1) ? 3471bec145cSJagannathan Raman PCI_BASE_ADDRESS_SPACE_IO : PCI_BASE_ADDRESS_SPACE_MEMORY; 3481bec145cSJagannathan Raman 3491bec145cSJagannathan Raman if (size) { 350*d9022680SZenghui Yu g_autofree char *name = g_strdup_printf("bar-region-%d", i); 3511bec145cSJagannathan Raman pdev->region[i].dev = pdev; 3521bec145cSJagannathan Raman pdev->region[i].present = true; 3531bec145cSJagannathan Raman if (type == PCI_BASE_ADDRESS_SPACE_MEMORY) { 3541bec145cSJagannathan Raman pdev->region[i].memory = true; 3551bec145cSJagannathan Raman } 3561bec145cSJagannathan Raman memory_region_init_io(&pdev->region[i].mr, OBJECT(pdev), 3571bec145cSJagannathan Raman &proxy_mr_ops, &pdev->region[i], 3581bec145cSJagannathan Raman name, size); 3591bec145cSJagannathan Raman pci_register_bar(dev, i, type, &pdev->region[i].mr); 3601bec145cSJagannathan Raman } 3611bec145cSJagannathan Raman } 3621bec145cSJagannathan Raman } 363b6cc02d9SElena Ufimtseva 364b6cc02d9SElena Ufimtseva static void proxy_device_reset(DeviceState *dev) 365b6cc02d9SElena Ufimtseva { 366b6cc02d9SElena Ufimtseva PCIProxyDev *pdev = PCI_PROXY_DEV(dev); 367b6cc02d9SElena Ufimtseva MPQemuMsg msg = { 0 }; 368b6cc02d9SElena Ufimtseva Error *local_err = NULL; 369b6cc02d9SElena Ufimtseva 370b6cc02d9SElena Ufimtseva msg.cmd = MPQEMU_CMD_DEVICE_RESET; 371b6cc02d9SElena Ufimtseva msg.size = 0; 372b6cc02d9SElena Ufimtseva 373b6cc02d9SElena Ufimtseva mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); 374b6cc02d9SElena Ufimtseva if (local_err) { 375b6cc02d9SElena Ufimtseva error_report_err(local_err); 376b6cc02d9SElena Ufimtseva } 377b6cc02d9SElena Ufimtseva 378b6cc02d9SElena Ufimtseva } 379