12bea128cSEddie James /*
22bea128cSEddie James * Aspeed SD Host Controller
32bea128cSEddie James * Eddie James <eajames@linux.ibm.com>
42bea128cSEddie James *
52bea128cSEddie James * Copyright (C) 2019 IBM Corp
65054ba10SRyan Finnie * SPDX-License-Identifier: GPL-2.0-or-later
72bea128cSEddie James */
82bea128cSEddie James
92bea128cSEddie James #include "qemu/osdep.h"
102bea128cSEddie James #include "qemu/log.h"
112bea128cSEddie James #include "qemu/error-report.h"
122bea128cSEddie James #include "hw/sd/aspeed_sdhci.h"
132bea128cSEddie James #include "qapi/error.h"
142bea128cSEddie James #include "hw/irq.h"
152bea128cSEddie James #include "migration/vmstate.h"
160e2c24c6SAndrew Jeffery #include "hw/qdev-properties.h"
17b12fa611SCédric Le Goater #include "trace.h"
182bea128cSEddie James
192bea128cSEddie James #define ASPEED_SDHCI_INFO 0x00
20f31e8f13SCédric Le Goater #define ASPEED_SDHCI_INFO_SLOT1 (1 << 17)
21f31e8f13SCédric Le Goater #define ASPEED_SDHCI_INFO_SLOT0 (1 << 16)
22f31e8f13SCédric Le Goater #define ASPEED_SDHCI_INFO_RESET (1 << 0)
232bea128cSEddie James #define ASPEED_SDHCI_DEBOUNCE 0x04
242bea128cSEddie James #define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005
252bea128cSEddie James #define ASPEED_SDHCI_BUS 0x08
262bea128cSEddie James #define ASPEED_SDHCI_SDIO_140 0x10
272bea128cSEddie James #define ASPEED_SDHCI_SDIO_148 0x18
282bea128cSEddie James #define ASPEED_SDHCI_SDIO_240 0x20
292bea128cSEddie James #define ASPEED_SDHCI_SDIO_248 0x28
302bea128cSEddie James #define ASPEED_SDHCI_WP_POL 0xec
312bea128cSEddie James #define ASPEED_SDHCI_CARD_DET 0xf0
322bea128cSEddie James #define ASPEED_SDHCI_IRQ_STAT 0xfc
332bea128cSEddie James
342bea128cSEddie James #define TO_REG(addr) ((addr) / sizeof(uint32_t))
352bea128cSEddie James
aspeed_sdhci_read(void * opaque,hwaddr addr,unsigned int size)362bea128cSEddie James static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
372bea128cSEddie James {
382bea128cSEddie James uint32_t val = 0;
392bea128cSEddie James AspeedSDHCIState *sdhci = opaque;
402bea128cSEddie James
412bea128cSEddie James switch (addr) {
422bea128cSEddie James case ASPEED_SDHCI_SDIO_140:
432bea128cSEddie James val = (uint32_t)sdhci->slots[0].capareg;
442bea128cSEddie James break;
452bea128cSEddie James case ASPEED_SDHCI_SDIO_148:
462bea128cSEddie James val = (uint32_t)sdhci->slots[0].maxcurr;
472bea128cSEddie James break;
482bea128cSEddie James case ASPEED_SDHCI_SDIO_240:
492bea128cSEddie James val = (uint32_t)sdhci->slots[1].capareg;
502bea128cSEddie James break;
512bea128cSEddie James case ASPEED_SDHCI_SDIO_248:
522bea128cSEddie James val = (uint32_t)sdhci->slots[1].maxcurr;
532bea128cSEddie James break;
542bea128cSEddie James default:
552bea128cSEddie James if (addr < ASPEED_SDHCI_REG_SIZE) {
562bea128cSEddie James val = sdhci->regs[TO_REG(addr)];
572bea128cSEddie James } else {
582bea128cSEddie James qemu_log_mask(LOG_GUEST_ERROR,
592bea128cSEddie James "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n",
602bea128cSEddie James __func__, addr);
612bea128cSEddie James }
622bea128cSEddie James }
632bea128cSEddie James
64b12fa611SCédric Le Goater trace_aspeed_sdhci_read(addr, size, (uint64_t) val);
65b12fa611SCédric Le Goater
662bea128cSEddie James return (uint64_t)val;
672bea128cSEddie James }
682bea128cSEddie James
aspeed_sdhci_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)692bea128cSEddie James static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
702bea128cSEddie James unsigned int size)
712bea128cSEddie James {
722bea128cSEddie James AspeedSDHCIState *sdhci = opaque;
732bea128cSEddie James
74b12fa611SCédric Le Goater trace_aspeed_sdhci_write(addr, size, val);
75b12fa611SCédric Le Goater
762bea128cSEddie James switch (addr) {
77f31e8f13SCédric Le Goater case ASPEED_SDHCI_INFO:
78f31e8f13SCédric Le Goater /* The RESET bit automatically clears. */
79f31e8f13SCédric Le Goater sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;
80f31e8f13SCédric Le Goater break;
812bea128cSEddie James case ASPEED_SDHCI_SDIO_140:
822bea128cSEddie James sdhci->slots[0].capareg = (uint64_t)(uint32_t)val;
832bea128cSEddie James break;
842bea128cSEddie James case ASPEED_SDHCI_SDIO_148:
852bea128cSEddie James sdhci->slots[0].maxcurr = (uint64_t)(uint32_t)val;
862bea128cSEddie James break;
872bea128cSEddie James case ASPEED_SDHCI_SDIO_240:
882bea128cSEddie James sdhci->slots[1].capareg = (uint64_t)(uint32_t)val;
892bea128cSEddie James break;
902bea128cSEddie James case ASPEED_SDHCI_SDIO_248:
912bea128cSEddie James sdhci->slots[1].maxcurr = (uint64_t)(uint32_t)val;
922bea128cSEddie James break;
932bea128cSEddie James default:
942bea128cSEddie James if (addr < ASPEED_SDHCI_REG_SIZE) {
952bea128cSEddie James sdhci->regs[TO_REG(addr)] = (uint32_t)val;
962bea128cSEddie James } else {
972bea128cSEddie James qemu_log_mask(LOG_GUEST_ERROR,
982bea128cSEddie James "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n",
992bea128cSEddie James __func__, addr);
1002bea128cSEddie James }
1012bea128cSEddie James }
1022bea128cSEddie James }
1032bea128cSEddie James
1042bea128cSEddie James static const MemoryRegionOps aspeed_sdhci_ops = {
1052bea128cSEddie James .read = aspeed_sdhci_read,
1062bea128cSEddie James .write = aspeed_sdhci_write,
1072bea128cSEddie James .endianness = DEVICE_NATIVE_ENDIAN,
1082bea128cSEddie James .valid.min_access_size = 4,
1092bea128cSEddie James .valid.max_access_size = 4,
1102bea128cSEddie James };
1112bea128cSEddie James
aspeed_sdhci_set_irq(void * opaque,int n,int level)1122bea128cSEddie James static void aspeed_sdhci_set_irq(void *opaque, int n, int level)
1132bea128cSEddie James {
1142bea128cSEddie James AspeedSDHCIState *sdhci = opaque;
1152bea128cSEddie James
1162bea128cSEddie James if (level) {
1172bea128cSEddie James sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n);
1182bea128cSEddie James
1192bea128cSEddie James qemu_irq_raise(sdhci->irq);
1202bea128cSEddie James } else {
1212bea128cSEddie James sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n);
1222bea128cSEddie James
1232bea128cSEddie James qemu_irq_lower(sdhci->irq);
1242bea128cSEddie James }
1252bea128cSEddie James }
1262bea128cSEddie James
aspeed_sdhci_realize(DeviceState * dev,Error ** errp)1272bea128cSEddie James static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
1282bea128cSEddie James {
1292bea128cSEddie James SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1302bea128cSEddie James AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
1312bea128cSEddie James
1322bea128cSEddie James /* Create input irqs for the slots */
1332bea128cSEddie James qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
1340e2c24c6SAndrew Jeffery sdhci, NULL, sdhci->num_slots);
1352bea128cSEddie James
1362bea128cSEddie James sysbus_init_irq(sbd, &sdhci->irq);
1372bea128cSEddie James memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops,
1382bea128cSEddie James sdhci, TYPE_ASPEED_SDHCI, 0x1000);
1392bea128cSEddie James sysbus_init_mmio(sbd, &sdhci->iomem);
1402bea128cSEddie James
1410e2c24c6SAndrew Jeffery for (int i = 0; i < sdhci->num_slots; ++i) {
1422bea128cSEddie James Object *sdhci_slot = OBJECT(&sdhci->slots[i]);
1432bea128cSEddie James SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]);
1442bea128cSEddie James
145668f62ecSMarkus Armbruster if (!object_property_set_int(sdhci_slot, "sd-spec-version", 2, errp)) {
1462bea128cSEddie James return;
1472bea128cSEddie James }
1482bea128cSEddie James
149778a2dc5SMarkus Armbruster if (!object_property_set_uint(sdhci_slot, "capareg",
150668f62ecSMarkus Armbruster ASPEED_SDHCI_CAPABILITIES, errp)) {
1512bea128cSEddie James return;
1522bea128cSEddie James }
1532bea128cSEddie James
154668f62ecSMarkus Armbruster if (!sysbus_realize(sbd_slot, errp)) {
1552bea128cSEddie James return;
1562bea128cSEddie James }
1572bea128cSEddie James
1582bea128cSEddie James sysbus_connect_irq(sbd_slot, 0, qdev_get_gpio_in(DEVICE(sbd), i));
1592bea128cSEddie James memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100,
1602bea128cSEddie James &sdhci->slots[i].iomem);
1612bea128cSEddie James }
1622bea128cSEddie James }
1632bea128cSEddie James
aspeed_sdhci_reset(DeviceState * dev)1642bea128cSEddie James static void aspeed_sdhci_reset(DeviceState *dev)
1652bea128cSEddie James {
1662bea128cSEddie James AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
1672bea128cSEddie James
1682bea128cSEddie James memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);
169f31e8f13SCédric Le Goater
170f31e8f13SCédric Le Goater sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0;
171f31e8f13SCédric Le Goater if (sdhci->num_slots == 2) {
172f31e8f13SCédric Le Goater sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1;
173f31e8f13SCédric Le Goater }
1742bea128cSEddie James sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;
1752bea128cSEddie James }
1762bea128cSEddie James
1772bea128cSEddie James static const VMStateDescription vmstate_aspeed_sdhci = {
1782bea128cSEddie James .name = TYPE_ASPEED_SDHCI,
1792bea128cSEddie James .version_id = 1,
180307119baSRichard Henderson .fields = (const VMStateField[]) {
1812bea128cSEddie James VMSTATE_UINT32_ARRAY(regs, AspeedSDHCIState, ASPEED_SDHCI_NUM_REGS),
1822bea128cSEddie James VMSTATE_END_OF_LIST(),
1832bea128cSEddie James },
1842bea128cSEddie James };
1852bea128cSEddie James
1860e2c24c6SAndrew Jeffery static Property aspeed_sdhci_properties[] = {
1870e2c24c6SAndrew Jeffery DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0),
1880e2c24c6SAndrew Jeffery DEFINE_PROP_END_OF_LIST(),
1890e2c24c6SAndrew Jeffery };
1900e2c24c6SAndrew Jeffery
aspeed_sdhci_class_init(ObjectClass * classp,void * data)1912bea128cSEddie James static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
1922bea128cSEddie James {
1932bea128cSEddie James DeviceClass *dc = DEVICE_CLASS(classp);
1942bea128cSEddie James
1952bea128cSEddie James dc->realize = aspeed_sdhci_realize;
196*e3d08143SPeter Maydell device_class_set_legacy_reset(dc, aspeed_sdhci_reset);
1972bea128cSEddie James dc->vmsd = &vmstate_aspeed_sdhci;
1980e2c24c6SAndrew Jeffery device_class_set_props(dc, aspeed_sdhci_properties);
1992bea128cSEddie James }
2002bea128cSEddie James
20188d2198cSPhilippe Mathieu-Daudé static const TypeInfo aspeed_sdhci_types[] = {
20288d2198cSPhilippe Mathieu-Daudé {
2032bea128cSEddie James .name = TYPE_ASPEED_SDHCI,
2042bea128cSEddie James .parent = TYPE_SYS_BUS_DEVICE,
2052bea128cSEddie James .instance_size = sizeof(AspeedSDHCIState),
2062bea128cSEddie James .class_init = aspeed_sdhci_class_init,
20788d2198cSPhilippe Mathieu-Daudé },
2082bea128cSEddie James };
2092bea128cSEddie James
21088d2198cSPhilippe Mathieu-Daudé DEFINE_TYPES(aspeed_sdhci_types)
211