1*d831c5fdSJamin Lin /* 2*d831c5fdSJamin Lin * ASPEED INTC Controller 3*d831c5fdSJamin Lin * 4*d831c5fdSJamin Lin * Copyright (C) 2024 ASPEED Technology Inc. 5*d831c5fdSJamin Lin * 6*d831c5fdSJamin Lin * SPDX-License-Identifier: GPL-2.0-or-later 7*d831c5fdSJamin Lin */ 8*d831c5fdSJamin Lin #ifndef ASPEED_INTC_H 9*d831c5fdSJamin Lin #define ASPEED_INTC_H 10*d831c5fdSJamin Lin 11*d831c5fdSJamin Lin #include "hw/sysbus.h" 12*d831c5fdSJamin Lin #include "qom/object.h" 13*d831c5fdSJamin Lin #include "hw/or-irq.h" 14*d831c5fdSJamin Lin 15*d831c5fdSJamin Lin #define TYPE_ASPEED_INTC "aspeed.intc" 16*d831c5fdSJamin Lin #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" 17*d831c5fdSJamin Lin OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC) 18*d831c5fdSJamin Lin 19*d831c5fdSJamin Lin #define ASPEED_INTC_NR_REGS (0x2000 >> 2) 20*d831c5fdSJamin Lin #define ASPEED_INTC_NR_INTS 9 21*d831c5fdSJamin Lin 22*d831c5fdSJamin Lin struct AspeedINTCState { 23*d831c5fdSJamin Lin /*< private >*/ 24*d831c5fdSJamin Lin SysBusDevice parent_obj; 25*d831c5fdSJamin Lin 26*d831c5fdSJamin Lin /*< public >*/ 27*d831c5fdSJamin Lin MemoryRegion iomem; 28*d831c5fdSJamin Lin uint32_t regs[ASPEED_INTC_NR_REGS]; 29*d831c5fdSJamin Lin OrIRQState orgates[ASPEED_INTC_NR_INTS]; 30*d831c5fdSJamin Lin qemu_irq output_pins[ASPEED_INTC_NR_INTS]; 31*d831c5fdSJamin Lin 32*d831c5fdSJamin Lin uint32_t enable[ASPEED_INTC_NR_INTS]; 33*d831c5fdSJamin Lin uint32_t mask[ASPEED_INTC_NR_INTS]; 34*d831c5fdSJamin Lin uint32_t pending[ASPEED_INTC_NR_INTS]; 35*d831c5fdSJamin Lin }; 36*d831c5fdSJamin Lin 37*d831c5fdSJamin Lin struct AspeedINTCClass { 38*d831c5fdSJamin Lin SysBusDeviceClass parent_class; 39*d831c5fdSJamin Lin 40*d831c5fdSJamin Lin uint32_t num_lines; 41*d831c5fdSJamin Lin uint32_t num_ints; 42*d831c5fdSJamin Lin }; 43*d831c5fdSJamin Lin 44*d831c5fdSJamin Lin #endif /* ASPEED_INTC_H */ 45