1f250c6a7SJean-Christophe Dubois /* 2f250c6a7SJean-Christophe Dubois * i.MX31 Vectored Interrupt Controller 3f250c6a7SJean-Christophe Dubois * 4f250c6a7SJean-Christophe Dubois * Note this is NOT the PL192 provided by ARM, but 5f250c6a7SJean-Christophe Dubois * a custom implementation by Freescale. 6f250c6a7SJean-Christophe Dubois * 7f250c6a7SJean-Christophe Dubois * Copyright (c) 2008 OKL 8f250c6a7SJean-Christophe Dubois * Copyright (c) 2011 NICTA Pty Ltd 9f250c6a7SJean-Christophe Dubois * Originally written by Hans Jiang 10f250c6a7SJean-Christophe Dubois * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 11f250c6a7SJean-Christophe Dubois * 12f250c6a7SJean-Christophe Dubois * This code is licensed under the GPL version 2 or later. See 13f250c6a7SJean-Christophe Dubois * the COPYING file in the top-level directory. 14f250c6a7SJean-Christophe Dubois * 15f250c6a7SJean-Christophe Dubois * TODO: implement vectors. 16f250c6a7SJean-Christophe Dubois */ 17f250c6a7SJean-Christophe Dubois #ifndef IMX_AVIC_H 18f250c6a7SJean-Christophe Dubois #define IMX_AVIC_H 19f250c6a7SJean-Christophe Dubois 20f250c6a7SJean-Christophe Dubois #include "hw/sysbus.h" 21db1015e9SEduardo Habkost #include "qom/object.h" 22f250c6a7SJean-Christophe Dubois 23f250c6a7SJean-Christophe Dubois #define TYPE_IMX_AVIC "imx.avic" 24*8063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(IMXAVICState, IMX_AVIC) 25f250c6a7SJean-Christophe Dubois 26f250c6a7SJean-Christophe Dubois #define IMX_AVIC_NUM_IRQS 64 27f250c6a7SJean-Christophe Dubois 28f250c6a7SJean-Christophe Dubois /* Interrupt Control Bits */ 29f250c6a7SJean-Christophe Dubois #define ABFLAG (1<<25) 30f250c6a7SJean-Christophe Dubois #define ABFEN (1<<24) 31f250c6a7SJean-Christophe Dubois #define NIDIS (1<<22) /* Normal Interrupt disable */ 32f250c6a7SJean-Christophe Dubois #define FIDIS (1<<21) /* Fast interrupt disable */ 33f250c6a7SJean-Christophe Dubois #define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */ 34f250c6a7SJean-Christophe Dubois #define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */ 35f250c6a7SJean-Christophe Dubois #define NM (1<<18) /* Normal interrupt mode */ 36f250c6a7SJean-Christophe Dubois 37f250c6a7SJean-Christophe Dubois #define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4) 38f250c6a7SJean-Christophe Dubois #define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD) 39f250c6a7SJean-Christophe Dubois 40db1015e9SEduardo Habkost struct IMXAVICState { 41f250c6a7SJean-Christophe Dubois /*< private >*/ 42f250c6a7SJean-Christophe Dubois SysBusDevice parent_obj; 43f250c6a7SJean-Christophe Dubois 44f250c6a7SJean-Christophe Dubois /*< public >*/ 45f250c6a7SJean-Christophe Dubois MemoryRegion iomem; 46f250c6a7SJean-Christophe Dubois uint64_t pending; 47f250c6a7SJean-Christophe Dubois uint64_t enabled; 48f250c6a7SJean-Christophe Dubois uint64_t is_fiq; 49f250c6a7SJean-Christophe Dubois uint32_t intcntl; 50f250c6a7SJean-Christophe Dubois uint32_t intmask; 51f250c6a7SJean-Christophe Dubois qemu_irq irq; 52f250c6a7SJean-Christophe Dubois qemu_irq fiq; 53f250c6a7SJean-Christophe Dubois uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */ 54db1015e9SEduardo Habkost }; 55f250c6a7SJean-Christophe Dubois 56f250c6a7SJean-Christophe Dubois #endif /* IMX_AVIC_H */ 57