1 /* 2 * i.MX FEC/ENET Ethernet Controller emulation. 3 * 4 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> 5 * 6 * Based on Coldfire Fast Ethernet Controller emulation. 7 * 8 * Copyright (c) 2007 CodeSourcery. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18 * for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef IMX_FEC_H 25 #define IMX_FEC_H 26 27 #define TYPE_IMX_FEC "imx.fec" 28 #define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC) 29 30 #define TYPE_IMX_ENET "imx.enet" 31 32 #include "hw/sysbus.h" 33 #include "net/net.h" 34 35 #define ENET_EIR 1 36 #define ENET_EIMR 2 37 #define ENET_RDAR 4 38 #define ENET_TDAR 5 39 #define ENET_ECR 9 40 #define ENET_MMFR 16 41 #define ENET_MSCR 17 42 #define ENET_MIBC 25 43 #define ENET_RCR 33 44 #define ENET_TCR 49 45 #define ENET_PALR 57 46 #define ENET_PAUR 58 47 #define ENET_OPD 59 48 #define ENET_IAUR 70 49 #define ENET_IALR 71 50 #define ENET_GAUR 72 51 #define ENET_GALR 73 52 #define ENET_TFWR 81 53 #define ENET_FRBR 83 54 #define ENET_FRSR 84 55 #define ENET_RDSR 96 56 #define ENET_TDSR 97 57 #define ENET_MRBR 98 58 #define ENET_RSFL 100 59 #define ENET_RSEM 101 60 #define ENET_RAEM 102 61 #define ENET_RAFL 103 62 #define ENET_TSEM 104 63 #define ENET_TAEM 105 64 #define ENET_TAFL 106 65 #define ENET_TIPG 107 66 #define ENET_FTRL 108 67 #define ENET_TACC 112 68 #define ENET_RACC 113 69 #define ENET_MIIGSK_CFGR 192 70 #define ENET_MIIGSK_ENR 194 71 #define ENET_ATCR 256 72 #define ENET_ATVR 257 73 #define ENET_ATOFF 258 74 #define ENET_ATPER 259 75 #define ENET_ATCOR 260 76 #define ENET_ATINC 261 77 #define ENET_ATSTMP 262 78 #define ENET_TGSR 385 79 #define ENET_TCSR0 386 80 #define ENET_TCCR0 387 81 #define ENET_TCSR1 388 82 #define ENET_TCCR1 389 83 #define ENET_TCSR2 390 84 #define ENET_TCCR2 391 85 #define ENET_TCSR3 392 86 #define ENET_TCCR3 393 87 #define ENET_MAX 400 88 89 90 /* EIR and EIMR */ 91 #define ENET_INT_HB (1 << 31) 92 #define ENET_INT_BABR (1 << 30) 93 #define ENET_INT_BABT (1 << 29) 94 #define ENET_INT_GRA (1 << 28) 95 #define ENET_INT_TXF (1 << 27) 96 #define ENET_INT_TXB (1 << 26) 97 #define ENET_INT_RXF (1 << 25) 98 #define ENET_INT_RXB (1 << 24) 99 #define ENET_INT_MII (1 << 23) 100 #define ENET_INT_EBERR (1 << 22) 101 #define ENET_INT_LC (1 << 21) 102 #define ENET_INT_RL (1 << 20) 103 #define ENET_INT_UN (1 << 19) 104 #define ENET_INT_PLR (1 << 18) 105 #define ENET_INT_WAKEUP (1 << 17) 106 #define ENET_INT_TS_AVAIL (1 << 16) 107 #define ENET_INT_TS_TIMER (1 << 15) 108 109 #define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \ 110 ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \ 111 ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \ 112 ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \ 113 ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \ 114 ENET_INT_TS_AVAIL) 115 116 /* RDAR */ 117 #define ENET_RDAR_RDAR (1 << 24) 118 119 /* TDAR */ 120 #define ENET_TDAR_TDAR (1 << 24) 121 122 /* ECR */ 123 #define ENET_ECR_RESET (1 << 0) 124 #define ENET_ECR_ETHEREN (1 << 1) 125 #define ENET_ECR_MAGICEN (1 << 2) 126 #define ENET_ECR_SLEEP (1 << 3) 127 #define ENET_ECR_EN1588 (1 << 4) 128 #define ENET_ECR_SPEED (1 << 5) 129 #define ENET_ECR_DBGEN (1 << 6) 130 #define ENET_ECR_STOPEN (1 << 7) 131 #define ENET_ECR_DSBWP (1 << 8) 132 133 /* MIBC */ 134 #define ENET_MIBC_MIB_DIS (1 << 31) 135 #define ENET_MIBC_MIB_IDLE (1 << 30) 136 #define ENET_MIBC_MIB_CLEAR (1 << 29) 137 138 /* RCR */ 139 #define ENET_RCR_LOOP (1 << 0) 140 #define ENET_RCR_DRT (1 << 1) 141 #define ENET_RCR_MII_MODE (1 << 2) 142 #define ENET_RCR_PROM (1 << 3) 143 #define ENET_RCR_BC_REJ (1 << 4) 144 #define ENET_RCR_FCE (1 << 5) 145 #define ENET_RCR_RGMII_EN (1 << 6) 146 #define ENET_RCR_RMII_MODE (1 << 8) 147 #define ENET_RCR_RMII_10T (1 << 9) 148 #define ENET_RCR_PADEN (1 << 12) 149 #define ENET_RCR_PAUFWD (1 << 13) 150 #define ENET_RCR_CRCFWD (1 << 14) 151 #define ENET_RCR_CFEN (1 << 15) 152 #define ENET_RCR_MAX_FL_SHIFT (16) 153 #define ENET_RCR_MAX_FL_LENGTH (14) 154 #define ENET_RCR_NLC (1 << 30) 155 #define ENET_RCR_GRS (1 << 31) 156 157 #define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH) 158 159 /* TCR */ 160 #define ENET_TCR_GTS (1 << 0) 161 #define ENET_TCR_FDEN (1 << 2) 162 #define ENET_TCR_TFC_PAUSE (1 << 3) 163 #define ENET_TCR_RFC_PAUSE (1 << 4) 164 #define ENET_TCR_ADDSEL_SHIFT (5) 165 #define ENET_TCR_ADDSEL_LENGTH (3) 166 #define ENET_TCR_CRCFWD (1 << 9) 167 168 /* RDSR */ 169 #define ENET_TWFR_TFWR_SHIFT (0) 170 #define ENET_TWFR_TFWR_LENGTH (6) 171 #define ENET_TWFR_STRFWD (1 << 8) 172 173 #define ENET_RACC_SHIFT16 BIT(7) 174 175 /* Buffer Descriptor. */ 176 typedef struct { 177 uint16_t length; 178 uint16_t flags; 179 uint32_t data; 180 } IMXFECBufDesc; 181 182 #define ENET_BD_R (1 << 15) 183 #define ENET_BD_E (1 << 15) 184 #define ENET_BD_O1 (1 << 14) 185 #define ENET_BD_W (1 << 13) 186 #define ENET_BD_O2 (1 << 12) 187 #define ENET_BD_L (1 << 11) 188 #define ENET_BD_TC (1 << 10) 189 #define ENET_BD_ABC (1 << 9) 190 #define ENET_BD_M (1 << 8) 191 #define ENET_BD_BC (1 << 7) 192 #define ENET_BD_MC (1 << 6) 193 #define ENET_BD_LG (1 << 5) 194 #define ENET_BD_NO (1 << 4) 195 #define ENET_BD_CR (1 << 2) 196 #define ENET_BD_OV (1 << 1) 197 #define ENET_BD_TR (1 << 0) 198 199 typedef struct { 200 uint16_t length; 201 uint16_t flags; 202 uint32_t data; 203 uint16_t status; 204 uint16_t option; 205 uint16_t checksum; 206 uint16_t head_proto; 207 uint32_t last_buffer; 208 uint32_t timestamp; 209 uint32_t reserved[2]; 210 } IMXENETBufDesc; 211 212 #define ENET_BD_ME (1 << 15) 213 #define ENET_BD_TX_INT (1 << 14) 214 #define ENET_BD_TS (1 << 13) 215 #define ENET_BD_PINS (1 << 12) 216 #define ENET_BD_IINS (1 << 11) 217 #define ENET_BD_PE (1 << 10) 218 #define ENET_BD_CE (1 << 9) 219 #define ENET_BD_UC (1 << 8) 220 #define ENET_BD_RX_INT (1 << 7) 221 222 #define ENET_BD_TXE (1 << 15) 223 #define ENET_BD_UE (1 << 13) 224 #define ENET_BD_EE (1 << 12) 225 #define ENET_BD_FE (1 << 11) 226 #define ENET_BD_LCE (1 << 10) 227 #define ENET_BD_OE (1 << 9) 228 #define ENET_BD_TSE (1 << 8) 229 #define ENET_BD_ICE (1 << 5) 230 #define ENET_BD_PCR (1 << 4) 231 #define ENET_BD_VLAN (1 << 2) 232 #define ENET_BD_IPV6 (1 << 1) 233 #define ENET_BD_FRAG (1 << 0) 234 235 #define ENET_BD_BDU (1 << 31) 236 237 typedef struct IMXFECState { 238 /*< private >*/ 239 SysBusDevice parent_obj; 240 241 /*< public >*/ 242 NICState *nic; 243 NICConf conf; 244 qemu_irq irq[2]; 245 MemoryRegion iomem; 246 247 uint32_t regs[ENET_MAX]; 248 uint32_t rx_descriptor; 249 uint32_t tx_descriptor; 250 251 uint32_t phy_status; 252 uint32_t phy_control; 253 uint32_t phy_advertise; 254 uint32_t phy_int; 255 uint32_t phy_int_mask; 256 257 bool is_fec; 258 259 /* Buffer used to assemble a Tx frame */ 260 uint8_t frame[ENET_MAX_FRAME_SIZE]; 261 } IMXFECState; 262 263 #endif 264