1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "target/arm/idau.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "cpu.h" 26 #include "internals.h" 27 #include "qemu-common.h" 28 #include "exec/exec-all.h" 29 #include "hw/qdev-properties.h" 30 #if !defined(CONFIG_USER_ONLY) 31 #include "hw/loader.h" 32 #endif 33 #include "hw/arm/arm.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hw_accel.h" 36 #include "kvm_arm.h" 37 #include "disas/capstone.h" 38 #include "fpu/softfloat.h" 39 40 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 41 { 42 ARMCPU *cpu = ARM_CPU(cs); 43 44 cpu->env.regs[15] = value; 45 } 46 47 static bool arm_cpu_has_work(CPUState *cs) 48 { 49 ARMCPU *cpu = ARM_CPU(cs); 50 51 return (cpu->power_state != PSCI_OFF) 52 && cs->interrupt_request & 53 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ 55 | CPU_INTERRUPT_EXITTB); 56 } 57 58 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 59 void *opaque) 60 { 61 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 62 63 entry->hook = hook; 64 entry->opaque = opaque; 65 66 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 67 } 68 69 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 70 void *opaque) 71 { 72 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 73 74 entry->hook = hook; 75 entry->opaque = opaque; 76 77 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 78 } 79 80 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 81 { 82 /* Reset a single ARMCPRegInfo register */ 83 ARMCPRegInfo *ri = value; 84 ARMCPU *cpu = opaque; 85 86 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { 87 return; 88 } 89 90 if (ri->resetfn) { 91 ri->resetfn(&cpu->env, ri); 92 return; 93 } 94 95 /* A zero offset is never possible as it would be regs[0] 96 * so we use it to indicate that reset is being handled elsewhere. 97 * This is basically only used for fields in non-core coprocessors 98 * (like the pxa2xx ones). 99 */ 100 if (!ri->fieldoffset) { 101 return; 102 } 103 104 if (cpreg_field_is_64bit(ri)) { 105 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 106 } else { 107 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 108 } 109 } 110 111 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 112 { 113 /* Purely an assertion check: we've already done reset once, 114 * so now check that running the reset for the cpreg doesn't 115 * change its value. This traps bugs where two different cpregs 116 * both try to reset the same state field but to different values. 117 */ 118 ARMCPRegInfo *ri = value; 119 ARMCPU *cpu = opaque; 120 uint64_t oldvalue, newvalue; 121 122 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 123 return; 124 } 125 126 oldvalue = read_raw_cp_reg(&cpu->env, ri); 127 cp_reg_reset(key, value, opaque); 128 newvalue = read_raw_cp_reg(&cpu->env, ri); 129 assert(oldvalue == newvalue); 130 } 131 132 /* CPUClass::reset() */ 133 static void arm_cpu_reset(CPUState *s) 134 { 135 ARMCPU *cpu = ARM_CPU(s); 136 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 137 CPUARMState *env = &cpu->env; 138 139 acc->parent_reset(s); 140 141 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 142 143 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 144 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 145 146 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 147 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; 148 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; 149 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; 150 151 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; 152 s->halted = cpu->start_powered_off; 153 154 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 155 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 156 } 157 158 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 159 /* 64 bit CPUs always start in 64 bit mode */ 160 env->aarch64 = 1; 161 #if defined(CONFIG_USER_ONLY) 162 env->pstate = PSTATE_MODE_EL0t; 163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 164 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 165 /* and to the FP/Neon instructions */ 166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); 167 /* and to the SVE instructions */ 168 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); 169 env->cp15.cptr_el[3] |= CPTR_EZ; 170 /* with maximum vector length */ 171 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; 172 env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; 173 env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; 174 #else 175 /* Reset into the highest available EL */ 176 if (arm_feature(env, ARM_FEATURE_EL3)) { 177 env->pstate = PSTATE_MODE_EL3h; 178 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 179 env->pstate = PSTATE_MODE_EL2h; 180 } else { 181 env->pstate = PSTATE_MODE_EL1h; 182 } 183 env->pc = cpu->rvbar; 184 #endif 185 } else { 186 #if defined(CONFIG_USER_ONLY) 187 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 188 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); 189 #endif 190 } 191 192 #if defined(CONFIG_USER_ONLY) 193 env->uncached_cpsr = ARM_CPU_MODE_USR; 194 /* For user mode we must enable access to coprocessors */ 195 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 196 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 197 env->cp15.c15_cpar = 3; 198 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 199 env->cp15.c15_cpar = 1; 200 } 201 #else 202 /* SVC mode with interrupts disabled. */ 203 env->uncached_cpsr = ARM_CPU_MODE_SVC; 204 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 205 206 if (arm_feature(env, ARM_FEATURE_M)) { 207 uint32_t initial_msp; /* Loaded from 0x0 */ 208 uint32_t initial_pc; /* Loaded from 0x4 */ 209 uint8_t *rom; 210 uint32_t vecbase; 211 212 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 213 env->v7m.secure = true; 214 } else { 215 /* This bit resets to 0 if security is supported, but 1 if 216 * it is not. The bit is not present in v7M, but we set it 217 * here so we can avoid having to make checks on it conditional 218 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 219 */ 220 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 221 } 222 223 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 224 * that it resets to 1, so QEMU always does that rather than making 225 * it dependent on CPU model. In v8M it is RES1. 226 */ 227 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 228 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 229 if (arm_feature(env, ARM_FEATURE_V8)) { 230 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 231 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 232 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 233 } 234 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 235 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 236 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 237 } 238 239 /* Unlike A/R profile, M profile defines the reset LR value */ 240 env->regs[14] = 0xffffffff; 241 242 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 243 244 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 245 vecbase = env->v7m.vecbase[env->v7m.secure]; 246 rom = rom_ptr(vecbase, 8); 247 if (rom) { 248 /* Address zero is covered by ROM which hasn't yet been 249 * copied into physical memory. 250 */ 251 initial_msp = ldl_p(rom); 252 initial_pc = ldl_p(rom + 4); 253 } else { 254 /* Address zero not covered by a ROM blob, or the ROM blob 255 * is in non-modifiable memory and this is a second reset after 256 * it got copied into memory. In the latter case, rom_ptr 257 * will return a NULL pointer and we should use ldl_phys instead. 258 */ 259 initial_msp = ldl_phys(s->as, vecbase); 260 initial_pc = ldl_phys(s->as, vecbase + 4); 261 } 262 263 env->regs[13] = initial_msp & 0xFFFFFFFC; 264 env->regs[15] = initial_pc & ~1; 265 env->thumb = initial_pc & 1; 266 } 267 268 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 269 * executing as AArch32 then check if highvecs are enabled and 270 * adjust the PC accordingly. 271 */ 272 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 273 env->regs[15] = 0xFFFF0000; 274 } 275 276 /* M profile requires that reset clears the exclusive monitor; 277 * A profile does not, but clearing it makes more sense than having it 278 * set with an exclusive access on address zero. 279 */ 280 arm_clear_exclusive(env); 281 282 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 283 #endif 284 285 if (arm_feature(env, ARM_FEATURE_PMSA)) { 286 if (cpu->pmsav7_dregion > 0) { 287 if (arm_feature(env, ARM_FEATURE_V8)) { 288 memset(env->pmsav8.rbar[M_REG_NS], 0, 289 sizeof(*env->pmsav8.rbar[M_REG_NS]) 290 * cpu->pmsav7_dregion); 291 memset(env->pmsav8.rlar[M_REG_NS], 0, 292 sizeof(*env->pmsav8.rlar[M_REG_NS]) 293 * cpu->pmsav7_dregion); 294 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 295 memset(env->pmsav8.rbar[M_REG_S], 0, 296 sizeof(*env->pmsav8.rbar[M_REG_S]) 297 * cpu->pmsav7_dregion); 298 memset(env->pmsav8.rlar[M_REG_S], 0, 299 sizeof(*env->pmsav8.rlar[M_REG_S]) 300 * cpu->pmsav7_dregion); 301 } 302 } else if (arm_feature(env, ARM_FEATURE_V7)) { 303 memset(env->pmsav7.drbar, 0, 304 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 305 memset(env->pmsav7.drsr, 0, 306 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 307 memset(env->pmsav7.dracr, 0, 308 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 309 } 310 } 311 env->pmsav7.rnr[M_REG_NS] = 0; 312 env->pmsav7.rnr[M_REG_S] = 0; 313 env->pmsav8.mair0[M_REG_NS] = 0; 314 env->pmsav8.mair0[M_REG_S] = 0; 315 env->pmsav8.mair1[M_REG_NS] = 0; 316 env->pmsav8.mair1[M_REG_S] = 0; 317 } 318 319 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 320 if (cpu->sau_sregion > 0) { 321 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 322 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 323 } 324 env->sau.rnr = 0; 325 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 326 * the Cortex-M33 does. 327 */ 328 env->sau.ctrl = 0; 329 } 330 331 set_flush_to_zero(1, &env->vfp.standard_fp_status); 332 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 333 set_default_nan_mode(1, &env->vfp.standard_fp_status); 334 set_float_detect_tininess(float_tininess_before_rounding, 335 &env->vfp.fp_status); 336 set_float_detect_tininess(float_tininess_before_rounding, 337 &env->vfp.standard_fp_status); 338 set_float_detect_tininess(float_tininess_before_rounding, 339 &env->vfp.fp_status_f16); 340 #ifndef CONFIG_USER_ONLY 341 if (kvm_enabled()) { 342 kvm_arm_reset_vcpu(cpu); 343 } 344 #endif 345 346 hw_breakpoint_update_all(cpu); 347 hw_watchpoint_update_all(cpu); 348 } 349 350 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 351 { 352 CPUClass *cc = CPU_GET_CLASS(cs); 353 CPUARMState *env = cs->env_ptr; 354 uint32_t cur_el = arm_current_el(env); 355 bool secure = arm_is_secure(env); 356 uint32_t target_el; 357 uint32_t excp_idx; 358 bool ret = false; 359 360 if (interrupt_request & CPU_INTERRUPT_FIQ) { 361 excp_idx = EXCP_FIQ; 362 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 363 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 364 cs->exception_index = excp_idx; 365 env->exception.target_el = target_el; 366 cc->do_interrupt(cs); 367 ret = true; 368 } 369 } 370 if (interrupt_request & CPU_INTERRUPT_HARD) { 371 excp_idx = EXCP_IRQ; 372 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 373 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 374 cs->exception_index = excp_idx; 375 env->exception.target_el = target_el; 376 cc->do_interrupt(cs); 377 ret = true; 378 } 379 } 380 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 381 excp_idx = EXCP_VIRQ; 382 target_el = 1; 383 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 384 cs->exception_index = excp_idx; 385 env->exception.target_el = target_el; 386 cc->do_interrupt(cs); 387 ret = true; 388 } 389 } 390 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 391 excp_idx = EXCP_VFIQ; 392 target_el = 1; 393 if (arm_excp_unmasked(cs, excp_idx, target_el)) { 394 cs->exception_index = excp_idx; 395 env->exception.target_el = target_el; 396 cc->do_interrupt(cs); 397 ret = true; 398 } 399 } 400 401 return ret; 402 } 403 404 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 405 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 406 { 407 CPUClass *cc = CPU_GET_CLASS(cs); 408 ARMCPU *cpu = ARM_CPU(cs); 409 CPUARMState *env = &cpu->env; 410 bool ret = false; 411 412 /* ARMv7-M interrupt masking works differently than -A or -R. 413 * There is no FIQ/IRQ distinction. Instead of I and F bits 414 * masking FIQ and IRQ interrupts, an exception is taken only 415 * if it is higher priority than the current execution priority 416 * (which depends on state like BASEPRI, FAULTMASK and the 417 * currently active exception). 418 */ 419 if (interrupt_request & CPU_INTERRUPT_HARD 420 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 421 cs->exception_index = EXCP_IRQ; 422 cc->do_interrupt(cs); 423 ret = true; 424 } 425 return ret; 426 } 427 #endif 428 429 #ifndef CONFIG_USER_ONLY 430 static void arm_cpu_set_irq(void *opaque, int irq, int level) 431 { 432 ARMCPU *cpu = opaque; 433 CPUARMState *env = &cpu->env; 434 CPUState *cs = CPU(cpu); 435 static const int mask[] = { 436 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 437 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 438 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 439 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 440 }; 441 442 switch (irq) { 443 case ARM_CPU_VIRQ: 444 case ARM_CPU_VFIQ: 445 assert(arm_feature(env, ARM_FEATURE_EL2)); 446 /* fall through */ 447 case ARM_CPU_IRQ: 448 case ARM_CPU_FIQ: 449 if (level) { 450 cpu_interrupt(cs, mask[irq]); 451 } else { 452 cpu_reset_interrupt(cs, mask[irq]); 453 } 454 break; 455 default: 456 g_assert_not_reached(); 457 } 458 } 459 460 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 461 { 462 #ifdef CONFIG_KVM 463 ARMCPU *cpu = opaque; 464 CPUState *cs = CPU(cpu); 465 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; 466 467 switch (irq) { 468 case ARM_CPU_IRQ: 469 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; 470 break; 471 case ARM_CPU_FIQ: 472 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; 473 break; 474 default: 475 g_assert_not_reached(); 476 } 477 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; 478 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); 479 #endif 480 } 481 482 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 483 { 484 ARMCPU *cpu = ARM_CPU(cs); 485 CPUARMState *env = &cpu->env; 486 487 cpu_synchronize_state(cs); 488 return arm_cpu_data_is_big_endian(env); 489 } 490 491 #endif 492 493 static inline void set_feature(CPUARMState *env, int feature) 494 { 495 env->features |= 1ULL << feature; 496 } 497 498 static inline void unset_feature(CPUARMState *env, int feature) 499 { 500 env->features &= ~(1ULL << feature); 501 } 502 503 static int 504 print_insn_thumb1(bfd_vma pc, disassemble_info *info) 505 { 506 return print_insn_arm(pc | 1, info); 507 } 508 509 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 510 { 511 ARMCPU *ac = ARM_CPU(cpu); 512 CPUARMState *env = &ac->env; 513 bool sctlr_b; 514 515 if (is_a64(env)) { 516 /* We might not be compiled with the A64 disassembler 517 * because it needs a C++ compiler. Leave print_insn 518 * unset in this case to use the caller default behaviour. 519 */ 520 #if defined(CONFIG_ARM_A64_DIS) 521 info->print_insn = print_insn_arm_a64; 522 #endif 523 info->cap_arch = CS_ARCH_ARM64; 524 info->cap_insn_unit = 4; 525 info->cap_insn_split = 4; 526 } else { 527 int cap_mode; 528 if (env->thumb) { 529 info->print_insn = print_insn_thumb1; 530 info->cap_insn_unit = 2; 531 info->cap_insn_split = 4; 532 cap_mode = CS_MODE_THUMB; 533 } else { 534 info->print_insn = print_insn_arm; 535 info->cap_insn_unit = 4; 536 info->cap_insn_split = 4; 537 cap_mode = CS_MODE_ARM; 538 } 539 if (arm_feature(env, ARM_FEATURE_V8)) { 540 cap_mode |= CS_MODE_V8; 541 } 542 if (arm_feature(env, ARM_FEATURE_M)) { 543 cap_mode |= CS_MODE_MCLASS; 544 } 545 info->cap_arch = CS_ARCH_ARM; 546 info->cap_mode = cap_mode; 547 } 548 549 sctlr_b = arm_sctlr_b(env); 550 if (bswap_code(sctlr_b)) { 551 #ifdef TARGET_WORDS_BIGENDIAN 552 info->endian = BFD_ENDIAN_LITTLE; 553 #else 554 info->endian = BFD_ENDIAN_BIG; 555 #endif 556 } 557 info->flags &= ~INSN_ARM_BE32; 558 #ifndef CONFIG_USER_ONLY 559 if (sctlr_b) { 560 info->flags |= INSN_ARM_BE32; 561 } 562 #endif 563 } 564 565 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 566 { 567 uint32_t Aff1 = idx / clustersz; 568 uint32_t Aff0 = idx % clustersz; 569 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 570 } 571 572 static void arm_cpu_initfn(Object *obj) 573 { 574 CPUState *cs = CPU(obj); 575 ARMCPU *cpu = ARM_CPU(obj); 576 577 cs->env_ptr = &cpu->env; 578 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, 579 g_free, g_free); 580 581 QLIST_INIT(&cpu->pre_el_change_hooks); 582 QLIST_INIT(&cpu->el_change_hooks); 583 584 #ifndef CONFIG_USER_ONLY 585 /* Our inbound IRQ and FIQ lines */ 586 if (kvm_enabled()) { 587 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 588 * the same interface as non-KVM CPUs. 589 */ 590 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 591 } else { 592 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 593 } 594 595 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 596 arm_gt_ptimer_cb, cpu); 597 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 598 arm_gt_vtimer_cb, cpu); 599 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 600 arm_gt_htimer_cb, cpu); 601 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, 602 arm_gt_stimer_cb, cpu); 603 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 604 ARRAY_SIZE(cpu->gt_timer_outputs)); 605 606 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 607 "gicv3-maintenance-interrupt", 1); 608 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 609 "pmu-interrupt", 1); 610 #endif 611 612 /* DTB consumers generally don't in fact care what the 'compatible' 613 * string is, so always provide some string and trust that a hypothetical 614 * picky DTB consumer will also provide a helpful error message. 615 */ 616 cpu->dtb_compatible = "qemu,unknown"; 617 cpu->psci_version = 1; /* By default assume PSCI v0.1 */ 618 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 619 620 if (tcg_enabled()) { 621 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ 622 } 623 } 624 625 static Property arm_cpu_reset_cbar_property = 626 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 627 628 static Property arm_cpu_reset_hivecs_property = 629 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 630 631 static Property arm_cpu_rvbar_property = 632 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); 633 634 static Property arm_cpu_has_el2_property = 635 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 636 637 static Property arm_cpu_has_el3_property = 638 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 639 640 static Property arm_cpu_cfgend_property = 641 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 642 643 /* use property name "pmu" to match other archs and virt tools */ 644 static Property arm_cpu_has_pmu_property = 645 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); 646 647 static Property arm_cpu_has_mpu_property = 648 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 649 650 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 651 * because the CPU initfn will have already set cpu->pmsav7_dregion to 652 * the right value for that particular CPU type, and we don't want 653 * to override that with an incorrect constant value. 654 */ 655 static Property arm_cpu_pmsav7_dregion_property = 656 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 657 pmsav7_dregion, 658 qdev_prop_uint32, uint32_t); 659 660 /* M profile: initial value of the Secure VTOR */ 661 static Property arm_cpu_initsvtor_property = 662 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); 663 664 static void arm_cpu_post_init(Object *obj) 665 { 666 ARMCPU *cpu = ARM_CPU(obj); 667 668 /* M profile implies PMSA. We have to do this here rather than 669 * in realize with the other feature-implication checks because 670 * we look at the PMSA bit to see if we should add some properties. 671 */ 672 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 673 set_feature(&cpu->env, ARM_FEATURE_PMSA); 674 } 675 676 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 677 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 678 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, 679 &error_abort); 680 } 681 682 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 683 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, 684 &error_abort); 685 } 686 687 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 688 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, 689 &error_abort); 690 } 691 692 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 693 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 694 * prevent "has_el3" from existing on CPUs which cannot support EL3. 695 */ 696 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, 697 &error_abort); 698 699 #ifndef CONFIG_USER_ONLY 700 object_property_add_link(obj, "secure-memory", 701 TYPE_MEMORY_REGION, 702 (Object **)&cpu->secure_memory, 703 qdev_prop_allow_set_link_before_realize, 704 OBJ_PROP_LINK_STRONG, 705 &error_abort); 706 #endif 707 } 708 709 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 710 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, 711 &error_abort); 712 } 713 714 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 715 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, 716 &error_abort); 717 } 718 719 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 720 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, 721 &error_abort); 722 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 723 qdev_property_add_static(DEVICE(obj), 724 &arm_cpu_pmsav7_dregion_property, 725 &error_abort); 726 } 727 } 728 729 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 730 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 731 qdev_prop_allow_set_link_before_realize, 732 OBJ_PROP_LINK_STRONG, 733 &error_abort); 734 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, 735 &error_abort); 736 } 737 738 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, 739 &error_abort); 740 } 741 742 static void arm_cpu_finalizefn(Object *obj) 743 { 744 ARMCPU *cpu = ARM_CPU(obj); 745 ARMELChangeHook *hook, *next; 746 747 g_hash_table_destroy(cpu->cp_regs); 748 749 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 750 QLIST_REMOVE(hook, node); 751 g_free(hook); 752 } 753 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 754 QLIST_REMOVE(hook, node); 755 g_free(hook); 756 } 757 } 758 759 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 760 { 761 CPUState *cs = CPU(dev); 762 ARMCPU *cpu = ARM_CPU(dev); 763 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 764 CPUARMState *env = &cpu->env; 765 int pagebits; 766 Error *local_err = NULL; 767 768 /* If we needed to query the host kernel for the CPU features 769 * then it's possible that might have failed in the initfn, but 770 * this is the first point where we can report it. 771 */ 772 if (cpu->host_cpu_probe_failed) { 773 if (!kvm_enabled()) { 774 error_setg(errp, "The 'host' CPU type can only be used with KVM"); 775 } else { 776 error_setg(errp, "Failed to retrieve host CPU features"); 777 } 778 return; 779 } 780 781 #ifndef CONFIG_USER_ONLY 782 /* The NVIC and M-profile CPU are two halves of a single piece of 783 * hardware; trying to use one without the other is a command line 784 * error and will result in segfaults if not caught here. 785 */ 786 if (arm_feature(env, ARM_FEATURE_M)) { 787 if (!env->nvic) { 788 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 789 return; 790 } 791 } else { 792 if (env->nvic) { 793 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 794 return; 795 } 796 } 797 #endif 798 799 cpu_exec_realizefn(cs, &local_err); 800 if (local_err != NULL) { 801 error_propagate(errp, local_err); 802 return; 803 } 804 805 /* Some features automatically imply others: */ 806 if (arm_feature(env, ARM_FEATURE_V8)) { 807 set_feature(env, ARM_FEATURE_V7VE); 808 } 809 if (arm_feature(env, ARM_FEATURE_V7VE)) { 810 /* v7 Virtualization Extensions. In real hardware this implies 811 * EL2 and also the presence of the Security Extensions. 812 * For QEMU, for backwards-compatibility we implement some 813 * CPUs or CPU configs which have no actual EL2 or EL3 but do 814 * include the various other features that V7VE implies. 815 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 816 * Security Extensions is ARM_FEATURE_EL3. 817 */ 818 set_feature(env, ARM_FEATURE_ARM_DIV); 819 set_feature(env, ARM_FEATURE_LPAE); 820 set_feature(env, ARM_FEATURE_V7); 821 } 822 if (arm_feature(env, ARM_FEATURE_V7)) { 823 set_feature(env, ARM_FEATURE_VAPA); 824 set_feature(env, ARM_FEATURE_THUMB2); 825 set_feature(env, ARM_FEATURE_MPIDR); 826 if (!arm_feature(env, ARM_FEATURE_M)) { 827 set_feature(env, ARM_FEATURE_V6K); 828 } else { 829 set_feature(env, ARM_FEATURE_V6); 830 } 831 832 /* Always define VBAR for V7 CPUs even if it doesn't exist in 833 * non-EL3 configs. This is needed by some legacy boards. 834 */ 835 set_feature(env, ARM_FEATURE_VBAR); 836 } 837 if (arm_feature(env, ARM_FEATURE_V6K)) { 838 set_feature(env, ARM_FEATURE_V6); 839 set_feature(env, ARM_FEATURE_MVFR); 840 } 841 if (arm_feature(env, ARM_FEATURE_V6)) { 842 set_feature(env, ARM_FEATURE_V5); 843 set_feature(env, ARM_FEATURE_JAZELLE); 844 if (!arm_feature(env, ARM_FEATURE_M)) { 845 set_feature(env, ARM_FEATURE_AUXCR); 846 } 847 } 848 if (arm_feature(env, ARM_FEATURE_V5)) { 849 set_feature(env, ARM_FEATURE_V4T); 850 } 851 if (arm_feature(env, ARM_FEATURE_M)) { 852 set_feature(env, ARM_FEATURE_THUMB_DIV); 853 } 854 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { 855 set_feature(env, ARM_FEATURE_THUMB_DIV); 856 } 857 if (arm_feature(env, ARM_FEATURE_VFP4)) { 858 set_feature(env, ARM_FEATURE_VFP3); 859 set_feature(env, ARM_FEATURE_VFP_FP16); 860 } 861 if (arm_feature(env, ARM_FEATURE_VFP3)) { 862 set_feature(env, ARM_FEATURE_VFP); 863 } 864 if (arm_feature(env, ARM_FEATURE_LPAE)) { 865 set_feature(env, ARM_FEATURE_V7MP); 866 set_feature(env, ARM_FEATURE_PXN); 867 } 868 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 869 set_feature(env, ARM_FEATURE_CBAR); 870 } 871 if (arm_feature(env, ARM_FEATURE_THUMB2) && 872 !arm_feature(env, ARM_FEATURE_M)) { 873 set_feature(env, ARM_FEATURE_THUMB_DSP); 874 } 875 876 if (arm_feature(env, ARM_FEATURE_V7) && 877 !arm_feature(env, ARM_FEATURE_M) && 878 !arm_feature(env, ARM_FEATURE_PMSA)) { 879 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 880 * can use 4K pages. 881 */ 882 pagebits = 12; 883 } else { 884 /* For CPUs which might have tiny 1K pages, or which have an 885 * MPU and might have small region sizes, stick with 1K pages. 886 */ 887 pagebits = 10; 888 } 889 if (!set_preferred_target_page_bits(pagebits)) { 890 /* This can only ever happen for hotplugging a CPU, or if 891 * the board code incorrectly creates a CPU which it has 892 * promised via minimum_page_size that it will not. 893 */ 894 error_setg(errp, "This CPU requires a smaller page size than the " 895 "system is using"); 896 return; 897 } 898 899 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 900 * We don't support setting cluster ID ([16..23]) (known as Aff2 901 * in later ARM ARM versions), or any of the higher affinity level fields, 902 * so these bits always RAZ. 903 */ 904 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 905 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 906 ARM_DEFAULT_CPUS_PER_CLUSTER); 907 } 908 909 if (cpu->reset_hivecs) { 910 cpu->reset_sctlr |= (1 << 13); 911 } 912 913 if (cpu->cfgend) { 914 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 915 cpu->reset_sctlr |= SCTLR_EE; 916 } else { 917 cpu->reset_sctlr |= SCTLR_B; 918 } 919 } 920 921 if (!cpu->has_el3) { 922 /* If the has_el3 CPU property is disabled then we need to disable the 923 * feature. 924 */ 925 unset_feature(env, ARM_FEATURE_EL3); 926 927 /* Disable the security extension feature bits in the processor feature 928 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. 929 */ 930 cpu->id_pfr1 &= ~0xf0; 931 cpu->id_aa64pfr0 &= ~0xf000; 932 } 933 934 if (!cpu->has_el2) { 935 unset_feature(env, ARM_FEATURE_EL2); 936 } 937 938 if (!cpu->has_pmu) { 939 unset_feature(env, ARM_FEATURE_PMU); 940 cpu->id_aa64dfr0 &= ~0xf00; 941 } 942 943 if (!arm_feature(env, ARM_FEATURE_EL2)) { 944 /* Disable the hypervisor feature bits in the processor feature 945 * registers if we don't have EL2. These are id_pfr1[15:12] and 946 * id_aa64pfr0_el1[11:8]. 947 */ 948 cpu->id_aa64pfr0 &= ~0xf00; 949 cpu->id_pfr1 &= ~0xf000; 950 } 951 952 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 953 * to false or by setting pmsav7-dregion to 0. 954 */ 955 if (!cpu->has_mpu) { 956 cpu->pmsav7_dregion = 0; 957 } 958 if (cpu->pmsav7_dregion == 0) { 959 cpu->has_mpu = false; 960 } 961 962 if (arm_feature(env, ARM_FEATURE_PMSA) && 963 arm_feature(env, ARM_FEATURE_V7)) { 964 uint32_t nr = cpu->pmsav7_dregion; 965 966 if (nr > 0xff) { 967 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 968 return; 969 } 970 971 if (nr) { 972 if (arm_feature(env, ARM_FEATURE_V8)) { 973 /* PMSAv8 */ 974 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 975 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 976 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 977 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 978 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 979 } 980 } else { 981 env->pmsav7.drbar = g_new0(uint32_t, nr); 982 env->pmsav7.drsr = g_new0(uint32_t, nr); 983 env->pmsav7.dracr = g_new0(uint32_t, nr); 984 } 985 } 986 } 987 988 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 989 uint32_t nr = cpu->sau_sregion; 990 991 if (nr > 0xff) { 992 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 993 return; 994 } 995 996 if (nr) { 997 env->sau.rbar = g_new0(uint32_t, nr); 998 env->sau.rlar = g_new0(uint32_t, nr); 999 } 1000 } 1001 1002 if (arm_feature(env, ARM_FEATURE_EL3)) { 1003 set_feature(env, ARM_FEATURE_VBAR); 1004 } 1005 1006 register_cp_regs_for_features(cpu); 1007 arm_cpu_register_gdb_regs_for_features(cpu); 1008 1009 init_cpreg_list(cpu); 1010 1011 #ifndef CONFIG_USER_ONLY 1012 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1013 cs->num_ases = 2; 1014 1015 if (!cpu->secure_memory) { 1016 cpu->secure_memory = cs->memory; 1017 } 1018 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1019 cpu->secure_memory); 1020 } else { 1021 cs->num_ases = 1; 1022 } 1023 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1024 1025 /* No core_count specified, default to smp_cpus. */ 1026 if (cpu->core_count == -1) { 1027 cpu->core_count = smp_cpus; 1028 } 1029 #endif 1030 1031 qemu_init_vcpu(cs); 1032 cpu_reset(cs); 1033 1034 acc->parent_realize(dev, errp); 1035 } 1036 1037 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 1038 { 1039 ObjectClass *oc; 1040 char *typename; 1041 char **cpuname; 1042 const char *cpunamestr; 1043 1044 cpuname = g_strsplit(cpu_model, ",", 1); 1045 cpunamestr = cpuname[0]; 1046 #ifdef CONFIG_USER_ONLY 1047 /* For backwards compatibility usermode emulation allows "-cpu any", 1048 * which has the same semantics as "-cpu max". 1049 */ 1050 if (!strcmp(cpunamestr, "any")) { 1051 cpunamestr = "max"; 1052 } 1053 #endif 1054 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 1055 oc = object_class_by_name(typename); 1056 g_strfreev(cpuname); 1057 g_free(typename); 1058 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 1059 object_class_is_abstract(oc)) { 1060 return NULL; 1061 } 1062 return oc; 1063 } 1064 1065 /* CPU models. These are not needed for the AArch64 linux-user build. */ 1066 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1067 1068 static void arm926_initfn(Object *obj) 1069 { 1070 ARMCPU *cpu = ARM_CPU(obj); 1071 1072 cpu->dtb_compatible = "arm,arm926"; 1073 set_feature(&cpu->env, ARM_FEATURE_V5); 1074 set_feature(&cpu->env, ARM_FEATURE_VFP); 1075 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1076 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1077 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 1078 cpu->midr = 0x41069265; 1079 cpu->reset_fpsid = 0x41011090; 1080 cpu->ctr = 0x1dd20d2; 1081 cpu->reset_sctlr = 0x00090078; 1082 } 1083 1084 static void arm946_initfn(Object *obj) 1085 { 1086 ARMCPU *cpu = ARM_CPU(obj); 1087 1088 cpu->dtb_compatible = "arm,arm946"; 1089 set_feature(&cpu->env, ARM_FEATURE_V5); 1090 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1091 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1092 cpu->midr = 0x41059461; 1093 cpu->ctr = 0x0f004006; 1094 cpu->reset_sctlr = 0x00000078; 1095 } 1096 1097 static void arm1026_initfn(Object *obj) 1098 { 1099 ARMCPU *cpu = ARM_CPU(obj); 1100 1101 cpu->dtb_compatible = "arm,arm1026"; 1102 set_feature(&cpu->env, ARM_FEATURE_V5); 1103 set_feature(&cpu->env, ARM_FEATURE_VFP); 1104 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 1105 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1106 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 1107 set_feature(&cpu->env, ARM_FEATURE_JAZELLE); 1108 cpu->midr = 0x4106a262; 1109 cpu->reset_fpsid = 0x410110a0; 1110 cpu->ctr = 0x1dd20d2; 1111 cpu->reset_sctlr = 0x00090078; 1112 cpu->reset_auxcr = 1; 1113 { 1114 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 1115 ARMCPRegInfo ifar = { 1116 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 1117 .access = PL1_RW, 1118 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 1119 .resetvalue = 0 1120 }; 1121 define_one_arm_cp_reg(cpu, &ifar); 1122 } 1123 } 1124 1125 static void arm1136_r2_initfn(Object *obj) 1126 { 1127 ARMCPU *cpu = ARM_CPU(obj); 1128 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 1129 * older core than plain "arm1136". In particular this does not 1130 * have the v6K features. 1131 * These ID register values are correct for 1136 but may be wrong 1132 * for 1136_r2 (in particular r0p2 does not actually implement most 1133 * of the ID registers). 1134 */ 1135 1136 cpu->dtb_compatible = "arm,arm1136"; 1137 set_feature(&cpu->env, ARM_FEATURE_V6); 1138 set_feature(&cpu->env, ARM_FEATURE_VFP); 1139 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1140 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1141 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1142 cpu->midr = 0x4107b362; 1143 cpu->reset_fpsid = 0x410120b4; 1144 cpu->mvfr0 = 0x11111111; 1145 cpu->mvfr1 = 0x00000000; 1146 cpu->ctr = 0x1dd20d2; 1147 cpu->reset_sctlr = 0x00050078; 1148 cpu->id_pfr0 = 0x111; 1149 cpu->id_pfr1 = 0x1; 1150 cpu->id_dfr0 = 0x2; 1151 cpu->id_afr0 = 0x3; 1152 cpu->id_mmfr0 = 0x01130003; 1153 cpu->id_mmfr1 = 0x10030302; 1154 cpu->id_mmfr2 = 0x01222110; 1155 cpu->id_isar0 = 0x00140011; 1156 cpu->id_isar1 = 0x12002111; 1157 cpu->id_isar2 = 0x11231111; 1158 cpu->id_isar3 = 0x01102131; 1159 cpu->id_isar4 = 0x141; 1160 cpu->reset_auxcr = 7; 1161 } 1162 1163 static void arm1136_initfn(Object *obj) 1164 { 1165 ARMCPU *cpu = ARM_CPU(obj); 1166 1167 cpu->dtb_compatible = "arm,arm1136"; 1168 set_feature(&cpu->env, ARM_FEATURE_V6K); 1169 set_feature(&cpu->env, ARM_FEATURE_V6); 1170 set_feature(&cpu->env, ARM_FEATURE_VFP); 1171 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1172 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1173 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1174 cpu->midr = 0x4117b363; 1175 cpu->reset_fpsid = 0x410120b4; 1176 cpu->mvfr0 = 0x11111111; 1177 cpu->mvfr1 = 0x00000000; 1178 cpu->ctr = 0x1dd20d2; 1179 cpu->reset_sctlr = 0x00050078; 1180 cpu->id_pfr0 = 0x111; 1181 cpu->id_pfr1 = 0x1; 1182 cpu->id_dfr0 = 0x2; 1183 cpu->id_afr0 = 0x3; 1184 cpu->id_mmfr0 = 0x01130003; 1185 cpu->id_mmfr1 = 0x10030302; 1186 cpu->id_mmfr2 = 0x01222110; 1187 cpu->id_isar0 = 0x00140011; 1188 cpu->id_isar1 = 0x12002111; 1189 cpu->id_isar2 = 0x11231111; 1190 cpu->id_isar3 = 0x01102131; 1191 cpu->id_isar4 = 0x141; 1192 cpu->reset_auxcr = 7; 1193 } 1194 1195 static void arm1176_initfn(Object *obj) 1196 { 1197 ARMCPU *cpu = ARM_CPU(obj); 1198 1199 cpu->dtb_compatible = "arm,arm1176"; 1200 set_feature(&cpu->env, ARM_FEATURE_V6K); 1201 set_feature(&cpu->env, ARM_FEATURE_VFP); 1202 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1203 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1204 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 1205 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 1206 set_feature(&cpu->env, ARM_FEATURE_EL3); 1207 cpu->midr = 0x410fb767; 1208 cpu->reset_fpsid = 0x410120b5; 1209 cpu->mvfr0 = 0x11111111; 1210 cpu->mvfr1 = 0x00000000; 1211 cpu->ctr = 0x1dd20d2; 1212 cpu->reset_sctlr = 0x00050078; 1213 cpu->id_pfr0 = 0x111; 1214 cpu->id_pfr1 = 0x11; 1215 cpu->id_dfr0 = 0x33; 1216 cpu->id_afr0 = 0; 1217 cpu->id_mmfr0 = 0x01130003; 1218 cpu->id_mmfr1 = 0x10030302; 1219 cpu->id_mmfr2 = 0x01222100; 1220 cpu->id_isar0 = 0x0140011; 1221 cpu->id_isar1 = 0x12002111; 1222 cpu->id_isar2 = 0x11231121; 1223 cpu->id_isar3 = 0x01102131; 1224 cpu->id_isar4 = 0x01141; 1225 cpu->reset_auxcr = 7; 1226 } 1227 1228 static void arm11mpcore_initfn(Object *obj) 1229 { 1230 ARMCPU *cpu = ARM_CPU(obj); 1231 1232 cpu->dtb_compatible = "arm,arm11mpcore"; 1233 set_feature(&cpu->env, ARM_FEATURE_V6K); 1234 set_feature(&cpu->env, ARM_FEATURE_VFP); 1235 set_feature(&cpu->env, ARM_FEATURE_VAPA); 1236 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 1237 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1238 cpu->midr = 0x410fb022; 1239 cpu->reset_fpsid = 0x410120b4; 1240 cpu->mvfr0 = 0x11111111; 1241 cpu->mvfr1 = 0x00000000; 1242 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 1243 cpu->id_pfr0 = 0x111; 1244 cpu->id_pfr1 = 0x1; 1245 cpu->id_dfr0 = 0; 1246 cpu->id_afr0 = 0x2; 1247 cpu->id_mmfr0 = 0x01100103; 1248 cpu->id_mmfr1 = 0x10020302; 1249 cpu->id_mmfr2 = 0x01222000; 1250 cpu->id_isar0 = 0x00100011; 1251 cpu->id_isar1 = 0x12002111; 1252 cpu->id_isar2 = 0x11221011; 1253 cpu->id_isar3 = 0x01102131; 1254 cpu->id_isar4 = 0x141; 1255 cpu->reset_auxcr = 1; 1256 } 1257 1258 static void cortex_m0_initfn(Object *obj) 1259 { 1260 ARMCPU *cpu = ARM_CPU(obj); 1261 set_feature(&cpu->env, ARM_FEATURE_V6); 1262 set_feature(&cpu->env, ARM_FEATURE_M); 1263 1264 cpu->midr = 0x410cc200; 1265 } 1266 1267 static void cortex_m3_initfn(Object *obj) 1268 { 1269 ARMCPU *cpu = ARM_CPU(obj); 1270 set_feature(&cpu->env, ARM_FEATURE_V7); 1271 set_feature(&cpu->env, ARM_FEATURE_M); 1272 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1273 cpu->midr = 0x410fc231; 1274 cpu->pmsav7_dregion = 8; 1275 cpu->id_pfr0 = 0x00000030; 1276 cpu->id_pfr1 = 0x00000200; 1277 cpu->id_dfr0 = 0x00100000; 1278 cpu->id_afr0 = 0x00000000; 1279 cpu->id_mmfr0 = 0x00000030; 1280 cpu->id_mmfr1 = 0x00000000; 1281 cpu->id_mmfr2 = 0x00000000; 1282 cpu->id_mmfr3 = 0x00000000; 1283 cpu->id_isar0 = 0x01141110; 1284 cpu->id_isar1 = 0x02111000; 1285 cpu->id_isar2 = 0x21112231; 1286 cpu->id_isar3 = 0x01111110; 1287 cpu->id_isar4 = 0x01310102; 1288 cpu->id_isar5 = 0x00000000; 1289 cpu->id_isar6 = 0x00000000; 1290 } 1291 1292 static void cortex_m4_initfn(Object *obj) 1293 { 1294 ARMCPU *cpu = ARM_CPU(obj); 1295 1296 set_feature(&cpu->env, ARM_FEATURE_V7); 1297 set_feature(&cpu->env, ARM_FEATURE_M); 1298 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1299 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1300 cpu->midr = 0x410fc240; /* r0p0 */ 1301 cpu->pmsav7_dregion = 8; 1302 cpu->id_pfr0 = 0x00000030; 1303 cpu->id_pfr1 = 0x00000200; 1304 cpu->id_dfr0 = 0x00100000; 1305 cpu->id_afr0 = 0x00000000; 1306 cpu->id_mmfr0 = 0x00000030; 1307 cpu->id_mmfr1 = 0x00000000; 1308 cpu->id_mmfr2 = 0x00000000; 1309 cpu->id_mmfr3 = 0x00000000; 1310 cpu->id_isar0 = 0x01141110; 1311 cpu->id_isar1 = 0x02111000; 1312 cpu->id_isar2 = 0x21112231; 1313 cpu->id_isar3 = 0x01111110; 1314 cpu->id_isar4 = 0x01310102; 1315 cpu->id_isar5 = 0x00000000; 1316 cpu->id_isar6 = 0x00000000; 1317 } 1318 1319 static void cortex_m33_initfn(Object *obj) 1320 { 1321 ARMCPU *cpu = ARM_CPU(obj); 1322 1323 set_feature(&cpu->env, ARM_FEATURE_V8); 1324 set_feature(&cpu->env, ARM_FEATURE_M); 1325 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 1326 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 1327 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 1328 cpu->midr = 0x410fd213; /* r0p3 */ 1329 cpu->pmsav7_dregion = 16; 1330 cpu->sau_sregion = 8; 1331 cpu->id_pfr0 = 0x00000030; 1332 cpu->id_pfr1 = 0x00000210; 1333 cpu->id_dfr0 = 0x00200000; 1334 cpu->id_afr0 = 0x00000000; 1335 cpu->id_mmfr0 = 0x00101F40; 1336 cpu->id_mmfr1 = 0x00000000; 1337 cpu->id_mmfr2 = 0x01000000; 1338 cpu->id_mmfr3 = 0x00000000; 1339 cpu->id_isar0 = 0x01101110; 1340 cpu->id_isar1 = 0x02212000; 1341 cpu->id_isar2 = 0x20232232; 1342 cpu->id_isar3 = 0x01111131; 1343 cpu->id_isar4 = 0x01310132; 1344 cpu->id_isar5 = 0x00000000; 1345 cpu->id_isar6 = 0x00000000; 1346 cpu->clidr = 0x00000000; 1347 cpu->ctr = 0x8000c000; 1348 } 1349 1350 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1351 { 1352 CPUClass *cc = CPU_CLASS(oc); 1353 1354 #ifndef CONFIG_USER_ONLY 1355 cc->do_interrupt = arm_v7m_cpu_do_interrupt; 1356 #endif 1357 1358 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; 1359 } 1360 1361 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 1362 /* Dummy the TCM region regs for the moment */ 1363 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 1364 .access = PL1_RW, .type = ARM_CP_CONST }, 1365 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 1366 .access = PL1_RW, .type = ARM_CP_CONST }, 1367 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 1368 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 1369 REGINFO_SENTINEL 1370 }; 1371 1372 static void cortex_r5_initfn(Object *obj) 1373 { 1374 ARMCPU *cpu = ARM_CPU(obj); 1375 1376 set_feature(&cpu->env, ARM_FEATURE_V7); 1377 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); 1378 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); 1379 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1380 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1381 cpu->midr = 0x411fc153; /* r1p3 */ 1382 cpu->id_pfr0 = 0x0131; 1383 cpu->id_pfr1 = 0x001; 1384 cpu->id_dfr0 = 0x010400; 1385 cpu->id_afr0 = 0x0; 1386 cpu->id_mmfr0 = 0x0210030; 1387 cpu->id_mmfr1 = 0x00000000; 1388 cpu->id_mmfr2 = 0x01200000; 1389 cpu->id_mmfr3 = 0x0211; 1390 cpu->id_isar0 = 0x2101111; 1391 cpu->id_isar1 = 0x13112111; 1392 cpu->id_isar2 = 0x21232141; 1393 cpu->id_isar3 = 0x01112131; 1394 cpu->id_isar4 = 0x0010142; 1395 cpu->id_isar5 = 0x0; 1396 cpu->id_isar6 = 0x0; 1397 cpu->mp_is_up = true; 1398 cpu->pmsav7_dregion = 16; 1399 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 1400 } 1401 1402 static void cortex_r5f_initfn(Object *obj) 1403 { 1404 ARMCPU *cpu = ARM_CPU(obj); 1405 1406 cortex_r5_initfn(obj); 1407 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1408 } 1409 1410 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 1411 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 1412 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1413 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1414 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1415 REGINFO_SENTINEL 1416 }; 1417 1418 static void cortex_a8_initfn(Object *obj) 1419 { 1420 ARMCPU *cpu = ARM_CPU(obj); 1421 1422 cpu->dtb_compatible = "arm,cortex-a8"; 1423 set_feature(&cpu->env, ARM_FEATURE_V7); 1424 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1425 set_feature(&cpu->env, ARM_FEATURE_NEON); 1426 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1427 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1428 set_feature(&cpu->env, ARM_FEATURE_EL3); 1429 cpu->midr = 0x410fc080; 1430 cpu->reset_fpsid = 0x410330c0; 1431 cpu->mvfr0 = 0x11110222; 1432 cpu->mvfr1 = 0x00011111; 1433 cpu->ctr = 0x82048004; 1434 cpu->reset_sctlr = 0x00c50078; 1435 cpu->id_pfr0 = 0x1031; 1436 cpu->id_pfr1 = 0x11; 1437 cpu->id_dfr0 = 0x400; 1438 cpu->id_afr0 = 0; 1439 cpu->id_mmfr0 = 0x31100003; 1440 cpu->id_mmfr1 = 0x20000000; 1441 cpu->id_mmfr2 = 0x01202000; 1442 cpu->id_mmfr3 = 0x11; 1443 cpu->id_isar0 = 0x00101111; 1444 cpu->id_isar1 = 0x12112111; 1445 cpu->id_isar2 = 0x21232031; 1446 cpu->id_isar3 = 0x11112131; 1447 cpu->id_isar4 = 0x00111142; 1448 cpu->dbgdidr = 0x15141000; 1449 cpu->clidr = (1 << 27) | (2 << 24) | 3; 1450 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 1451 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 1452 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 1453 cpu->reset_auxcr = 2; 1454 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 1455 } 1456 1457 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 1458 /* power_control should be set to maximum latency. Again, 1459 * default to 0 and set by private hook 1460 */ 1461 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 1462 .access = PL1_RW, .resetvalue = 0, 1463 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 1464 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 1465 .access = PL1_RW, .resetvalue = 0, 1466 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 1467 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 1468 .access = PL1_RW, .resetvalue = 0, 1469 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 1470 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 1471 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1472 /* TLB lockdown control */ 1473 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 1474 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1475 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 1476 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 1477 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 1478 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1479 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 1480 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1481 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 1482 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 1483 REGINFO_SENTINEL 1484 }; 1485 1486 static void cortex_a9_initfn(Object *obj) 1487 { 1488 ARMCPU *cpu = ARM_CPU(obj); 1489 1490 cpu->dtb_compatible = "arm,cortex-a9"; 1491 set_feature(&cpu->env, ARM_FEATURE_V7); 1492 set_feature(&cpu->env, ARM_FEATURE_VFP3); 1493 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); 1494 set_feature(&cpu->env, ARM_FEATURE_NEON); 1495 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1496 set_feature(&cpu->env, ARM_FEATURE_EL3); 1497 /* Note that A9 supports the MP extensions even for 1498 * A9UP and single-core A9MP (which are both different 1499 * and valid configurations; we don't model A9UP). 1500 */ 1501 set_feature(&cpu->env, ARM_FEATURE_V7MP); 1502 set_feature(&cpu->env, ARM_FEATURE_CBAR); 1503 cpu->midr = 0x410fc090; 1504 cpu->reset_fpsid = 0x41033090; 1505 cpu->mvfr0 = 0x11110222; 1506 cpu->mvfr1 = 0x01111111; 1507 cpu->ctr = 0x80038003; 1508 cpu->reset_sctlr = 0x00c50078; 1509 cpu->id_pfr0 = 0x1031; 1510 cpu->id_pfr1 = 0x11; 1511 cpu->id_dfr0 = 0x000; 1512 cpu->id_afr0 = 0; 1513 cpu->id_mmfr0 = 0x00100103; 1514 cpu->id_mmfr1 = 0x20000000; 1515 cpu->id_mmfr2 = 0x01230000; 1516 cpu->id_mmfr3 = 0x00002111; 1517 cpu->id_isar0 = 0x00101111; 1518 cpu->id_isar1 = 0x13112111; 1519 cpu->id_isar2 = 0x21232041; 1520 cpu->id_isar3 = 0x11112131; 1521 cpu->id_isar4 = 0x00111142; 1522 cpu->dbgdidr = 0x35141000; 1523 cpu->clidr = (1 << 27) | (1 << 24) | 3; 1524 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 1525 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 1526 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 1527 } 1528 1529 #ifndef CONFIG_USER_ONLY 1530 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 1531 { 1532 /* Linux wants the number of processors from here. 1533 * Might as well set the interrupt-controller bit too. 1534 */ 1535 return ((smp_cpus - 1) << 24) | (1 << 23); 1536 } 1537 #endif 1538 1539 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 1540 #ifndef CONFIG_USER_ONLY 1541 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 1542 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 1543 .writefn = arm_cp_write_ignore, }, 1544 #endif 1545 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 1546 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 1547 REGINFO_SENTINEL 1548 }; 1549 1550 static void cortex_a7_initfn(Object *obj) 1551 { 1552 ARMCPU *cpu = ARM_CPU(obj); 1553 1554 cpu->dtb_compatible = "arm,cortex-a7"; 1555 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1556 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1557 set_feature(&cpu->env, ARM_FEATURE_NEON); 1558 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1559 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1560 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1561 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1562 set_feature(&cpu->env, ARM_FEATURE_EL3); 1563 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 1564 cpu->midr = 0x410fc075; 1565 cpu->reset_fpsid = 0x41023075; 1566 cpu->mvfr0 = 0x10110222; 1567 cpu->mvfr1 = 0x11111111; 1568 cpu->ctr = 0x84448003; 1569 cpu->reset_sctlr = 0x00c50078; 1570 cpu->id_pfr0 = 0x00001131; 1571 cpu->id_pfr1 = 0x00011011; 1572 cpu->id_dfr0 = 0x02010555; 1573 cpu->pmceid0 = 0x00000000; 1574 cpu->pmceid1 = 0x00000000; 1575 cpu->id_afr0 = 0x00000000; 1576 cpu->id_mmfr0 = 0x10101105; 1577 cpu->id_mmfr1 = 0x40000000; 1578 cpu->id_mmfr2 = 0x01240000; 1579 cpu->id_mmfr3 = 0x02102211; 1580 cpu->id_isar0 = 0x01101110; 1581 cpu->id_isar1 = 0x13112111; 1582 cpu->id_isar2 = 0x21232041; 1583 cpu->id_isar3 = 0x11112131; 1584 cpu->id_isar4 = 0x10011142; 1585 cpu->dbgdidr = 0x3515f005; 1586 cpu->clidr = 0x0a200023; 1587 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1588 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1589 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1590 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 1591 } 1592 1593 static void cortex_a15_initfn(Object *obj) 1594 { 1595 ARMCPU *cpu = ARM_CPU(obj); 1596 1597 cpu->dtb_compatible = "arm,cortex-a15"; 1598 set_feature(&cpu->env, ARM_FEATURE_V7VE); 1599 set_feature(&cpu->env, ARM_FEATURE_VFP4); 1600 set_feature(&cpu->env, ARM_FEATURE_NEON); 1601 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 1602 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1603 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1604 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1605 set_feature(&cpu->env, ARM_FEATURE_EL3); 1606 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 1607 cpu->midr = 0x412fc0f1; 1608 cpu->reset_fpsid = 0x410430f0; 1609 cpu->mvfr0 = 0x10110222; 1610 cpu->mvfr1 = 0x11111111; 1611 cpu->ctr = 0x8444c004; 1612 cpu->reset_sctlr = 0x00c50078; 1613 cpu->id_pfr0 = 0x00001131; 1614 cpu->id_pfr1 = 0x00011011; 1615 cpu->id_dfr0 = 0x02010555; 1616 cpu->pmceid0 = 0x0000000; 1617 cpu->pmceid1 = 0x00000000; 1618 cpu->id_afr0 = 0x00000000; 1619 cpu->id_mmfr0 = 0x10201105; 1620 cpu->id_mmfr1 = 0x20000000; 1621 cpu->id_mmfr2 = 0x01240000; 1622 cpu->id_mmfr3 = 0x02102211; 1623 cpu->id_isar0 = 0x02101110; 1624 cpu->id_isar1 = 0x13112111; 1625 cpu->id_isar2 = 0x21232041; 1626 cpu->id_isar3 = 0x11112131; 1627 cpu->id_isar4 = 0x10011142; 1628 cpu->dbgdidr = 0x3515f021; 1629 cpu->clidr = 0x0a200023; 1630 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 1631 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 1632 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 1633 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 1634 } 1635 1636 static void ti925t_initfn(Object *obj) 1637 { 1638 ARMCPU *cpu = ARM_CPU(obj); 1639 set_feature(&cpu->env, ARM_FEATURE_V4T); 1640 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 1641 cpu->midr = ARM_CPUID_TI925T; 1642 cpu->ctr = 0x5109149; 1643 cpu->reset_sctlr = 0x00000070; 1644 } 1645 1646 static void sa1100_initfn(Object *obj) 1647 { 1648 ARMCPU *cpu = ARM_CPU(obj); 1649 1650 cpu->dtb_compatible = "intel,sa1100"; 1651 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1652 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1653 cpu->midr = 0x4401A11B; 1654 cpu->reset_sctlr = 0x00000070; 1655 } 1656 1657 static void sa1110_initfn(Object *obj) 1658 { 1659 ARMCPU *cpu = ARM_CPU(obj); 1660 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 1661 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 1662 cpu->midr = 0x6901B119; 1663 cpu->reset_sctlr = 0x00000070; 1664 } 1665 1666 static void pxa250_initfn(Object *obj) 1667 { 1668 ARMCPU *cpu = ARM_CPU(obj); 1669 1670 cpu->dtb_compatible = "marvell,xscale"; 1671 set_feature(&cpu->env, ARM_FEATURE_V5); 1672 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1673 cpu->midr = 0x69052100; 1674 cpu->ctr = 0xd172172; 1675 cpu->reset_sctlr = 0x00000078; 1676 } 1677 1678 static void pxa255_initfn(Object *obj) 1679 { 1680 ARMCPU *cpu = ARM_CPU(obj); 1681 1682 cpu->dtb_compatible = "marvell,xscale"; 1683 set_feature(&cpu->env, ARM_FEATURE_V5); 1684 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1685 cpu->midr = 0x69052d00; 1686 cpu->ctr = 0xd172172; 1687 cpu->reset_sctlr = 0x00000078; 1688 } 1689 1690 static void pxa260_initfn(Object *obj) 1691 { 1692 ARMCPU *cpu = ARM_CPU(obj); 1693 1694 cpu->dtb_compatible = "marvell,xscale"; 1695 set_feature(&cpu->env, ARM_FEATURE_V5); 1696 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1697 cpu->midr = 0x69052903; 1698 cpu->ctr = 0xd172172; 1699 cpu->reset_sctlr = 0x00000078; 1700 } 1701 1702 static void pxa261_initfn(Object *obj) 1703 { 1704 ARMCPU *cpu = ARM_CPU(obj); 1705 1706 cpu->dtb_compatible = "marvell,xscale"; 1707 set_feature(&cpu->env, ARM_FEATURE_V5); 1708 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1709 cpu->midr = 0x69052d05; 1710 cpu->ctr = 0xd172172; 1711 cpu->reset_sctlr = 0x00000078; 1712 } 1713 1714 static void pxa262_initfn(Object *obj) 1715 { 1716 ARMCPU *cpu = ARM_CPU(obj); 1717 1718 cpu->dtb_compatible = "marvell,xscale"; 1719 set_feature(&cpu->env, ARM_FEATURE_V5); 1720 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1721 cpu->midr = 0x69052d06; 1722 cpu->ctr = 0xd172172; 1723 cpu->reset_sctlr = 0x00000078; 1724 } 1725 1726 static void pxa270a0_initfn(Object *obj) 1727 { 1728 ARMCPU *cpu = ARM_CPU(obj); 1729 1730 cpu->dtb_compatible = "marvell,xscale"; 1731 set_feature(&cpu->env, ARM_FEATURE_V5); 1732 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1733 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1734 cpu->midr = 0x69054110; 1735 cpu->ctr = 0xd172172; 1736 cpu->reset_sctlr = 0x00000078; 1737 } 1738 1739 static void pxa270a1_initfn(Object *obj) 1740 { 1741 ARMCPU *cpu = ARM_CPU(obj); 1742 1743 cpu->dtb_compatible = "marvell,xscale"; 1744 set_feature(&cpu->env, ARM_FEATURE_V5); 1745 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1746 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1747 cpu->midr = 0x69054111; 1748 cpu->ctr = 0xd172172; 1749 cpu->reset_sctlr = 0x00000078; 1750 } 1751 1752 static void pxa270b0_initfn(Object *obj) 1753 { 1754 ARMCPU *cpu = ARM_CPU(obj); 1755 1756 cpu->dtb_compatible = "marvell,xscale"; 1757 set_feature(&cpu->env, ARM_FEATURE_V5); 1758 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1759 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1760 cpu->midr = 0x69054112; 1761 cpu->ctr = 0xd172172; 1762 cpu->reset_sctlr = 0x00000078; 1763 } 1764 1765 static void pxa270b1_initfn(Object *obj) 1766 { 1767 ARMCPU *cpu = ARM_CPU(obj); 1768 1769 cpu->dtb_compatible = "marvell,xscale"; 1770 set_feature(&cpu->env, ARM_FEATURE_V5); 1771 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1772 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1773 cpu->midr = 0x69054113; 1774 cpu->ctr = 0xd172172; 1775 cpu->reset_sctlr = 0x00000078; 1776 } 1777 1778 static void pxa270c0_initfn(Object *obj) 1779 { 1780 ARMCPU *cpu = ARM_CPU(obj); 1781 1782 cpu->dtb_compatible = "marvell,xscale"; 1783 set_feature(&cpu->env, ARM_FEATURE_V5); 1784 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1785 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1786 cpu->midr = 0x69054114; 1787 cpu->ctr = 0xd172172; 1788 cpu->reset_sctlr = 0x00000078; 1789 } 1790 1791 static void pxa270c5_initfn(Object *obj) 1792 { 1793 ARMCPU *cpu = ARM_CPU(obj); 1794 1795 cpu->dtb_compatible = "marvell,xscale"; 1796 set_feature(&cpu->env, ARM_FEATURE_V5); 1797 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1798 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1799 cpu->midr = 0x69054117; 1800 cpu->ctr = 0xd172172; 1801 cpu->reset_sctlr = 0x00000078; 1802 } 1803 1804 #ifndef TARGET_AARCH64 1805 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); 1806 * otherwise, a CPU with as many features enabled as our emulation supports. 1807 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1808 * this only needs to handle 32 bits. 1809 */ 1810 static void arm_max_initfn(Object *obj) 1811 { 1812 ARMCPU *cpu = ARM_CPU(obj); 1813 1814 if (kvm_enabled()) { 1815 kvm_arm_set_cpu_features_from_host(cpu); 1816 } else { 1817 cortex_a15_initfn(obj); 1818 #ifdef CONFIG_USER_ONLY 1819 /* We don't set these in system emulation mode for the moment, 1820 * since we don't correctly set the ID registers to advertise them, 1821 */ 1822 set_feature(&cpu->env, ARM_FEATURE_V8); 1823 set_feature(&cpu->env, ARM_FEATURE_V8_AES); 1824 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); 1825 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); 1826 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); 1827 set_feature(&cpu->env, ARM_FEATURE_CRC); 1828 set_feature(&cpu->env, ARM_FEATURE_V8_RDM); 1829 set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); 1830 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); 1831 #endif 1832 } 1833 } 1834 #endif 1835 1836 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ 1837 1838 typedef struct ARMCPUInfo { 1839 const char *name; 1840 void (*initfn)(Object *obj); 1841 void (*class_init)(ObjectClass *oc, void *data); 1842 } ARMCPUInfo; 1843 1844 static const ARMCPUInfo arm_cpus[] = { 1845 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 1846 { .name = "arm926", .initfn = arm926_initfn }, 1847 { .name = "arm946", .initfn = arm946_initfn }, 1848 { .name = "arm1026", .initfn = arm1026_initfn }, 1849 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1850 * older core than plain "arm1136". In particular this does not 1851 * have the v6K features. 1852 */ 1853 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1854 { .name = "arm1136", .initfn = arm1136_initfn }, 1855 { .name = "arm1176", .initfn = arm1176_initfn }, 1856 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1857 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 1858 .class_init = arm_v7m_class_init }, 1859 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1860 .class_init = arm_v7m_class_init }, 1861 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1862 .class_init = arm_v7m_class_init }, 1863 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 1864 .class_init = arm_v7m_class_init }, 1865 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1866 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 1867 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1868 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1869 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1870 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1871 { .name = "ti925t", .initfn = ti925t_initfn }, 1872 { .name = "sa1100", .initfn = sa1100_initfn }, 1873 { .name = "sa1110", .initfn = sa1110_initfn }, 1874 { .name = "pxa250", .initfn = pxa250_initfn }, 1875 { .name = "pxa255", .initfn = pxa255_initfn }, 1876 { .name = "pxa260", .initfn = pxa260_initfn }, 1877 { .name = "pxa261", .initfn = pxa261_initfn }, 1878 { .name = "pxa262", .initfn = pxa262_initfn }, 1879 /* "pxa270" is an alias for "pxa270-a0" */ 1880 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1881 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1882 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1883 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1884 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1885 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1886 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1887 #ifndef TARGET_AARCH64 1888 { .name = "max", .initfn = arm_max_initfn }, 1889 #endif 1890 #ifdef CONFIG_USER_ONLY 1891 { .name = "any", .initfn = arm_max_initfn }, 1892 #endif 1893 #endif 1894 { .name = NULL } 1895 }; 1896 1897 static Property arm_cpu_properties[] = { 1898 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), 1899 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), 1900 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), 1901 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 1902 mp_affinity, ARM64_AFFINITY_INVALID), 1903 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 1904 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 1905 DEFINE_PROP_END_OF_LIST() 1906 }; 1907 1908 #ifdef CONFIG_USER_ONLY 1909 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, 1910 int rw, int mmu_idx) 1911 { 1912 ARMCPU *cpu = ARM_CPU(cs); 1913 CPUARMState *env = &cpu->env; 1914 1915 env->exception.vaddress = address; 1916 if (rw == 2) { 1917 cs->exception_index = EXCP_PREFETCH_ABORT; 1918 } else { 1919 cs->exception_index = EXCP_DATA_ABORT; 1920 } 1921 return 1; 1922 } 1923 #endif 1924 1925 static gchar *arm_gdb_arch_name(CPUState *cs) 1926 { 1927 ARMCPU *cpu = ARM_CPU(cs); 1928 CPUARMState *env = &cpu->env; 1929 1930 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 1931 return g_strdup("iwmmxt"); 1932 } 1933 return g_strdup("arm"); 1934 } 1935 1936 static void arm_cpu_class_init(ObjectClass *oc, void *data) 1937 { 1938 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1939 CPUClass *cc = CPU_CLASS(acc); 1940 DeviceClass *dc = DEVICE_CLASS(oc); 1941 1942 device_class_set_parent_realize(dc, arm_cpu_realizefn, 1943 &acc->parent_realize); 1944 dc->props = arm_cpu_properties; 1945 1946 acc->parent_reset = cc->reset; 1947 cc->reset = arm_cpu_reset; 1948 1949 cc->class_by_name = arm_cpu_class_by_name; 1950 cc->has_work = arm_cpu_has_work; 1951 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; 1952 cc->dump_state = arm_cpu_dump_state; 1953 cc->set_pc = arm_cpu_set_pc; 1954 cc->gdb_read_register = arm_cpu_gdb_read_register; 1955 cc->gdb_write_register = arm_cpu_gdb_write_register; 1956 #ifdef CONFIG_USER_ONLY 1957 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; 1958 #else 1959 cc->do_interrupt = arm_cpu_do_interrupt; 1960 cc->do_unaligned_access = arm_cpu_do_unaligned_access; 1961 cc->do_transaction_failed = arm_cpu_do_transaction_failed; 1962 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; 1963 cc->asidx_from_attrs = arm_asidx_from_attrs; 1964 cc->vmsd = &vmstate_arm_cpu; 1965 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; 1966 cc->write_elf64_note = arm_cpu_write_elf64_note; 1967 cc->write_elf32_note = arm_cpu_write_elf32_note; 1968 #endif 1969 cc->gdb_num_core_regs = 26; 1970 cc->gdb_core_xml_file = "arm-core.xml"; 1971 cc->gdb_arch_name = arm_gdb_arch_name; 1972 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 1973 cc->gdb_stop_before_watchpoint = true; 1974 cc->debug_excp_handler = arm_debug_excp_handler; 1975 cc->debug_check_watchpoint = arm_debug_check_watchpoint; 1976 #if !defined(CONFIG_USER_ONLY) 1977 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; 1978 #endif 1979 1980 cc->disas_set_info = arm_disas_set_info; 1981 #ifdef CONFIG_TCG 1982 cc->tcg_initialize = arm_translate_init; 1983 #endif 1984 } 1985 1986 #ifdef CONFIG_KVM 1987 static void arm_host_initfn(Object *obj) 1988 { 1989 ARMCPU *cpu = ARM_CPU(obj); 1990 1991 kvm_arm_set_cpu_features_from_host(cpu); 1992 } 1993 1994 static const TypeInfo host_arm_cpu_type_info = { 1995 .name = TYPE_ARM_HOST_CPU, 1996 #ifdef TARGET_AARCH64 1997 .parent = TYPE_AARCH64_CPU, 1998 #else 1999 .parent = TYPE_ARM_CPU, 2000 #endif 2001 .instance_init = arm_host_initfn, 2002 }; 2003 2004 #endif 2005 2006 static void cpu_register(const ARMCPUInfo *info) 2007 { 2008 TypeInfo type_info = { 2009 .parent = TYPE_ARM_CPU, 2010 .instance_size = sizeof(ARMCPU), 2011 .instance_init = info->initfn, 2012 .class_size = sizeof(ARMCPUClass), 2013 .class_init = info->class_init, 2014 }; 2015 2016 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2017 type_register(&type_info); 2018 g_free((void *)type_info.name); 2019 } 2020 2021 static const TypeInfo arm_cpu_type_info = { 2022 .name = TYPE_ARM_CPU, 2023 .parent = TYPE_CPU, 2024 .instance_size = sizeof(ARMCPU), 2025 .instance_init = arm_cpu_initfn, 2026 .instance_post_init = arm_cpu_post_init, 2027 .instance_finalize = arm_cpu_finalizefn, 2028 .abstract = true, 2029 .class_size = sizeof(ARMCPUClass), 2030 .class_init = arm_cpu_class_init, 2031 }; 2032 2033 static const TypeInfo idau_interface_type_info = { 2034 .name = TYPE_IDAU_INTERFACE, 2035 .parent = TYPE_INTERFACE, 2036 .class_size = sizeof(IDAUInterfaceClass), 2037 }; 2038 2039 static void arm_cpu_register_types(void) 2040 { 2041 const ARMCPUInfo *info = arm_cpus; 2042 2043 type_register_static(&arm_cpu_type_info); 2044 type_register_static(&idau_interface_type_info); 2045 2046 while (info->name) { 2047 cpu_register(info); 2048 info++; 2049 } 2050 2051 #ifdef CONFIG_KVM 2052 type_register_static(&host_arm_cpu_type_info); 2053 #endif 2054 } 2055 2056 type_init(arm_cpu_register_types) 2057