1 /* 2 * QEMU ARM CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/qemu-print.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "exec/page-vary.h" 26 #include "target/arm/idau.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "cpu.h" 31 #ifdef CONFIG_TCG 32 #include "hw/core/tcg-cpu-ops.h" 33 #endif /* CONFIG_TCG */ 34 #include "internals.h" 35 #include "exec/exec-all.h" 36 #include "hw/qdev-properties.h" 37 #if !defined(CONFIG_USER_ONLY) 38 #include "hw/loader.h" 39 #include "hw/boards.h" 40 #endif 41 #include "sysemu/tcg.h" 42 #include "sysemu/hw_accel.h" 43 #include "kvm_arm.h" 44 #include "disas/capstone.h" 45 #include "fpu/softfloat.h" 46 #include "cpregs.h" 47 48 static void arm_cpu_set_pc(CPUState *cs, vaddr value) 49 { 50 ARMCPU *cpu = ARM_CPU(cs); 51 CPUARMState *env = &cpu->env; 52 53 if (is_a64(env)) { 54 env->pc = value; 55 env->thumb = false; 56 } else { 57 env->regs[15] = value & ~1; 58 env->thumb = value & 1; 59 } 60 } 61 62 #ifdef CONFIG_TCG 63 void arm_cpu_synchronize_from_tb(CPUState *cs, 64 const TranslationBlock *tb) 65 { 66 ARMCPU *cpu = ARM_CPU(cs); 67 CPUARMState *env = &cpu->env; 68 69 /* 70 * It's OK to look at env for the current mode here, because it's 71 * never possible for an AArch64 TB to chain to an AArch32 TB. 72 */ 73 if (is_a64(env)) { 74 env->pc = tb->pc; 75 } else { 76 env->regs[15] = tb->pc; 77 } 78 } 79 #endif /* CONFIG_TCG */ 80 81 static bool arm_cpu_has_work(CPUState *cs) 82 { 83 ARMCPU *cpu = ARM_CPU(cs); 84 85 return (cpu->power_state != PSCI_OFF) 86 && cs->interrupt_request & 87 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD 88 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR 89 | CPU_INTERRUPT_EXITTB); 90 } 91 92 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 93 void *opaque) 94 { 95 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 96 97 entry->hook = hook; 98 entry->opaque = opaque; 99 100 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); 101 } 102 103 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 104 void *opaque) 105 { 106 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); 107 108 entry->hook = hook; 109 entry->opaque = opaque; 110 111 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); 112 } 113 114 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) 115 { 116 /* Reset a single ARMCPRegInfo register */ 117 ARMCPRegInfo *ri = value; 118 ARMCPU *cpu = opaque; 119 120 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { 121 return; 122 } 123 124 if (ri->resetfn) { 125 ri->resetfn(&cpu->env, ri); 126 return; 127 } 128 129 /* A zero offset is never possible as it would be regs[0] 130 * so we use it to indicate that reset is being handled elsewhere. 131 * This is basically only used for fields in non-core coprocessors 132 * (like the pxa2xx ones). 133 */ 134 if (!ri->fieldoffset) { 135 return; 136 } 137 138 if (cpreg_field_is_64bit(ri)) { 139 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; 140 } else { 141 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; 142 } 143 } 144 145 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) 146 { 147 /* Purely an assertion check: we've already done reset once, 148 * so now check that running the reset for the cpreg doesn't 149 * change its value. This traps bugs where two different cpregs 150 * both try to reset the same state field but to different values. 151 */ 152 ARMCPRegInfo *ri = value; 153 ARMCPU *cpu = opaque; 154 uint64_t oldvalue, newvalue; 155 156 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { 157 return; 158 } 159 160 oldvalue = read_raw_cp_reg(&cpu->env, ri); 161 cp_reg_reset(key, value, opaque); 162 newvalue = read_raw_cp_reg(&cpu->env, ri); 163 assert(oldvalue == newvalue); 164 } 165 166 static void arm_cpu_reset(DeviceState *dev) 167 { 168 CPUState *s = CPU(dev); 169 ARMCPU *cpu = ARM_CPU(s); 170 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); 171 CPUARMState *env = &cpu->env; 172 173 acc->parent_reset(dev); 174 175 memset(env, 0, offsetof(CPUARMState, end_reset_fields)); 176 177 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); 178 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); 179 180 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; 181 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; 182 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; 183 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; 184 185 cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; 186 187 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 188 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; 189 } 190 191 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 192 /* 64 bit CPUs always start in 64 bit mode */ 193 env->aarch64 = true; 194 #if defined(CONFIG_USER_ONLY) 195 env->pstate = PSTATE_MODE_EL0t; 196 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ 197 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; 198 /* Enable all PAC keys. */ 199 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | 200 SCTLR_EnDA | SCTLR_EnDB); 201 /* Trap on btype=3 for PACIxSP. */ 202 env->cp15.sctlr_el[1] |= SCTLR_BT0; 203 /* and to the FP/Neon instructions */ 204 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 205 CPACR_EL1, FPEN, 3); 206 /* and to the SVE instructions */ 207 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 208 CPACR_EL1, ZEN, 3); 209 /* with reasonable vector length */ 210 if (cpu_isar_feature(aa64_sve, cpu)) { 211 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; 212 } 213 /* 214 * Enable 48-bit address space (TODO: take reserved_va into account). 215 * Enable TBI0 but not TBI1. 216 * Note that this must match useronly_clean_ptr. 217 */ 218 env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); 219 220 /* Enable MTE */ 221 if (cpu_isar_feature(aa64_mte, cpu)) { 222 /* Enable tag access, but leave TCF0 as No Effect (0). */ 223 env->cp15.sctlr_el[1] |= SCTLR_ATA0; 224 /* 225 * Exclude all tags, so that tag 0 is always used. 226 * This corresponds to Linux current->thread.gcr_incl = 0. 227 * 228 * Set RRND, so that helper_irg() will generate a seed later. 229 * Here in cpu_reset(), the crypto subsystem has not yet been 230 * initialized. 231 */ 232 env->cp15.gcr_el1 = 0x1ffff; 233 } 234 /* 235 * Disable access to SCXTNUM_EL0 from CSV2_1p2. 236 * This is not yet exposed from the Linux kernel in any way. 237 */ 238 env->cp15.sctlr_el[1] |= SCTLR_TSCXT; 239 #else 240 /* Reset into the highest available EL */ 241 if (arm_feature(env, ARM_FEATURE_EL3)) { 242 env->pstate = PSTATE_MODE_EL3h; 243 } else if (arm_feature(env, ARM_FEATURE_EL2)) { 244 env->pstate = PSTATE_MODE_EL2h; 245 } else { 246 env->pstate = PSTATE_MODE_EL1h; 247 } 248 249 /* Sample rvbar at reset. */ 250 env->cp15.rvbar = cpu->rvbar_prop; 251 env->pc = env->cp15.rvbar; 252 #endif 253 } else { 254 #if defined(CONFIG_USER_ONLY) 255 /* Userspace expects access to cp10 and cp11 for FP/Neon */ 256 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 257 CPACR, CP10, 3); 258 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, 259 CPACR, CP11, 3); 260 #endif 261 } 262 263 #if defined(CONFIG_USER_ONLY) 264 env->uncached_cpsr = ARM_CPU_MODE_USR; 265 /* For user mode we must enable access to coprocessors */ 266 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; 267 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 268 env->cp15.c15_cpar = 3; 269 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { 270 env->cp15.c15_cpar = 1; 271 } 272 #else 273 274 /* 275 * If the highest available EL is EL2, AArch32 will start in Hyp 276 * mode; otherwise it starts in SVC. Note that if we start in 277 * AArch64 then these values in the uncached_cpsr will be ignored. 278 */ 279 if (arm_feature(env, ARM_FEATURE_EL2) && 280 !arm_feature(env, ARM_FEATURE_EL3)) { 281 env->uncached_cpsr = ARM_CPU_MODE_HYP; 282 } else { 283 env->uncached_cpsr = ARM_CPU_MODE_SVC; 284 } 285 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; 286 287 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently 288 * executing as AArch32 then check if highvecs are enabled and 289 * adjust the PC accordingly. 290 */ 291 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { 292 env->regs[15] = 0xFFFF0000; 293 } 294 295 env->vfp.xregs[ARM_VFP_FPEXC] = 0; 296 #endif 297 298 if (arm_feature(env, ARM_FEATURE_M)) { 299 #ifndef CONFIG_USER_ONLY 300 uint32_t initial_msp; /* Loaded from 0x0 */ 301 uint32_t initial_pc; /* Loaded from 0x4 */ 302 uint8_t *rom; 303 uint32_t vecbase; 304 #endif 305 306 if (cpu_isar_feature(aa32_lob, cpu)) { 307 /* 308 * LTPSIZE is constant 4 if MVE not implemented, and resets 309 * to an UNKNOWN value if MVE is implemented. We choose to 310 * always reset to 4. 311 */ 312 env->v7m.ltpsize = 4; 313 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ 314 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; 315 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; 316 } 317 318 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 319 env->v7m.secure = true; 320 } else { 321 /* This bit resets to 0 if security is supported, but 1 if 322 * it is not. The bit is not present in v7M, but we set it 323 * here so we can avoid having to make checks on it conditional 324 * on ARM_FEATURE_V8 (we don't let the guest see the bit). 325 */ 326 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; 327 /* 328 * Set NSACR to indicate "NS access permitted to everything"; 329 * this avoids having to have all the tests of it being 330 * conditional on ARM_FEATURE_M_SECURITY. Note also that from 331 * v8.1M the guest-visible value of NSACR in a CPU without the 332 * Security Extension is 0xcff. 333 */ 334 env->v7m.nsacr = 0xcff; 335 } 336 337 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends 338 * that it resets to 1, so QEMU always does that rather than making 339 * it dependent on CPU model. In v8M it is RES1. 340 */ 341 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; 342 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; 343 if (arm_feature(env, ARM_FEATURE_V8)) { 344 /* in v8M the NONBASETHRDENA bit [0] is RES1 */ 345 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; 346 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; 347 } 348 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { 349 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; 350 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; 351 } 352 353 if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 354 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; 355 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | 356 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; 357 } 358 359 #ifndef CONFIG_USER_ONLY 360 /* Unlike A/R profile, M profile defines the reset LR value */ 361 env->regs[14] = 0xffffffff; 362 363 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; 364 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; 365 366 /* Load the initial SP and PC from offset 0 and 4 in the vector table */ 367 vecbase = env->v7m.vecbase[env->v7m.secure]; 368 rom = rom_ptr_for_as(s->as, vecbase, 8); 369 if (rom) { 370 /* Address zero is covered by ROM which hasn't yet been 371 * copied into physical memory. 372 */ 373 initial_msp = ldl_p(rom); 374 initial_pc = ldl_p(rom + 4); 375 } else { 376 /* Address zero not covered by a ROM blob, or the ROM blob 377 * is in non-modifiable memory and this is a second reset after 378 * it got copied into memory. In the latter case, rom_ptr 379 * will return a NULL pointer and we should use ldl_phys instead. 380 */ 381 initial_msp = ldl_phys(s->as, vecbase); 382 initial_pc = ldl_phys(s->as, vecbase + 4); 383 } 384 385 qemu_log_mask(CPU_LOG_INT, 386 "Loaded reset SP 0x%x PC 0x%x from vector table\n", 387 initial_msp, initial_pc); 388 389 env->regs[13] = initial_msp & 0xFFFFFFFC; 390 env->regs[15] = initial_pc & ~1; 391 env->thumb = initial_pc & 1; 392 #else 393 /* 394 * For user mode we run non-secure and with access to the FPU. 395 * The FPU context is active (ie does not need further setup) 396 * and is owned by non-secure. 397 */ 398 env->v7m.secure = false; 399 env->v7m.nsacr = 0xcff; 400 env->v7m.cpacr[M_REG_NS] = 0xf0ffff; 401 env->v7m.fpccr[M_REG_S] &= 402 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); 403 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; 404 #endif 405 } 406 407 /* M profile requires that reset clears the exclusive monitor; 408 * A profile does not, but clearing it makes more sense than having it 409 * set with an exclusive access on address zero. 410 */ 411 arm_clear_exclusive(env); 412 413 if (arm_feature(env, ARM_FEATURE_PMSA)) { 414 if (cpu->pmsav7_dregion > 0) { 415 if (arm_feature(env, ARM_FEATURE_V8)) { 416 memset(env->pmsav8.rbar[M_REG_NS], 0, 417 sizeof(*env->pmsav8.rbar[M_REG_NS]) 418 * cpu->pmsav7_dregion); 419 memset(env->pmsav8.rlar[M_REG_NS], 0, 420 sizeof(*env->pmsav8.rlar[M_REG_NS]) 421 * cpu->pmsav7_dregion); 422 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 423 memset(env->pmsav8.rbar[M_REG_S], 0, 424 sizeof(*env->pmsav8.rbar[M_REG_S]) 425 * cpu->pmsav7_dregion); 426 memset(env->pmsav8.rlar[M_REG_S], 0, 427 sizeof(*env->pmsav8.rlar[M_REG_S]) 428 * cpu->pmsav7_dregion); 429 } 430 } else if (arm_feature(env, ARM_FEATURE_V7)) { 431 memset(env->pmsav7.drbar, 0, 432 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); 433 memset(env->pmsav7.drsr, 0, 434 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); 435 memset(env->pmsav7.dracr, 0, 436 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); 437 } 438 } 439 env->pmsav7.rnr[M_REG_NS] = 0; 440 env->pmsav7.rnr[M_REG_S] = 0; 441 env->pmsav8.mair0[M_REG_NS] = 0; 442 env->pmsav8.mair0[M_REG_S] = 0; 443 env->pmsav8.mair1[M_REG_NS] = 0; 444 env->pmsav8.mair1[M_REG_S] = 0; 445 } 446 447 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 448 if (cpu->sau_sregion > 0) { 449 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); 450 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); 451 } 452 env->sau.rnr = 0; 453 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what 454 * the Cortex-M33 does. 455 */ 456 env->sau.ctrl = 0; 457 } 458 459 set_flush_to_zero(1, &env->vfp.standard_fp_status); 460 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); 461 set_default_nan_mode(1, &env->vfp.standard_fp_status); 462 set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); 463 set_float_detect_tininess(float_tininess_before_rounding, 464 &env->vfp.fp_status); 465 set_float_detect_tininess(float_tininess_before_rounding, 466 &env->vfp.standard_fp_status); 467 set_float_detect_tininess(float_tininess_before_rounding, 468 &env->vfp.fp_status_f16); 469 set_float_detect_tininess(float_tininess_before_rounding, 470 &env->vfp.standard_fp_status_f16); 471 #ifndef CONFIG_USER_ONLY 472 if (kvm_enabled()) { 473 kvm_arm_reset_vcpu(cpu); 474 } 475 #endif 476 477 hw_breakpoint_update_all(cpu); 478 hw_watchpoint_update_all(cpu); 479 arm_rebuild_hflags(env); 480 } 481 482 #ifndef CONFIG_USER_ONLY 483 484 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, 485 unsigned int target_el, 486 unsigned int cur_el, bool secure, 487 uint64_t hcr_el2) 488 { 489 CPUARMState *env = cs->env_ptr; 490 bool pstate_unmasked; 491 bool unmasked = false; 492 493 /* 494 * Don't take exceptions if they target a lower EL. 495 * This check should catch any exceptions that would not be taken 496 * but left pending. 497 */ 498 if (cur_el > target_el) { 499 return false; 500 } 501 502 switch (excp_idx) { 503 case EXCP_FIQ: 504 pstate_unmasked = !(env->daif & PSTATE_F); 505 break; 506 507 case EXCP_IRQ: 508 pstate_unmasked = !(env->daif & PSTATE_I); 509 break; 510 511 case EXCP_VFIQ: 512 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { 513 /* VFIQs are only taken when hypervized. */ 514 return false; 515 } 516 return !(env->daif & PSTATE_F); 517 case EXCP_VIRQ: 518 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { 519 /* VIRQs are only taken when hypervized. */ 520 return false; 521 } 522 return !(env->daif & PSTATE_I); 523 case EXCP_VSERR: 524 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { 525 /* VIRQs are only taken when hypervized. */ 526 return false; 527 } 528 return !(env->daif & PSTATE_A); 529 default: 530 g_assert_not_reached(); 531 } 532 533 /* 534 * Use the target EL, current execution state and SCR/HCR settings to 535 * determine whether the corresponding CPSR bit is used to mask the 536 * interrupt. 537 */ 538 if ((target_el > cur_el) && (target_el != 1)) { 539 /* Exceptions targeting a higher EL may not be maskable */ 540 if (arm_feature(env, ARM_FEATURE_AARCH64)) { 541 /* 542 * 64-bit masking rules are simple: exceptions to EL3 543 * can't be masked, and exceptions to EL2 can only be 544 * masked from Secure state. The HCR and SCR settings 545 * don't affect the masking logic, only the interrupt routing. 546 */ 547 if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { 548 unmasked = true; 549 } 550 } else { 551 /* 552 * The old 32-bit-only environment has a more complicated 553 * masking setup. HCR and SCR bits not only affect interrupt 554 * routing but also change the behaviour of masking. 555 */ 556 bool hcr, scr; 557 558 switch (excp_idx) { 559 case EXCP_FIQ: 560 /* 561 * If FIQs are routed to EL3 or EL2 then there are cases where 562 * we override the CPSR.F in determining if the exception is 563 * masked or not. If neither of these are set then we fall back 564 * to the CPSR.F setting otherwise we further assess the state 565 * below. 566 */ 567 hcr = hcr_el2 & HCR_FMO; 568 scr = (env->cp15.scr_el3 & SCR_FIQ); 569 570 /* 571 * When EL3 is 32-bit, the SCR.FW bit controls whether the 572 * CPSR.F bit masks FIQ interrupts when taken in non-secure 573 * state. If SCR.FW is set then FIQs can be masked by CPSR.F 574 * when non-secure but only when FIQs are only routed to EL3. 575 */ 576 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); 577 break; 578 case EXCP_IRQ: 579 /* 580 * When EL3 execution state is 32-bit, if HCR.IMO is set then 581 * we may override the CPSR.I masking when in non-secure state. 582 * The SCR.IRQ setting has already been taken into consideration 583 * when setting the target EL, so it does not have a further 584 * affect here. 585 */ 586 hcr = hcr_el2 & HCR_IMO; 587 scr = false; 588 break; 589 default: 590 g_assert_not_reached(); 591 } 592 593 if ((scr || hcr) && !secure) { 594 unmasked = true; 595 } 596 } 597 } 598 599 /* 600 * The PSTATE bits only mask the interrupt if we have not overriden the 601 * ability above. 602 */ 603 return unmasked || pstate_unmasked; 604 } 605 606 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 607 { 608 CPUClass *cc = CPU_GET_CLASS(cs); 609 CPUARMState *env = cs->env_ptr; 610 uint32_t cur_el = arm_current_el(env); 611 bool secure = arm_is_secure(env); 612 uint64_t hcr_el2 = arm_hcr_el2_eff(env); 613 uint32_t target_el; 614 uint32_t excp_idx; 615 616 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ 617 618 if (interrupt_request & CPU_INTERRUPT_FIQ) { 619 excp_idx = EXCP_FIQ; 620 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 621 if (arm_excp_unmasked(cs, excp_idx, target_el, 622 cur_el, secure, hcr_el2)) { 623 goto found; 624 } 625 } 626 if (interrupt_request & CPU_INTERRUPT_HARD) { 627 excp_idx = EXCP_IRQ; 628 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); 629 if (arm_excp_unmasked(cs, excp_idx, target_el, 630 cur_el, secure, hcr_el2)) { 631 goto found; 632 } 633 } 634 if (interrupt_request & CPU_INTERRUPT_VIRQ) { 635 excp_idx = EXCP_VIRQ; 636 target_el = 1; 637 if (arm_excp_unmasked(cs, excp_idx, target_el, 638 cur_el, secure, hcr_el2)) { 639 goto found; 640 } 641 } 642 if (interrupt_request & CPU_INTERRUPT_VFIQ) { 643 excp_idx = EXCP_VFIQ; 644 target_el = 1; 645 if (arm_excp_unmasked(cs, excp_idx, target_el, 646 cur_el, secure, hcr_el2)) { 647 goto found; 648 } 649 } 650 if (interrupt_request & CPU_INTERRUPT_VSERR) { 651 excp_idx = EXCP_VSERR; 652 target_el = 1; 653 if (arm_excp_unmasked(cs, excp_idx, target_el, 654 cur_el, secure, hcr_el2)) { 655 /* Taking a virtual abort clears HCR_EL2.VSE */ 656 env->cp15.hcr_el2 &= ~HCR_VSE; 657 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 658 goto found; 659 } 660 } 661 return false; 662 663 found: 664 cs->exception_index = excp_idx; 665 env->exception.target_el = target_el; 666 cc->tcg_ops->do_interrupt(cs); 667 return true; 668 } 669 #endif /* !CONFIG_USER_ONLY */ 670 671 void arm_cpu_update_virq(ARMCPU *cpu) 672 { 673 /* 674 * Update the interrupt level for VIRQ, which is the logical OR of 675 * the HCR_EL2.VI bit and the input line level from the GIC. 676 */ 677 CPUARMState *env = &cpu->env; 678 CPUState *cs = CPU(cpu); 679 680 bool new_state = (env->cp15.hcr_el2 & HCR_VI) || 681 (env->irq_line_state & CPU_INTERRUPT_VIRQ); 682 683 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { 684 if (new_state) { 685 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); 686 } else { 687 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); 688 } 689 } 690 } 691 692 void arm_cpu_update_vfiq(ARMCPU *cpu) 693 { 694 /* 695 * Update the interrupt level for VFIQ, which is the logical OR of 696 * the HCR_EL2.VF bit and the input line level from the GIC. 697 */ 698 CPUARMState *env = &cpu->env; 699 CPUState *cs = CPU(cpu); 700 701 bool new_state = (env->cp15.hcr_el2 & HCR_VF) || 702 (env->irq_line_state & CPU_INTERRUPT_VFIQ); 703 704 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { 705 if (new_state) { 706 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); 707 } else { 708 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); 709 } 710 } 711 } 712 713 void arm_cpu_update_vserr(ARMCPU *cpu) 714 { 715 /* 716 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. 717 */ 718 CPUARMState *env = &cpu->env; 719 CPUState *cs = CPU(cpu); 720 721 bool new_state = env->cp15.hcr_el2 & HCR_VSE; 722 723 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { 724 if (new_state) { 725 cpu_interrupt(cs, CPU_INTERRUPT_VSERR); 726 } else { 727 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); 728 } 729 } 730 } 731 732 #ifndef CONFIG_USER_ONLY 733 static void arm_cpu_set_irq(void *opaque, int irq, int level) 734 { 735 ARMCPU *cpu = opaque; 736 CPUARMState *env = &cpu->env; 737 CPUState *cs = CPU(cpu); 738 static const int mask[] = { 739 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, 740 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, 741 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, 742 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ 743 }; 744 745 if (!arm_feature(env, ARM_FEATURE_EL2) && 746 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { 747 /* 748 * The GIC might tell us about VIRQ and VFIQ state, but if we don't 749 * have EL2 support we don't care. (Unless the guest is doing something 750 * silly this will only be calls saying "level is still 0".) 751 */ 752 return; 753 } 754 755 if (level) { 756 env->irq_line_state |= mask[irq]; 757 } else { 758 env->irq_line_state &= ~mask[irq]; 759 } 760 761 switch (irq) { 762 case ARM_CPU_VIRQ: 763 arm_cpu_update_virq(cpu); 764 break; 765 case ARM_CPU_VFIQ: 766 arm_cpu_update_vfiq(cpu); 767 break; 768 case ARM_CPU_IRQ: 769 case ARM_CPU_FIQ: 770 if (level) { 771 cpu_interrupt(cs, mask[irq]); 772 } else { 773 cpu_reset_interrupt(cs, mask[irq]); 774 } 775 break; 776 default: 777 g_assert_not_reached(); 778 } 779 } 780 781 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) 782 { 783 #ifdef CONFIG_KVM 784 ARMCPU *cpu = opaque; 785 CPUARMState *env = &cpu->env; 786 CPUState *cs = CPU(cpu); 787 uint32_t linestate_bit; 788 int irq_id; 789 790 switch (irq) { 791 case ARM_CPU_IRQ: 792 irq_id = KVM_ARM_IRQ_CPU_IRQ; 793 linestate_bit = CPU_INTERRUPT_HARD; 794 break; 795 case ARM_CPU_FIQ: 796 irq_id = KVM_ARM_IRQ_CPU_FIQ; 797 linestate_bit = CPU_INTERRUPT_FIQ; 798 break; 799 default: 800 g_assert_not_reached(); 801 } 802 803 if (level) { 804 env->irq_line_state |= linestate_bit; 805 } else { 806 env->irq_line_state &= ~linestate_bit; 807 } 808 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); 809 #endif 810 } 811 812 static bool arm_cpu_virtio_is_big_endian(CPUState *cs) 813 { 814 ARMCPU *cpu = ARM_CPU(cs); 815 CPUARMState *env = &cpu->env; 816 817 cpu_synchronize_state(cs); 818 return arm_cpu_data_is_big_endian(env); 819 } 820 821 #endif 822 823 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) 824 { 825 ARMCPU *ac = ARM_CPU(cpu); 826 CPUARMState *env = &ac->env; 827 bool sctlr_b; 828 829 if (is_a64(env)) { 830 /* We might not be compiled with the A64 disassembler 831 * because it needs a C++ compiler. Leave print_insn 832 * unset in this case to use the caller default behaviour. 833 */ 834 #if defined(CONFIG_ARM_A64_DIS) 835 info->print_insn = print_insn_arm_a64; 836 #endif 837 info->cap_arch = CS_ARCH_ARM64; 838 info->cap_insn_unit = 4; 839 info->cap_insn_split = 4; 840 } else { 841 int cap_mode; 842 if (env->thumb) { 843 info->cap_insn_unit = 2; 844 info->cap_insn_split = 4; 845 cap_mode = CS_MODE_THUMB; 846 } else { 847 info->cap_insn_unit = 4; 848 info->cap_insn_split = 4; 849 cap_mode = CS_MODE_ARM; 850 } 851 if (arm_feature(env, ARM_FEATURE_V8)) { 852 cap_mode |= CS_MODE_V8; 853 } 854 if (arm_feature(env, ARM_FEATURE_M)) { 855 cap_mode |= CS_MODE_MCLASS; 856 } 857 info->cap_arch = CS_ARCH_ARM; 858 info->cap_mode = cap_mode; 859 } 860 861 sctlr_b = arm_sctlr_b(env); 862 if (bswap_code(sctlr_b)) { 863 #if TARGET_BIG_ENDIAN 864 info->endian = BFD_ENDIAN_LITTLE; 865 #else 866 info->endian = BFD_ENDIAN_BIG; 867 #endif 868 } 869 info->flags &= ~INSN_ARM_BE32; 870 #ifndef CONFIG_USER_ONLY 871 if (sctlr_b) { 872 info->flags |= INSN_ARM_BE32; 873 } 874 #endif 875 } 876 877 #ifdef TARGET_AARCH64 878 879 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 880 { 881 ARMCPU *cpu = ARM_CPU(cs); 882 CPUARMState *env = &cpu->env; 883 uint32_t psr = pstate_read(env); 884 int i; 885 int el = arm_current_el(env); 886 const char *ns_status; 887 888 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); 889 for (i = 0; i < 32; i++) { 890 if (i == 31) { 891 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); 892 } else { 893 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], 894 (i + 2) % 3 ? " " : "\n"); 895 } 896 } 897 898 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { 899 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 900 } else { 901 ns_status = ""; 902 } 903 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", 904 psr, 905 psr & PSTATE_N ? 'N' : '-', 906 psr & PSTATE_Z ? 'Z' : '-', 907 psr & PSTATE_C ? 'C' : '-', 908 psr & PSTATE_V ? 'V' : '-', 909 ns_status, 910 el, 911 psr & PSTATE_SP ? 'h' : 't'); 912 913 if (cpu_isar_feature(aa64_bti, cpu)) { 914 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); 915 } 916 if (!(flags & CPU_DUMP_FPU)) { 917 qemu_fprintf(f, "\n"); 918 return; 919 } 920 if (fp_exception_el(env, el) != 0) { 921 qemu_fprintf(f, " FPU disabled\n"); 922 return; 923 } 924 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", 925 vfp_get_fpcr(env), vfp_get_fpsr(env)); 926 927 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { 928 int j, zcr_len = sve_vqm1_for_el(env, el); 929 930 for (i = 0; i <= FFR_PRED_NUM; i++) { 931 bool eol; 932 if (i == FFR_PRED_NUM) { 933 qemu_fprintf(f, "FFR="); 934 /* It's last, so end the line. */ 935 eol = true; 936 } else { 937 qemu_fprintf(f, "P%02d=", i); 938 switch (zcr_len) { 939 case 0: 940 eol = i % 8 == 7; 941 break; 942 case 1: 943 eol = i % 6 == 5; 944 break; 945 case 2: 946 case 3: 947 eol = i % 3 == 2; 948 break; 949 default: 950 /* More than one quadword per predicate. */ 951 eol = true; 952 break; 953 } 954 } 955 for (j = zcr_len / 4; j >= 0; j--) { 956 int digits; 957 if (j * 4 + 4 <= zcr_len + 1) { 958 digits = 16; 959 } else { 960 digits = (zcr_len % 4 + 1) * 4; 961 } 962 qemu_fprintf(f, "%0*" PRIx64 "%s", digits, 963 env->vfp.pregs[i].p[j], 964 j ? ":" : eol ? "\n" : " "); 965 } 966 } 967 968 for (i = 0; i < 32; i++) { 969 if (zcr_len == 0) { 970 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", 971 i, env->vfp.zregs[i].d[1], 972 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); 973 } else if (zcr_len == 1) { 974 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 975 ":%016" PRIx64 ":%016" PRIx64 "\n", 976 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], 977 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); 978 } else { 979 for (j = zcr_len; j >= 0; j--) { 980 bool odd = (zcr_len - j) % 2 != 0; 981 if (j == zcr_len) { 982 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); 983 } else if (!odd) { 984 if (j > 0) { 985 qemu_fprintf(f, " [%x-%x]=", j, j - 1); 986 } else { 987 qemu_fprintf(f, " [%x]=", j); 988 } 989 } 990 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", 991 env->vfp.zregs[i].d[j * 2 + 1], 992 env->vfp.zregs[i].d[j * 2], 993 odd || j == 0 ? "\n" : ":"); 994 } 995 } 996 } 997 } else { 998 for (i = 0; i < 32; i++) { 999 uint64_t *q = aa64_vfp_qreg(env, i); 1000 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", 1001 i, q[1], q[0], (i & 1 ? "\n" : " ")); 1002 } 1003 } 1004 } 1005 1006 #else 1007 1008 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1009 { 1010 g_assert_not_reached(); 1011 } 1012 1013 #endif 1014 1015 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) 1016 { 1017 ARMCPU *cpu = ARM_CPU(cs); 1018 CPUARMState *env = &cpu->env; 1019 int i; 1020 1021 if (is_a64(env)) { 1022 aarch64_cpu_dump_state(cs, f, flags); 1023 return; 1024 } 1025 1026 for (i = 0; i < 16; i++) { 1027 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); 1028 if ((i % 4) == 3) { 1029 qemu_fprintf(f, "\n"); 1030 } else { 1031 qemu_fprintf(f, " "); 1032 } 1033 } 1034 1035 if (arm_feature(env, ARM_FEATURE_M)) { 1036 uint32_t xpsr = xpsr_read(env); 1037 const char *mode; 1038 const char *ns_status = ""; 1039 1040 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1041 ns_status = env->v7m.secure ? "S " : "NS "; 1042 } 1043 1044 if (xpsr & XPSR_EXCP) { 1045 mode = "handler"; 1046 } else { 1047 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { 1048 mode = "unpriv-thread"; 1049 } else { 1050 mode = "priv-thread"; 1051 } 1052 } 1053 1054 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", 1055 xpsr, 1056 xpsr & XPSR_N ? 'N' : '-', 1057 xpsr & XPSR_Z ? 'Z' : '-', 1058 xpsr & XPSR_C ? 'C' : '-', 1059 xpsr & XPSR_V ? 'V' : '-', 1060 xpsr & XPSR_T ? 'T' : 'A', 1061 ns_status, 1062 mode); 1063 } else { 1064 uint32_t psr = cpsr_read(env); 1065 const char *ns_status = ""; 1066 1067 if (arm_feature(env, ARM_FEATURE_EL3) && 1068 (psr & CPSR_M) != ARM_CPU_MODE_MON) { 1069 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; 1070 } 1071 1072 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", 1073 psr, 1074 psr & CPSR_N ? 'N' : '-', 1075 psr & CPSR_Z ? 'Z' : '-', 1076 psr & CPSR_C ? 'C' : '-', 1077 psr & CPSR_V ? 'V' : '-', 1078 psr & CPSR_T ? 'T' : 'A', 1079 ns_status, 1080 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); 1081 } 1082 1083 if (flags & CPU_DUMP_FPU) { 1084 int numvfpregs = 0; 1085 if (cpu_isar_feature(aa32_simd_r32, cpu)) { 1086 numvfpregs = 32; 1087 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { 1088 numvfpregs = 16; 1089 } 1090 for (i = 0; i < numvfpregs; i++) { 1091 uint64_t v = *aa32_vfp_dreg(env, i); 1092 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", 1093 i * 2, (uint32_t)v, 1094 i * 2 + 1, (uint32_t)(v >> 32), 1095 i, v); 1096 } 1097 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); 1098 if (cpu_isar_feature(aa32_mve, cpu)) { 1099 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); 1100 } 1101 } 1102 } 1103 1104 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) 1105 { 1106 uint32_t Aff1 = idx / clustersz; 1107 uint32_t Aff0 = idx % clustersz; 1108 return (Aff1 << ARM_AFF1_SHIFT) | Aff0; 1109 } 1110 1111 static void arm_cpu_initfn(Object *obj) 1112 { 1113 ARMCPU *cpu = ARM_CPU(obj); 1114 1115 cpu_set_cpustate_pointers(cpu); 1116 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, 1117 NULL, g_free); 1118 1119 QLIST_INIT(&cpu->pre_el_change_hooks); 1120 QLIST_INIT(&cpu->el_change_hooks); 1121 1122 #ifdef CONFIG_USER_ONLY 1123 # ifdef TARGET_AARCH64 1124 /* 1125 * The linux kernel defaults to 512-bit vectors, when sve is supported. 1126 * See documentation for /proc/sys/abi/sve_default_vector_length, and 1127 * our corresponding sve-default-vector-length cpu property. 1128 */ 1129 cpu->sve_default_vq = 4; 1130 # endif 1131 #else 1132 /* Our inbound IRQ and FIQ lines */ 1133 if (kvm_enabled()) { 1134 /* VIRQ and VFIQ are unused with KVM but we add them to maintain 1135 * the same interface as non-KVM CPUs. 1136 */ 1137 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); 1138 } else { 1139 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); 1140 } 1141 1142 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, 1143 ARRAY_SIZE(cpu->gt_timer_outputs)); 1144 1145 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, 1146 "gicv3-maintenance-interrupt", 1); 1147 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, 1148 "pmu-interrupt", 1); 1149 #endif 1150 1151 /* DTB consumers generally don't in fact care what the 'compatible' 1152 * string is, so always provide some string and trust that a hypothetical 1153 * picky DTB consumer will also provide a helpful error message. 1154 */ 1155 cpu->dtb_compatible = "qemu,unknown"; 1156 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ 1157 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; 1158 1159 if (tcg_enabled() || hvf_enabled()) { 1160 /* TCG and HVF implement PSCI 1.1 */ 1161 cpu->psci_version = QEMU_PSCI_VERSION_1_1; 1162 } 1163 } 1164 1165 static Property arm_cpu_gt_cntfrq_property = 1166 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 1167 NANOSECONDS_PER_SECOND / GTIMER_SCALE); 1168 1169 static Property arm_cpu_reset_cbar_property = 1170 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); 1171 1172 static Property arm_cpu_reset_hivecs_property = 1173 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); 1174 1175 #ifndef CONFIG_USER_ONLY 1176 static Property arm_cpu_has_el2_property = 1177 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); 1178 1179 static Property arm_cpu_has_el3_property = 1180 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); 1181 #endif 1182 1183 static Property arm_cpu_cfgend_property = 1184 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); 1185 1186 static Property arm_cpu_has_vfp_property = 1187 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); 1188 1189 static Property arm_cpu_has_neon_property = 1190 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); 1191 1192 static Property arm_cpu_has_dsp_property = 1193 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); 1194 1195 static Property arm_cpu_has_mpu_property = 1196 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); 1197 1198 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, 1199 * because the CPU initfn will have already set cpu->pmsav7_dregion to 1200 * the right value for that particular CPU type, and we don't want 1201 * to override that with an incorrect constant value. 1202 */ 1203 static Property arm_cpu_pmsav7_dregion_property = 1204 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, 1205 pmsav7_dregion, 1206 qdev_prop_uint32, uint32_t); 1207 1208 static bool arm_get_pmu(Object *obj, Error **errp) 1209 { 1210 ARMCPU *cpu = ARM_CPU(obj); 1211 1212 return cpu->has_pmu; 1213 } 1214 1215 static void arm_set_pmu(Object *obj, bool value, Error **errp) 1216 { 1217 ARMCPU *cpu = ARM_CPU(obj); 1218 1219 if (value) { 1220 if (kvm_enabled() && !kvm_arm_pmu_supported()) { 1221 error_setg(errp, "'pmu' feature not supported by KVM on this host"); 1222 return; 1223 } 1224 set_feature(&cpu->env, ARM_FEATURE_PMU); 1225 } else { 1226 unset_feature(&cpu->env, ARM_FEATURE_PMU); 1227 } 1228 cpu->has_pmu = value; 1229 } 1230 1231 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) 1232 { 1233 /* 1234 * The exact approach to calculating guest ticks is: 1235 * 1236 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, 1237 * NANOSECONDS_PER_SECOND); 1238 * 1239 * We don't do that. Rather we intentionally use integer division 1240 * truncation below and in the caller for the conversion of host monotonic 1241 * time to guest ticks to provide the exact inverse for the semantics of 1242 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so 1243 * it loses precision when representing frequencies where 1244 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to 1245 * provide an exact inverse leads to scheduling timers with negative 1246 * periods, which in turn leads to sticky behaviour in the guest. 1247 * 1248 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor 1249 * cannot become zero. 1250 */ 1251 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? 1252 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; 1253 } 1254 1255 void arm_cpu_post_init(Object *obj) 1256 { 1257 ARMCPU *cpu = ARM_CPU(obj); 1258 1259 /* M profile implies PMSA. We have to do this here rather than 1260 * in realize with the other feature-implication checks because 1261 * we look at the PMSA bit to see if we should add some properties. 1262 */ 1263 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1264 set_feature(&cpu->env, ARM_FEATURE_PMSA); 1265 } 1266 1267 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || 1268 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { 1269 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); 1270 } 1271 1272 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { 1273 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); 1274 } 1275 1276 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1277 object_property_add_uint64_ptr(obj, "rvbar", 1278 &cpu->rvbar_prop, 1279 OBJ_PROP_FLAG_READWRITE); 1280 } 1281 1282 #ifndef CONFIG_USER_ONLY 1283 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1284 /* Add the has_el3 state CPU property only if EL3 is allowed. This will 1285 * prevent "has_el3" from existing on CPUs which cannot support EL3. 1286 */ 1287 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); 1288 1289 object_property_add_link(obj, "secure-memory", 1290 TYPE_MEMORY_REGION, 1291 (Object **)&cpu->secure_memory, 1292 qdev_prop_allow_set_link_before_realize, 1293 OBJ_PROP_LINK_STRONG); 1294 } 1295 1296 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { 1297 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); 1298 } 1299 #endif 1300 1301 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { 1302 cpu->has_pmu = true; 1303 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); 1304 } 1305 1306 /* 1307 * Allow user to turn off VFP and Neon support, but only for TCG -- 1308 * KVM does not currently allow us to lie to the guest about its 1309 * ID/feature registers, so the guest always sees what the host has. 1310 */ 1311 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 1312 ? cpu_isar_feature(aa64_fp_simd, cpu) 1313 : cpu_isar_feature(aa32_vfp, cpu)) { 1314 cpu->has_vfp = true; 1315 if (!kvm_enabled()) { 1316 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); 1317 } 1318 } 1319 1320 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { 1321 cpu->has_neon = true; 1322 if (!kvm_enabled()) { 1323 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); 1324 } 1325 } 1326 1327 if (arm_feature(&cpu->env, ARM_FEATURE_M) && 1328 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { 1329 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); 1330 } 1331 1332 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { 1333 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); 1334 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1335 qdev_property_add_static(DEVICE(obj), 1336 &arm_cpu_pmsav7_dregion_property); 1337 } 1338 } 1339 1340 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { 1341 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, 1342 qdev_prop_allow_set_link_before_realize, 1343 OBJ_PROP_LINK_STRONG); 1344 /* 1345 * M profile: initial value of the Secure VTOR. We can't just use 1346 * a simple DEFINE_PROP_UINT32 for this because we want to permit 1347 * the property to be set after realize. 1348 */ 1349 object_property_add_uint32_ptr(obj, "init-svtor", 1350 &cpu->init_svtor, 1351 OBJ_PROP_FLAG_READWRITE); 1352 } 1353 if (arm_feature(&cpu->env, ARM_FEATURE_M)) { 1354 /* 1355 * Initial value of the NS VTOR (for cores without the Security 1356 * extension, this is the only VTOR) 1357 */ 1358 object_property_add_uint32_ptr(obj, "init-nsvtor", 1359 &cpu->init_nsvtor, 1360 OBJ_PROP_FLAG_READWRITE); 1361 } 1362 1363 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ 1364 object_property_add_uint32_ptr(obj, "psci-conduit", 1365 &cpu->psci_conduit, 1366 OBJ_PROP_FLAG_READWRITE); 1367 1368 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); 1369 1370 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { 1371 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); 1372 } 1373 1374 if (kvm_enabled()) { 1375 kvm_arm_add_vcpu_properties(obj); 1376 } 1377 1378 #ifndef CONFIG_USER_ONLY 1379 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && 1380 cpu_isar_feature(aa64_mte, cpu)) { 1381 object_property_add_link(obj, "tag-memory", 1382 TYPE_MEMORY_REGION, 1383 (Object **)&cpu->tag_memory, 1384 qdev_prop_allow_set_link_before_realize, 1385 OBJ_PROP_LINK_STRONG); 1386 1387 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { 1388 object_property_add_link(obj, "secure-tag-memory", 1389 TYPE_MEMORY_REGION, 1390 (Object **)&cpu->secure_tag_memory, 1391 qdev_prop_allow_set_link_before_realize, 1392 OBJ_PROP_LINK_STRONG); 1393 } 1394 } 1395 #endif 1396 } 1397 1398 static void arm_cpu_finalizefn(Object *obj) 1399 { 1400 ARMCPU *cpu = ARM_CPU(obj); 1401 ARMELChangeHook *hook, *next; 1402 1403 g_hash_table_destroy(cpu->cp_regs); 1404 1405 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { 1406 QLIST_REMOVE(hook, node); 1407 g_free(hook); 1408 } 1409 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { 1410 QLIST_REMOVE(hook, node); 1411 g_free(hook); 1412 } 1413 #ifndef CONFIG_USER_ONLY 1414 if (cpu->pmu_timer) { 1415 timer_free(cpu->pmu_timer); 1416 } 1417 #endif 1418 } 1419 1420 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) 1421 { 1422 Error *local_err = NULL; 1423 1424 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1425 arm_cpu_sve_finalize(cpu, &local_err); 1426 if (local_err != NULL) { 1427 error_propagate(errp, local_err); 1428 return; 1429 } 1430 1431 arm_cpu_pauth_finalize(cpu, &local_err); 1432 if (local_err != NULL) { 1433 error_propagate(errp, local_err); 1434 return; 1435 } 1436 1437 arm_cpu_lpa2_finalize(cpu, &local_err); 1438 if (local_err != NULL) { 1439 error_propagate(errp, local_err); 1440 return; 1441 } 1442 } 1443 1444 if (kvm_enabled()) { 1445 kvm_arm_steal_time_finalize(cpu, &local_err); 1446 if (local_err != NULL) { 1447 error_propagate(errp, local_err); 1448 return; 1449 } 1450 } 1451 } 1452 1453 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 1454 { 1455 CPUState *cs = CPU(dev); 1456 ARMCPU *cpu = ARM_CPU(dev); 1457 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); 1458 CPUARMState *env = &cpu->env; 1459 int pagebits; 1460 Error *local_err = NULL; 1461 bool no_aa32 = false; 1462 1463 /* If we needed to query the host kernel for the CPU features 1464 * then it's possible that might have failed in the initfn, but 1465 * this is the first point where we can report it. 1466 */ 1467 if (cpu->host_cpu_probe_failed) { 1468 if (!kvm_enabled() && !hvf_enabled()) { 1469 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); 1470 } else { 1471 error_setg(errp, "Failed to retrieve host CPU features"); 1472 } 1473 return; 1474 } 1475 1476 #ifndef CONFIG_USER_ONLY 1477 /* The NVIC and M-profile CPU are two halves of a single piece of 1478 * hardware; trying to use one without the other is a command line 1479 * error and will result in segfaults if not caught here. 1480 */ 1481 if (arm_feature(env, ARM_FEATURE_M)) { 1482 if (!env->nvic) { 1483 error_setg(errp, "This board cannot be used with Cortex-M CPUs"); 1484 return; 1485 } 1486 } else { 1487 if (env->nvic) { 1488 error_setg(errp, "This board can only be used with Cortex-M CPUs"); 1489 return; 1490 } 1491 } 1492 1493 if (kvm_enabled()) { 1494 /* 1495 * Catch all the cases which might cause us to create more than one 1496 * address space for the CPU (otherwise we will assert() later in 1497 * cpu_address_space_init()). 1498 */ 1499 if (arm_feature(env, ARM_FEATURE_M)) { 1500 error_setg(errp, 1501 "Cannot enable KVM when using an M-profile guest CPU"); 1502 return; 1503 } 1504 if (cpu->has_el3) { 1505 error_setg(errp, 1506 "Cannot enable KVM when guest CPU has EL3 enabled"); 1507 return; 1508 } 1509 if (cpu->tag_memory) { 1510 error_setg(errp, 1511 "Cannot enable KVM when guest CPUs has MTE enabled"); 1512 return; 1513 } 1514 } 1515 1516 { 1517 uint64_t scale; 1518 1519 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { 1520 if (!cpu->gt_cntfrq_hz) { 1521 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", 1522 cpu->gt_cntfrq_hz); 1523 return; 1524 } 1525 scale = gt_cntfrq_period_ns(cpu); 1526 } else { 1527 scale = GTIMER_SCALE; 1528 } 1529 1530 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1531 arm_gt_ptimer_cb, cpu); 1532 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1533 arm_gt_vtimer_cb, cpu); 1534 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1535 arm_gt_htimer_cb, cpu); 1536 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1537 arm_gt_stimer_cb, cpu); 1538 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, 1539 arm_gt_hvtimer_cb, cpu); 1540 } 1541 #endif 1542 1543 cpu_exec_realizefn(cs, &local_err); 1544 if (local_err != NULL) { 1545 error_propagate(errp, local_err); 1546 return; 1547 } 1548 1549 arm_cpu_finalize_features(cpu, &local_err); 1550 if (local_err != NULL) { 1551 error_propagate(errp, local_err); 1552 return; 1553 } 1554 1555 if (arm_feature(env, ARM_FEATURE_AARCH64) && 1556 cpu->has_vfp != cpu->has_neon) { 1557 /* 1558 * This is an architectural requirement for AArch64; AArch32 is 1559 * more flexible and permits VFP-no-Neon and Neon-no-VFP. 1560 */ 1561 error_setg(errp, 1562 "AArch64 CPUs must have both VFP and Neon or neither"); 1563 return; 1564 } 1565 1566 if (!cpu->has_vfp) { 1567 uint64_t t; 1568 uint32_t u; 1569 1570 t = cpu->isar.id_aa64isar1; 1571 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); 1572 cpu->isar.id_aa64isar1 = t; 1573 1574 t = cpu->isar.id_aa64pfr0; 1575 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); 1576 cpu->isar.id_aa64pfr0 = t; 1577 1578 u = cpu->isar.id_isar6; 1579 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); 1580 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1581 cpu->isar.id_isar6 = u; 1582 1583 u = cpu->isar.mvfr0; 1584 u = FIELD_DP32(u, MVFR0, FPSP, 0); 1585 u = FIELD_DP32(u, MVFR0, FPDP, 0); 1586 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); 1587 u = FIELD_DP32(u, MVFR0, FPSQRT, 0); 1588 u = FIELD_DP32(u, MVFR0, FPROUND, 0); 1589 if (!arm_feature(env, ARM_FEATURE_M)) { 1590 u = FIELD_DP32(u, MVFR0, FPTRAP, 0); 1591 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); 1592 } 1593 cpu->isar.mvfr0 = u; 1594 1595 u = cpu->isar.mvfr1; 1596 u = FIELD_DP32(u, MVFR1, FPFTZ, 0); 1597 u = FIELD_DP32(u, MVFR1, FPDNAN, 0); 1598 u = FIELD_DP32(u, MVFR1, FPHP, 0); 1599 if (arm_feature(env, ARM_FEATURE_M)) { 1600 u = FIELD_DP32(u, MVFR1, FP16, 0); 1601 } 1602 cpu->isar.mvfr1 = u; 1603 1604 u = cpu->isar.mvfr2; 1605 u = FIELD_DP32(u, MVFR2, FPMISC, 0); 1606 cpu->isar.mvfr2 = u; 1607 } 1608 1609 if (!cpu->has_neon) { 1610 uint64_t t; 1611 uint32_t u; 1612 1613 unset_feature(env, ARM_FEATURE_NEON); 1614 1615 t = cpu->isar.id_aa64isar0; 1616 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); 1617 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); 1618 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); 1619 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); 1620 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); 1621 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); 1622 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); 1623 cpu->isar.id_aa64isar0 = t; 1624 1625 t = cpu->isar.id_aa64isar1; 1626 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); 1627 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); 1628 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); 1629 cpu->isar.id_aa64isar1 = t; 1630 1631 t = cpu->isar.id_aa64pfr0; 1632 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); 1633 cpu->isar.id_aa64pfr0 = t; 1634 1635 u = cpu->isar.id_isar5; 1636 u = FIELD_DP32(u, ID_ISAR5, AES, 0); 1637 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); 1638 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); 1639 u = FIELD_DP32(u, ID_ISAR5, RDM, 0); 1640 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); 1641 cpu->isar.id_isar5 = u; 1642 1643 u = cpu->isar.id_isar6; 1644 u = FIELD_DP32(u, ID_ISAR6, DP, 0); 1645 u = FIELD_DP32(u, ID_ISAR6, FHM, 0); 1646 u = FIELD_DP32(u, ID_ISAR6, BF16, 0); 1647 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); 1648 cpu->isar.id_isar6 = u; 1649 1650 if (!arm_feature(env, ARM_FEATURE_M)) { 1651 u = cpu->isar.mvfr1; 1652 u = FIELD_DP32(u, MVFR1, SIMDLS, 0); 1653 u = FIELD_DP32(u, MVFR1, SIMDINT, 0); 1654 u = FIELD_DP32(u, MVFR1, SIMDSP, 0); 1655 u = FIELD_DP32(u, MVFR1, SIMDHP, 0); 1656 cpu->isar.mvfr1 = u; 1657 1658 u = cpu->isar.mvfr2; 1659 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); 1660 cpu->isar.mvfr2 = u; 1661 } 1662 } 1663 1664 if (!cpu->has_neon && !cpu->has_vfp) { 1665 uint64_t t; 1666 uint32_t u; 1667 1668 t = cpu->isar.id_aa64isar0; 1669 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); 1670 cpu->isar.id_aa64isar0 = t; 1671 1672 t = cpu->isar.id_aa64isar1; 1673 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); 1674 cpu->isar.id_aa64isar1 = t; 1675 1676 u = cpu->isar.mvfr0; 1677 u = FIELD_DP32(u, MVFR0, SIMDREG, 0); 1678 cpu->isar.mvfr0 = u; 1679 1680 /* Despite the name, this field covers both VFP and Neon */ 1681 u = cpu->isar.mvfr1; 1682 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); 1683 cpu->isar.mvfr1 = u; 1684 } 1685 1686 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { 1687 uint32_t u; 1688 1689 unset_feature(env, ARM_FEATURE_THUMB_DSP); 1690 1691 u = cpu->isar.id_isar1; 1692 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); 1693 cpu->isar.id_isar1 = u; 1694 1695 u = cpu->isar.id_isar2; 1696 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); 1697 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); 1698 cpu->isar.id_isar2 = u; 1699 1700 u = cpu->isar.id_isar3; 1701 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); 1702 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); 1703 cpu->isar.id_isar3 = u; 1704 } 1705 1706 /* Some features automatically imply others: */ 1707 if (arm_feature(env, ARM_FEATURE_V8)) { 1708 if (arm_feature(env, ARM_FEATURE_M)) { 1709 set_feature(env, ARM_FEATURE_V7); 1710 } else { 1711 set_feature(env, ARM_FEATURE_V7VE); 1712 } 1713 } 1714 1715 /* 1716 * There exist AArch64 cpus without AArch32 support. When KVM 1717 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. 1718 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. 1719 * As a general principle, we also do not make ID register 1720 * consistency checks anywhere unless using TCG, because only 1721 * for TCG would a consistency-check failure be a QEMU bug. 1722 */ 1723 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { 1724 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); 1725 } 1726 1727 if (arm_feature(env, ARM_FEATURE_V7VE)) { 1728 /* v7 Virtualization Extensions. In real hardware this implies 1729 * EL2 and also the presence of the Security Extensions. 1730 * For QEMU, for backwards-compatibility we implement some 1731 * CPUs or CPU configs which have no actual EL2 or EL3 but do 1732 * include the various other features that V7VE implies. 1733 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the 1734 * Security Extensions is ARM_FEATURE_EL3. 1735 */ 1736 assert(!tcg_enabled() || no_aa32 || 1737 cpu_isar_feature(aa32_arm_div, cpu)); 1738 set_feature(env, ARM_FEATURE_LPAE); 1739 set_feature(env, ARM_FEATURE_V7); 1740 } 1741 if (arm_feature(env, ARM_FEATURE_V7)) { 1742 set_feature(env, ARM_FEATURE_VAPA); 1743 set_feature(env, ARM_FEATURE_THUMB2); 1744 set_feature(env, ARM_FEATURE_MPIDR); 1745 if (!arm_feature(env, ARM_FEATURE_M)) { 1746 set_feature(env, ARM_FEATURE_V6K); 1747 } else { 1748 set_feature(env, ARM_FEATURE_V6); 1749 } 1750 1751 /* Always define VBAR for V7 CPUs even if it doesn't exist in 1752 * non-EL3 configs. This is needed by some legacy boards. 1753 */ 1754 set_feature(env, ARM_FEATURE_VBAR); 1755 } 1756 if (arm_feature(env, ARM_FEATURE_V6K)) { 1757 set_feature(env, ARM_FEATURE_V6); 1758 set_feature(env, ARM_FEATURE_MVFR); 1759 } 1760 if (arm_feature(env, ARM_FEATURE_V6)) { 1761 set_feature(env, ARM_FEATURE_V5); 1762 if (!arm_feature(env, ARM_FEATURE_M)) { 1763 assert(!tcg_enabled() || no_aa32 || 1764 cpu_isar_feature(aa32_jazelle, cpu)); 1765 set_feature(env, ARM_FEATURE_AUXCR); 1766 } 1767 } 1768 if (arm_feature(env, ARM_FEATURE_V5)) { 1769 set_feature(env, ARM_FEATURE_V4T); 1770 } 1771 if (arm_feature(env, ARM_FEATURE_LPAE)) { 1772 set_feature(env, ARM_FEATURE_V7MP); 1773 } 1774 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { 1775 set_feature(env, ARM_FEATURE_CBAR); 1776 } 1777 if (arm_feature(env, ARM_FEATURE_THUMB2) && 1778 !arm_feature(env, ARM_FEATURE_M)) { 1779 set_feature(env, ARM_FEATURE_THUMB_DSP); 1780 } 1781 1782 /* 1783 * We rely on no XScale CPU having VFP so we can use the same bits in the 1784 * TB flags field for VECSTRIDE and XSCALE_CPAR. 1785 */ 1786 assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || 1787 !cpu_isar_feature(aa32_vfp_simd, cpu) || 1788 !arm_feature(env, ARM_FEATURE_XSCALE)); 1789 1790 if (arm_feature(env, ARM_FEATURE_V7) && 1791 !arm_feature(env, ARM_FEATURE_M) && 1792 !arm_feature(env, ARM_FEATURE_PMSA)) { 1793 /* v7VMSA drops support for the old ARMv5 tiny pages, so we 1794 * can use 4K pages. 1795 */ 1796 pagebits = 12; 1797 } else { 1798 /* For CPUs which might have tiny 1K pages, or which have an 1799 * MPU and might have small region sizes, stick with 1K pages. 1800 */ 1801 pagebits = 10; 1802 } 1803 if (!set_preferred_target_page_bits(pagebits)) { 1804 /* This can only ever happen for hotplugging a CPU, or if 1805 * the board code incorrectly creates a CPU which it has 1806 * promised via minimum_page_size that it will not. 1807 */ 1808 error_setg(errp, "This CPU requires a smaller page size than the " 1809 "system is using"); 1810 return; 1811 } 1812 1813 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. 1814 * We don't support setting cluster ID ([16..23]) (known as Aff2 1815 * in later ARM ARM versions), or any of the higher affinity level fields, 1816 * so these bits always RAZ. 1817 */ 1818 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { 1819 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, 1820 ARM_DEFAULT_CPUS_PER_CLUSTER); 1821 } 1822 1823 if (cpu->reset_hivecs) { 1824 cpu->reset_sctlr |= (1 << 13); 1825 } 1826 1827 if (cpu->cfgend) { 1828 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { 1829 cpu->reset_sctlr |= SCTLR_EE; 1830 } else { 1831 cpu->reset_sctlr |= SCTLR_B; 1832 } 1833 } 1834 1835 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { 1836 /* If the has_el3 CPU property is disabled then we need to disable the 1837 * feature. 1838 */ 1839 unset_feature(env, ARM_FEATURE_EL3); 1840 1841 /* 1842 * Disable the security extension feature bits in the processor 1843 * feature registers as well. 1844 */ 1845 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); 1846 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); 1847 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1848 ID_AA64PFR0, EL3, 0); 1849 } 1850 1851 if (!cpu->has_el2) { 1852 unset_feature(env, ARM_FEATURE_EL2); 1853 } 1854 1855 if (!cpu->has_pmu) { 1856 unset_feature(env, ARM_FEATURE_PMU); 1857 } 1858 if (arm_feature(env, ARM_FEATURE_PMU)) { 1859 pmu_init(cpu); 1860 1861 if (!kvm_enabled()) { 1862 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); 1863 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); 1864 } 1865 1866 #ifndef CONFIG_USER_ONLY 1867 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, 1868 cpu); 1869 #endif 1870 } else { 1871 cpu->isar.id_aa64dfr0 = 1872 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); 1873 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); 1874 cpu->pmceid0 = 0; 1875 cpu->pmceid1 = 0; 1876 } 1877 1878 if (!arm_feature(env, ARM_FEATURE_EL2)) { 1879 /* 1880 * Disable the hypervisor feature bits in the processor feature 1881 * registers if we don't have EL2. 1882 */ 1883 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, 1884 ID_AA64PFR0, EL2, 0); 1885 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, 1886 ID_PFR1, VIRTUALIZATION, 0); 1887 } 1888 1889 #ifndef CONFIG_USER_ONLY 1890 if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { 1891 /* 1892 * Disable the MTE feature bits if we do not have tag-memory 1893 * provided by the machine. 1894 */ 1895 cpu->isar.id_aa64pfr1 = 1896 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); 1897 } 1898 #endif 1899 1900 /* MPU can be configured out of a PMSA CPU either by setting has-mpu 1901 * to false or by setting pmsav7-dregion to 0. 1902 */ 1903 if (!cpu->has_mpu) { 1904 cpu->pmsav7_dregion = 0; 1905 } 1906 if (cpu->pmsav7_dregion == 0) { 1907 cpu->has_mpu = false; 1908 } 1909 1910 if (arm_feature(env, ARM_FEATURE_PMSA) && 1911 arm_feature(env, ARM_FEATURE_V7)) { 1912 uint32_t nr = cpu->pmsav7_dregion; 1913 1914 if (nr > 0xff) { 1915 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); 1916 return; 1917 } 1918 1919 if (nr) { 1920 if (arm_feature(env, ARM_FEATURE_V8)) { 1921 /* PMSAv8 */ 1922 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); 1923 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); 1924 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1925 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); 1926 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); 1927 } 1928 } else { 1929 env->pmsav7.drbar = g_new0(uint32_t, nr); 1930 env->pmsav7.drsr = g_new0(uint32_t, nr); 1931 env->pmsav7.dracr = g_new0(uint32_t, nr); 1932 } 1933 } 1934 } 1935 1936 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { 1937 uint32_t nr = cpu->sau_sregion; 1938 1939 if (nr > 0xff) { 1940 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); 1941 return; 1942 } 1943 1944 if (nr) { 1945 env->sau.rbar = g_new0(uint32_t, nr); 1946 env->sau.rlar = g_new0(uint32_t, nr); 1947 } 1948 } 1949 1950 if (arm_feature(env, ARM_FEATURE_EL3)) { 1951 set_feature(env, ARM_FEATURE_VBAR); 1952 } 1953 1954 register_cp_regs_for_features(cpu); 1955 arm_cpu_register_gdb_regs_for_features(cpu); 1956 1957 init_cpreg_list(cpu); 1958 1959 #ifndef CONFIG_USER_ONLY 1960 MachineState *ms = MACHINE(qdev_get_machine()); 1961 unsigned int smp_cpus = ms->smp.cpus; 1962 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); 1963 1964 /* 1965 * We must set cs->num_ases to the final value before 1966 * the first call to cpu_address_space_init. 1967 */ 1968 if (cpu->tag_memory != NULL) { 1969 cs->num_ases = 3 + has_secure; 1970 } else { 1971 cs->num_ases = 1 + has_secure; 1972 } 1973 1974 if (has_secure) { 1975 if (!cpu->secure_memory) { 1976 cpu->secure_memory = cs->memory; 1977 } 1978 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", 1979 cpu->secure_memory); 1980 } 1981 1982 if (cpu->tag_memory != NULL) { 1983 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", 1984 cpu->tag_memory); 1985 if (has_secure) { 1986 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", 1987 cpu->secure_tag_memory); 1988 } 1989 } 1990 1991 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); 1992 1993 /* No core_count specified, default to smp_cpus. */ 1994 if (cpu->core_count == -1) { 1995 cpu->core_count = smp_cpus; 1996 } 1997 #endif 1998 1999 if (tcg_enabled()) { 2000 int dcz_blocklen = 4 << cpu->dcz_blocksize; 2001 2002 /* 2003 * We only support DCZ blocklen that fits on one page. 2004 * 2005 * Architectually this is always true. However TARGET_PAGE_SIZE 2006 * is variable and, for compatibility with -machine virt-2.7, 2007 * is only 1KiB, as an artifact of legacy ARMv5 subpage support. 2008 * But even then, while the largest architectural DCZ blocklen 2009 * is 2KiB, no cpu actually uses such a large blocklen. 2010 */ 2011 assert(dcz_blocklen <= TARGET_PAGE_SIZE); 2012 2013 /* 2014 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say 2015 * both nibbles of each byte storing tag data may be written at once. 2016 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. 2017 */ 2018 if (cpu_isar_feature(aa64_mte, cpu)) { 2019 assert(dcz_blocklen >= 2 * TAG_GRANULE); 2020 } 2021 } 2022 2023 qemu_init_vcpu(cs); 2024 cpu_reset(cs); 2025 2026 acc->parent_realize(dev, errp); 2027 } 2028 2029 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) 2030 { 2031 ObjectClass *oc; 2032 char *typename; 2033 char **cpuname; 2034 const char *cpunamestr; 2035 2036 cpuname = g_strsplit(cpu_model, ",", 1); 2037 cpunamestr = cpuname[0]; 2038 #ifdef CONFIG_USER_ONLY 2039 /* For backwards compatibility usermode emulation allows "-cpu any", 2040 * which has the same semantics as "-cpu max". 2041 */ 2042 if (!strcmp(cpunamestr, "any")) { 2043 cpunamestr = "max"; 2044 } 2045 #endif 2046 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); 2047 oc = object_class_by_name(typename); 2048 g_strfreev(cpuname); 2049 g_free(typename); 2050 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || 2051 object_class_is_abstract(oc)) { 2052 return NULL; 2053 } 2054 return oc; 2055 } 2056 2057 static Property arm_cpu_properties[] = { 2058 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), 2059 DEFINE_PROP_UINT64("mp-affinity", ARMCPU, 2060 mp_affinity, ARM64_AFFINITY_INVALID), 2061 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), 2062 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), 2063 DEFINE_PROP_END_OF_LIST() 2064 }; 2065 2066 static gchar *arm_gdb_arch_name(CPUState *cs) 2067 { 2068 ARMCPU *cpu = ARM_CPU(cs); 2069 CPUARMState *env = &cpu->env; 2070 2071 if (arm_feature(env, ARM_FEATURE_IWMMXT)) { 2072 return g_strdup("iwmmxt"); 2073 } 2074 return g_strdup("arm"); 2075 } 2076 2077 #ifndef CONFIG_USER_ONLY 2078 #include "hw/core/sysemu-cpu-ops.h" 2079 2080 static const struct SysemuCPUOps arm_sysemu_ops = { 2081 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, 2082 .asidx_from_attrs = arm_asidx_from_attrs, 2083 .write_elf32_note = arm_cpu_write_elf32_note, 2084 .write_elf64_note = arm_cpu_write_elf64_note, 2085 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, 2086 .legacy_vmsd = &vmstate_arm_cpu, 2087 }; 2088 #endif 2089 2090 #ifdef CONFIG_TCG 2091 static const struct TCGCPUOps arm_tcg_ops = { 2092 .initialize = arm_translate_init, 2093 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 2094 .debug_excp_handler = arm_debug_excp_handler, 2095 2096 #ifdef CONFIG_USER_ONLY 2097 .record_sigsegv = arm_cpu_record_sigsegv, 2098 .record_sigbus = arm_cpu_record_sigbus, 2099 #else 2100 .tlb_fill = arm_cpu_tlb_fill, 2101 .cpu_exec_interrupt = arm_cpu_exec_interrupt, 2102 .do_interrupt = arm_cpu_do_interrupt, 2103 .do_transaction_failed = arm_cpu_do_transaction_failed, 2104 .do_unaligned_access = arm_cpu_do_unaligned_access, 2105 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 2106 .debug_check_watchpoint = arm_debug_check_watchpoint, 2107 .debug_check_breakpoint = arm_debug_check_breakpoint, 2108 #endif /* !CONFIG_USER_ONLY */ 2109 }; 2110 #endif /* CONFIG_TCG */ 2111 2112 static void arm_cpu_class_init(ObjectClass *oc, void *data) 2113 { 2114 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2115 CPUClass *cc = CPU_CLASS(acc); 2116 DeviceClass *dc = DEVICE_CLASS(oc); 2117 2118 device_class_set_parent_realize(dc, arm_cpu_realizefn, 2119 &acc->parent_realize); 2120 2121 device_class_set_props(dc, arm_cpu_properties); 2122 device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); 2123 2124 cc->class_by_name = arm_cpu_class_by_name; 2125 cc->has_work = arm_cpu_has_work; 2126 cc->dump_state = arm_cpu_dump_state; 2127 cc->set_pc = arm_cpu_set_pc; 2128 cc->gdb_read_register = arm_cpu_gdb_read_register; 2129 cc->gdb_write_register = arm_cpu_gdb_write_register; 2130 #ifndef CONFIG_USER_ONLY 2131 cc->sysemu_ops = &arm_sysemu_ops; 2132 #endif 2133 cc->gdb_num_core_regs = 26; 2134 cc->gdb_core_xml_file = "arm-core.xml"; 2135 cc->gdb_arch_name = arm_gdb_arch_name; 2136 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; 2137 cc->gdb_stop_before_watchpoint = true; 2138 cc->disas_set_info = arm_disas_set_info; 2139 2140 #ifdef CONFIG_TCG 2141 cc->tcg_ops = &arm_tcg_ops; 2142 #endif /* CONFIG_TCG */ 2143 } 2144 2145 static void arm_cpu_instance_init(Object *obj) 2146 { 2147 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); 2148 2149 acc->info->initfn(obj); 2150 arm_cpu_post_init(obj); 2151 } 2152 2153 static void cpu_register_class_init(ObjectClass *oc, void *data) 2154 { 2155 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 2156 2157 acc->info = data; 2158 } 2159 2160 void arm_cpu_register(const ARMCPUInfo *info) 2161 { 2162 TypeInfo type_info = { 2163 .parent = TYPE_ARM_CPU, 2164 .instance_size = sizeof(ARMCPU), 2165 .instance_align = __alignof__(ARMCPU), 2166 .instance_init = arm_cpu_instance_init, 2167 .class_size = sizeof(ARMCPUClass), 2168 .class_init = info->class_init ?: cpu_register_class_init, 2169 .class_data = (void *)info, 2170 }; 2171 2172 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); 2173 type_register(&type_info); 2174 g_free((void *)type_info.name); 2175 } 2176 2177 static const TypeInfo arm_cpu_type_info = { 2178 .name = TYPE_ARM_CPU, 2179 .parent = TYPE_CPU, 2180 .instance_size = sizeof(ARMCPU), 2181 .instance_align = __alignof__(ARMCPU), 2182 .instance_init = arm_cpu_initfn, 2183 .instance_finalize = arm_cpu_finalizefn, 2184 .abstract = true, 2185 .class_size = sizeof(ARMCPUClass), 2186 .class_init = arm_cpu_class_init, 2187 }; 2188 2189 static void arm_cpu_register_types(void) 2190 { 2191 type_register_static(&arm_cpu_type_info); 2192 } 2193 2194 type_init(arm_cpu_register_types) 2195