1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/gdbstub.h" 29 #include "qapi/qapi-types-common.h" 30 #include "target/arm/multiprocessing.h" 31 #include "target/arm/gtimer.h" 32 33 /* ARM processors have a weak memory model */ 34 #define TCG_GUEST_DEFAULT_MO (0) 35 36 #ifdef TARGET_AARCH64 37 #define KVM_HAVE_MCE_INJECTION 1 38 #endif 39 40 #define EXCP_UDEF 1 /* undefined instruction */ 41 #define EXCP_SWI 2 /* software interrupt */ 42 #define EXCP_PREFETCH_ABORT 3 43 #define EXCP_DATA_ABORT 4 44 #define EXCP_IRQ 5 45 #define EXCP_FIQ 6 46 #define EXCP_BKPT 7 47 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 48 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 49 #define EXCP_HVC 11 /* HyperVisor Call */ 50 #define EXCP_HYP_TRAP 12 51 #define EXCP_SMC 13 /* Secure Monitor Call */ 52 #define EXCP_VIRQ 14 53 #define EXCP_VFIQ 15 54 #define EXCP_SEMIHOST 16 /* semihosting call */ 55 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 56 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 57 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 58 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 59 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 60 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 61 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 62 #define EXCP_VSERR 24 63 #define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ 64 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 65 66 #define ARMV7M_EXCP_RESET 1 67 #define ARMV7M_EXCP_NMI 2 68 #define ARMV7M_EXCP_HARD 3 69 #define ARMV7M_EXCP_MEM 4 70 #define ARMV7M_EXCP_BUS 5 71 #define ARMV7M_EXCP_USAGE 6 72 #define ARMV7M_EXCP_SECURE 7 73 #define ARMV7M_EXCP_SVC 11 74 #define ARMV7M_EXCP_DEBUG 12 75 #define ARMV7M_EXCP_PENDSV 14 76 #define ARMV7M_EXCP_SYSTICK 15 77 78 /* ARM-specific interrupt pending bits. */ 79 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 80 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 81 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 82 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 83 84 /* The usual mapping for an AArch64 system register to its AArch32 85 * counterpart is for the 32 bit world to have access to the lower 86 * half only (with writes leaving the upper half untouched). It's 87 * therefore useful to be able to pass TCG the offset of the least 88 * significant half of a uint64_t struct member. 89 */ 90 #if HOST_BIG_ENDIAN 91 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 92 #define offsetofhigh32(S, M) offsetof(S, M) 93 #else 94 #define offsetoflow32(S, M) offsetof(S, M) 95 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 96 #endif 97 98 /* ARM-specific extra insn start words: 99 * 1: Conditional execution bits 100 * 2: Partial exception syndrome for data aborts 101 */ 102 #define TARGET_INSN_START_EXTRA_WORDS 2 103 104 /* The 2nd extra word holding syndrome info for data aborts does not use 105 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to 106 * help the sleb128 encoder do a better job. 107 * When restoring the CPU state, we shift it back up. 108 */ 109 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 110 #define ARM_INSN_START_WORD2_SHIFT 13 111 112 /* We currently assume float and double are IEEE single and double 113 precision respectively. 114 Doing runtime conversions is tricky because VFP registers may contain 115 integer values (eg. as the result of a FTOSI instruction). 116 s<2n> maps to the least significant half of d<n> 117 s<2n+1> maps to the most significant half of d<n> 118 */ 119 120 /** 121 * DynamicGDBFeatureInfo: 122 * @desc: Contains the feature descriptions. 123 * @data: A union with data specific to the set of registers 124 * @cpregs_keys: Array that contains the corresponding Key of 125 * a given cpreg with the same order of the cpreg 126 * in the XML description. 127 */ 128 typedef struct DynamicGDBFeatureInfo { 129 GDBFeature desc; 130 union { 131 struct { 132 uint32_t *keys; 133 } cpregs; 134 } data; 135 } DynamicGDBFeatureInfo; 136 137 /* CPU state for each instance of a generic timer (in cp15 c14) */ 138 typedef struct ARMGenericTimer { 139 uint64_t cval; /* Timer CompareValue register */ 140 uint64_t ctl; /* Timer Control register */ 141 } ARMGenericTimer; 142 143 /* Define a maximum sized vector register. 144 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 145 * For 64-bit, this is a 2048-bit SVE register. 146 * 147 * Note that the mapping between S, D, and Q views of the register bank 148 * differs between AArch64 and AArch32. 149 * In AArch32: 150 * Qn = regs[n].d[1]:regs[n].d[0] 151 * Dn = regs[n / 2].d[n & 1] 152 * Sn = regs[n / 4].d[n % 4 / 2], 153 * bits 31..0 for even n, and bits 63..32 for odd n 154 * (and regs[16] to regs[31] are inaccessible) 155 * In AArch64: 156 * Zn = regs[n].d[*] 157 * Qn = regs[n].d[1]:regs[n].d[0] 158 * Dn = regs[n].d[0] 159 * Sn = regs[n].d[0] bits 31..0 160 * Hn = regs[n].d[0] bits 15..0 161 * 162 * This corresponds to the architecturally defined mapping between 163 * the two execution states, and means we do not need to explicitly 164 * map these registers when changing states. 165 * 166 * Align the data for use with TCG host vector operations. 167 */ 168 169 #ifdef TARGET_AARCH64 170 # define ARM_MAX_VQ 16 171 #else 172 # define ARM_MAX_VQ 1 173 #endif 174 175 typedef struct ARMVectorReg { 176 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 177 } ARMVectorReg; 178 179 #ifdef TARGET_AARCH64 180 /* In AArch32 mode, predicate registers do not exist at all. */ 181 typedef struct ARMPredicateReg { 182 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 183 } ARMPredicateReg; 184 185 /* In AArch32 mode, PAC keys do not exist at all. */ 186 typedef struct ARMPACKey { 187 uint64_t lo, hi; 188 } ARMPACKey; 189 #endif 190 191 /* See the commentary above the TBFLAG field definitions. */ 192 typedef struct CPUARMTBFlags { 193 uint32_t flags; 194 target_ulong flags2; 195 } CPUARMTBFlags; 196 197 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; 198 199 typedef struct NVICState NVICState; 200 201 typedef struct CPUArchState { 202 /* Regs for current mode. */ 203 uint32_t regs[16]; 204 205 /* 32/64 switch only happens when taking and returning from 206 * exceptions so the overlap semantics are taken care of then 207 * instead of having a complicated union. 208 */ 209 /* Regs for A64 mode. */ 210 uint64_t xregs[32]; 211 uint64_t pc; 212 /* PSTATE isn't an architectural register for ARMv8. However, it is 213 * convenient for us to assemble the underlying state into a 32 bit format 214 * identical to the architectural format used for the SPSR. (This is also 215 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 216 * 'pstate' register are.) Of the PSTATE bits: 217 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 218 * semantics as for AArch32, as described in the comments on each field) 219 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 220 * DAIF (exception masks) are kept in env->daif 221 * BTYPE is kept in env->btype 222 * SM and ZA are kept in env->svcr 223 * all other bits are stored in their correct places in env->pstate 224 */ 225 uint32_t pstate; 226 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 227 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 228 229 /* Cached TBFLAGS state. See below for which bits are included. */ 230 CPUARMTBFlags hflags; 231 232 /* Frequently accessed CPSR bits are stored separately for efficiency. 233 This contains all the other bits. Use cpsr_{read,write} to access 234 the whole CPSR. */ 235 uint32_t uncached_cpsr; 236 uint32_t spsr; 237 238 /* Banked registers. */ 239 uint64_t banked_spsr[8]; 240 uint32_t banked_r13[8]; 241 uint32_t banked_r14[8]; 242 243 /* These hold r8-r12. */ 244 uint32_t usr_regs[5]; 245 uint32_t fiq_regs[5]; 246 247 /* cpsr flag cache for faster execution */ 248 uint32_t CF; /* 0 or 1 */ 249 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 250 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 251 uint32_t ZF; /* Z set if zero. */ 252 uint32_t QF; /* 0 or 1 */ 253 uint32_t GE; /* cpsr[19:16] */ 254 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 255 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 256 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 257 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */ 258 259 uint64_t elr_el[4]; /* AArch64 exception link regs */ 260 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 261 262 /* System control coprocessor (cp15) */ 263 struct { 264 uint32_t c0_cpuid; 265 union { /* Cache size selection */ 266 struct { 267 uint64_t _unused_csselr0; 268 uint64_t csselr_ns; 269 uint64_t _unused_csselr1; 270 uint64_t csselr_s; 271 }; 272 uint64_t csselr_el[4]; 273 }; 274 union { /* System control register. */ 275 struct { 276 uint64_t _unused_sctlr; 277 uint64_t sctlr_ns; 278 uint64_t hsctlr; 279 uint64_t sctlr_s; 280 }; 281 uint64_t sctlr_el[4]; 282 }; 283 uint64_t vsctlr; /* Virtualization System control register. */ 284 uint64_t cpacr_el1; /* Architectural feature access control register */ 285 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 286 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 287 uint64_t sder; /* Secure debug enable register. */ 288 uint32_t nsacr; /* Non-secure access control register. */ 289 union { /* MMU translation table base 0. */ 290 struct { 291 uint64_t _unused_ttbr0_0; 292 uint64_t ttbr0_ns; 293 uint64_t _unused_ttbr0_1; 294 uint64_t ttbr0_s; 295 }; 296 uint64_t ttbr0_el[4]; 297 }; 298 union { /* MMU translation table base 1. */ 299 struct { 300 uint64_t _unused_ttbr1_0; 301 uint64_t ttbr1_ns; 302 uint64_t _unused_ttbr1_1; 303 uint64_t ttbr1_s; 304 }; 305 uint64_t ttbr1_el[4]; 306 }; 307 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 308 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 309 /* MMU translation table base control. */ 310 uint64_t tcr_el[4]; 311 uint64_t vtcr_el2; /* Virtualization Translation Control. */ 312 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */ 313 uint32_t c2_data; /* MPU data cacheable bits. */ 314 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 315 union { /* MMU domain access control register 316 * MPU write buffer control. 317 */ 318 struct { 319 uint64_t dacr_ns; 320 uint64_t dacr_s; 321 }; 322 struct { 323 uint64_t dacr32_el2; 324 }; 325 }; 326 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 327 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 328 uint64_t hcr_el2; /* Hypervisor configuration register */ 329 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 330 uint64_t scr_el3; /* Secure configuration register. */ 331 union { /* Fault status registers. */ 332 struct { 333 uint64_t ifsr_ns; 334 uint64_t ifsr_s; 335 }; 336 struct { 337 uint64_t ifsr32_el2; 338 }; 339 }; 340 union { 341 struct { 342 uint64_t _unused_dfsr; 343 uint64_t dfsr_ns; 344 uint64_t hsr; 345 uint64_t dfsr_s; 346 }; 347 uint64_t esr_el[4]; 348 }; 349 uint32_t c6_region[8]; /* MPU base/size registers. */ 350 union { /* Fault address registers. */ 351 struct { 352 uint64_t _unused_far0; 353 #if HOST_BIG_ENDIAN 354 uint32_t ifar_ns; 355 uint32_t dfar_ns; 356 uint32_t ifar_s; 357 uint32_t dfar_s; 358 #else 359 uint32_t dfar_ns; 360 uint32_t ifar_ns; 361 uint32_t dfar_s; 362 uint32_t ifar_s; 363 #endif 364 uint64_t _unused_far3; 365 }; 366 uint64_t far_el[4]; 367 }; 368 uint64_t hpfar_el2; 369 uint64_t hstr_el2; 370 union { /* Translation result. */ 371 struct { 372 uint64_t _unused_par_0; 373 uint64_t par_ns; 374 uint64_t _unused_par_1; 375 uint64_t par_s; 376 }; 377 uint64_t par_el[4]; 378 }; 379 380 uint32_t c9_insn; /* Cache lockdown registers. */ 381 uint32_t c9_data; 382 uint64_t c9_pmcr; /* performance monitor control register */ 383 uint64_t c9_pmcnten; /* perf monitor counter enables */ 384 uint64_t c9_pmovsr; /* perf monitor overflow status */ 385 uint64_t c9_pmuserenr; /* perf monitor user enable */ 386 uint64_t c9_pmselr; /* perf monitor counter selection register */ 387 uint64_t c9_pminten; /* perf monitor interrupt enables */ 388 union { /* Memory attribute redirection */ 389 struct { 390 #if HOST_BIG_ENDIAN 391 uint64_t _unused_mair_0; 392 uint32_t mair1_ns; 393 uint32_t mair0_ns; 394 uint64_t _unused_mair_1; 395 uint32_t mair1_s; 396 uint32_t mair0_s; 397 #else 398 uint64_t _unused_mair_0; 399 uint32_t mair0_ns; 400 uint32_t mair1_ns; 401 uint64_t _unused_mair_1; 402 uint32_t mair0_s; 403 uint32_t mair1_s; 404 #endif 405 }; 406 uint64_t mair_el[4]; 407 }; 408 union { /* vector base address register */ 409 struct { 410 uint64_t _unused_vbar; 411 uint64_t vbar_ns; 412 uint64_t hvbar; 413 uint64_t vbar_s; 414 }; 415 uint64_t vbar_el[4]; 416 }; 417 uint32_t mvbar; /* (monitor) vector base address register */ 418 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 419 struct { /* FCSE PID. */ 420 uint32_t fcseidr_ns; 421 uint32_t fcseidr_s; 422 }; 423 union { /* Context ID. */ 424 struct { 425 uint64_t _unused_contextidr_0; 426 uint64_t contextidr_ns; 427 uint64_t _unused_contextidr_1; 428 uint64_t contextidr_s; 429 }; 430 uint64_t contextidr_el[4]; 431 }; 432 union { /* User RW Thread register. */ 433 struct { 434 uint64_t tpidrurw_ns; 435 uint64_t tpidrprw_ns; 436 uint64_t htpidr; 437 uint64_t _tpidr_el3; 438 }; 439 uint64_t tpidr_el[4]; 440 }; 441 uint64_t tpidr2_el0; 442 /* The secure banks of these registers don't map anywhere */ 443 uint64_t tpidrurw_s; 444 uint64_t tpidrprw_s; 445 uint64_t tpidruro_s; 446 447 union { /* User RO Thread register. */ 448 uint64_t tpidruro_ns; 449 uint64_t tpidrro_el[1]; 450 }; 451 uint64_t c14_cntfrq; /* Counter Frequency register */ 452 uint64_t c14_cntkctl; /* Timer Control register */ 453 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 454 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 455 ARMGenericTimer c14_timer[NUM_GTIMERS]; 456 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 457 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 458 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 459 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 460 uint32_t c15_threadid; /* TI debugger thread-ID. */ 461 uint32_t c15_config_base_address; /* SCU base address. */ 462 uint32_t c15_diagnostic; /* diagnostic register */ 463 uint32_t c15_power_diagnostic; 464 uint32_t c15_power_control; /* power control */ 465 uint64_t dbgbvr[16]; /* breakpoint value registers */ 466 uint64_t dbgbcr[16]; /* breakpoint control registers */ 467 uint64_t dbgwvr[16]; /* watchpoint value registers */ 468 uint64_t dbgwcr[16]; /* watchpoint control registers */ 469 uint64_t dbgclaim; /* DBGCLAIM bits */ 470 uint64_t mdscr_el1; 471 uint64_t oslsr_el1; /* OS Lock Status */ 472 uint64_t osdlr_el1; /* OS DoubleLock status */ 473 uint64_t mdcr_el2; 474 uint64_t mdcr_el3; 475 /* Stores the architectural value of the counter *the last time it was 476 * updated* by pmccntr_op_start. Accesses should always be surrounded 477 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 478 * architecturally-correct value is being read/set. 479 */ 480 uint64_t c15_ccnt; 481 /* Stores the delta between the architectural value and the underlying 482 * cycle count during normal operation. It is used to update c15_ccnt 483 * to be the correct architectural value before accesses. During 484 * accesses, c15_ccnt_delta contains the underlying count being used 485 * for the access, after which it reverts to the delta value in 486 * pmccntr_op_finish. 487 */ 488 uint64_t c15_ccnt_delta; 489 uint64_t c14_pmevcntr[31]; 490 uint64_t c14_pmevcntr_delta[31]; 491 uint64_t c14_pmevtyper[31]; 492 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 493 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 494 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 495 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 496 uint64_t gcr_el1; 497 uint64_t rgsr_el1; 498 499 /* Minimal RAS registers */ 500 uint64_t disr_el1; 501 uint64_t vdisr_el2; 502 uint64_t vsesr_el2; 503 504 /* 505 * Fine-Grained Trap registers. We store these as arrays so the 506 * access checking code doesn't have to manually select 507 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. 508 * FEAT_FGT2 will add more elements to these arrays. 509 */ 510 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ 511 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ 512 uint64_t fgt_exec[1]; /* HFGITR */ 513 514 /* RME registers */ 515 uint64_t gpccr_el3; 516 uint64_t gptbr_el3; 517 uint64_t mfar_el3; 518 519 /* NV2 register */ 520 uint64_t vncr_el2; 521 } cp15; 522 523 struct { 524 /* M profile has up to 4 stack pointers: 525 * a Main Stack Pointer and a Process Stack Pointer for each 526 * of the Secure and Non-Secure states. (If the CPU doesn't support 527 * the security extension then it has only two SPs.) 528 * In QEMU we always store the currently active SP in regs[13], 529 * and the non-active SP for the current security state in 530 * v7m.other_sp. The stack pointers for the inactive security state 531 * are stored in other_ss_msp and other_ss_psp. 532 * switch_v7m_security_state() is responsible for rearranging them 533 * when we change security state. 534 */ 535 uint32_t other_sp; 536 uint32_t other_ss_msp; 537 uint32_t other_ss_psp; 538 uint32_t vecbase[M_REG_NUM_BANKS]; 539 uint32_t basepri[M_REG_NUM_BANKS]; 540 uint32_t control[M_REG_NUM_BANKS]; 541 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 542 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 543 uint32_t hfsr; /* HardFault Status */ 544 uint32_t dfsr; /* Debug Fault Status Register */ 545 uint32_t sfsr; /* Secure Fault Status Register */ 546 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 547 uint32_t bfar; /* BusFault Address */ 548 uint32_t sfar; /* Secure Fault Address Register */ 549 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 550 int exception; 551 uint32_t primask[M_REG_NUM_BANKS]; 552 uint32_t faultmask[M_REG_NUM_BANKS]; 553 uint32_t aircr; /* only holds r/w state if security extn implemented */ 554 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 555 uint32_t csselr[M_REG_NUM_BANKS]; 556 uint32_t scr[M_REG_NUM_BANKS]; 557 uint32_t msplim[M_REG_NUM_BANKS]; 558 uint32_t psplim[M_REG_NUM_BANKS]; 559 uint32_t fpcar[M_REG_NUM_BANKS]; 560 uint32_t fpccr[M_REG_NUM_BANKS]; 561 uint32_t fpdscr[M_REG_NUM_BANKS]; 562 uint32_t cpacr[M_REG_NUM_BANKS]; 563 uint32_t nsacr; 564 uint32_t ltpsize; 565 uint32_t vpr; 566 } v7m; 567 568 /* Information associated with an exception about to be taken: 569 * code which raises an exception must set cs->exception_index and 570 * the relevant parts of this structure; the cpu_do_interrupt function 571 * will then set the guest-visible registers as part of the exception 572 * entry process. 573 */ 574 struct { 575 uint32_t syndrome; /* AArch64 format syndrome register */ 576 uint32_t fsr; /* AArch32 format fault status register info */ 577 uint64_t vaddress; /* virtual addr associated with exception, if any */ 578 uint32_t target_el; /* EL the exception should be targeted for */ 579 /* If we implement EL2 we will also need to store information 580 * about the intermediate physical address for stage 2 faults. 581 */ 582 } exception; 583 584 /* Information associated with an SError */ 585 struct { 586 uint8_t pending; 587 uint8_t has_esr; 588 uint64_t esr; 589 } serror; 590 591 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 592 593 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 594 uint32_t irq_line_state; 595 596 /* Thumb-2 EE state. */ 597 uint32_t teecr; 598 uint32_t teehbr; 599 600 /* VFP coprocessor state. */ 601 struct { 602 ARMVectorReg zregs[32]; 603 604 #ifdef TARGET_AARCH64 605 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 606 #define FFR_PRED_NUM 16 607 ARMPredicateReg pregs[17]; 608 /* Scratch space for aa64 sve predicate temporary. */ 609 ARMPredicateReg preg_tmp; 610 #endif 611 612 /* We store these fpcsr fields separately for convenience. */ 613 uint32_t qc[4] QEMU_ALIGNED(16); 614 int vec_len; 615 int vec_stride; 616 617 uint32_t xregs[16]; 618 619 /* Scratch space for aa32 neon expansion. */ 620 uint32_t scratch[8]; 621 622 /* There are a number of distinct float control structures: 623 * 624 * fp_status: is the "normal" fp status. 625 * fp_status_fp16: used for half-precision calculations 626 * standard_fp_status : the ARM "Standard FPSCR Value" 627 * standard_fp_status_fp16 : used for half-precision 628 * calculations with the ARM "Standard FPSCR Value" 629 * 630 * Half-precision operations are governed by a separate 631 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 632 * status structure to control this. 633 * 634 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 635 * round-to-nearest and is used by any operations (generally 636 * Neon) which the architecture defines as controlled by the 637 * standard FPSCR value rather than the FPSCR. 638 * 639 * The "standard FPSCR but for fp16 ops" is needed because 640 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 641 * using a fixed value for it. 642 * 643 * To avoid having to transfer exception bits around, we simply 644 * say that the FPSCR cumulative exception flags are the logical 645 * OR of the flags in the four fp statuses. This relies on the 646 * only thing which needs to read the exception flags being 647 * an explicit FPSCR read. 648 */ 649 float_status fp_status; 650 float_status fp_status_f16; 651 float_status standard_fp_status; 652 float_status standard_fp_status_f16; 653 654 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */ 655 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */ 656 } vfp; 657 658 uint64_t exclusive_addr; 659 uint64_t exclusive_val; 660 /* 661 * Contains the 'val' for the second 64-bit register of LDXP, which comes 662 * from the higher address, not the high part of a complete 128-bit value. 663 * In some ways it might be more convenient to record the exclusive value 664 * as the low and high halves of a 128 bit data value, but the current 665 * semantics of these fields are baked into the migration format. 666 */ 667 uint64_t exclusive_high; 668 669 /* iwMMXt coprocessor state. */ 670 struct { 671 uint64_t regs[16]; 672 uint64_t val; 673 674 uint32_t cregs[16]; 675 } iwmmxt; 676 677 #ifdef TARGET_AARCH64 678 struct { 679 ARMPACKey apia; 680 ARMPACKey apib; 681 ARMPACKey apda; 682 ARMPACKey apdb; 683 ARMPACKey apga; 684 } keys; 685 686 uint64_t scxtnum_el[4]; 687 688 /* 689 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order, 690 * as we do with vfp.zregs[]. This corresponds to the architectural ZA 691 * array, where ZA[N] is in the least-significant bytes of env->zarray[N]. 692 * When SVL is less than the architectural maximum, the accessible 693 * storage is restricted, such that if the SVL is X bytes the guest can 694 * see only the bottom X elements of zarray[], and only the least 695 * significant X bytes of each element of the array. (In other words, 696 * the observable part is always square.) 697 * 698 * The ZA storage can also be considered as a set of square tiles of 699 * elements of different sizes. The mapping from tiles to the ZA array 700 * is architecturally defined, such that for tiles of elements of esz 701 * bytes, the Nth row (or "horizontal slice") of tile T is in 702 * ZA[T + N * esz]. Note that this means that each tile is not contiguous 703 * in the ZA storage, because its rows are striped through the ZA array. 704 * 705 * Because this is so large, keep this toward the end of the reset area, 706 * to keep the offsets into the rest of the structure smaller. 707 */ 708 ARMVectorReg zarray[ARM_MAX_VQ * 16]; 709 #endif 710 711 struct CPUBreakpoint *cpu_breakpoint[16]; 712 struct CPUWatchpoint *cpu_watchpoint[16]; 713 714 /* Optional fault info across tlb lookup. */ 715 ARMMMUFaultInfo *tlb_fi; 716 717 /* Fields up to this point are cleared by a CPU reset */ 718 struct {} end_reset_fields; 719 720 /* Fields after this point are preserved across CPU reset. */ 721 722 /* Internal CPU feature flags. */ 723 uint64_t features; 724 725 /* PMSAv7 MPU */ 726 struct { 727 uint32_t *drbar; 728 uint32_t *drsr; 729 uint32_t *dracr; 730 uint32_t rnr[M_REG_NUM_BANKS]; 731 } pmsav7; 732 733 /* PMSAv8 MPU */ 734 struct { 735 /* The PMSAv8 implementation also shares some PMSAv7 config 736 * and state: 737 * pmsav7.rnr (region number register) 738 * pmsav7_dregion (number of configured regions) 739 */ 740 uint32_t *rbar[M_REG_NUM_BANKS]; 741 uint32_t *rlar[M_REG_NUM_BANKS]; 742 uint32_t *hprbar; 743 uint32_t *hprlar; 744 uint32_t mair0[M_REG_NUM_BANKS]; 745 uint32_t mair1[M_REG_NUM_BANKS]; 746 uint32_t hprselr; 747 } pmsav8; 748 749 /* v8M SAU */ 750 struct { 751 uint32_t *rbar; 752 uint32_t *rlar; 753 uint32_t rnr; 754 uint32_t ctrl; 755 } sau; 756 757 #if !defined(CONFIG_USER_ONLY) 758 NVICState *nvic; 759 const struct arm_boot_info *boot_info; 760 /* Store GICv3CPUState to access from this struct */ 761 void *gicv3state; 762 #else /* CONFIG_USER_ONLY */ 763 /* For usermode syscall translation. */ 764 bool eabi; 765 #endif /* CONFIG_USER_ONLY */ 766 767 #ifdef TARGET_TAGGED_ADDRESSES 768 /* Linux syscall tagged address support */ 769 bool tagged_addr_enable; 770 #endif 771 } CPUARMState; 772 773 static inline void set_feature(CPUARMState *env, int feature) 774 { 775 env->features |= 1ULL << feature; 776 } 777 778 static inline void unset_feature(CPUARMState *env, int feature) 779 { 780 env->features &= ~(1ULL << feature); 781 } 782 783 /** 784 * ARMELChangeHookFn: 785 * type of a function which can be registered via arm_register_el_change_hook() 786 * to get callbacks when the CPU changes its exception level or mode. 787 */ 788 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 789 typedef struct ARMELChangeHook ARMELChangeHook; 790 struct ARMELChangeHook { 791 ARMELChangeHookFn *hook; 792 void *opaque; 793 QLIST_ENTRY(ARMELChangeHook) node; 794 }; 795 796 /* These values map onto the return values for 797 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 798 typedef enum ARMPSCIState { 799 PSCI_ON = 0, 800 PSCI_OFF = 1, 801 PSCI_ON_PENDING = 2 802 } ARMPSCIState; 803 804 typedef struct ARMISARegisters ARMISARegisters; 805 806 /* 807 * In map, each set bit is a supported vector length of (bit-number + 1) * 16 808 * bytes, i.e. each bit number + 1 is the vector length in quadwords. 809 * 810 * While processing properties during initialization, corresponding init bits 811 * are set for bits in sve_vq_map that have been set by properties. 812 * 813 * Bits set in supported represent valid vector lengths for the CPU type. 814 */ 815 typedef struct { 816 uint32_t map, init, supported; 817 } ARMVQMap; 818 819 /** 820 * ARMCPU: 821 * @env: #CPUARMState 822 * 823 * An ARM CPU core. 824 */ 825 struct ArchCPU { 826 CPUState parent_obj; 827 828 CPUARMState env; 829 830 /* Coprocessor information */ 831 GHashTable *cp_regs; 832 /* For marshalling (mostly coprocessor) register state between the 833 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 834 * we use these arrays. 835 */ 836 /* List of register indexes managed via these arrays; (full KVM style 837 * 64 bit indexes, not CPRegInfo 32 bit indexes) 838 */ 839 uint64_t *cpreg_indexes; 840 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 841 uint64_t *cpreg_values; 842 /* Length of the indexes, values, reset_values arrays */ 843 int32_t cpreg_array_len; 844 /* These are used only for migration: incoming data arrives in 845 * these fields and is sanity checked in post_load before copying 846 * to the working data structures above. 847 */ 848 uint64_t *cpreg_vmstate_indexes; 849 uint64_t *cpreg_vmstate_values; 850 int32_t cpreg_vmstate_array_len; 851 852 DynamicGDBFeatureInfo dyn_sysreg_feature; 853 DynamicGDBFeatureInfo dyn_svereg_feature; 854 DynamicGDBFeatureInfo dyn_m_systemreg_feature; 855 DynamicGDBFeatureInfo dyn_m_secextreg_feature; 856 857 /* Timers used by the generic (architected) timer */ 858 QEMUTimer *gt_timer[NUM_GTIMERS]; 859 /* 860 * Timer used by the PMU. Its state is restored after migration by 861 * pmu_op_finish() - it does not need other handling during migration 862 */ 863 QEMUTimer *pmu_timer; 864 /* GPIO outputs for generic timer */ 865 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 866 /* GPIO output for GICv3 maintenance interrupt signal */ 867 qemu_irq gicv3_maintenance_interrupt; 868 /* GPIO output for the PMU interrupt */ 869 qemu_irq pmu_interrupt; 870 871 /* MemoryRegion to use for secure physical accesses */ 872 MemoryRegion *secure_memory; 873 874 /* MemoryRegion to use for allocation tag accesses */ 875 MemoryRegion *tag_memory; 876 MemoryRegion *secure_tag_memory; 877 878 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 879 Object *idau; 880 881 /* 'compatible' string for this CPU for Linux device trees */ 882 const char *dtb_compatible; 883 884 /* PSCI version for this CPU 885 * Bits[31:16] = Major Version 886 * Bits[15:0] = Minor Version 887 */ 888 uint32_t psci_version; 889 890 /* Current power state, access guarded by BQL */ 891 ARMPSCIState power_state; 892 893 /* CPU has virtualization extension */ 894 bool has_el2; 895 /* CPU has security extension */ 896 bool has_el3; 897 /* CPU has PMU (Performance Monitor Unit) */ 898 bool has_pmu; 899 /* CPU has VFP */ 900 bool has_vfp; 901 /* CPU has 32 VFP registers */ 902 bool has_vfp_d32; 903 /* CPU has Neon */ 904 bool has_neon; 905 /* CPU has M-profile DSP extension */ 906 bool has_dsp; 907 908 /* CPU has memory protection unit */ 909 bool has_mpu; 910 /* PMSAv7 MPU number of supported regions */ 911 uint32_t pmsav7_dregion; 912 /* PMSAv8 MPU number of supported hyp regions */ 913 uint32_t pmsav8r_hdregion; 914 /* v8M SAU number of supported regions */ 915 uint32_t sau_sregion; 916 917 /* PSCI conduit used to invoke PSCI methods 918 * 0 - disabled, 1 - smc, 2 - hvc 919 */ 920 uint32_t psci_conduit; 921 922 /* For v8M, initial value of the Secure VTOR */ 923 uint32_t init_svtor; 924 /* For v8M, initial value of the Non-secure VTOR */ 925 uint32_t init_nsvtor; 926 927 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 928 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 929 */ 930 uint32_t kvm_target; 931 932 #ifdef CONFIG_KVM 933 /* KVM init features for this CPU */ 934 uint32_t kvm_init_features[7]; 935 936 /* KVM CPU state */ 937 938 /* KVM virtual time adjustment */ 939 bool kvm_adjvtime; 940 bool kvm_vtime_dirty; 941 uint64_t kvm_vtime; 942 943 /* KVM steal time */ 944 OnOffAuto kvm_steal_time; 945 #endif /* CONFIG_KVM */ 946 947 /* Uniprocessor system with MP extensions */ 948 bool mp_is_up; 949 950 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 951 * and the probe failed (so we need to report the error in realize) 952 */ 953 bool host_cpu_probe_failed; 954 955 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 956 * register. 957 */ 958 int32_t core_count; 959 960 /* The instance init functions for implementation-specific subclasses 961 * set these fields to specify the implementation-dependent values of 962 * various constant registers and reset values of non-constant 963 * registers. 964 * Some of these might become QOM properties eventually. 965 * Field names match the official register names as defined in the 966 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 967 * is used for reset values of non-constant registers; no reset_ 968 * prefix means a constant register. 969 * Some of these registers are split out into a substructure that 970 * is shared with the translators to control the ISA. 971 * 972 * Note that if you add an ID register to the ARMISARegisters struct 973 * you need to also update the 32-bit and 64-bit versions of the 974 * kvm_arm_get_host_cpu_features() function to correctly populate the 975 * field by reading the value from the KVM vCPU. 976 */ 977 struct ARMISARegisters { 978 uint32_t id_isar0; 979 uint32_t id_isar1; 980 uint32_t id_isar2; 981 uint32_t id_isar3; 982 uint32_t id_isar4; 983 uint32_t id_isar5; 984 uint32_t id_isar6; 985 uint32_t id_mmfr0; 986 uint32_t id_mmfr1; 987 uint32_t id_mmfr2; 988 uint32_t id_mmfr3; 989 uint32_t id_mmfr4; 990 uint32_t id_mmfr5; 991 uint32_t id_pfr0; 992 uint32_t id_pfr1; 993 uint32_t id_pfr2; 994 uint32_t mvfr0; 995 uint32_t mvfr1; 996 uint32_t mvfr2; 997 uint32_t id_dfr0; 998 uint32_t id_dfr1; 999 uint32_t dbgdidr; 1000 uint32_t dbgdevid; 1001 uint32_t dbgdevid1; 1002 uint64_t id_aa64isar0; 1003 uint64_t id_aa64isar1; 1004 uint64_t id_aa64isar2; 1005 uint64_t id_aa64pfr0; 1006 uint64_t id_aa64pfr1; 1007 uint64_t id_aa64mmfr0; 1008 uint64_t id_aa64mmfr1; 1009 uint64_t id_aa64mmfr2; 1010 uint64_t id_aa64dfr0; 1011 uint64_t id_aa64dfr1; 1012 uint64_t id_aa64zfr0; 1013 uint64_t id_aa64smfr0; 1014 uint64_t reset_pmcr_el0; 1015 } isar; 1016 uint64_t midr; 1017 uint32_t revidr; 1018 uint32_t reset_fpsid; 1019 uint64_t ctr; 1020 uint32_t reset_sctlr; 1021 uint64_t pmceid0; 1022 uint64_t pmceid1; 1023 uint32_t id_afr0; 1024 uint64_t id_aa64afr0; 1025 uint64_t id_aa64afr1; 1026 uint64_t clidr; 1027 uint64_t mp_affinity; /* MP ID without feature bits */ 1028 /* The elements of this array are the CCSIDR values for each cache, 1029 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 1030 */ 1031 uint64_t ccsidr[16]; 1032 uint64_t reset_cbar; 1033 uint32_t reset_auxcr; 1034 bool reset_hivecs; 1035 uint8_t reset_l0gptsz; 1036 1037 /* 1038 * Intermediate values used during property parsing. 1039 * Once finalized, the values should be read from ID_AA64*. 1040 */ 1041 bool prop_pauth; 1042 bool prop_pauth_impdef; 1043 bool prop_pauth_qarma3; 1044 bool prop_lpa2; 1045 1046 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1047 uint8_t dcz_blocksize; 1048 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ 1049 uint8_t gm_blocksize; 1050 1051 uint64_t rvbar_prop; /* Property/input signals. */ 1052 1053 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1054 int gic_num_lrs; /* number of list registers */ 1055 int gic_vpribits; /* number of virtual priority bits */ 1056 int gic_vprebits; /* number of virtual preemption bits */ 1057 int gic_pribits; /* number of physical priority bits */ 1058 1059 /* Whether the cfgend input is high (i.e. this CPU should reset into 1060 * big-endian mode). This setting isn't used directly: instead it modifies 1061 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1062 * architecture version. 1063 */ 1064 bool cfgend; 1065 1066 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1067 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1068 1069 int32_t node_id; /* NUMA node this CPU belongs to */ 1070 1071 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1072 uint8_t device_irq_level; 1073 1074 /* Used to set the maximum vector length the cpu will support. */ 1075 uint32_t sve_max_vq; 1076 1077 #ifdef CONFIG_USER_ONLY 1078 /* Used to set the default vector length at process start. */ 1079 uint32_t sve_default_vq; 1080 uint32_t sme_default_vq; 1081 #endif 1082 1083 ARMVQMap sve_vq; 1084 ARMVQMap sme_vq; 1085 1086 /* Generic timer counter frequency, in Hz */ 1087 uint64_t gt_cntfrq_hz; 1088 }; 1089 1090 typedef struct ARMCPUInfo { 1091 const char *name; 1092 void (*initfn)(Object *obj); 1093 void (*class_init)(ObjectClass *oc, void *data); 1094 } ARMCPUInfo; 1095 1096 /** 1097 * ARMCPUClass: 1098 * @parent_realize: The parent class' realize handler. 1099 * @parent_phases: The parent class' reset phase handlers. 1100 * 1101 * An ARM CPU model. 1102 */ 1103 struct ARMCPUClass { 1104 CPUClass parent_class; 1105 1106 const ARMCPUInfo *info; 1107 DeviceRealize parent_realize; 1108 ResettablePhases parent_phases; 1109 }; 1110 1111 struct AArch64CPUClass { 1112 ARMCPUClass parent_class; 1113 }; 1114 1115 /* Callback functions for the generic timer's timers. */ 1116 void arm_gt_ptimer_cb(void *opaque); 1117 void arm_gt_vtimer_cb(void *opaque); 1118 void arm_gt_htimer_cb(void *opaque); 1119 void arm_gt_stimer_cb(void *opaque); 1120 void arm_gt_hvtimer_cb(void *opaque); 1121 1122 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1123 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); 1124 1125 void arm_cpu_post_init(Object *obj); 1126 1127 #define ARM_AFF0_SHIFT 0 1128 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) 1129 #define ARM_AFF1_SHIFT 8 1130 #define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) 1131 #define ARM_AFF2_SHIFT 16 1132 #define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) 1133 #define ARM_AFF3_SHIFT 32 1134 #define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) 1135 #define ARM_DEFAULT_CPUS_PER_CLUSTER 8 1136 1137 #define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) 1138 #define ARM64_AFFINITY_MASK \ 1139 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) 1140 #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) 1141 1142 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); 1143 1144 #ifndef CONFIG_USER_ONLY 1145 extern const VMStateDescription vmstate_arm_cpu; 1146 1147 void arm_cpu_do_interrupt(CPUState *cpu); 1148 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1149 1150 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1151 MemTxAttrs *attrs); 1152 #endif /* !CONFIG_USER_ONLY */ 1153 1154 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1155 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1156 1157 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1158 int cpuid, DumpState *s); 1159 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1160 int cpuid, DumpState *s); 1161 1162 /** 1163 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling 1164 * @cpu: CPU (which must have been freshly reset) 1165 * @target_el: exception level to put the CPU into 1166 * @secure: whether to put the CPU in secure state 1167 * 1168 * When QEMU is directly running a guest kernel at a lower level than 1169 * EL3 it implicitly emulates some aspects of the guest firmware. 1170 * This includes that on reset we need to configure the parts of the 1171 * CPU corresponding to EL3 so that the real guest code can run at its 1172 * lower exception level. This function does that post-reset CPU setup, 1173 * for when we do direct boot of a guest kernel, and for when we 1174 * emulate PSCI and similar firmware interfaces starting a CPU at a 1175 * lower exception level. 1176 * 1177 * @target_el must be an EL implemented by the CPU between 1 and 3. 1178 * We do not support dropping into a Secure EL other than 3. 1179 * 1180 * It is the responsibility of the caller to call arm_rebuild_hflags(). 1181 */ 1182 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); 1183 1184 #ifdef TARGET_AARCH64 1185 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1186 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1187 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1188 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1189 int new_el, bool el0_a64); 1190 void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); 1191 1192 /* 1193 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1194 * The byte at offset i from the start of the in-memory representation contains 1195 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1196 * lowest offsets are stored in the lowest memory addresses, then that nearly 1197 * matches QEMU's representation, which is to use an array of host-endian 1198 * uint64_t's, where the lower offsets are at the lower indices. To complete 1199 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1200 */ 1201 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1202 { 1203 #if HOST_BIG_ENDIAN 1204 int i; 1205 1206 for (i = 0; i < nr; ++i) { 1207 dst[i] = bswap64(src[i]); 1208 } 1209 1210 return dst; 1211 #else 1212 return src; 1213 #endif 1214 } 1215 1216 #else 1217 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1218 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1219 int n, bool a) 1220 { } 1221 #endif 1222 1223 void aarch64_sync_32_to_64(CPUARMState *env); 1224 void aarch64_sync_64_to_32(CPUARMState *env); 1225 1226 int fp_exception_el(CPUARMState *env, int cur_el); 1227 int sve_exception_el(CPUARMState *env, int cur_el); 1228 int sme_exception_el(CPUARMState *env, int cur_el); 1229 1230 /** 1231 * sve_vqm1_for_el_sm: 1232 * @env: CPUARMState 1233 * @el: exception level 1234 * @sm: streaming mode 1235 * 1236 * Compute the current vector length for @el & @sm, in units of 1237 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1238 * If @sm, compute for SVL, otherwise NVL. 1239 */ 1240 uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm); 1241 1242 /* Likewise, but using @sm = PSTATE.SM. */ 1243 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1244 1245 static inline bool is_a64(CPUARMState *env) 1246 { 1247 return env->aarch64; 1248 } 1249 1250 /** 1251 * pmu_op_start/finish 1252 * @env: CPUARMState 1253 * 1254 * Convert all PMU counters between their delta form (the typical mode when 1255 * they are enabled) and the guest-visible values. These two calls must 1256 * surround any action which might affect the counters. 1257 */ 1258 void pmu_op_start(CPUARMState *env); 1259 void pmu_op_finish(CPUARMState *env); 1260 1261 /* 1262 * Called when a PMU counter is due to overflow 1263 */ 1264 void arm_pmu_timer_cb(void *opaque); 1265 1266 /** 1267 * Functions to register as EL change hooks for PMU mode filtering 1268 */ 1269 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1270 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1271 1272 /* 1273 * pmu_init 1274 * @cpu: ARMCPU 1275 * 1276 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1277 * for the current configuration 1278 */ 1279 void pmu_init(ARMCPU *cpu); 1280 1281 /* SCTLR bit meanings. Several bits have been reused in newer 1282 * versions of the architecture; in that case we define constants 1283 * for both old and new bit meanings. Code which tests against those 1284 * bits should probably check or otherwise arrange that the CPU 1285 * is the architectural version it expects. 1286 */ 1287 #define SCTLR_M (1U << 0) 1288 #define SCTLR_A (1U << 1) 1289 #define SCTLR_C (1U << 2) 1290 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1291 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1292 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1293 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1294 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1295 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1296 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1297 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1298 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1299 #define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */ 1300 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1301 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1302 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1303 #define SCTLR_SED (1U << 8) /* v8 onward */ 1304 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1305 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1306 #define SCTLR_F (1U << 10) /* up to v6 */ 1307 #define SCTLR_SW (1U << 10) /* v7 */ 1308 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1309 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1310 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1311 #define SCTLR_I (1U << 12) 1312 #define SCTLR_V (1U << 13) /* AArch32 only */ 1313 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1314 #define SCTLR_RR (1U << 14) /* up to v7 */ 1315 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1316 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1317 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1318 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1319 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1320 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1321 #define SCTLR_BR (1U << 17) /* PMSA only */ 1322 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1323 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1324 #define SCTLR_WXN (1U << 19) 1325 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1326 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1327 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1328 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1329 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1330 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1331 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1332 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1333 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1334 #define SCTLR_VE (1U << 24) /* up to v7 */ 1335 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1336 #define SCTLR_EE (1U << 25) 1337 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1338 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1339 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1340 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1341 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1342 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1343 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1344 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1345 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1346 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1347 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1348 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1349 #define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ 1350 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1351 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1352 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1353 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1354 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1355 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1356 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1357 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1358 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1359 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1360 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1361 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1362 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1363 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1364 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1365 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1366 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1367 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1368 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1369 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1370 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1371 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1372 1373 #define CPSR_M (0x1fU) 1374 #define CPSR_T (1U << 5) 1375 #define CPSR_F (1U << 6) 1376 #define CPSR_I (1U << 7) 1377 #define CPSR_A (1U << 8) 1378 #define CPSR_E (1U << 9) 1379 #define CPSR_IT_2_7 (0xfc00U) 1380 #define CPSR_GE (0xfU << 16) 1381 #define CPSR_IL (1U << 20) 1382 #define CPSR_DIT (1U << 21) 1383 #define CPSR_PAN (1U << 22) 1384 #define CPSR_SSBS (1U << 23) 1385 #define CPSR_J (1U << 24) 1386 #define CPSR_IT_0_1 (3U << 25) 1387 #define CPSR_Q (1U << 27) 1388 #define CPSR_V (1U << 28) 1389 #define CPSR_C (1U << 29) 1390 #define CPSR_Z (1U << 30) 1391 #define CPSR_N (1U << 31) 1392 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1393 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1394 1395 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1396 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1397 | CPSR_NZCV) 1398 /* Bits writable in user mode. */ 1399 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1400 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1401 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1402 1403 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1404 #define XPSR_EXCP 0x1ffU 1405 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1406 #define XPSR_IT_2_7 CPSR_IT_2_7 1407 #define XPSR_GE CPSR_GE 1408 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1409 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1410 #define XPSR_IT_0_1 CPSR_IT_0_1 1411 #define XPSR_Q CPSR_Q 1412 #define XPSR_V CPSR_V 1413 #define XPSR_C CPSR_C 1414 #define XPSR_Z CPSR_Z 1415 #define XPSR_N CPSR_N 1416 #define XPSR_NZCV CPSR_NZCV 1417 #define XPSR_IT CPSR_IT 1418 1419 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1420 * Only these are valid when in AArch64 mode; in 1421 * AArch32 mode SPSRs are basically CPSR-format. 1422 */ 1423 #define PSTATE_SP (1U) 1424 #define PSTATE_M (0xFU) 1425 #define PSTATE_nRW (1U << 4) 1426 #define PSTATE_F (1U << 6) 1427 #define PSTATE_I (1U << 7) 1428 #define PSTATE_A (1U << 8) 1429 #define PSTATE_D (1U << 9) 1430 #define PSTATE_BTYPE (3U << 10) 1431 #define PSTATE_SSBS (1U << 12) 1432 #define PSTATE_IL (1U << 20) 1433 #define PSTATE_SS (1U << 21) 1434 #define PSTATE_PAN (1U << 22) 1435 #define PSTATE_UAO (1U << 23) 1436 #define PSTATE_DIT (1U << 24) 1437 #define PSTATE_TCO (1U << 25) 1438 #define PSTATE_V (1U << 28) 1439 #define PSTATE_C (1U << 29) 1440 #define PSTATE_Z (1U << 30) 1441 #define PSTATE_N (1U << 31) 1442 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1443 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1444 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1445 /* Mode values for AArch64 */ 1446 #define PSTATE_MODE_EL3h 13 1447 #define PSTATE_MODE_EL3t 12 1448 #define PSTATE_MODE_EL2h 9 1449 #define PSTATE_MODE_EL2t 8 1450 #define PSTATE_MODE_EL1h 5 1451 #define PSTATE_MODE_EL1t 4 1452 #define PSTATE_MODE_EL0t 0 1453 1454 /* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */ 1455 FIELD(SVCR, SM, 0, 1) 1456 FIELD(SVCR, ZA, 1, 1) 1457 1458 /* Fields for SMCR_ELx. */ 1459 FIELD(SMCR, LEN, 0, 4) 1460 FIELD(SMCR, FA64, 31, 1) 1461 1462 /* Write a new value to v7m.exception, thus transitioning into or out 1463 * of Handler mode; this may result in a change of active stack pointer. 1464 */ 1465 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1466 1467 /* Map EL and handler into a PSTATE_MODE. */ 1468 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1469 { 1470 return (el << 2) | handler; 1471 } 1472 1473 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1474 * interprocessing, so we don't attempt to sync with the cpsr state used by 1475 * the 32 bit decoder. 1476 */ 1477 static inline uint32_t pstate_read(CPUARMState *env) 1478 { 1479 int ZF; 1480 1481 ZF = (env->ZF == 0); 1482 return (env->NF & 0x80000000) | (ZF << 30) 1483 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1484 | env->pstate | env->daif | (env->btype << 10); 1485 } 1486 1487 static inline void pstate_write(CPUARMState *env, uint32_t val) 1488 { 1489 env->ZF = (~val) & PSTATE_Z; 1490 env->NF = val; 1491 env->CF = (val >> 29) & 1; 1492 env->VF = (val << 3) & 0x80000000; 1493 env->daif = val & PSTATE_DAIF; 1494 env->btype = (val >> 10) & 3; 1495 env->pstate = val & ~CACHED_PSTATE_BITS; 1496 } 1497 1498 /* Return the current CPSR value. */ 1499 uint32_t cpsr_read(CPUARMState *env); 1500 1501 typedef enum CPSRWriteType { 1502 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1503 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1504 CPSRWriteRaw = 2, 1505 /* trust values, no reg bank switch, no hflags rebuild */ 1506 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1507 } CPSRWriteType; 1508 1509 /* 1510 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1511 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1512 * correspond to TB flags bits cached in the hflags, unless @write_type 1513 * is CPSRWriteRaw. 1514 */ 1515 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1516 CPSRWriteType write_type); 1517 1518 /* Return the current xPSR value. */ 1519 static inline uint32_t xpsr_read(CPUARMState *env) 1520 { 1521 int ZF; 1522 ZF = (env->ZF == 0); 1523 return (env->NF & 0x80000000) | (ZF << 30) 1524 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1525 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1526 | ((env->condexec_bits & 0xfc) << 8) 1527 | (env->GE << 16) 1528 | env->v7m.exception; 1529 } 1530 1531 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1532 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1533 { 1534 if (mask & XPSR_NZCV) { 1535 env->ZF = (~val) & XPSR_Z; 1536 env->NF = val; 1537 env->CF = (val >> 29) & 1; 1538 env->VF = (val << 3) & 0x80000000; 1539 } 1540 if (mask & XPSR_Q) { 1541 env->QF = ((val & XPSR_Q) != 0); 1542 } 1543 if (mask & XPSR_GE) { 1544 env->GE = (val & XPSR_GE) >> 16; 1545 } 1546 #ifndef CONFIG_USER_ONLY 1547 if (mask & XPSR_T) { 1548 env->thumb = ((val & XPSR_T) != 0); 1549 } 1550 if (mask & XPSR_IT_0_1) { 1551 env->condexec_bits &= ~3; 1552 env->condexec_bits |= (val >> 25) & 3; 1553 } 1554 if (mask & XPSR_IT_2_7) { 1555 env->condexec_bits &= 3; 1556 env->condexec_bits |= (val >> 8) & 0xfc; 1557 } 1558 if (mask & XPSR_EXCP) { 1559 /* Note that this only happens on exception exit */ 1560 write_v7m_exception(env, val & XPSR_EXCP); 1561 } 1562 #endif 1563 } 1564 1565 #define HCR_VM (1ULL << 0) 1566 #define HCR_SWIO (1ULL << 1) 1567 #define HCR_PTW (1ULL << 2) 1568 #define HCR_FMO (1ULL << 3) 1569 #define HCR_IMO (1ULL << 4) 1570 #define HCR_AMO (1ULL << 5) 1571 #define HCR_VF (1ULL << 6) 1572 #define HCR_VI (1ULL << 7) 1573 #define HCR_VSE (1ULL << 8) 1574 #define HCR_FB (1ULL << 9) 1575 #define HCR_BSU_MASK (3ULL << 10) 1576 #define HCR_DC (1ULL << 12) 1577 #define HCR_TWI (1ULL << 13) 1578 #define HCR_TWE (1ULL << 14) 1579 #define HCR_TID0 (1ULL << 15) 1580 #define HCR_TID1 (1ULL << 16) 1581 #define HCR_TID2 (1ULL << 17) 1582 #define HCR_TID3 (1ULL << 18) 1583 #define HCR_TSC (1ULL << 19) 1584 #define HCR_TIDCP (1ULL << 20) 1585 #define HCR_TACR (1ULL << 21) 1586 #define HCR_TSW (1ULL << 22) 1587 #define HCR_TPCP (1ULL << 23) 1588 #define HCR_TPU (1ULL << 24) 1589 #define HCR_TTLB (1ULL << 25) 1590 #define HCR_TVM (1ULL << 26) 1591 #define HCR_TGE (1ULL << 27) 1592 #define HCR_TDZ (1ULL << 28) 1593 #define HCR_HCD (1ULL << 29) 1594 #define HCR_TRVM (1ULL << 30) 1595 #define HCR_RW (1ULL << 31) 1596 #define HCR_CD (1ULL << 32) 1597 #define HCR_ID (1ULL << 33) 1598 #define HCR_E2H (1ULL << 34) 1599 #define HCR_TLOR (1ULL << 35) 1600 #define HCR_TERR (1ULL << 36) 1601 #define HCR_TEA (1ULL << 37) 1602 #define HCR_MIOCNCE (1ULL << 38) 1603 #define HCR_TME (1ULL << 39) 1604 #define HCR_APK (1ULL << 40) 1605 #define HCR_API (1ULL << 41) 1606 #define HCR_NV (1ULL << 42) 1607 #define HCR_NV1 (1ULL << 43) 1608 #define HCR_AT (1ULL << 44) 1609 #define HCR_NV2 (1ULL << 45) 1610 #define HCR_FWB (1ULL << 46) 1611 #define HCR_FIEN (1ULL << 47) 1612 #define HCR_GPF (1ULL << 48) 1613 #define HCR_TID4 (1ULL << 49) 1614 #define HCR_TICAB (1ULL << 50) 1615 #define HCR_AMVOFFEN (1ULL << 51) 1616 #define HCR_TOCU (1ULL << 52) 1617 #define HCR_ENSCXT (1ULL << 53) 1618 #define HCR_TTLBIS (1ULL << 54) 1619 #define HCR_TTLBOS (1ULL << 55) 1620 #define HCR_ATA (1ULL << 56) 1621 #define HCR_DCT (1ULL << 57) 1622 #define HCR_TID5 (1ULL << 58) 1623 #define HCR_TWEDEN (1ULL << 59) 1624 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1625 1626 #define SCR_NS (1ULL << 0) 1627 #define SCR_IRQ (1ULL << 1) 1628 #define SCR_FIQ (1ULL << 2) 1629 #define SCR_EA (1ULL << 3) 1630 #define SCR_FW (1ULL << 4) 1631 #define SCR_AW (1ULL << 5) 1632 #define SCR_NET (1ULL << 6) 1633 #define SCR_SMD (1ULL << 7) 1634 #define SCR_HCE (1ULL << 8) 1635 #define SCR_SIF (1ULL << 9) 1636 #define SCR_RW (1ULL << 10) 1637 #define SCR_ST (1ULL << 11) 1638 #define SCR_TWI (1ULL << 12) 1639 #define SCR_TWE (1ULL << 13) 1640 #define SCR_TLOR (1ULL << 14) 1641 #define SCR_TERR (1ULL << 15) 1642 #define SCR_APK (1ULL << 16) 1643 #define SCR_API (1ULL << 17) 1644 #define SCR_EEL2 (1ULL << 18) 1645 #define SCR_EASE (1ULL << 19) 1646 #define SCR_NMEA (1ULL << 20) 1647 #define SCR_FIEN (1ULL << 21) 1648 #define SCR_ENSCXT (1ULL << 25) 1649 #define SCR_ATA (1ULL << 26) 1650 #define SCR_FGTEN (1ULL << 27) 1651 #define SCR_ECVEN (1ULL << 28) 1652 #define SCR_TWEDEN (1ULL << 29) 1653 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1654 #define SCR_TME (1ULL << 34) 1655 #define SCR_AMVOFFEN (1ULL << 35) 1656 #define SCR_ENAS0 (1ULL << 36) 1657 #define SCR_ADEN (1ULL << 37) 1658 #define SCR_HXEN (1ULL << 38) 1659 #define SCR_TRNDR (1ULL << 40) 1660 #define SCR_ENTP2 (1ULL << 41) 1661 #define SCR_GPF (1ULL << 48) 1662 #define SCR_NSE (1ULL << 62) 1663 1664 /* Return the current FPSCR value. */ 1665 uint32_t vfp_get_fpscr(CPUARMState *env); 1666 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1667 1668 /* FPCR, Floating Point Control Register 1669 * FPSR, Floating Poiht Status Register 1670 * 1671 * For A64 the FPSCR is split into two logically distinct registers, 1672 * FPCR and FPSR. However since they still use non-overlapping bits 1673 * we store the underlying state in fpscr and just mask on read/write. 1674 */ 1675 #define FPSR_MASK 0xf800009f 1676 #define FPCR_MASK 0x07ff9f00 1677 1678 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1679 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1680 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1681 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1682 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1683 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1684 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1685 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1686 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1687 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1688 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1689 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1690 #define FPCR_V (1 << 28) /* FP overflow flag */ 1691 #define FPCR_C (1 << 29) /* FP carry flag */ 1692 #define FPCR_Z (1 << 30) /* FP zero flag */ 1693 #define FPCR_N (1 << 31) /* FP negative flag */ 1694 1695 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1696 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1697 #define FPCR_LTPSIZE_LENGTH 3 1698 1699 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1700 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1701 1702 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1703 { 1704 return vfp_get_fpscr(env) & FPSR_MASK; 1705 } 1706 1707 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1708 { 1709 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1710 vfp_set_fpscr(env, new_fpscr); 1711 } 1712 1713 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1714 { 1715 return vfp_get_fpscr(env) & FPCR_MASK; 1716 } 1717 1718 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1719 { 1720 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1721 vfp_set_fpscr(env, new_fpscr); 1722 } 1723 1724 enum arm_cpu_mode { 1725 ARM_CPU_MODE_USR = 0x10, 1726 ARM_CPU_MODE_FIQ = 0x11, 1727 ARM_CPU_MODE_IRQ = 0x12, 1728 ARM_CPU_MODE_SVC = 0x13, 1729 ARM_CPU_MODE_MON = 0x16, 1730 ARM_CPU_MODE_ABT = 0x17, 1731 ARM_CPU_MODE_HYP = 0x1a, 1732 ARM_CPU_MODE_UND = 0x1b, 1733 ARM_CPU_MODE_SYS = 0x1f 1734 }; 1735 1736 /* VFP system registers. */ 1737 #define ARM_VFP_FPSID 0 1738 #define ARM_VFP_FPSCR 1 1739 #define ARM_VFP_MVFR2 5 1740 #define ARM_VFP_MVFR1 6 1741 #define ARM_VFP_MVFR0 7 1742 #define ARM_VFP_FPEXC 8 1743 #define ARM_VFP_FPINST 9 1744 #define ARM_VFP_FPINST2 10 1745 /* These ones are M-profile only */ 1746 #define ARM_VFP_FPSCR_NZCVQC 2 1747 #define ARM_VFP_VPR 12 1748 #define ARM_VFP_P0 13 1749 #define ARM_VFP_FPCXT_NS 14 1750 #define ARM_VFP_FPCXT_S 15 1751 1752 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1753 #define QEMU_VFP_FPSCR_NZCV 0xffff 1754 1755 /* iwMMXt coprocessor control registers. */ 1756 #define ARM_IWMMXT_wCID 0 1757 #define ARM_IWMMXT_wCon 1 1758 #define ARM_IWMMXT_wCSSF 2 1759 #define ARM_IWMMXT_wCASF 3 1760 #define ARM_IWMMXT_wCGR0 8 1761 #define ARM_IWMMXT_wCGR1 9 1762 #define ARM_IWMMXT_wCGR2 10 1763 #define ARM_IWMMXT_wCGR3 11 1764 1765 /* V7M CCR bits */ 1766 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1767 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1768 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1769 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1770 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1771 FIELD(V7M_CCR, STKALIGN, 9, 1) 1772 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1773 FIELD(V7M_CCR, DC, 16, 1) 1774 FIELD(V7M_CCR, IC, 17, 1) 1775 FIELD(V7M_CCR, BP, 18, 1) 1776 FIELD(V7M_CCR, LOB, 19, 1) 1777 FIELD(V7M_CCR, TRD, 20, 1) 1778 1779 /* V7M SCR bits */ 1780 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1781 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1782 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1783 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1784 1785 /* V7M AIRCR bits */ 1786 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1787 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1788 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1789 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1790 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1791 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1792 FIELD(V7M_AIRCR, PRIS, 14, 1) 1793 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1794 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1795 1796 /* V7M CFSR bits for MMFSR */ 1797 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1798 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1799 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1800 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1801 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1802 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1803 1804 /* V7M CFSR bits for BFSR */ 1805 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1806 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1807 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1808 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1809 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1810 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1811 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1812 1813 /* V7M CFSR bits for UFSR */ 1814 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1815 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1816 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1817 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1818 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1819 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1820 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1821 1822 /* V7M CFSR bit masks covering all of the subregister bits */ 1823 FIELD(V7M_CFSR, MMFSR, 0, 8) 1824 FIELD(V7M_CFSR, BFSR, 8, 8) 1825 FIELD(V7M_CFSR, UFSR, 16, 16) 1826 1827 /* V7M HFSR bits */ 1828 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1829 FIELD(V7M_HFSR, FORCED, 30, 1) 1830 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1831 1832 /* V7M DFSR bits */ 1833 FIELD(V7M_DFSR, HALTED, 0, 1) 1834 FIELD(V7M_DFSR, BKPT, 1, 1) 1835 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1836 FIELD(V7M_DFSR, VCATCH, 3, 1) 1837 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1838 1839 /* V7M SFSR bits */ 1840 FIELD(V7M_SFSR, INVEP, 0, 1) 1841 FIELD(V7M_SFSR, INVIS, 1, 1) 1842 FIELD(V7M_SFSR, INVER, 2, 1) 1843 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1844 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1845 FIELD(V7M_SFSR, LSPERR, 5, 1) 1846 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1847 FIELD(V7M_SFSR, LSERR, 7, 1) 1848 1849 /* v7M MPU_CTRL bits */ 1850 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1851 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1852 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1853 1854 /* v7M CLIDR bits */ 1855 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1856 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1857 FIELD(V7M_CLIDR, LOC, 24, 3) 1858 FIELD(V7M_CLIDR, LOUU, 27, 3) 1859 FIELD(V7M_CLIDR, ICB, 30, 2) 1860 1861 FIELD(V7M_CSSELR, IND, 0, 1) 1862 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1863 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1864 * define a mask for this and check that it doesn't permit running off 1865 * the end of the array. 1866 */ 1867 FIELD(V7M_CSSELR, INDEX, 0, 4) 1868 1869 /* v7M FPCCR bits */ 1870 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1871 FIELD(V7M_FPCCR, USER, 1, 1) 1872 FIELD(V7M_FPCCR, S, 2, 1) 1873 FIELD(V7M_FPCCR, THREAD, 3, 1) 1874 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1875 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1876 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1877 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1878 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1879 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1880 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1881 FIELD(V7M_FPCCR, RES0, 11, 15) 1882 FIELD(V7M_FPCCR, TS, 26, 1) 1883 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1884 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1885 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1886 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1887 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1888 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1889 #define R_V7M_FPCCR_BANKED_MASK \ 1890 (R_V7M_FPCCR_LSPACT_MASK | \ 1891 R_V7M_FPCCR_USER_MASK | \ 1892 R_V7M_FPCCR_THREAD_MASK | \ 1893 R_V7M_FPCCR_MMRDY_MASK | \ 1894 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1895 R_V7M_FPCCR_UFRDY_MASK | \ 1896 R_V7M_FPCCR_ASPEN_MASK) 1897 1898 /* v7M VPR bits */ 1899 FIELD(V7M_VPR, P0, 0, 16) 1900 FIELD(V7M_VPR, MASK01, 16, 4) 1901 FIELD(V7M_VPR, MASK23, 20, 4) 1902 1903 /* 1904 * System register ID fields. 1905 */ 1906 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1907 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1908 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1909 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1910 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1911 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1912 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1913 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1914 FIELD(CLIDR_EL1, LOC, 24, 3) 1915 FIELD(CLIDR_EL1, LOUU, 27, 3) 1916 FIELD(CLIDR_EL1, ICB, 30, 3) 1917 1918 /* When FEAT_CCIDX is implemented */ 1919 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1920 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1921 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1922 1923 /* When FEAT_CCIDX is not implemented */ 1924 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1925 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1926 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1927 1928 FIELD(CTR_EL0, IMINLINE, 0, 4) 1929 FIELD(CTR_EL0, L1IP, 14, 2) 1930 FIELD(CTR_EL0, DMINLINE, 16, 4) 1931 FIELD(CTR_EL0, ERG, 20, 4) 1932 FIELD(CTR_EL0, CWG, 24, 4) 1933 FIELD(CTR_EL0, IDC, 28, 1) 1934 FIELD(CTR_EL0, DIC, 29, 1) 1935 FIELD(CTR_EL0, TMINLINE, 32, 6) 1936 1937 FIELD(MIDR_EL1, REVISION, 0, 4) 1938 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1939 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1940 FIELD(MIDR_EL1, VARIANT, 20, 4) 1941 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1942 1943 FIELD(ID_ISAR0, SWAP, 0, 4) 1944 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1945 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1946 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1947 FIELD(ID_ISAR0, COPROC, 16, 4) 1948 FIELD(ID_ISAR0, DEBUG, 20, 4) 1949 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1950 1951 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1952 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1953 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1954 FIELD(ID_ISAR1, EXTEND, 12, 4) 1955 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1956 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1957 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1958 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1959 1960 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1961 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1962 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1963 FIELD(ID_ISAR2, MULT, 12, 4) 1964 FIELD(ID_ISAR2, MULTS, 16, 4) 1965 FIELD(ID_ISAR2, MULTU, 20, 4) 1966 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1967 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1968 1969 FIELD(ID_ISAR3, SATURATE, 0, 4) 1970 FIELD(ID_ISAR3, SIMD, 4, 4) 1971 FIELD(ID_ISAR3, SVC, 8, 4) 1972 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1973 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1974 FIELD(ID_ISAR3, T32COPY, 20, 4) 1975 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1976 FIELD(ID_ISAR3, T32EE, 28, 4) 1977 1978 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1979 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1980 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1981 FIELD(ID_ISAR4, SMC, 12, 4) 1982 FIELD(ID_ISAR4, BARRIER, 16, 4) 1983 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1984 FIELD(ID_ISAR4, PSR_M, 24, 4) 1985 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1986 1987 FIELD(ID_ISAR5, SEVL, 0, 4) 1988 FIELD(ID_ISAR5, AES, 4, 4) 1989 FIELD(ID_ISAR5, SHA1, 8, 4) 1990 FIELD(ID_ISAR5, SHA2, 12, 4) 1991 FIELD(ID_ISAR5, CRC32, 16, 4) 1992 FIELD(ID_ISAR5, RDM, 24, 4) 1993 FIELD(ID_ISAR5, VCMA, 28, 4) 1994 1995 FIELD(ID_ISAR6, JSCVT, 0, 4) 1996 FIELD(ID_ISAR6, DP, 4, 4) 1997 FIELD(ID_ISAR6, FHM, 8, 4) 1998 FIELD(ID_ISAR6, SB, 12, 4) 1999 FIELD(ID_ISAR6, SPECRES, 16, 4) 2000 FIELD(ID_ISAR6, BF16, 20, 4) 2001 FIELD(ID_ISAR6, I8MM, 24, 4) 2002 2003 FIELD(ID_MMFR0, VMSA, 0, 4) 2004 FIELD(ID_MMFR0, PMSA, 4, 4) 2005 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 2006 FIELD(ID_MMFR0, SHARELVL, 12, 4) 2007 FIELD(ID_MMFR0, TCM, 16, 4) 2008 FIELD(ID_MMFR0, AUXREG, 20, 4) 2009 FIELD(ID_MMFR0, FCSE, 24, 4) 2010 FIELD(ID_MMFR0, INNERSHR, 28, 4) 2011 2012 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 2013 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 2014 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 2015 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2016 FIELD(ID_MMFR1, L1HVD, 16, 4) 2017 FIELD(ID_MMFR1, L1UNI, 20, 4) 2018 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2019 FIELD(ID_MMFR1, BPRED, 28, 4) 2020 2021 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2022 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2023 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2024 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2025 FIELD(ID_MMFR2, UNITLB, 16, 4) 2026 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2027 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2028 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2029 2030 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2031 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2032 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2033 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2034 FIELD(ID_MMFR3, PAN, 16, 4) 2035 FIELD(ID_MMFR3, COHWALK, 20, 4) 2036 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2037 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2038 2039 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2040 FIELD(ID_MMFR4, AC2, 4, 4) 2041 FIELD(ID_MMFR4, XNX, 8, 4) 2042 FIELD(ID_MMFR4, CNP, 12, 4) 2043 FIELD(ID_MMFR4, HPDS, 16, 4) 2044 FIELD(ID_MMFR4, LSM, 20, 4) 2045 FIELD(ID_MMFR4, CCIDX, 24, 4) 2046 FIELD(ID_MMFR4, EVT, 28, 4) 2047 2048 FIELD(ID_MMFR5, ETS, 0, 4) 2049 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2050 2051 FIELD(ID_PFR0, STATE0, 0, 4) 2052 FIELD(ID_PFR0, STATE1, 4, 4) 2053 FIELD(ID_PFR0, STATE2, 8, 4) 2054 FIELD(ID_PFR0, STATE3, 12, 4) 2055 FIELD(ID_PFR0, CSV2, 16, 4) 2056 FIELD(ID_PFR0, AMU, 20, 4) 2057 FIELD(ID_PFR0, DIT, 24, 4) 2058 FIELD(ID_PFR0, RAS, 28, 4) 2059 2060 FIELD(ID_PFR1, PROGMOD, 0, 4) 2061 FIELD(ID_PFR1, SECURITY, 4, 4) 2062 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2063 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2064 FIELD(ID_PFR1, GENTIMER, 16, 4) 2065 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2066 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2067 FIELD(ID_PFR1, GIC, 28, 4) 2068 2069 FIELD(ID_PFR2, CSV3, 0, 4) 2070 FIELD(ID_PFR2, SSBS, 4, 4) 2071 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2072 2073 FIELD(ID_AA64ISAR0, AES, 4, 4) 2074 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2075 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2076 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2077 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2078 FIELD(ID_AA64ISAR0, TME, 24, 4) 2079 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2080 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2081 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2082 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2083 FIELD(ID_AA64ISAR0, DP, 44, 4) 2084 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2085 FIELD(ID_AA64ISAR0, TS, 52, 4) 2086 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2087 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2088 2089 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2090 FIELD(ID_AA64ISAR1, APA, 4, 4) 2091 FIELD(ID_AA64ISAR1, API, 8, 4) 2092 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2093 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2094 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2095 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2096 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2097 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2098 FIELD(ID_AA64ISAR1, SB, 36, 4) 2099 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2100 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2101 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2102 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2103 FIELD(ID_AA64ISAR1, XS, 56, 4) 2104 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2105 2106 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2107 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2108 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2109 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2110 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2111 FIELD(ID_AA64ISAR2, BC, 20, 4) 2112 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2113 FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) 2114 FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) 2115 FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) 2116 FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) 2117 FIELD(ID_AA64ISAR2, RPRFM, 48, 4) 2118 FIELD(ID_AA64ISAR2, CSSC, 52, 4) 2119 FIELD(ID_AA64ISAR2, ATS1A, 60, 4) 2120 2121 FIELD(ID_AA64PFR0, EL0, 0, 4) 2122 FIELD(ID_AA64PFR0, EL1, 4, 4) 2123 FIELD(ID_AA64PFR0, EL2, 8, 4) 2124 FIELD(ID_AA64PFR0, EL3, 12, 4) 2125 FIELD(ID_AA64PFR0, FP, 16, 4) 2126 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2127 FIELD(ID_AA64PFR0, GIC, 24, 4) 2128 FIELD(ID_AA64PFR0, RAS, 28, 4) 2129 FIELD(ID_AA64PFR0, SVE, 32, 4) 2130 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2131 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2132 FIELD(ID_AA64PFR0, AMU, 44, 4) 2133 FIELD(ID_AA64PFR0, DIT, 48, 4) 2134 FIELD(ID_AA64PFR0, RME, 52, 4) 2135 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2136 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2137 2138 FIELD(ID_AA64PFR1, BT, 0, 4) 2139 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2140 FIELD(ID_AA64PFR1, MTE, 8, 4) 2141 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2142 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2143 FIELD(ID_AA64PFR1, SME, 24, 4) 2144 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2145 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2146 FIELD(ID_AA64PFR1, NMI, 36, 4) 2147 FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) 2148 FIELD(ID_AA64PFR1, GCS, 44, 4) 2149 FIELD(ID_AA64PFR1, THE, 48, 4) 2150 FIELD(ID_AA64PFR1, MTEX, 52, 4) 2151 FIELD(ID_AA64PFR1, DF2, 56, 4) 2152 FIELD(ID_AA64PFR1, PFAR, 60, 4) 2153 2154 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2155 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2156 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2157 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2158 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2159 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2160 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2161 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2162 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2163 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2164 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2165 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2166 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2167 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2168 2169 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2170 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2171 FIELD(ID_AA64MMFR1, VH, 8, 4) 2172 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2173 FIELD(ID_AA64MMFR1, LO, 16, 4) 2174 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2175 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2176 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2177 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2178 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2179 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2180 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2181 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2182 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2183 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2184 FIELD(ID_AA64MMFR1, ECBHB, 60, 4) 2185 2186 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2187 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2188 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2189 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2190 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2191 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2192 FIELD(ID_AA64MMFR2, NV, 24, 4) 2193 FIELD(ID_AA64MMFR2, ST, 28, 4) 2194 FIELD(ID_AA64MMFR2, AT, 32, 4) 2195 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2196 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2197 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2198 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2199 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2200 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2201 2202 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2203 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2204 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2205 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2206 FIELD(ID_AA64DFR0, PMSS, 16, 4) 2207 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2208 FIELD(ID_AA64DFR0, SEBEP, 24, 4) 2209 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2210 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2211 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2212 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2213 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2214 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2215 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2216 FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) 2217 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2218 2219 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2220 FIELD(ID_AA64ZFR0, AES, 4, 4) 2221 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2222 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2223 FIELD(ID_AA64ZFR0, B16B16, 24, 4) 2224 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2225 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2226 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2227 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2228 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2229 2230 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2231 FIELD(ID_AA64SMFR0, BI32I32, 33, 1) 2232 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2233 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2234 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2235 FIELD(ID_AA64SMFR0, F16F16, 42, 1) 2236 FIELD(ID_AA64SMFR0, B16B16, 43, 1) 2237 FIELD(ID_AA64SMFR0, I16I32, 44, 4) 2238 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2239 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2240 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2241 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2242 2243 FIELD(ID_DFR0, COPDBG, 0, 4) 2244 FIELD(ID_DFR0, COPSDBG, 4, 4) 2245 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2246 FIELD(ID_DFR0, COPTRC, 12, 4) 2247 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2248 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2249 FIELD(ID_DFR0, PERFMON, 24, 4) 2250 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2251 2252 FIELD(ID_DFR1, MTPMU, 0, 4) 2253 FIELD(ID_DFR1, HPMN0, 4, 4) 2254 2255 FIELD(DBGDIDR, SE_IMP, 12, 1) 2256 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2257 FIELD(DBGDIDR, VERSION, 16, 4) 2258 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2259 FIELD(DBGDIDR, BRPS, 24, 4) 2260 FIELD(DBGDIDR, WRPS, 28, 4) 2261 2262 FIELD(DBGDEVID, PCSAMPLE, 0, 4) 2263 FIELD(DBGDEVID, WPADDRMASK, 4, 4) 2264 FIELD(DBGDEVID, BPADDRMASK, 8, 4) 2265 FIELD(DBGDEVID, VECTORCATCH, 12, 4) 2266 FIELD(DBGDEVID, VIRTEXTNS, 16, 4) 2267 FIELD(DBGDEVID, DOUBLELOCK, 20, 4) 2268 FIELD(DBGDEVID, AUXREGS, 24, 4) 2269 FIELD(DBGDEVID, CIDMASK, 28, 4) 2270 2271 FIELD(MVFR0, SIMDREG, 0, 4) 2272 FIELD(MVFR0, FPSP, 4, 4) 2273 FIELD(MVFR0, FPDP, 8, 4) 2274 FIELD(MVFR0, FPTRAP, 12, 4) 2275 FIELD(MVFR0, FPDIVIDE, 16, 4) 2276 FIELD(MVFR0, FPSQRT, 20, 4) 2277 FIELD(MVFR0, FPSHVEC, 24, 4) 2278 FIELD(MVFR0, FPROUND, 28, 4) 2279 2280 FIELD(MVFR1, FPFTZ, 0, 4) 2281 FIELD(MVFR1, FPDNAN, 4, 4) 2282 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2283 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2284 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2285 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2286 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2287 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2288 FIELD(MVFR1, FPHP, 24, 4) 2289 FIELD(MVFR1, SIMDFMAC, 28, 4) 2290 2291 FIELD(MVFR2, SIMDMISC, 0, 4) 2292 FIELD(MVFR2, FPMISC, 4, 4) 2293 2294 FIELD(GPCCR, PPS, 0, 3) 2295 FIELD(GPCCR, IRGN, 8, 2) 2296 FIELD(GPCCR, ORGN, 10, 2) 2297 FIELD(GPCCR, SH, 12, 2) 2298 FIELD(GPCCR, PGS, 14, 2) 2299 FIELD(GPCCR, GPC, 16, 1) 2300 FIELD(GPCCR, GPCP, 17, 1) 2301 FIELD(GPCCR, L0GPTSZ, 20, 4) 2302 2303 FIELD(MFAR, FPA, 12, 40) 2304 FIELD(MFAR, NSE, 62, 1) 2305 FIELD(MFAR, NS, 63, 1) 2306 2307 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2308 2309 /* If adding a feature bit which corresponds to a Linux ELF 2310 * HWCAP bit, remember to update the feature-bit-to-hwcap 2311 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2312 */ 2313 enum arm_features { 2314 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2315 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2316 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2317 ARM_FEATURE_V6, 2318 ARM_FEATURE_V6K, 2319 ARM_FEATURE_V7, 2320 ARM_FEATURE_THUMB2, 2321 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2322 ARM_FEATURE_NEON, 2323 ARM_FEATURE_M, /* Microcontroller profile. */ 2324 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2325 ARM_FEATURE_THUMB2EE, 2326 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2327 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2328 ARM_FEATURE_V4T, 2329 ARM_FEATURE_V5, 2330 ARM_FEATURE_STRONGARM, 2331 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2332 ARM_FEATURE_GENERIC_TIMER, 2333 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2334 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2335 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2336 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2337 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2338 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2339 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2340 ARM_FEATURE_V8, 2341 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2342 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2343 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2344 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2345 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2346 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2347 ARM_FEATURE_PMU, /* has PMU support */ 2348 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2349 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2350 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2351 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2352 }; 2353 2354 static inline int arm_feature(CPUARMState *env, int feature) 2355 { 2356 return (env->features & (1ULL << feature)) != 0; 2357 } 2358 2359 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2360 2361 /* 2362 * ARM v9 security states. 2363 * The ordering of the enumeration corresponds to the low 2 bits 2364 * of the GPI value, and (except for Root) the concat of NSE:NS. 2365 */ 2366 2367 typedef enum ARMSecuritySpace { 2368 ARMSS_Secure = 0, 2369 ARMSS_NonSecure = 1, 2370 ARMSS_Root = 2, 2371 ARMSS_Realm = 3, 2372 } ARMSecuritySpace; 2373 2374 /* Return true if @space is secure, in the pre-v9 sense. */ 2375 static inline bool arm_space_is_secure(ARMSecuritySpace space) 2376 { 2377 return space == ARMSS_Secure || space == ARMSS_Root; 2378 } 2379 2380 /* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ 2381 static inline ARMSecuritySpace arm_secure_to_space(bool secure) 2382 { 2383 return secure ? ARMSS_Secure : ARMSS_NonSecure; 2384 } 2385 2386 #if !defined(CONFIG_USER_ONLY) 2387 /** 2388 * arm_security_space_below_el3: 2389 * @env: cpu context 2390 * 2391 * Return the security space of exception levels below EL3, following 2392 * an exception return to those levels. Unlike arm_security_space, 2393 * this doesn't care about the current EL. 2394 */ 2395 ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); 2396 2397 /** 2398 * arm_is_secure_below_el3: 2399 * @env: cpu context 2400 * 2401 * Return true if exception levels below EL3 are in secure state, 2402 * or would be following an exception return to those levels. 2403 */ 2404 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2405 { 2406 ARMSecuritySpace ss = arm_security_space_below_el3(env); 2407 return ss == ARMSS_Secure; 2408 } 2409 2410 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2411 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2412 { 2413 assert(!arm_feature(env, ARM_FEATURE_M)); 2414 if (arm_feature(env, ARM_FEATURE_EL3)) { 2415 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2416 /* CPU currently in AArch64 state and EL3 */ 2417 return true; 2418 } else if (!is_a64(env) && 2419 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2420 /* CPU currently in AArch32 state and monitor mode */ 2421 return true; 2422 } 2423 } 2424 return false; 2425 } 2426 2427 /** 2428 * arm_security_space: 2429 * @env: cpu context 2430 * 2431 * Return the current security space of the cpu. 2432 */ 2433 ARMSecuritySpace arm_security_space(CPUARMState *env); 2434 2435 /** 2436 * arm_is_secure: 2437 * @env: cpu context 2438 * 2439 * Return true if the processor is in secure state. 2440 */ 2441 static inline bool arm_is_secure(CPUARMState *env) 2442 { 2443 return arm_space_is_secure(arm_security_space(env)); 2444 } 2445 2446 /* 2447 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2448 * This corresponds to the pseudocode EL2Enabled(). 2449 */ 2450 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2451 ARMSecuritySpace space) 2452 { 2453 assert(space != ARMSS_Root); 2454 return arm_feature(env, ARM_FEATURE_EL2) 2455 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); 2456 } 2457 2458 static inline bool arm_is_el2_enabled(CPUARMState *env) 2459 { 2460 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); 2461 } 2462 2463 #else 2464 static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) 2465 { 2466 return ARMSS_NonSecure; 2467 } 2468 2469 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2470 { 2471 return false; 2472 } 2473 2474 static inline ARMSecuritySpace arm_security_space(CPUARMState *env) 2475 { 2476 return ARMSS_NonSecure; 2477 } 2478 2479 static inline bool arm_is_secure(CPUARMState *env) 2480 { 2481 return false; 2482 } 2483 2484 static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, 2485 ARMSecuritySpace space) 2486 { 2487 return false; 2488 } 2489 2490 static inline bool arm_is_el2_enabled(CPUARMState *env) 2491 { 2492 return false; 2493 } 2494 #endif 2495 2496 /** 2497 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2498 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2499 * "for all purposes other than a direct read or write access of HCR_EL2." 2500 * Not included here is HCR_RW. 2501 */ 2502 uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); 2503 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2504 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2505 2506 /* Return true if the specified exception level is running in AArch64 state. */ 2507 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2508 { 2509 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2510 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2511 */ 2512 assert(el >= 1 && el <= 3); 2513 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2514 2515 /* The highest exception level is always at the maximum supported 2516 * register width, and then lower levels have a register width controlled 2517 * by bits in the SCR or HCR registers. 2518 */ 2519 if (el == 3) { 2520 return aa64; 2521 } 2522 2523 if (arm_feature(env, ARM_FEATURE_EL3) && 2524 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2525 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2526 } 2527 2528 if (el == 2) { 2529 return aa64; 2530 } 2531 2532 if (arm_is_el2_enabled(env)) { 2533 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2534 } 2535 2536 return aa64; 2537 } 2538 2539 /* Function for determining whether guest cp register reads and writes should 2540 * access the secure or non-secure bank of a cp register. When EL3 is 2541 * operating in AArch32 state, the NS-bit determines whether the secure 2542 * instance of a cp register should be used. When EL3 is AArch64 (or if 2543 * it doesn't exist at all) then there is no register banking, and all 2544 * accesses are to the non-secure version. 2545 */ 2546 static inline bool access_secure_reg(CPUARMState *env) 2547 { 2548 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2549 !arm_el_is_aa64(env, 3) && 2550 !(env->cp15.scr_el3 & SCR_NS)); 2551 2552 return ret; 2553 } 2554 2555 /* Macros for accessing a specified CP register bank */ 2556 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2557 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2558 2559 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2560 do { \ 2561 if (_secure) { \ 2562 (_env)->cp15._regname##_s = (_val); \ 2563 } else { \ 2564 (_env)->cp15._regname##_ns = (_val); \ 2565 } \ 2566 } while (0) 2567 2568 /* Macros for automatically accessing a specific CP register bank depending on 2569 * the current secure state of the system. These macros are not intended for 2570 * supporting instruction translation reads/writes as these are dependent 2571 * solely on the SCR.NS bit and not the mode. 2572 */ 2573 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2574 A32_BANKED_REG_GET((_env), _regname, \ 2575 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2576 2577 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2578 A32_BANKED_REG_SET((_env), _regname, \ 2579 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2580 (_val)) 2581 2582 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2583 uint32_t cur_el, bool secure); 2584 2585 /* Return the highest implemented Exception Level */ 2586 static inline int arm_highest_el(CPUARMState *env) 2587 { 2588 if (arm_feature(env, ARM_FEATURE_EL3)) { 2589 return 3; 2590 } 2591 if (arm_feature(env, ARM_FEATURE_EL2)) { 2592 return 2; 2593 } 2594 return 1; 2595 } 2596 2597 /* Return true if a v7M CPU is in Handler mode */ 2598 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2599 { 2600 return env->v7m.exception != 0; 2601 } 2602 2603 /* Return the current Exception Level (as per ARMv8; note that this differs 2604 * from the ARMv7 Privilege Level). 2605 */ 2606 static inline int arm_current_el(CPUARMState *env) 2607 { 2608 if (arm_feature(env, ARM_FEATURE_M)) { 2609 return arm_v7m_is_handler_mode(env) || 2610 !(env->v7m.control[env->v7m.secure] & 1); 2611 } 2612 2613 if (is_a64(env)) { 2614 return extract32(env->pstate, 2, 2); 2615 } 2616 2617 switch (env->uncached_cpsr & 0x1f) { 2618 case ARM_CPU_MODE_USR: 2619 return 0; 2620 case ARM_CPU_MODE_HYP: 2621 return 2; 2622 case ARM_CPU_MODE_MON: 2623 return 3; 2624 default: 2625 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2626 /* If EL3 is 32-bit then all secure privileged modes run in 2627 * EL3 2628 */ 2629 return 3; 2630 } 2631 2632 return 1; 2633 } 2634 } 2635 2636 /** 2637 * write_list_to_cpustate 2638 * @cpu: ARMCPU 2639 * 2640 * For each register listed in the ARMCPU cpreg_indexes list, write 2641 * its value from the cpreg_values list into the ARMCPUState structure. 2642 * This updates TCG's working data structures from KVM data or 2643 * from incoming migration state. 2644 * 2645 * Returns: true if all register values were updated correctly, 2646 * false if some register was unknown or could not be written. 2647 * Note that we do not stop early on failure -- we will attempt 2648 * writing all registers in the list. 2649 */ 2650 bool write_list_to_cpustate(ARMCPU *cpu); 2651 2652 /** 2653 * write_cpustate_to_list: 2654 * @cpu: ARMCPU 2655 * @kvm_sync: true if this is for syncing back to KVM 2656 * 2657 * For each register listed in the ARMCPU cpreg_indexes list, write 2658 * its value from the ARMCPUState structure into the cpreg_values list. 2659 * This is used to copy info from TCG's working data structures into 2660 * KVM or for outbound migration. 2661 * 2662 * @kvm_sync is true if we are doing this in order to sync the 2663 * register state back to KVM. In this case we will only update 2664 * values in the list if the previous list->cpustate sync actually 2665 * successfully wrote the CPU state. Otherwise we will keep the value 2666 * that is in the list. 2667 * 2668 * Returns: true if all register values were read correctly, 2669 * false if some register was unknown or could not be read. 2670 * Note that we do not stop early on failure -- we will attempt 2671 * reading all registers in the list. 2672 */ 2673 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2674 2675 #define ARM_CPUID_TI915T 0x54029152 2676 #define ARM_CPUID_TI925T 0x54029252 2677 2678 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2679 2680 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2681 2682 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2683 * 2684 * If EL3 is 64-bit: 2685 * + NonSecure EL1 & 0 stage 1 2686 * + NonSecure EL1 & 0 stage 2 2687 * + NonSecure EL2 2688 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2689 * + Secure EL1 & 0 2690 * + Secure EL3 2691 * If EL3 is 32-bit: 2692 * + NonSecure PL1 & 0 stage 1 2693 * + NonSecure PL1 & 0 stage 2 2694 * + NonSecure PL2 2695 * + Secure PL0 2696 * + Secure PL1 2697 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2698 * 2699 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2700 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2701 * because they may differ in access permissions even if the VA->PA map is 2702 * the same 2703 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2704 * translation, which means that we have one mmu_idx that deals with two 2705 * concatenated translation regimes [this sort of combined s1+2 TLB is 2706 * architecturally permitted] 2707 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2708 * handling via the TLB. The only way to do a stage 1 translation without 2709 * the immediate stage 2 translation is via the ATS or AT system insns, 2710 * which can be slow-pathed and always do a page table walk. 2711 * The only use of stage 2 translations is either as part of an s1+2 2712 * lookup or when loading the descriptors during a stage 1 page table walk, 2713 * and in both those cases we don't use the TLB. 2714 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2715 * translation regimes, because they map reasonably well to each other 2716 * and they can't both be active at the same time. 2717 * 5. we want to be able to use the TLB for accesses done as part of a 2718 * stage1 page table walk, rather than having to walk the stage2 page 2719 * table over and over. 2720 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2721 * Never (PAN) bit within PSTATE. 2722 * 7. we fold together the secure and non-secure regimes for A-profile, 2723 * because there are no banked system registers for aarch64, so the 2724 * process of switching between secure and non-secure is 2725 * already heavyweight. 2726 * 2727 * This gives us the following list of cases: 2728 * 2729 * EL0 EL1&0 stage 1+2 (aka NS PL0) 2730 * EL1 EL1&0 stage 1+2 (aka NS PL1) 2731 * EL1 EL1&0 stage 1+2 +PAN 2732 * EL0 EL2&0 2733 * EL2 EL2&0 2734 * EL2 EL2&0 +PAN 2735 * EL2 (aka NS PL2) 2736 * EL3 (aka S PL1) 2737 * Physical (NS & S) 2738 * Stage2 (NS & S) 2739 * 2740 * for a total of 12 different mmu_idx. 2741 * 2742 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2743 * as A profile. They only need to distinguish EL0 and EL1 (and 2744 * EL2 if we ever model a Cortex-R52). 2745 * 2746 * M profile CPUs are rather different as they do not have a true MMU. 2747 * They have the following different MMU indexes: 2748 * User 2749 * Privileged 2750 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2751 * Privileged, execution priority negative (ditto) 2752 * If the CPU supports the v8M Security Extension then there are also: 2753 * Secure User 2754 * Secure Privileged 2755 * Secure User, execution priority negative 2756 * Secure Privileged, execution priority negative 2757 * 2758 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2759 * are not quite the same -- different CPU types (most notably M profile 2760 * vs A/R profile) would like to use MMU indexes with different semantics, 2761 * but since we don't ever need to use all of those in a single CPU we 2762 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2763 * modes + total number of M profile MMU modes". The lower bits of 2764 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2765 * the same for any particular CPU. 2766 * Variables of type ARMMUIdx are always full values, and the core 2767 * index values are in variables of type 'int'. 2768 * 2769 * Our enumeration includes at the end some entries which are not "true" 2770 * mmu_idx values in that they don't have corresponding TLBs and are only 2771 * valid for doing slow path page table walks. 2772 * 2773 * The constant names here are patterned after the general style of the names 2774 * of the AT/ATS operations. 2775 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2776 * For M profile we arrange them to have a bit for priv, a bit for negpri 2777 * and a bit for secure. 2778 */ 2779 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2780 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2781 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2782 2783 /* Meanings of the bits for M profile mmu idx values */ 2784 #define ARM_MMU_IDX_M_PRIV 0x1 2785 #define ARM_MMU_IDX_M_NEGPRI 0x2 2786 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2787 2788 #define ARM_MMU_IDX_TYPE_MASK \ 2789 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2790 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2791 2792 typedef enum ARMMMUIdx { 2793 /* 2794 * A-profile. 2795 */ 2796 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, 2797 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, 2798 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, 2799 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A, 2800 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A, 2801 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A, 2802 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A, 2803 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A, 2804 2805 /* 2806 * Used for second stage of an S12 page table walk, or for descriptor 2807 * loads during first stage of an S1 page table walk. Note that both 2808 * are in use simultaneously for SecureEL2: the security state for 2809 * the S2 ptw is selected by the NS bit from the S1 ptw. 2810 */ 2811 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A, 2812 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, 2813 2814 /* TLBs with 1-1 mapping to the physical address spaces. */ 2815 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, 2816 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, 2817 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, 2818 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, 2819 2820 /* 2821 * These are not allocated TLBs and are used only for AT system 2822 * instructions or for the first stage of an S12 page table walk. 2823 */ 2824 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2825 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2826 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2827 2828 /* 2829 * M-profile. 2830 */ 2831 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2832 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2833 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2834 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2835 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2836 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2837 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2838 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2839 } ARMMMUIdx; 2840 2841 /* 2842 * Bit macros for the core-mmu-index values for each index, 2843 * for use when calling tlb_flush_by_mmuidx() and friends. 2844 */ 2845 #define TO_CORE_BIT(NAME) \ 2846 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2847 2848 typedef enum ARMMMUIdxBit { 2849 TO_CORE_BIT(E10_0), 2850 TO_CORE_BIT(E20_0), 2851 TO_CORE_BIT(E10_1), 2852 TO_CORE_BIT(E10_1_PAN), 2853 TO_CORE_BIT(E2), 2854 TO_CORE_BIT(E20_2), 2855 TO_CORE_BIT(E20_2_PAN), 2856 TO_CORE_BIT(E3), 2857 TO_CORE_BIT(Stage2), 2858 TO_CORE_BIT(Stage2_S), 2859 2860 TO_CORE_BIT(MUser), 2861 TO_CORE_BIT(MPriv), 2862 TO_CORE_BIT(MUserNegPri), 2863 TO_CORE_BIT(MPrivNegPri), 2864 TO_CORE_BIT(MSUser), 2865 TO_CORE_BIT(MSPriv), 2866 TO_CORE_BIT(MSUserNegPri), 2867 TO_CORE_BIT(MSPrivNegPri), 2868 } ARMMMUIdxBit; 2869 2870 #undef TO_CORE_BIT 2871 2872 #define MMU_USER_IDX 0 2873 2874 /* Indexes used when registering address spaces with cpu_address_space_init */ 2875 typedef enum ARMASIdx { 2876 ARMASIdx_NS = 0, 2877 ARMASIdx_S = 1, 2878 ARMASIdx_TagNS = 2, 2879 ARMASIdx_TagS = 3, 2880 } ARMASIdx; 2881 2882 static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) 2883 { 2884 /* Assert the relative order of the physical mmu indexes. */ 2885 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); 2886 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); 2887 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); 2888 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); 2889 2890 return ARMMMUIdx_Phys_S + space; 2891 } 2892 2893 static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) 2894 { 2895 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); 2896 return idx - ARMMMUIdx_Phys_S; 2897 } 2898 2899 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2900 { 2901 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2902 * CSSELR is RAZ/WI. 2903 */ 2904 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2905 } 2906 2907 static inline bool arm_sctlr_b(CPUARMState *env) 2908 { 2909 return 2910 /* We need not implement SCTLR.ITD in user-mode emulation, so 2911 * let linux-user ignore the fact that it conflicts with SCTLR_B. 2912 * This lets people run BE32 binaries with "-cpu any". 2913 */ 2914 #ifndef CONFIG_USER_ONLY 2915 !arm_feature(env, ARM_FEATURE_V7) && 2916 #endif 2917 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 2918 } 2919 2920 uint64_t arm_sctlr(CPUARMState *env, int el); 2921 2922 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 2923 bool sctlr_b) 2924 { 2925 #ifdef CONFIG_USER_ONLY 2926 /* 2927 * In system mode, BE32 is modelled in line with the 2928 * architecture (as word-invariant big-endianness), where loads 2929 * and stores are done little endian but from addresses which 2930 * are adjusted by XORing with the appropriate constant. So the 2931 * endianness to use for the raw data access is not affected by 2932 * SCTLR.B. 2933 * In user mode, however, we model BE32 as byte-invariant 2934 * big-endianness (because user-only code cannot tell the 2935 * difference), and so we need to use a data access endianness 2936 * that depends on SCTLR.B. 2937 */ 2938 if (sctlr_b) { 2939 return true; 2940 } 2941 #endif 2942 /* In 32bit endianness is determined by looking at CPSR's E bit */ 2943 return env->uncached_cpsr & CPSR_E; 2944 } 2945 2946 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 2947 { 2948 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 2949 } 2950 2951 /* Return true if the processor is in big-endian mode. */ 2952 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 2953 { 2954 if (!is_a64(env)) { 2955 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 2956 } else { 2957 int cur_el = arm_current_el(env); 2958 uint64_t sctlr = arm_sctlr(env, cur_el); 2959 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 2960 } 2961 } 2962 2963 #include "exec/cpu-all.h" 2964 2965 /* 2966 * We have more than 32-bits worth of state per TB, so we split the data 2967 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 2968 * We collect these two parts in CPUARMTBFlags where they are named 2969 * flags and flags2 respectively. 2970 * 2971 * The flags that are shared between all execution modes, TBFLAG_ANY, 2972 * are stored in flags. The flags that are specific to a given mode 2973 * are stores in flags2. Since cs_base is sized on the configured 2974 * address size, flags2 always has 64-bits for A64, and a minimum of 2975 * 32-bits for A32 and M32. 2976 * 2977 * The bits for 32-bit A-profile and M-profile partially overlap: 2978 * 2979 * 31 23 11 10 0 2980 * +-------------+----------+----------------+ 2981 * | | | TBFLAG_A32 | 2982 * | TBFLAG_AM32 | +-----+----------+ 2983 * | | |TBFLAG_M32| 2984 * +-------------+----------------+----------+ 2985 * 31 23 6 5 0 2986 * 2987 * Unless otherwise noted, these bits are cached in env->hflags. 2988 */ 2989 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 2990 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 2991 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 2992 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 2993 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 2994 /* Target EL if we take a floating-point-disabled exception */ 2995 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 2996 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 2997 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 2998 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 2999 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) 3000 FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) 3001 3002 /* 3003 * Bit usage when in AArch32 state, both A- and M-profile. 3004 */ 3005 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3006 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3007 3008 /* 3009 * Bit usage when in AArch32 state, for A-profile only. 3010 */ 3011 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3012 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3013 /* 3014 * We store the bottom two bits of the CPAR as TB flags and handle 3015 * checks on the other bits at runtime. This shares the same bits as 3016 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3017 * Not cached, because VECLEN+VECSTRIDE are not cached. 3018 */ 3019 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3020 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3021 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3022 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3023 /* 3024 * Indicates whether cp register reads and writes by guest code should access 3025 * the secure or nonsecure bank of banked registers; note that this is not 3026 * the same thing as the current security state of the processor! 3027 */ 3028 FIELD(TBFLAG_A32, NS, 10, 1) 3029 /* 3030 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. 3031 * This requires an SME trap from AArch32 mode when using NEON. 3032 */ 3033 FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1) 3034 3035 /* 3036 * Bit usage when in AArch32 state, for M-profile only. 3037 */ 3038 /* Handler (ie not Thread) mode */ 3039 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3040 /* Whether we should generate stack-limit checks */ 3041 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3042 /* Set if FPCCR.LSPACT is set */ 3043 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3044 /* Set if we must create a new FP context */ 3045 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3046 /* Set if FPCCR.S does not match current security state */ 3047 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3048 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3049 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3050 /* Set if in secure mode */ 3051 FIELD(TBFLAG_M32, SECURE, 6, 1) 3052 3053 /* 3054 * Bit usage when in AArch64 state 3055 */ 3056 FIELD(TBFLAG_A64, TBII, 0, 2) 3057 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3058 /* The current vector length, either NVL or SVL. */ 3059 FIELD(TBFLAG_A64, VL, 4, 4) 3060 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3061 FIELD(TBFLAG_A64, BT, 9, 1) 3062 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3063 FIELD(TBFLAG_A64, TBID, 12, 2) 3064 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3065 FIELD(TBFLAG_A64, ATA, 15, 1) 3066 FIELD(TBFLAG_A64, TCMA, 16, 2) 3067 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3068 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3069 FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2) 3070 FIELD(TBFLAG_A64, PSTATE_SM, 22, 1) 3071 FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) 3072 FIELD(TBFLAG_A64, SVL, 24, 4) 3073 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ 3074 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) 3075 FIELD(TBFLAG_A64, TRAP_ERET, 29, 1) 3076 FIELD(TBFLAG_A64, NAA, 30, 1) 3077 FIELD(TBFLAG_A64, ATA0, 31, 1) 3078 FIELD(TBFLAG_A64, NV, 32, 1) 3079 FIELD(TBFLAG_A64, NV1, 33, 1) 3080 FIELD(TBFLAG_A64, NV2, 34, 1) 3081 /* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */ 3082 FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1) 3083 /* Set if FEAT_NV2 RAM accesses are big-endian */ 3084 FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) 3085 3086 /* 3087 * Helpers for using the above. Note that only the A64 accessors use 3088 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags 3089 * word either is or might be 32 bits only. 3090 */ 3091 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3092 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3093 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3094 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3095 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3096 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3097 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3098 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3099 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3100 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3101 3102 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3103 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH) 3104 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3105 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3106 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3107 3108 /** 3109 * sve_vq 3110 * @env: the cpu context 3111 * 3112 * Return the VL cached within env->hflags, in units of quadwords. 3113 */ 3114 static inline int sve_vq(CPUARMState *env) 3115 { 3116 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3117 } 3118 3119 /** 3120 * sme_vq 3121 * @env: the cpu context 3122 * 3123 * Return the SVL cached within env->hflags, in units of quadwords. 3124 */ 3125 static inline int sme_vq(CPUARMState *env) 3126 { 3127 return EX_TBFLAG_A64(env->hflags, SVL) + 1; 3128 } 3129 3130 static inline bool bswap_code(bool sctlr_b) 3131 { 3132 #ifdef CONFIG_USER_ONLY 3133 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3134 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3135 * would also end up as a mixed-endian mode with BE code, LE data. 3136 */ 3137 return TARGET_BIG_ENDIAN ^ sctlr_b; 3138 #else 3139 /* All code access in ARM is little endian, and there are no loaders 3140 * doing swaps that need to be reversed 3141 */ 3142 return 0; 3143 #endif 3144 } 3145 3146 #ifdef CONFIG_USER_ONLY 3147 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3148 { 3149 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env); 3150 } 3151 #endif 3152 3153 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, 3154 uint64_t *cs_base, uint32_t *flags); 3155 3156 enum { 3157 QEMU_PSCI_CONDUIT_DISABLED = 0, 3158 QEMU_PSCI_CONDUIT_SMC = 1, 3159 QEMU_PSCI_CONDUIT_HVC = 2, 3160 }; 3161 3162 #ifndef CONFIG_USER_ONLY 3163 /* Return the address space index to use for a memory access */ 3164 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3165 { 3166 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3167 } 3168 3169 /* Return the AddressSpace to use for a memory access 3170 * (which depends on whether the access is S or NS, and whether 3171 * the board gave us a separate AddressSpace for S accesses). 3172 */ 3173 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3174 { 3175 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3176 } 3177 #endif 3178 3179 /** 3180 * arm_register_pre_el_change_hook: 3181 * Register a hook function which will be called immediately before this 3182 * CPU changes exception level or mode. The hook function will be 3183 * passed a pointer to the ARMCPU and the opaque data pointer passed 3184 * to this function when the hook was registered. 3185 * 3186 * Note that if a pre-change hook is called, any registered post-change hooks 3187 * are guaranteed to subsequently be called. 3188 */ 3189 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3190 void *opaque); 3191 /** 3192 * arm_register_el_change_hook: 3193 * Register a hook function which will be called immediately after this 3194 * CPU changes exception level or mode. The hook function will be 3195 * passed a pointer to the ARMCPU and the opaque data pointer passed 3196 * to this function when the hook was registered. 3197 * 3198 * Note that any registered hooks registered here are guaranteed to be called 3199 * if pre-change hooks have been. 3200 */ 3201 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3202 *opaque); 3203 3204 /** 3205 * arm_rebuild_hflags: 3206 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3207 */ 3208 void arm_rebuild_hflags(CPUARMState *env); 3209 3210 /** 3211 * aa32_vfp_dreg: 3212 * Return a pointer to the Dn register within env in 32-bit mode. 3213 */ 3214 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3215 { 3216 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3217 } 3218 3219 /** 3220 * aa32_vfp_qreg: 3221 * Return a pointer to the Qn register within env in 32-bit mode. 3222 */ 3223 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3224 { 3225 return &env->vfp.zregs[regno].d[0]; 3226 } 3227 3228 /** 3229 * aa64_vfp_qreg: 3230 * Return a pointer to the Qn register within env in 64-bit mode. 3231 */ 3232 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3233 { 3234 return &env->vfp.zregs[regno].d[0]; 3235 } 3236 3237 /* Shared between translate-sve.c and sve_helper.c. */ 3238 extern const uint64_t pred_esz_masks[5]; 3239 3240 /* 3241 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3242 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect 3243 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR. 3244 */ 3245 #define PAGE_BTI PAGE_TARGET_1 3246 #define PAGE_MTE PAGE_TARGET_2 3247 #define PAGE_TARGET_STICKY PAGE_MTE 3248 3249 /* We associate one allocation tag per 16 bytes, the minimum. */ 3250 #define LOG2_TAG_GRANULE 4 3251 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) 3252 3253 #ifdef CONFIG_USER_ONLY 3254 #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) 3255 #endif 3256 3257 #ifdef TARGET_TAGGED_ADDRESSES 3258 /** 3259 * cpu_untagged_addr: 3260 * @cs: CPU context 3261 * @x: tagged address 3262 * 3263 * Remove any address tag from @x. This is explicitly related to the 3264 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3265 * 3266 * There should be a better place to put this, but we need this in 3267 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3268 */ 3269 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3270 { 3271 ARMCPU *cpu = ARM_CPU(cs); 3272 if (cpu->env.tagged_addr_enable) { 3273 /* 3274 * TBI is enabled for userspace but not kernelspace addresses. 3275 * Only clear the tag if bit 55 is clear. 3276 */ 3277 x &= sextract64(x, 0, 56); 3278 } 3279 return x; 3280 } 3281 #endif 3282 3283 #endif 3284