1 /* 2 * ARM virtual CPU header 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef ARM_CPU_H 21 #define ARM_CPU_H 22 23 #include "kvm-consts.h" 24 #include "qemu/cpu-float.h" 25 #include "hw/registerfields.h" 26 #include "cpu-qom.h" 27 #include "exec/cpu-defs.h" 28 #include "qapi/qapi-types-common.h" 29 30 /* ARM processors have a weak memory model */ 31 #define TCG_GUEST_DEFAULT_MO (0) 32 33 #ifdef TARGET_AARCH64 34 #define KVM_HAVE_MCE_INJECTION 1 35 #endif 36 37 #define EXCP_UDEF 1 /* undefined instruction */ 38 #define EXCP_SWI 2 /* software interrupt */ 39 #define EXCP_PREFETCH_ABORT 3 40 #define EXCP_DATA_ABORT 4 41 #define EXCP_IRQ 5 42 #define EXCP_FIQ 6 43 #define EXCP_BKPT 7 44 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ 45 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ 46 #define EXCP_HVC 11 /* HyperVisor Call */ 47 #define EXCP_HYP_TRAP 12 48 #define EXCP_SMC 13 /* Secure Monitor Call */ 49 #define EXCP_VIRQ 14 50 #define EXCP_VFIQ 15 51 #define EXCP_SEMIHOST 16 /* semihosting call */ 52 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ 53 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ 54 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ 55 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ 56 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ 57 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ 58 #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ 59 #define EXCP_VSERR 24 60 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ 61 62 #define ARMV7M_EXCP_RESET 1 63 #define ARMV7M_EXCP_NMI 2 64 #define ARMV7M_EXCP_HARD 3 65 #define ARMV7M_EXCP_MEM 4 66 #define ARMV7M_EXCP_BUS 5 67 #define ARMV7M_EXCP_USAGE 6 68 #define ARMV7M_EXCP_SECURE 7 69 #define ARMV7M_EXCP_SVC 11 70 #define ARMV7M_EXCP_DEBUG 12 71 #define ARMV7M_EXCP_PENDSV 14 72 #define ARMV7M_EXCP_SYSTICK 15 73 74 /* For M profile, some registers are banked secure vs non-secure; 75 * these are represented as a 2-element array where the first element 76 * is the non-secure copy and the second is the secure copy. 77 * When the CPU does not have implement the security extension then 78 * only the first element is used. 79 * This means that the copy for the current security state can be 80 * accessed via env->registerfield[env->v7m.secure] (whether the security 81 * extension is implemented or not). 82 */ 83 enum { 84 M_REG_NS = 0, 85 M_REG_S = 1, 86 M_REG_NUM_BANKS = 2, 87 }; 88 89 /* ARM-specific interrupt pending bits. */ 90 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 91 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 92 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 93 #define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 94 95 /* The usual mapping for an AArch64 system register to its AArch32 96 * counterpart is for the 32 bit world to have access to the lower 97 * half only (with writes leaving the upper half untouched). It's 98 * therefore useful to be able to pass TCG the offset of the least 99 * significant half of a uint64_t struct member. 100 */ 101 #if HOST_BIG_ENDIAN 102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 103 #define offsetofhigh32(S, M) offsetof(S, M) 104 #else 105 #define offsetoflow32(S, M) offsetof(S, M) 106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) 107 #endif 108 109 /* Meanings of the ARMCPU object's four inbound GPIO lines */ 110 #define ARM_CPU_IRQ 0 111 #define ARM_CPU_FIQ 1 112 #define ARM_CPU_VIRQ 2 113 #define ARM_CPU_VFIQ 3 114 115 /* ARM-specific extra insn start words: 116 * 1: Conditional execution bits 117 * 2: Partial exception syndrome for data aborts 118 */ 119 #define TARGET_INSN_START_EXTRA_WORDS 2 120 121 /* The 2nd extra word holding syndrome info for data aborts does not use 122 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to 123 * help the sleb128 encoder do a better job. 124 * When restoring the CPU state, we shift it back up. 125 */ 126 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) 127 #define ARM_INSN_START_WORD2_SHIFT 14 128 129 /* We currently assume float and double are IEEE single and double 130 precision respectively. 131 Doing runtime conversions is tricky because VFP registers may contain 132 integer values (eg. as the result of a FTOSI instruction). 133 s<2n> maps to the least significant half of d<n> 134 s<2n+1> maps to the most significant half of d<n> 135 */ 136 137 /** 138 * DynamicGDBXMLInfo: 139 * @desc: Contains the XML descriptions. 140 * @num: Number of the registers in this XML seen by GDB. 141 * @data: A union with data specific to the set of registers 142 * @cpregs_keys: Array that contains the corresponding Key of 143 * a given cpreg with the same order of the cpreg 144 * in the XML description. 145 */ 146 typedef struct DynamicGDBXMLInfo { 147 char *desc; 148 int num; 149 union { 150 struct { 151 uint32_t *keys; 152 } cpregs; 153 } data; 154 } DynamicGDBXMLInfo; 155 156 /* CPU state for each instance of a generic timer (in cp15 c14) */ 157 typedef struct ARMGenericTimer { 158 uint64_t cval; /* Timer CompareValue register */ 159 uint64_t ctl; /* Timer Control register */ 160 } ARMGenericTimer; 161 162 #define GTIMER_PHYS 0 163 #define GTIMER_VIRT 1 164 #define GTIMER_HYP 2 165 #define GTIMER_SEC 3 166 #define GTIMER_HYPVIRT 4 167 #define NUM_GTIMERS 5 168 169 typedef struct { 170 uint64_t raw_tcr; 171 uint32_t mask; 172 uint32_t base_mask; 173 } TCR; 174 175 #define VTCR_NSW (1u << 29) 176 #define VTCR_NSA (1u << 30) 177 #define VSTCR_SW VTCR_NSW 178 #define VSTCR_SA VTCR_NSA 179 180 /* Define a maximum sized vector register. 181 * For 32-bit, this is a 128-bit NEON/AdvSIMD register. 182 * For 64-bit, this is a 2048-bit SVE register. 183 * 184 * Note that the mapping between S, D, and Q views of the register bank 185 * differs between AArch64 and AArch32. 186 * In AArch32: 187 * Qn = regs[n].d[1]:regs[n].d[0] 188 * Dn = regs[n / 2].d[n & 1] 189 * Sn = regs[n / 4].d[n % 4 / 2], 190 * bits 31..0 for even n, and bits 63..32 for odd n 191 * (and regs[16] to regs[31] are inaccessible) 192 * In AArch64: 193 * Zn = regs[n].d[*] 194 * Qn = regs[n].d[1]:regs[n].d[0] 195 * Dn = regs[n].d[0] 196 * Sn = regs[n].d[0] bits 31..0 197 * Hn = regs[n].d[0] bits 15..0 198 * 199 * This corresponds to the architecturally defined mapping between 200 * the two execution states, and means we do not need to explicitly 201 * map these registers when changing states. 202 * 203 * Align the data for use with TCG host vector operations. 204 */ 205 206 #ifdef TARGET_AARCH64 207 # define ARM_MAX_VQ 16 208 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); 209 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); 210 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); 211 #else 212 # define ARM_MAX_VQ 1 213 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } 214 static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } 215 static inline void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) { } 216 #endif 217 218 typedef struct ARMVectorReg { 219 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); 220 } ARMVectorReg; 221 222 #ifdef TARGET_AARCH64 223 /* In AArch32 mode, predicate registers do not exist at all. */ 224 typedef struct ARMPredicateReg { 225 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); 226 } ARMPredicateReg; 227 228 /* In AArch32 mode, PAC keys do not exist at all. */ 229 typedef struct ARMPACKey { 230 uint64_t lo, hi; 231 } ARMPACKey; 232 #endif 233 234 /* See the commentary above the TBFLAG field definitions. */ 235 typedef struct CPUARMTBFlags { 236 uint32_t flags; 237 target_ulong flags2; 238 } CPUARMTBFlags; 239 240 typedef struct CPUArchState { 241 /* Regs for current mode. */ 242 uint32_t regs[16]; 243 244 /* 32/64 switch only happens when taking and returning from 245 * exceptions so the overlap semantics are taken care of then 246 * instead of having a complicated union. 247 */ 248 /* Regs for A64 mode. */ 249 uint64_t xregs[32]; 250 uint64_t pc; 251 /* PSTATE isn't an architectural register for ARMv8. However, it is 252 * convenient for us to assemble the underlying state into a 32 bit format 253 * identical to the architectural format used for the SPSR. (This is also 254 * what the Linux kernel's 'pstate' field in signal handlers and KVM's 255 * 'pstate' register are.) Of the PSTATE bits: 256 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same 257 * semantics as for AArch32, as described in the comments on each field) 258 * nRW (also known as M[4]) is kept, inverted, in env->aarch64 259 * DAIF (exception masks) are kept in env->daif 260 * BTYPE is kept in env->btype 261 * all other bits are stored in their correct places in env->pstate 262 */ 263 uint32_t pstate; 264 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */ 265 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ 266 267 /* Cached TBFLAGS state. See below for which bits are included. */ 268 CPUARMTBFlags hflags; 269 270 /* Frequently accessed CPSR bits are stored separately for efficiency. 271 This contains all the other bits. Use cpsr_{read,write} to access 272 the whole CPSR. */ 273 uint32_t uncached_cpsr; 274 uint32_t spsr; 275 276 /* Banked registers. */ 277 uint64_t banked_spsr[8]; 278 uint32_t banked_r13[8]; 279 uint32_t banked_r14[8]; 280 281 /* These hold r8-r12. */ 282 uint32_t usr_regs[5]; 283 uint32_t fiq_regs[5]; 284 285 /* cpsr flag cache for faster execution */ 286 uint32_t CF; /* 0 or 1 */ 287 uint32_t VF; /* V is the bit 31. All other bits are undefined */ 288 uint32_t NF; /* N is bit 31. All other bits are undefined. */ 289 uint32_t ZF; /* Z set if zero. */ 290 uint32_t QF; /* 0 or 1 */ 291 uint32_t GE; /* cpsr[19:16] */ 292 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ 293 uint32_t btype; /* BTI branch type. spsr[11:10]. */ 294 uint64_t daif; /* exception masks, in the bits they are in PSTATE */ 295 296 uint64_t elr_el[4]; /* AArch64 exception link regs */ 297 uint64_t sp_el[4]; /* AArch64 banked stack pointers */ 298 299 /* System control coprocessor (cp15) */ 300 struct { 301 uint32_t c0_cpuid; 302 union { /* Cache size selection */ 303 struct { 304 uint64_t _unused_csselr0; 305 uint64_t csselr_ns; 306 uint64_t _unused_csselr1; 307 uint64_t csselr_s; 308 }; 309 uint64_t csselr_el[4]; 310 }; 311 union { /* System control register. */ 312 struct { 313 uint64_t _unused_sctlr; 314 uint64_t sctlr_ns; 315 uint64_t hsctlr; 316 uint64_t sctlr_s; 317 }; 318 uint64_t sctlr_el[4]; 319 }; 320 uint64_t cpacr_el1; /* Architectural feature access control register */ 321 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ 322 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ 323 uint64_t sder; /* Secure debug enable register. */ 324 uint32_t nsacr; /* Non-secure access control register. */ 325 union { /* MMU translation table base 0. */ 326 struct { 327 uint64_t _unused_ttbr0_0; 328 uint64_t ttbr0_ns; 329 uint64_t _unused_ttbr0_1; 330 uint64_t ttbr0_s; 331 }; 332 uint64_t ttbr0_el[4]; 333 }; 334 union { /* MMU translation table base 1. */ 335 struct { 336 uint64_t _unused_ttbr1_0; 337 uint64_t ttbr1_ns; 338 uint64_t _unused_ttbr1_1; 339 uint64_t ttbr1_s; 340 }; 341 uint64_t ttbr1_el[4]; 342 }; 343 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ 344 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ 345 /* MMU translation table base control. */ 346 TCR tcr_el[4]; 347 TCR vtcr_el2; /* Virtualization Translation Control. */ 348 TCR vstcr_el2; /* Secure Virtualization Translation Control. */ 349 uint32_t c2_data; /* MPU data cacheable bits. */ 350 uint32_t c2_insn; /* MPU instruction cacheable bits. */ 351 union { /* MMU domain access control register 352 * MPU write buffer control. 353 */ 354 struct { 355 uint64_t dacr_ns; 356 uint64_t dacr_s; 357 }; 358 struct { 359 uint64_t dacr32_el2; 360 }; 361 }; 362 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ 363 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ 364 uint64_t hcr_el2; /* Hypervisor configuration register */ 365 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ 366 uint64_t scr_el3; /* Secure configuration register. */ 367 union { /* Fault status registers. */ 368 struct { 369 uint64_t ifsr_ns; 370 uint64_t ifsr_s; 371 }; 372 struct { 373 uint64_t ifsr32_el2; 374 }; 375 }; 376 union { 377 struct { 378 uint64_t _unused_dfsr; 379 uint64_t dfsr_ns; 380 uint64_t hsr; 381 uint64_t dfsr_s; 382 }; 383 uint64_t esr_el[4]; 384 }; 385 uint32_t c6_region[8]; /* MPU base/size registers. */ 386 union { /* Fault address registers. */ 387 struct { 388 uint64_t _unused_far0; 389 #if HOST_BIG_ENDIAN 390 uint32_t ifar_ns; 391 uint32_t dfar_ns; 392 uint32_t ifar_s; 393 uint32_t dfar_s; 394 #else 395 uint32_t dfar_ns; 396 uint32_t ifar_ns; 397 uint32_t dfar_s; 398 uint32_t ifar_s; 399 #endif 400 uint64_t _unused_far3; 401 }; 402 uint64_t far_el[4]; 403 }; 404 uint64_t hpfar_el2; 405 uint64_t hstr_el2; 406 union { /* Translation result. */ 407 struct { 408 uint64_t _unused_par_0; 409 uint64_t par_ns; 410 uint64_t _unused_par_1; 411 uint64_t par_s; 412 }; 413 uint64_t par_el[4]; 414 }; 415 416 uint32_t c9_insn; /* Cache lockdown registers. */ 417 uint32_t c9_data; 418 uint64_t c9_pmcr; /* performance monitor control register */ 419 uint64_t c9_pmcnten; /* perf monitor counter enables */ 420 uint64_t c9_pmovsr; /* perf monitor overflow status */ 421 uint64_t c9_pmuserenr; /* perf monitor user enable */ 422 uint64_t c9_pmselr; /* perf monitor counter selection register */ 423 uint64_t c9_pminten; /* perf monitor interrupt enables */ 424 union { /* Memory attribute redirection */ 425 struct { 426 #if HOST_BIG_ENDIAN 427 uint64_t _unused_mair_0; 428 uint32_t mair1_ns; 429 uint32_t mair0_ns; 430 uint64_t _unused_mair_1; 431 uint32_t mair1_s; 432 uint32_t mair0_s; 433 #else 434 uint64_t _unused_mair_0; 435 uint32_t mair0_ns; 436 uint32_t mair1_ns; 437 uint64_t _unused_mair_1; 438 uint32_t mair0_s; 439 uint32_t mair1_s; 440 #endif 441 }; 442 uint64_t mair_el[4]; 443 }; 444 union { /* vector base address register */ 445 struct { 446 uint64_t _unused_vbar; 447 uint64_t vbar_ns; 448 uint64_t hvbar; 449 uint64_t vbar_s; 450 }; 451 uint64_t vbar_el[4]; 452 }; 453 uint32_t mvbar; /* (monitor) vector base address register */ 454 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */ 455 struct { /* FCSE PID. */ 456 uint32_t fcseidr_ns; 457 uint32_t fcseidr_s; 458 }; 459 union { /* Context ID. */ 460 struct { 461 uint64_t _unused_contextidr_0; 462 uint64_t contextidr_ns; 463 uint64_t _unused_contextidr_1; 464 uint64_t contextidr_s; 465 }; 466 uint64_t contextidr_el[4]; 467 }; 468 union { /* User RW Thread register. */ 469 struct { 470 uint64_t tpidrurw_ns; 471 uint64_t tpidrprw_ns; 472 uint64_t htpidr; 473 uint64_t _tpidr_el3; 474 }; 475 uint64_t tpidr_el[4]; 476 }; 477 /* The secure banks of these registers don't map anywhere */ 478 uint64_t tpidrurw_s; 479 uint64_t tpidrprw_s; 480 uint64_t tpidruro_s; 481 482 union { /* User RO Thread register. */ 483 uint64_t tpidruro_ns; 484 uint64_t tpidrro_el[1]; 485 }; 486 uint64_t c14_cntfrq; /* Counter Frequency register */ 487 uint64_t c14_cntkctl; /* Timer Control register */ 488 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ 489 uint64_t cntvoff_el2; /* Counter Virtual Offset register */ 490 ARMGenericTimer c14_timer[NUM_GTIMERS]; 491 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ 492 uint32_t c15_ticonfig; /* TI925T configuration byte. */ 493 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ 494 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ 495 uint32_t c15_threadid; /* TI debugger thread-ID. */ 496 uint32_t c15_config_base_address; /* SCU base address. */ 497 uint32_t c15_diagnostic; /* diagnostic register */ 498 uint32_t c15_power_diagnostic; 499 uint32_t c15_power_control; /* power control */ 500 uint64_t dbgbvr[16]; /* breakpoint value registers */ 501 uint64_t dbgbcr[16]; /* breakpoint control registers */ 502 uint64_t dbgwvr[16]; /* watchpoint value registers */ 503 uint64_t dbgwcr[16]; /* watchpoint control registers */ 504 uint64_t mdscr_el1; 505 uint64_t oslsr_el1; /* OS Lock Status */ 506 uint64_t mdcr_el2; 507 uint64_t mdcr_el3; 508 /* Stores the architectural value of the counter *the last time it was 509 * updated* by pmccntr_op_start. Accesses should always be surrounded 510 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest 511 * architecturally-correct value is being read/set. 512 */ 513 uint64_t c15_ccnt; 514 /* Stores the delta between the architectural value and the underlying 515 * cycle count during normal operation. It is used to update c15_ccnt 516 * to be the correct architectural value before accesses. During 517 * accesses, c15_ccnt_delta contains the underlying count being used 518 * for the access, after which it reverts to the delta value in 519 * pmccntr_op_finish. 520 */ 521 uint64_t c15_ccnt_delta; 522 uint64_t c14_pmevcntr[31]; 523 uint64_t c14_pmevcntr_delta[31]; 524 uint64_t c14_pmevtyper[31]; 525 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ 526 uint64_t vpidr_el2; /* Virtualization Processor ID Register */ 527 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ 528 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ 529 uint64_t gcr_el1; 530 uint64_t rgsr_el1; 531 532 /* Minimal RAS registers */ 533 uint64_t disr_el1; 534 uint64_t vdisr_el2; 535 uint64_t vsesr_el2; 536 } cp15; 537 538 struct { 539 /* M profile has up to 4 stack pointers: 540 * a Main Stack Pointer and a Process Stack Pointer for each 541 * of the Secure and Non-Secure states. (If the CPU doesn't support 542 * the security extension then it has only two SPs.) 543 * In QEMU we always store the currently active SP in regs[13], 544 * and the non-active SP for the current security state in 545 * v7m.other_sp. The stack pointers for the inactive security state 546 * are stored in other_ss_msp and other_ss_psp. 547 * switch_v7m_security_state() is responsible for rearranging them 548 * when we change security state. 549 */ 550 uint32_t other_sp; 551 uint32_t other_ss_msp; 552 uint32_t other_ss_psp; 553 uint32_t vecbase[M_REG_NUM_BANKS]; 554 uint32_t basepri[M_REG_NUM_BANKS]; 555 uint32_t control[M_REG_NUM_BANKS]; 556 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ 557 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ 558 uint32_t hfsr; /* HardFault Status */ 559 uint32_t dfsr; /* Debug Fault Status Register */ 560 uint32_t sfsr; /* Secure Fault Status Register */ 561 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ 562 uint32_t bfar; /* BusFault Address */ 563 uint32_t sfar; /* Secure Fault Address Register */ 564 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ 565 int exception; 566 uint32_t primask[M_REG_NUM_BANKS]; 567 uint32_t faultmask[M_REG_NUM_BANKS]; 568 uint32_t aircr; /* only holds r/w state if security extn implemented */ 569 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ 570 uint32_t csselr[M_REG_NUM_BANKS]; 571 uint32_t scr[M_REG_NUM_BANKS]; 572 uint32_t msplim[M_REG_NUM_BANKS]; 573 uint32_t psplim[M_REG_NUM_BANKS]; 574 uint32_t fpcar[M_REG_NUM_BANKS]; 575 uint32_t fpccr[M_REG_NUM_BANKS]; 576 uint32_t fpdscr[M_REG_NUM_BANKS]; 577 uint32_t cpacr[M_REG_NUM_BANKS]; 578 uint32_t nsacr; 579 uint32_t ltpsize; 580 uint32_t vpr; 581 } v7m; 582 583 /* Information associated with an exception about to be taken: 584 * code which raises an exception must set cs->exception_index and 585 * the relevant parts of this structure; the cpu_do_interrupt function 586 * will then set the guest-visible registers as part of the exception 587 * entry process. 588 */ 589 struct { 590 uint32_t syndrome; /* AArch64 format syndrome register */ 591 uint32_t fsr; /* AArch32 format fault status register info */ 592 uint64_t vaddress; /* virtual addr associated with exception, if any */ 593 uint32_t target_el; /* EL the exception should be targeted for */ 594 /* If we implement EL2 we will also need to store information 595 * about the intermediate physical address for stage 2 faults. 596 */ 597 } exception; 598 599 /* Information associated with an SError */ 600 struct { 601 uint8_t pending; 602 uint8_t has_esr; 603 uint64_t esr; 604 } serror; 605 606 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ 607 608 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ 609 uint32_t irq_line_state; 610 611 /* Thumb-2 EE state. */ 612 uint32_t teecr; 613 uint32_t teehbr; 614 615 /* VFP coprocessor state. */ 616 struct { 617 ARMVectorReg zregs[32]; 618 619 #ifdef TARGET_AARCH64 620 /* Store FFR as pregs[16] to make it easier to treat as any other. */ 621 #define FFR_PRED_NUM 16 622 ARMPredicateReg pregs[17]; 623 /* Scratch space for aa64 sve predicate temporary. */ 624 ARMPredicateReg preg_tmp; 625 #endif 626 627 /* We store these fpcsr fields separately for convenience. */ 628 uint32_t qc[4] QEMU_ALIGNED(16); 629 int vec_len; 630 int vec_stride; 631 632 uint32_t xregs[16]; 633 634 /* Scratch space for aa32 neon expansion. */ 635 uint32_t scratch[8]; 636 637 /* There are a number of distinct float control structures: 638 * 639 * fp_status: is the "normal" fp status. 640 * fp_status_fp16: used for half-precision calculations 641 * standard_fp_status : the ARM "Standard FPSCR Value" 642 * standard_fp_status_fp16 : used for half-precision 643 * calculations with the ARM "Standard FPSCR Value" 644 * 645 * Half-precision operations are governed by a separate 646 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate 647 * status structure to control this. 648 * 649 * The "Standard FPSCR", ie default-NaN, flush-to-zero, 650 * round-to-nearest and is used by any operations (generally 651 * Neon) which the architecture defines as controlled by the 652 * standard FPSCR value rather than the FPSCR. 653 * 654 * The "standard FPSCR but for fp16 ops" is needed because 655 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than 656 * using a fixed value for it. 657 * 658 * To avoid having to transfer exception bits around, we simply 659 * say that the FPSCR cumulative exception flags are the logical 660 * OR of the flags in the four fp statuses. This relies on the 661 * only thing which needs to read the exception flags being 662 * an explicit FPSCR read. 663 */ 664 float_status fp_status; 665 float_status fp_status_f16; 666 float_status standard_fp_status; 667 float_status standard_fp_status_f16; 668 669 /* ZCR_EL[1-3] */ 670 uint64_t zcr_el[4]; 671 } vfp; 672 uint64_t exclusive_addr; 673 uint64_t exclusive_val; 674 uint64_t exclusive_high; 675 676 /* iwMMXt coprocessor state. */ 677 struct { 678 uint64_t regs[16]; 679 uint64_t val; 680 681 uint32_t cregs[16]; 682 } iwmmxt; 683 684 #ifdef TARGET_AARCH64 685 struct { 686 ARMPACKey apia; 687 ARMPACKey apib; 688 ARMPACKey apda; 689 ARMPACKey apdb; 690 ARMPACKey apga; 691 } keys; 692 693 uint64_t scxtnum_el[4]; 694 #endif 695 696 #if defined(CONFIG_USER_ONLY) 697 /* For usermode syscall translation. */ 698 int eabi; 699 #endif 700 701 struct CPUBreakpoint *cpu_breakpoint[16]; 702 struct CPUWatchpoint *cpu_watchpoint[16]; 703 704 /* Fields up to this point are cleared by a CPU reset */ 705 struct {} end_reset_fields; 706 707 /* Fields after this point are preserved across CPU reset. */ 708 709 /* Internal CPU feature flags. */ 710 uint64_t features; 711 712 /* PMSAv7 MPU */ 713 struct { 714 uint32_t *drbar; 715 uint32_t *drsr; 716 uint32_t *dracr; 717 uint32_t rnr[M_REG_NUM_BANKS]; 718 } pmsav7; 719 720 /* PMSAv8 MPU */ 721 struct { 722 /* The PMSAv8 implementation also shares some PMSAv7 config 723 * and state: 724 * pmsav7.rnr (region number register) 725 * pmsav7_dregion (number of configured regions) 726 */ 727 uint32_t *rbar[M_REG_NUM_BANKS]; 728 uint32_t *rlar[M_REG_NUM_BANKS]; 729 uint32_t mair0[M_REG_NUM_BANKS]; 730 uint32_t mair1[M_REG_NUM_BANKS]; 731 } pmsav8; 732 733 /* v8M SAU */ 734 struct { 735 uint32_t *rbar; 736 uint32_t *rlar; 737 uint32_t rnr; 738 uint32_t ctrl; 739 } sau; 740 741 void *nvic; 742 const struct arm_boot_info *boot_info; 743 /* Store GICv3CPUState to access from this struct */ 744 void *gicv3state; 745 746 #ifdef TARGET_TAGGED_ADDRESSES 747 /* Linux syscall tagged address support */ 748 bool tagged_addr_enable; 749 #endif 750 } CPUARMState; 751 752 static inline void set_feature(CPUARMState *env, int feature) 753 { 754 env->features |= 1ULL << feature; 755 } 756 757 static inline void unset_feature(CPUARMState *env, int feature) 758 { 759 env->features &= ~(1ULL << feature); 760 } 761 762 /** 763 * ARMELChangeHookFn: 764 * type of a function which can be registered via arm_register_el_change_hook() 765 * to get callbacks when the CPU changes its exception level or mode. 766 */ 767 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); 768 typedef struct ARMELChangeHook ARMELChangeHook; 769 struct ARMELChangeHook { 770 ARMELChangeHookFn *hook; 771 void *opaque; 772 QLIST_ENTRY(ARMELChangeHook) node; 773 }; 774 775 /* These values map onto the return values for 776 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ 777 typedef enum ARMPSCIState { 778 PSCI_ON = 0, 779 PSCI_OFF = 1, 780 PSCI_ON_PENDING = 2 781 } ARMPSCIState; 782 783 typedef struct ARMISARegisters ARMISARegisters; 784 785 /** 786 * ARMCPU: 787 * @env: #CPUARMState 788 * 789 * An ARM CPU core. 790 */ 791 struct ArchCPU { 792 /*< private >*/ 793 CPUState parent_obj; 794 /*< public >*/ 795 796 CPUNegativeOffsetState neg; 797 CPUARMState env; 798 799 /* Coprocessor information */ 800 GHashTable *cp_regs; 801 /* For marshalling (mostly coprocessor) register state between the 802 * kernel and QEMU (for KVM) and between two QEMUs (for migration), 803 * we use these arrays. 804 */ 805 /* List of register indexes managed via these arrays; (full KVM style 806 * 64 bit indexes, not CPRegInfo 32 bit indexes) 807 */ 808 uint64_t *cpreg_indexes; 809 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ 810 uint64_t *cpreg_values; 811 /* Length of the indexes, values, reset_values arrays */ 812 int32_t cpreg_array_len; 813 /* These are used only for migration: incoming data arrives in 814 * these fields and is sanity checked in post_load before copying 815 * to the working data structures above. 816 */ 817 uint64_t *cpreg_vmstate_indexes; 818 uint64_t *cpreg_vmstate_values; 819 int32_t cpreg_vmstate_array_len; 820 821 DynamicGDBXMLInfo dyn_sysreg_xml; 822 DynamicGDBXMLInfo dyn_svereg_xml; 823 824 /* Timers used by the generic (architected) timer */ 825 QEMUTimer *gt_timer[NUM_GTIMERS]; 826 /* 827 * Timer used by the PMU. Its state is restored after migration by 828 * pmu_op_finish() - it does not need other handling during migration 829 */ 830 QEMUTimer *pmu_timer; 831 /* GPIO outputs for generic timer */ 832 qemu_irq gt_timer_outputs[NUM_GTIMERS]; 833 /* GPIO output for GICv3 maintenance interrupt signal */ 834 qemu_irq gicv3_maintenance_interrupt; 835 /* GPIO output for the PMU interrupt */ 836 qemu_irq pmu_interrupt; 837 838 /* MemoryRegion to use for secure physical accesses */ 839 MemoryRegion *secure_memory; 840 841 /* MemoryRegion to use for allocation tag accesses */ 842 MemoryRegion *tag_memory; 843 MemoryRegion *secure_tag_memory; 844 845 /* For v8M, pointer to the IDAU interface provided by board/SoC */ 846 Object *idau; 847 848 /* 'compatible' string for this CPU for Linux device trees */ 849 const char *dtb_compatible; 850 851 /* PSCI version for this CPU 852 * Bits[31:16] = Major Version 853 * Bits[15:0] = Minor Version 854 */ 855 uint32_t psci_version; 856 857 /* Current power state, access guarded by BQL */ 858 ARMPSCIState power_state; 859 860 /* CPU has virtualization extension */ 861 bool has_el2; 862 /* CPU has security extension */ 863 bool has_el3; 864 /* CPU has PMU (Performance Monitor Unit) */ 865 bool has_pmu; 866 /* CPU has VFP */ 867 bool has_vfp; 868 /* CPU has Neon */ 869 bool has_neon; 870 /* CPU has M-profile DSP extension */ 871 bool has_dsp; 872 873 /* CPU has memory protection unit */ 874 bool has_mpu; 875 /* PMSAv7 MPU number of supported regions */ 876 uint32_t pmsav7_dregion; 877 /* v8M SAU number of supported regions */ 878 uint32_t sau_sregion; 879 880 /* PSCI conduit used to invoke PSCI methods 881 * 0 - disabled, 1 - smc, 2 - hvc 882 */ 883 uint32_t psci_conduit; 884 885 /* For v8M, initial value of the Secure VTOR */ 886 uint32_t init_svtor; 887 /* For v8M, initial value of the Non-secure VTOR */ 888 uint32_t init_nsvtor; 889 890 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or 891 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. 892 */ 893 uint32_t kvm_target; 894 895 /* KVM init features for this CPU */ 896 uint32_t kvm_init_features[7]; 897 898 /* KVM CPU state */ 899 900 /* KVM virtual time adjustment */ 901 bool kvm_adjvtime; 902 bool kvm_vtime_dirty; 903 uint64_t kvm_vtime; 904 905 /* KVM steal time */ 906 OnOffAuto kvm_steal_time; 907 908 /* Uniprocessor system with MP extensions */ 909 bool mp_is_up; 910 911 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init 912 * and the probe failed (so we need to report the error in realize) 913 */ 914 bool host_cpu_probe_failed; 915 916 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR 917 * register. 918 */ 919 int32_t core_count; 920 921 /* The instance init functions for implementation-specific subclasses 922 * set these fields to specify the implementation-dependent values of 923 * various constant registers and reset values of non-constant 924 * registers. 925 * Some of these might become QOM properties eventually. 926 * Field names match the official register names as defined in the 927 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix 928 * is used for reset values of non-constant registers; no reset_ 929 * prefix means a constant register. 930 * Some of these registers are split out into a substructure that 931 * is shared with the translators to control the ISA. 932 * 933 * Note that if you add an ID register to the ARMISARegisters struct 934 * you need to also update the 32-bit and 64-bit versions of the 935 * kvm_arm_get_host_cpu_features() function to correctly populate the 936 * field by reading the value from the KVM vCPU. 937 */ 938 struct ARMISARegisters { 939 uint32_t id_isar0; 940 uint32_t id_isar1; 941 uint32_t id_isar2; 942 uint32_t id_isar3; 943 uint32_t id_isar4; 944 uint32_t id_isar5; 945 uint32_t id_isar6; 946 uint32_t id_mmfr0; 947 uint32_t id_mmfr1; 948 uint32_t id_mmfr2; 949 uint32_t id_mmfr3; 950 uint32_t id_mmfr4; 951 uint32_t id_pfr0; 952 uint32_t id_pfr1; 953 uint32_t id_pfr2; 954 uint32_t mvfr0; 955 uint32_t mvfr1; 956 uint32_t mvfr2; 957 uint32_t id_dfr0; 958 uint32_t dbgdidr; 959 uint64_t id_aa64isar0; 960 uint64_t id_aa64isar1; 961 uint64_t id_aa64pfr0; 962 uint64_t id_aa64pfr1; 963 uint64_t id_aa64mmfr0; 964 uint64_t id_aa64mmfr1; 965 uint64_t id_aa64mmfr2; 966 uint64_t id_aa64dfr0; 967 uint64_t id_aa64dfr1; 968 uint64_t id_aa64zfr0; 969 uint64_t id_aa64smfr0; 970 uint64_t reset_pmcr_el0; 971 } isar; 972 uint64_t midr; 973 uint32_t revidr; 974 uint32_t reset_fpsid; 975 uint64_t ctr; 976 uint32_t reset_sctlr; 977 uint64_t pmceid0; 978 uint64_t pmceid1; 979 uint32_t id_afr0; 980 uint64_t id_aa64afr0; 981 uint64_t id_aa64afr1; 982 uint64_t clidr; 983 uint64_t mp_affinity; /* MP ID without feature bits */ 984 /* The elements of this array are the CCSIDR values for each cache, 985 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. 986 */ 987 uint64_t ccsidr[16]; 988 uint64_t reset_cbar; 989 uint32_t reset_auxcr; 990 bool reset_hivecs; 991 992 /* 993 * Intermediate values used during property parsing. 994 * Once finalized, the values should be read from ID_AA64*. 995 */ 996 bool prop_pauth; 997 bool prop_pauth_impdef; 998 bool prop_lpa2; 999 1000 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ 1001 uint32_t dcz_blocksize; 1002 uint64_t rvbar_prop; /* Property/input signals. */ 1003 1004 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ 1005 int gic_num_lrs; /* number of list registers */ 1006 int gic_vpribits; /* number of virtual priority bits */ 1007 int gic_vprebits; /* number of virtual preemption bits */ 1008 int gic_pribits; /* number of physical priority bits */ 1009 1010 /* Whether the cfgend input is high (i.e. this CPU should reset into 1011 * big-endian mode). This setting isn't used directly: instead it modifies 1012 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the 1013 * architecture version. 1014 */ 1015 bool cfgend; 1016 1017 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; 1018 QLIST_HEAD(, ARMELChangeHook) el_change_hooks; 1019 1020 int32_t node_id; /* NUMA node this CPU belongs to */ 1021 1022 /* Used to synchronize KVM and QEMU in-kernel device levels */ 1023 uint8_t device_irq_level; 1024 1025 /* Used to set the maximum vector length the cpu will support. */ 1026 uint32_t sve_max_vq; 1027 1028 #ifdef CONFIG_USER_ONLY 1029 /* Used to set the default vector length at process start. */ 1030 uint32_t sve_default_vq; 1031 #endif 1032 1033 /* 1034 * In sve_vq_map each set bit is a supported vector length of 1035 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector 1036 * length in quadwords. 1037 * 1038 * While processing properties during initialization, corresponding 1039 * sve_vq_init bits are set for bits in sve_vq_map that have been 1040 * set by properties. 1041 * 1042 * Bits set in sve_vq_supported represent valid vector lengths for 1043 * the CPU type. 1044 */ 1045 uint32_t sve_vq_map; 1046 uint32_t sve_vq_init; 1047 uint32_t sve_vq_supported; 1048 1049 /* Generic timer counter frequency, in Hz */ 1050 uint64_t gt_cntfrq_hz; 1051 }; 1052 1053 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); 1054 1055 void arm_cpu_post_init(Object *obj); 1056 1057 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); 1058 1059 #ifndef CONFIG_USER_ONLY 1060 extern const VMStateDescription vmstate_arm_cpu; 1061 1062 void arm_cpu_do_interrupt(CPUState *cpu); 1063 void arm_v7m_cpu_do_interrupt(CPUState *cpu); 1064 #endif /* !CONFIG_USER_ONLY */ 1065 1066 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 1067 MemTxAttrs *attrs); 1068 1069 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1070 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1071 1072 /* 1073 * Helpers to dynamically generates XML descriptions of the sysregs 1074 * and SVE registers. Returns the number of registers in each set. 1075 */ 1076 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); 1077 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); 1078 1079 /* Returns the dynamically generated XML for the gdb stub. 1080 * Returns a pointer to the XML contents for the specified XML file or NULL 1081 * if the XML name doesn't match the predefined one. 1082 */ 1083 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); 1084 1085 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1086 int cpuid, void *opaque); 1087 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1088 int cpuid, void *opaque); 1089 1090 #ifdef TARGET_AARCH64 1091 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 1092 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1093 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); 1094 void aarch64_sve_change_el(CPUARMState *env, int old_el, 1095 int new_el, bool el0_a64); 1096 void aarch64_add_sve_properties(Object *obj); 1097 void aarch64_add_pauth_properties(Object *obj); 1098 1099 /* 1100 * SVE registers are encoded in KVM's memory in an endianness-invariant format. 1101 * The byte at offset i from the start of the in-memory representation contains 1102 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the 1103 * lowest offsets are stored in the lowest memory addresses, then that nearly 1104 * matches QEMU's representation, which is to use an array of host-endian 1105 * uint64_t's, where the lower offsets are at the lower indices. To complete 1106 * the translation we just need to byte swap the uint64_t's on big-endian hosts. 1107 */ 1108 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) 1109 { 1110 #if HOST_BIG_ENDIAN 1111 int i; 1112 1113 for (i = 0; i < nr; ++i) { 1114 dst[i] = bswap64(src[i]); 1115 } 1116 1117 return dst; 1118 #else 1119 return src; 1120 #endif 1121 } 1122 1123 #else 1124 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } 1125 static inline void aarch64_sve_change_el(CPUARMState *env, int o, 1126 int n, bool a) 1127 { } 1128 static inline void aarch64_add_sve_properties(Object *obj) { } 1129 #endif 1130 1131 void aarch64_sync_32_to_64(CPUARMState *env); 1132 void aarch64_sync_64_to_32(CPUARMState *env); 1133 1134 int fp_exception_el(CPUARMState *env, int cur_el); 1135 int sve_exception_el(CPUARMState *env, int cur_el); 1136 1137 /** 1138 * sve_vqm1_for_el: 1139 * @env: CPUARMState 1140 * @el: exception level 1141 * 1142 * Compute the current SVE vector length for @el, in units of 1143 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN. 1144 */ 1145 uint32_t sve_vqm1_for_el(CPUARMState *env, int el); 1146 1147 static inline bool is_a64(CPUARMState *env) 1148 { 1149 return env->aarch64; 1150 } 1151 1152 /** 1153 * pmu_op_start/finish 1154 * @env: CPUARMState 1155 * 1156 * Convert all PMU counters between their delta form (the typical mode when 1157 * they are enabled) and the guest-visible values. These two calls must 1158 * surround any action which might affect the counters. 1159 */ 1160 void pmu_op_start(CPUARMState *env); 1161 void pmu_op_finish(CPUARMState *env); 1162 1163 /* 1164 * Called when a PMU counter is due to overflow 1165 */ 1166 void arm_pmu_timer_cb(void *opaque); 1167 1168 /** 1169 * Functions to register as EL change hooks for PMU mode filtering 1170 */ 1171 void pmu_pre_el_change(ARMCPU *cpu, void *ignored); 1172 void pmu_post_el_change(ARMCPU *cpu, void *ignored); 1173 1174 /* 1175 * pmu_init 1176 * @cpu: ARMCPU 1177 * 1178 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state 1179 * for the current configuration 1180 */ 1181 void pmu_init(ARMCPU *cpu); 1182 1183 /* SCTLR bit meanings. Several bits have been reused in newer 1184 * versions of the architecture; in that case we define constants 1185 * for both old and new bit meanings. Code which tests against those 1186 * bits should probably check or otherwise arrange that the CPU 1187 * is the architectural version it expects. 1188 */ 1189 #define SCTLR_M (1U << 0) 1190 #define SCTLR_A (1U << 1) 1191 #define SCTLR_C (1U << 2) 1192 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ 1193 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ 1194 #define SCTLR_SA (1U << 3) /* AArch64 only */ 1195 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ 1196 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ 1197 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ 1198 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ 1199 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ 1200 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ 1201 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ 1202 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ 1203 #define SCTLR_ITD (1U << 7) /* v8 onward */ 1204 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ 1205 #define SCTLR_SED (1U << 8) /* v8 onward */ 1206 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ 1207 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ 1208 #define SCTLR_F (1U << 10) /* up to v6 */ 1209 #define SCTLR_SW (1U << 10) /* v7 */ 1210 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ 1211 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ 1212 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ 1213 #define SCTLR_I (1U << 12) 1214 #define SCTLR_V (1U << 13) /* AArch32 only */ 1215 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ 1216 #define SCTLR_RR (1U << 14) /* up to v7 */ 1217 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ 1218 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ 1219 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ 1220 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ 1221 #define SCTLR_nTWI (1U << 16) /* v8 onward */ 1222 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ 1223 #define SCTLR_BR (1U << 17) /* PMSA only */ 1224 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ 1225 #define SCTLR_nTWE (1U << 18) /* v8 onward */ 1226 #define SCTLR_WXN (1U << 19) 1227 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ 1228 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ 1229 #define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ 1230 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ 1231 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ 1232 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ 1233 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ 1234 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ 1235 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ 1236 #define SCTLR_VE (1U << 24) /* up to v7 */ 1237 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ 1238 #define SCTLR_EE (1U << 25) 1239 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ 1240 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ 1241 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ 1242 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ 1243 #define SCTLR_TRE (1U << 28) /* AArch32 only */ 1244 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ 1245 #define SCTLR_AFE (1U << 29) /* AArch32 only */ 1246 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ 1247 #define SCTLR_TE (1U << 30) /* AArch32 only */ 1248 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ 1249 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ 1250 #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ 1251 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ 1252 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ 1253 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ 1254 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ 1255 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ 1256 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ 1257 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ 1258 #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ 1259 #define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ 1260 #define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ 1261 #define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ 1262 #define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ 1263 #define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ 1264 #define SCTLR_TME (1ULL << 53) /* FEAT_TME */ 1265 #define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ 1266 #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ 1267 #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ 1268 #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ 1269 #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ 1270 #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ 1271 #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ 1272 #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ 1273 1274 /* Bit definitions for CPACR (AArch32 only) */ 1275 FIELD(CPACR, CP10, 20, 2) 1276 FIELD(CPACR, CP11, 22, 2) 1277 FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ 1278 FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ 1279 FIELD(CPACR, ASEDIS, 31, 1) 1280 1281 /* Bit definitions for CPACR_EL1 (AArch64 only) */ 1282 FIELD(CPACR_EL1, ZEN, 16, 2) 1283 FIELD(CPACR_EL1, FPEN, 20, 2) 1284 FIELD(CPACR_EL1, SMEN, 24, 2) 1285 FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ 1286 1287 /* Bit definitions for HCPTR (AArch32 only) */ 1288 FIELD(HCPTR, TCP10, 10, 1) 1289 FIELD(HCPTR, TCP11, 11, 1) 1290 FIELD(HCPTR, TASE, 15, 1) 1291 FIELD(HCPTR, TTA, 20, 1) 1292 FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ 1293 FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ 1294 1295 /* Bit definitions for CPTR_EL2 (AArch64 only) */ 1296 FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ 1297 FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ 1298 FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ 1299 FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ 1300 FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ 1301 FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ 1302 FIELD(CPTR_EL2, TTA, 28, 1) 1303 FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ 1304 FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ 1305 1306 /* Bit definitions for CPTR_EL3 (AArch64 only) */ 1307 FIELD(CPTR_EL3, EZ, 8, 1) 1308 FIELD(CPTR_EL3, TFP, 10, 1) 1309 FIELD(CPTR_EL3, ESM, 12, 1) 1310 FIELD(CPTR_EL3, TTA, 20, 1) 1311 FIELD(CPTR_EL3, TAM, 30, 1) 1312 FIELD(CPTR_EL3, TCPAC, 31, 1) 1313 1314 #define MDCR_EPMAD (1U << 21) 1315 #define MDCR_EDAD (1U << 20) 1316 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ 1317 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ 1318 #define MDCR_SDD (1U << 16) 1319 #define MDCR_SPD (3U << 14) 1320 #define MDCR_TDRA (1U << 11) 1321 #define MDCR_TDOSA (1U << 10) 1322 #define MDCR_TDA (1U << 9) 1323 #define MDCR_TDE (1U << 8) 1324 #define MDCR_HPME (1U << 7) 1325 #define MDCR_TPM (1U << 6) 1326 #define MDCR_TPMCR (1U << 5) 1327 #define MDCR_HPMN (0x1fU) 1328 1329 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ 1330 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) 1331 1332 #define CPSR_M (0x1fU) 1333 #define CPSR_T (1U << 5) 1334 #define CPSR_F (1U << 6) 1335 #define CPSR_I (1U << 7) 1336 #define CPSR_A (1U << 8) 1337 #define CPSR_E (1U << 9) 1338 #define CPSR_IT_2_7 (0xfc00U) 1339 #define CPSR_GE (0xfU << 16) 1340 #define CPSR_IL (1U << 20) 1341 #define CPSR_DIT (1U << 21) 1342 #define CPSR_PAN (1U << 22) 1343 #define CPSR_SSBS (1U << 23) 1344 #define CPSR_J (1U << 24) 1345 #define CPSR_IT_0_1 (3U << 25) 1346 #define CPSR_Q (1U << 27) 1347 #define CPSR_V (1U << 28) 1348 #define CPSR_C (1U << 29) 1349 #define CPSR_Z (1U << 30) 1350 #define CPSR_N (1U << 31) 1351 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) 1352 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) 1353 1354 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) 1355 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1356 | CPSR_NZCV) 1357 /* Bits writable in user mode. */ 1358 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) 1359 /* Execution state bits. MRS read as zero, MSR writes ignored. */ 1360 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) 1361 1362 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ 1363 #define XPSR_EXCP 0x1ffU 1364 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ 1365 #define XPSR_IT_2_7 CPSR_IT_2_7 1366 #define XPSR_GE CPSR_GE 1367 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ 1368 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ 1369 #define XPSR_IT_0_1 CPSR_IT_0_1 1370 #define XPSR_Q CPSR_Q 1371 #define XPSR_V CPSR_V 1372 #define XPSR_C CPSR_C 1373 #define XPSR_Z CPSR_Z 1374 #define XPSR_N CPSR_N 1375 #define XPSR_NZCV CPSR_NZCV 1376 #define XPSR_IT CPSR_IT 1377 1378 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ 1379 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ 1380 #define TTBCR_PD0 (1U << 4) 1381 #define TTBCR_PD1 (1U << 5) 1382 #define TTBCR_EPD0 (1U << 7) 1383 #define TTBCR_IRGN0 (3U << 8) 1384 #define TTBCR_ORGN0 (3U << 10) 1385 #define TTBCR_SH0 (3U << 12) 1386 #define TTBCR_T1SZ (3U << 16) 1387 #define TTBCR_A1 (1U << 22) 1388 #define TTBCR_EPD1 (1U << 23) 1389 #define TTBCR_IRGN1 (3U << 24) 1390 #define TTBCR_ORGN1 (3U << 26) 1391 #define TTBCR_SH1 (1U << 28) 1392 #define TTBCR_EAE (1U << 31) 1393 1394 /* Bit definitions for ARMv8 SPSR (PSTATE) format. 1395 * Only these are valid when in AArch64 mode; in 1396 * AArch32 mode SPSRs are basically CPSR-format. 1397 */ 1398 #define PSTATE_SP (1U) 1399 #define PSTATE_M (0xFU) 1400 #define PSTATE_nRW (1U << 4) 1401 #define PSTATE_F (1U << 6) 1402 #define PSTATE_I (1U << 7) 1403 #define PSTATE_A (1U << 8) 1404 #define PSTATE_D (1U << 9) 1405 #define PSTATE_BTYPE (3U << 10) 1406 #define PSTATE_SSBS (1U << 12) 1407 #define PSTATE_IL (1U << 20) 1408 #define PSTATE_SS (1U << 21) 1409 #define PSTATE_PAN (1U << 22) 1410 #define PSTATE_UAO (1U << 23) 1411 #define PSTATE_DIT (1U << 24) 1412 #define PSTATE_TCO (1U << 25) 1413 #define PSTATE_V (1U << 28) 1414 #define PSTATE_C (1U << 29) 1415 #define PSTATE_Z (1U << 30) 1416 #define PSTATE_N (1U << 31) 1417 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) 1418 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) 1419 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) 1420 /* Mode values for AArch64 */ 1421 #define PSTATE_MODE_EL3h 13 1422 #define PSTATE_MODE_EL3t 12 1423 #define PSTATE_MODE_EL2h 9 1424 #define PSTATE_MODE_EL2t 8 1425 #define PSTATE_MODE_EL1h 5 1426 #define PSTATE_MODE_EL1t 4 1427 #define PSTATE_MODE_EL0t 0 1428 1429 /* Write a new value to v7m.exception, thus transitioning into or out 1430 * of Handler mode; this may result in a change of active stack pointer. 1431 */ 1432 void write_v7m_exception(CPUARMState *env, uint32_t new_exc); 1433 1434 /* Map EL and handler into a PSTATE_MODE. */ 1435 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) 1436 { 1437 return (el << 2) | handler; 1438 } 1439 1440 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit 1441 * interprocessing, so we don't attempt to sync with the cpsr state used by 1442 * the 32 bit decoder. 1443 */ 1444 static inline uint32_t pstate_read(CPUARMState *env) 1445 { 1446 int ZF; 1447 1448 ZF = (env->ZF == 0); 1449 return (env->NF & 0x80000000) | (ZF << 30) 1450 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) 1451 | env->pstate | env->daif | (env->btype << 10); 1452 } 1453 1454 static inline void pstate_write(CPUARMState *env, uint32_t val) 1455 { 1456 env->ZF = (~val) & PSTATE_Z; 1457 env->NF = val; 1458 env->CF = (val >> 29) & 1; 1459 env->VF = (val << 3) & 0x80000000; 1460 env->daif = val & PSTATE_DAIF; 1461 env->btype = (val >> 10) & 3; 1462 env->pstate = val & ~CACHED_PSTATE_BITS; 1463 } 1464 1465 /* Return the current CPSR value. */ 1466 uint32_t cpsr_read(CPUARMState *env); 1467 1468 typedef enum CPSRWriteType { 1469 CPSRWriteByInstr = 0, /* from guest MSR or CPS */ 1470 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ 1471 CPSRWriteRaw = 2, 1472 /* trust values, no reg bank switch, no hflags rebuild */ 1473 CPSRWriteByGDBStub = 3, /* from the GDB stub */ 1474 } CPSRWriteType; 1475 1476 /* 1477 * Set the CPSR. Note that some bits of mask must be all-set or all-clear. 1478 * This will do an arm_rebuild_hflags() if any of the bits in @mask 1479 * correspond to TB flags bits cached in the hflags, unless @write_type 1480 * is CPSRWriteRaw. 1481 */ 1482 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, 1483 CPSRWriteType write_type); 1484 1485 /* Return the current xPSR value. */ 1486 static inline uint32_t xpsr_read(CPUARMState *env) 1487 { 1488 int ZF; 1489 ZF = (env->ZF == 0); 1490 return (env->NF & 0x80000000) | (ZF << 30) 1491 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) 1492 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) 1493 | ((env->condexec_bits & 0xfc) << 8) 1494 | (env->GE << 16) 1495 | env->v7m.exception; 1496 } 1497 1498 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ 1499 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) 1500 { 1501 if (mask & XPSR_NZCV) { 1502 env->ZF = (~val) & XPSR_Z; 1503 env->NF = val; 1504 env->CF = (val >> 29) & 1; 1505 env->VF = (val << 3) & 0x80000000; 1506 } 1507 if (mask & XPSR_Q) { 1508 env->QF = ((val & XPSR_Q) != 0); 1509 } 1510 if (mask & XPSR_GE) { 1511 env->GE = (val & XPSR_GE) >> 16; 1512 } 1513 #ifndef CONFIG_USER_ONLY 1514 if (mask & XPSR_T) { 1515 env->thumb = ((val & XPSR_T) != 0); 1516 } 1517 if (mask & XPSR_IT_0_1) { 1518 env->condexec_bits &= ~3; 1519 env->condexec_bits |= (val >> 25) & 3; 1520 } 1521 if (mask & XPSR_IT_2_7) { 1522 env->condexec_bits &= 3; 1523 env->condexec_bits |= (val >> 8) & 0xfc; 1524 } 1525 if (mask & XPSR_EXCP) { 1526 /* Note that this only happens on exception exit */ 1527 write_v7m_exception(env, val & XPSR_EXCP); 1528 } 1529 #endif 1530 } 1531 1532 #define HCR_VM (1ULL << 0) 1533 #define HCR_SWIO (1ULL << 1) 1534 #define HCR_PTW (1ULL << 2) 1535 #define HCR_FMO (1ULL << 3) 1536 #define HCR_IMO (1ULL << 4) 1537 #define HCR_AMO (1ULL << 5) 1538 #define HCR_VF (1ULL << 6) 1539 #define HCR_VI (1ULL << 7) 1540 #define HCR_VSE (1ULL << 8) 1541 #define HCR_FB (1ULL << 9) 1542 #define HCR_BSU_MASK (3ULL << 10) 1543 #define HCR_DC (1ULL << 12) 1544 #define HCR_TWI (1ULL << 13) 1545 #define HCR_TWE (1ULL << 14) 1546 #define HCR_TID0 (1ULL << 15) 1547 #define HCR_TID1 (1ULL << 16) 1548 #define HCR_TID2 (1ULL << 17) 1549 #define HCR_TID3 (1ULL << 18) 1550 #define HCR_TSC (1ULL << 19) 1551 #define HCR_TIDCP (1ULL << 20) 1552 #define HCR_TACR (1ULL << 21) 1553 #define HCR_TSW (1ULL << 22) 1554 #define HCR_TPCP (1ULL << 23) 1555 #define HCR_TPU (1ULL << 24) 1556 #define HCR_TTLB (1ULL << 25) 1557 #define HCR_TVM (1ULL << 26) 1558 #define HCR_TGE (1ULL << 27) 1559 #define HCR_TDZ (1ULL << 28) 1560 #define HCR_HCD (1ULL << 29) 1561 #define HCR_TRVM (1ULL << 30) 1562 #define HCR_RW (1ULL << 31) 1563 #define HCR_CD (1ULL << 32) 1564 #define HCR_ID (1ULL << 33) 1565 #define HCR_E2H (1ULL << 34) 1566 #define HCR_TLOR (1ULL << 35) 1567 #define HCR_TERR (1ULL << 36) 1568 #define HCR_TEA (1ULL << 37) 1569 #define HCR_MIOCNCE (1ULL << 38) 1570 /* RES0 bit 39 */ 1571 #define HCR_APK (1ULL << 40) 1572 #define HCR_API (1ULL << 41) 1573 #define HCR_NV (1ULL << 42) 1574 #define HCR_NV1 (1ULL << 43) 1575 #define HCR_AT (1ULL << 44) 1576 #define HCR_NV2 (1ULL << 45) 1577 #define HCR_FWB (1ULL << 46) 1578 #define HCR_FIEN (1ULL << 47) 1579 /* RES0 bit 48 */ 1580 #define HCR_TID4 (1ULL << 49) 1581 #define HCR_TICAB (1ULL << 50) 1582 #define HCR_AMVOFFEN (1ULL << 51) 1583 #define HCR_TOCU (1ULL << 52) 1584 #define HCR_ENSCXT (1ULL << 53) 1585 #define HCR_TTLBIS (1ULL << 54) 1586 #define HCR_TTLBOS (1ULL << 55) 1587 #define HCR_ATA (1ULL << 56) 1588 #define HCR_DCT (1ULL << 57) 1589 #define HCR_TID5 (1ULL << 58) 1590 #define HCR_TWEDEN (1ULL << 59) 1591 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) 1592 1593 #define HCRX_ENAS0 (1ULL << 0) 1594 #define HCRX_ENALS (1ULL << 1) 1595 #define HCRX_ENASR (1ULL << 2) 1596 #define HCRX_FNXS (1ULL << 3) 1597 #define HCRX_FGTNXS (1ULL << 4) 1598 #define HCRX_SMPME (1ULL << 5) 1599 #define HCRX_TALLINT (1ULL << 6) 1600 #define HCRX_VINMI (1ULL << 7) 1601 #define HCRX_VFNMI (1ULL << 8) 1602 #define HCRX_CMOW (1ULL << 9) 1603 #define HCRX_MCE2 (1ULL << 10) 1604 #define HCRX_MSCEN (1ULL << 11) 1605 1606 #define HPFAR_NS (1ULL << 63) 1607 1608 #define SCR_NS (1U << 0) 1609 #define SCR_IRQ (1U << 1) 1610 #define SCR_FIQ (1U << 2) 1611 #define SCR_EA (1U << 3) 1612 #define SCR_FW (1U << 4) 1613 #define SCR_AW (1U << 5) 1614 #define SCR_NET (1U << 6) 1615 #define SCR_SMD (1U << 7) 1616 #define SCR_HCE (1U << 8) 1617 #define SCR_SIF (1U << 9) 1618 #define SCR_RW (1U << 10) 1619 #define SCR_ST (1U << 11) 1620 #define SCR_TWI (1U << 12) 1621 #define SCR_TWE (1U << 13) 1622 #define SCR_TLOR (1U << 14) 1623 #define SCR_TERR (1U << 15) 1624 #define SCR_APK (1U << 16) 1625 #define SCR_API (1U << 17) 1626 #define SCR_EEL2 (1U << 18) 1627 #define SCR_EASE (1U << 19) 1628 #define SCR_NMEA (1U << 20) 1629 #define SCR_FIEN (1U << 21) 1630 #define SCR_ENSCXT (1U << 25) 1631 #define SCR_ATA (1U << 26) 1632 #define SCR_FGTEN (1U << 27) 1633 #define SCR_ECVEN (1U << 28) 1634 #define SCR_TWEDEN (1U << 29) 1635 #define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) 1636 #define SCR_TME (1ULL << 34) 1637 #define SCR_AMVOFFEN (1ULL << 35) 1638 #define SCR_ENAS0 (1ULL << 36) 1639 #define SCR_ADEN (1ULL << 37) 1640 #define SCR_HXEN (1ULL << 38) 1641 #define SCR_TRNDR (1ULL << 40) 1642 #define SCR_ENTP2 (1ULL << 41) 1643 #define SCR_GPF (1ULL << 48) 1644 1645 #define HSTR_TTEE (1 << 16) 1646 #define HSTR_TJDBX (1 << 17) 1647 1648 /* Return the current FPSCR value. */ 1649 uint32_t vfp_get_fpscr(CPUARMState *env); 1650 void vfp_set_fpscr(CPUARMState *env, uint32_t val); 1651 1652 /* FPCR, Floating Point Control Register 1653 * FPSR, Floating Poiht Status Register 1654 * 1655 * For A64 the FPSCR is split into two logically distinct registers, 1656 * FPCR and FPSR. However since they still use non-overlapping bits 1657 * we store the underlying state in fpscr and just mask on read/write. 1658 */ 1659 #define FPSR_MASK 0xf800009f 1660 #define FPCR_MASK 0x07ff9f00 1661 1662 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ 1663 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ 1664 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ 1665 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ 1666 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ 1667 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ 1668 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ 1669 #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ 1670 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ 1671 #define FPCR_DN (1 << 25) /* Default NaN enable bit */ 1672 #define FPCR_AHP (1 << 26) /* Alternative half-precision */ 1673 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ 1674 #define FPCR_V (1 << 28) /* FP overflow flag */ 1675 #define FPCR_C (1 << 29) /* FP carry flag */ 1676 #define FPCR_Z (1 << 30) /* FP zero flag */ 1677 #define FPCR_N (1 << 31) /* FP negative flag */ 1678 1679 #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ 1680 #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) 1681 #define FPCR_LTPSIZE_LENGTH 3 1682 1683 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) 1684 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) 1685 1686 static inline uint32_t vfp_get_fpsr(CPUARMState *env) 1687 { 1688 return vfp_get_fpscr(env) & FPSR_MASK; 1689 } 1690 1691 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) 1692 { 1693 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); 1694 vfp_set_fpscr(env, new_fpscr); 1695 } 1696 1697 static inline uint32_t vfp_get_fpcr(CPUARMState *env) 1698 { 1699 return vfp_get_fpscr(env) & FPCR_MASK; 1700 } 1701 1702 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) 1703 { 1704 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); 1705 vfp_set_fpscr(env, new_fpscr); 1706 } 1707 1708 enum arm_cpu_mode { 1709 ARM_CPU_MODE_USR = 0x10, 1710 ARM_CPU_MODE_FIQ = 0x11, 1711 ARM_CPU_MODE_IRQ = 0x12, 1712 ARM_CPU_MODE_SVC = 0x13, 1713 ARM_CPU_MODE_MON = 0x16, 1714 ARM_CPU_MODE_ABT = 0x17, 1715 ARM_CPU_MODE_HYP = 0x1a, 1716 ARM_CPU_MODE_UND = 0x1b, 1717 ARM_CPU_MODE_SYS = 0x1f 1718 }; 1719 1720 /* VFP system registers. */ 1721 #define ARM_VFP_FPSID 0 1722 #define ARM_VFP_FPSCR 1 1723 #define ARM_VFP_MVFR2 5 1724 #define ARM_VFP_MVFR1 6 1725 #define ARM_VFP_MVFR0 7 1726 #define ARM_VFP_FPEXC 8 1727 #define ARM_VFP_FPINST 9 1728 #define ARM_VFP_FPINST2 10 1729 /* These ones are M-profile only */ 1730 #define ARM_VFP_FPSCR_NZCVQC 2 1731 #define ARM_VFP_VPR 12 1732 #define ARM_VFP_P0 13 1733 #define ARM_VFP_FPCXT_NS 14 1734 #define ARM_VFP_FPCXT_S 15 1735 1736 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ 1737 #define QEMU_VFP_FPSCR_NZCV 0xffff 1738 1739 /* iwMMXt coprocessor control registers. */ 1740 #define ARM_IWMMXT_wCID 0 1741 #define ARM_IWMMXT_wCon 1 1742 #define ARM_IWMMXT_wCSSF 2 1743 #define ARM_IWMMXT_wCASF 3 1744 #define ARM_IWMMXT_wCGR0 8 1745 #define ARM_IWMMXT_wCGR1 9 1746 #define ARM_IWMMXT_wCGR2 10 1747 #define ARM_IWMMXT_wCGR3 11 1748 1749 /* V7M CCR bits */ 1750 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) 1751 FIELD(V7M_CCR, USERSETMPEND, 1, 1) 1752 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) 1753 FIELD(V7M_CCR, DIV_0_TRP, 4, 1) 1754 FIELD(V7M_CCR, BFHFNMIGN, 8, 1) 1755 FIELD(V7M_CCR, STKALIGN, 9, 1) 1756 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) 1757 FIELD(V7M_CCR, DC, 16, 1) 1758 FIELD(V7M_CCR, IC, 17, 1) 1759 FIELD(V7M_CCR, BP, 18, 1) 1760 FIELD(V7M_CCR, LOB, 19, 1) 1761 FIELD(V7M_CCR, TRD, 20, 1) 1762 1763 /* V7M SCR bits */ 1764 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) 1765 FIELD(V7M_SCR, SLEEPDEEP, 2, 1) 1766 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) 1767 FIELD(V7M_SCR, SEVONPEND, 4, 1) 1768 1769 /* V7M AIRCR bits */ 1770 FIELD(V7M_AIRCR, VECTRESET, 0, 1) 1771 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) 1772 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) 1773 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) 1774 FIELD(V7M_AIRCR, PRIGROUP, 8, 3) 1775 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) 1776 FIELD(V7M_AIRCR, PRIS, 14, 1) 1777 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) 1778 FIELD(V7M_AIRCR, VECTKEY, 16, 16) 1779 1780 /* V7M CFSR bits for MMFSR */ 1781 FIELD(V7M_CFSR, IACCVIOL, 0, 1) 1782 FIELD(V7M_CFSR, DACCVIOL, 1, 1) 1783 FIELD(V7M_CFSR, MUNSTKERR, 3, 1) 1784 FIELD(V7M_CFSR, MSTKERR, 4, 1) 1785 FIELD(V7M_CFSR, MLSPERR, 5, 1) 1786 FIELD(V7M_CFSR, MMARVALID, 7, 1) 1787 1788 /* V7M CFSR bits for BFSR */ 1789 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) 1790 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) 1791 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) 1792 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) 1793 FIELD(V7M_CFSR, STKERR, 8 + 4, 1) 1794 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) 1795 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) 1796 1797 /* V7M CFSR bits for UFSR */ 1798 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) 1799 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) 1800 FIELD(V7M_CFSR, INVPC, 16 + 2, 1) 1801 FIELD(V7M_CFSR, NOCP, 16 + 3, 1) 1802 FIELD(V7M_CFSR, STKOF, 16 + 4, 1) 1803 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) 1804 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) 1805 1806 /* V7M CFSR bit masks covering all of the subregister bits */ 1807 FIELD(V7M_CFSR, MMFSR, 0, 8) 1808 FIELD(V7M_CFSR, BFSR, 8, 8) 1809 FIELD(V7M_CFSR, UFSR, 16, 16) 1810 1811 /* V7M HFSR bits */ 1812 FIELD(V7M_HFSR, VECTTBL, 1, 1) 1813 FIELD(V7M_HFSR, FORCED, 30, 1) 1814 FIELD(V7M_HFSR, DEBUGEVT, 31, 1) 1815 1816 /* V7M DFSR bits */ 1817 FIELD(V7M_DFSR, HALTED, 0, 1) 1818 FIELD(V7M_DFSR, BKPT, 1, 1) 1819 FIELD(V7M_DFSR, DWTTRAP, 2, 1) 1820 FIELD(V7M_DFSR, VCATCH, 3, 1) 1821 FIELD(V7M_DFSR, EXTERNAL, 4, 1) 1822 1823 /* V7M SFSR bits */ 1824 FIELD(V7M_SFSR, INVEP, 0, 1) 1825 FIELD(V7M_SFSR, INVIS, 1, 1) 1826 FIELD(V7M_SFSR, INVER, 2, 1) 1827 FIELD(V7M_SFSR, AUVIOL, 3, 1) 1828 FIELD(V7M_SFSR, INVTRAN, 4, 1) 1829 FIELD(V7M_SFSR, LSPERR, 5, 1) 1830 FIELD(V7M_SFSR, SFARVALID, 6, 1) 1831 FIELD(V7M_SFSR, LSERR, 7, 1) 1832 1833 /* v7M MPU_CTRL bits */ 1834 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) 1835 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) 1836 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) 1837 1838 /* v7M CLIDR bits */ 1839 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) 1840 FIELD(V7M_CLIDR, LOUIS, 21, 3) 1841 FIELD(V7M_CLIDR, LOC, 24, 3) 1842 FIELD(V7M_CLIDR, LOUU, 27, 3) 1843 FIELD(V7M_CLIDR, ICB, 30, 2) 1844 1845 FIELD(V7M_CSSELR, IND, 0, 1) 1846 FIELD(V7M_CSSELR, LEVEL, 1, 3) 1847 /* We use the combination of InD and Level to index into cpu->ccsidr[]; 1848 * define a mask for this and check that it doesn't permit running off 1849 * the end of the array. 1850 */ 1851 FIELD(V7M_CSSELR, INDEX, 0, 4) 1852 1853 /* v7M FPCCR bits */ 1854 FIELD(V7M_FPCCR, LSPACT, 0, 1) 1855 FIELD(V7M_FPCCR, USER, 1, 1) 1856 FIELD(V7M_FPCCR, S, 2, 1) 1857 FIELD(V7M_FPCCR, THREAD, 3, 1) 1858 FIELD(V7M_FPCCR, HFRDY, 4, 1) 1859 FIELD(V7M_FPCCR, MMRDY, 5, 1) 1860 FIELD(V7M_FPCCR, BFRDY, 6, 1) 1861 FIELD(V7M_FPCCR, SFRDY, 7, 1) 1862 FIELD(V7M_FPCCR, MONRDY, 8, 1) 1863 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) 1864 FIELD(V7M_FPCCR, UFRDY, 10, 1) 1865 FIELD(V7M_FPCCR, RES0, 11, 15) 1866 FIELD(V7M_FPCCR, TS, 26, 1) 1867 FIELD(V7M_FPCCR, CLRONRETS, 27, 1) 1868 FIELD(V7M_FPCCR, CLRONRET, 28, 1) 1869 FIELD(V7M_FPCCR, LSPENS, 29, 1) 1870 FIELD(V7M_FPCCR, LSPEN, 30, 1) 1871 FIELD(V7M_FPCCR, ASPEN, 31, 1) 1872 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ 1873 #define R_V7M_FPCCR_BANKED_MASK \ 1874 (R_V7M_FPCCR_LSPACT_MASK | \ 1875 R_V7M_FPCCR_USER_MASK | \ 1876 R_V7M_FPCCR_THREAD_MASK | \ 1877 R_V7M_FPCCR_MMRDY_MASK | \ 1878 R_V7M_FPCCR_SPLIMVIOL_MASK | \ 1879 R_V7M_FPCCR_UFRDY_MASK | \ 1880 R_V7M_FPCCR_ASPEN_MASK) 1881 1882 /* v7M VPR bits */ 1883 FIELD(V7M_VPR, P0, 0, 16) 1884 FIELD(V7M_VPR, MASK01, 16, 4) 1885 FIELD(V7M_VPR, MASK23, 20, 4) 1886 1887 /* 1888 * System register ID fields. 1889 */ 1890 FIELD(CLIDR_EL1, CTYPE1, 0, 3) 1891 FIELD(CLIDR_EL1, CTYPE2, 3, 3) 1892 FIELD(CLIDR_EL1, CTYPE3, 6, 3) 1893 FIELD(CLIDR_EL1, CTYPE4, 9, 3) 1894 FIELD(CLIDR_EL1, CTYPE5, 12, 3) 1895 FIELD(CLIDR_EL1, CTYPE6, 15, 3) 1896 FIELD(CLIDR_EL1, CTYPE7, 18, 3) 1897 FIELD(CLIDR_EL1, LOUIS, 21, 3) 1898 FIELD(CLIDR_EL1, LOC, 24, 3) 1899 FIELD(CLIDR_EL1, LOUU, 27, 3) 1900 FIELD(CLIDR_EL1, ICB, 30, 3) 1901 1902 /* When FEAT_CCIDX is implemented */ 1903 FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) 1904 FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) 1905 FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) 1906 1907 /* When FEAT_CCIDX is not implemented */ 1908 FIELD(CCSIDR_EL1, LINESIZE, 0, 3) 1909 FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) 1910 FIELD(CCSIDR_EL1, NUMSETS, 13, 15) 1911 1912 FIELD(CTR_EL0, IMINLINE, 0, 4) 1913 FIELD(CTR_EL0, L1IP, 14, 2) 1914 FIELD(CTR_EL0, DMINLINE, 16, 4) 1915 FIELD(CTR_EL0, ERG, 20, 4) 1916 FIELD(CTR_EL0, CWG, 24, 4) 1917 FIELD(CTR_EL0, IDC, 28, 1) 1918 FIELD(CTR_EL0, DIC, 29, 1) 1919 FIELD(CTR_EL0, TMINLINE, 32, 6) 1920 1921 FIELD(MIDR_EL1, REVISION, 0, 4) 1922 FIELD(MIDR_EL1, PARTNUM, 4, 12) 1923 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) 1924 FIELD(MIDR_EL1, VARIANT, 20, 4) 1925 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) 1926 1927 FIELD(ID_ISAR0, SWAP, 0, 4) 1928 FIELD(ID_ISAR0, BITCOUNT, 4, 4) 1929 FIELD(ID_ISAR0, BITFIELD, 8, 4) 1930 FIELD(ID_ISAR0, CMPBRANCH, 12, 4) 1931 FIELD(ID_ISAR0, COPROC, 16, 4) 1932 FIELD(ID_ISAR0, DEBUG, 20, 4) 1933 FIELD(ID_ISAR0, DIVIDE, 24, 4) 1934 1935 FIELD(ID_ISAR1, ENDIAN, 0, 4) 1936 FIELD(ID_ISAR1, EXCEPT, 4, 4) 1937 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) 1938 FIELD(ID_ISAR1, EXTEND, 12, 4) 1939 FIELD(ID_ISAR1, IFTHEN, 16, 4) 1940 FIELD(ID_ISAR1, IMMEDIATE, 20, 4) 1941 FIELD(ID_ISAR1, INTERWORK, 24, 4) 1942 FIELD(ID_ISAR1, JAZELLE, 28, 4) 1943 1944 FIELD(ID_ISAR2, LOADSTORE, 0, 4) 1945 FIELD(ID_ISAR2, MEMHINT, 4, 4) 1946 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) 1947 FIELD(ID_ISAR2, MULT, 12, 4) 1948 FIELD(ID_ISAR2, MULTS, 16, 4) 1949 FIELD(ID_ISAR2, MULTU, 20, 4) 1950 FIELD(ID_ISAR2, PSR_AR, 24, 4) 1951 FIELD(ID_ISAR2, REVERSAL, 28, 4) 1952 1953 FIELD(ID_ISAR3, SATURATE, 0, 4) 1954 FIELD(ID_ISAR3, SIMD, 4, 4) 1955 FIELD(ID_ISAR3, SVC, 8, 4) 1956 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) 1957 FIELD(ID_ISAR3, TABBRANCH, 16, 4) 1958 FIELD(ID_ISAR3, T32COPY, 20, 4) 1959 FIELD(ID_ISAR3, TRUENOP, 24, 4) 1960 FIELD(ID_ISAR3, T32EE, 28, 4) 1961 1962 FIELD(ID_ISAR4, UNPRIV, 0, 4) 1963 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) 1964 FIELD(ID_ISAR4, WRITEBACK, 8, 4) 1965 FIELD(ID_ISAR4, SMC, 12, 4) 1966 FIELD(ID_ISAR4, BARRIER, 16, 4) 1967 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) 1968 FIELD(ID_ISAR4, PSR_M, 24, 4) 1969 FIELD(ID_ISAR4, SWP_FRAC, 28, 4) 1970 1971 FIELD(ID_ISAR5, SEVL, 0, 4) 1972 FIELD(ID_ISAR5, AES, 4, 4) 1973 FIELD(ID_ISAR5, SHA1, 8, 4) 1974 FIELD(ID_ISAR5, SHA2, 12, 4) 1975 FIELD(ID_ISAR5, CRC32, 16, 4) 1976 FIELD(ID_ISAR5, RDM, 24, 4) 1977 FIELD(ID_ISAR5, VCMA, 28, 4) 1978 1979 FIELD(ID_ISAR6, JSCVT, 0, 4) 1980 FIELD(ID_ISAR6, DP, 4, 4) 1981 FIELD(ID_ISAR6, FHM, 8, 4) 1982 FIELD(ID_ISAR6, SB, 12, 4) 1983 FIELD(ID_ISAR6, SPECRES, 16, 4) 1984 FIELD(ID_ISAR6, BF16, 20, 4) 1985 FIELD(ID_ISAR6, I8MM, 24, 4) 1986 1987 FIELD(ID_MMFR0, VMSA, 0, 4) 1988 FIELD(ID_MMFR0, PMSA, 4, 4) 1989 FIELD(ID_MMFR0, OUTERSHR, 8, 4) 1990 FIELD(ID_MMFR0, SHARELVL, 12, 4) 1991 FIELD(ID_MMFR0, TCM, 16, 4) 1992 FIELD(ID_MMFR0, AUXREG, 20, 4) 1993 FIELD(ID_MMFR0, FCSE, 24, 4) 1994 FIELD(ID_MMFR0, INNERSHR, 28, 4) 1995 1996 FIELD(ID_MMFR1, L1HVDVA, 0, 4) 1997 FIELD(ID_MMFR1, L1UNIVA, 4, 4) 1998 FIELD(ID_MMFR1, L1HVDSW, 8, 4) 1999 FIELD(ID_MMFR1, L1UNISW, 12, 4) 2000 FIELD(ID_MMFR1, L1HVD, 16, 4) 2001 FIELD(ID_MMFR1, L1UNI, 20, 4) 2002 FIELD(ID_MMFR1, L1TSTCLN, 24, 4) 2003 FIELD(ID_MMFR1, BPRED, 28, 4) 2004 2005 FIELD(ID_MMFR2, L1HVDFG, 0, 4) 2006 FIELD(ID_MMFR2, L1HVDBG, 4, 4) 2007 FIELD(ID_MMFR2, L1HVDRNG, 8, 4) 2008 FIELD(ID_MMFR2, HVDTLB, 12, 4) 2009 FIELD(ID_MMFR2, UNITLB, 16, 4) 2010 FIELD(ID_MMFR2, MEMBARR, 20, 4) 2011 FIELD(ID_MMFR2, WFISTALL, 24, 4) 2012 FIELD(ID_MMFR2, HWACCFLG, 28, 4) 2013 2014 FIELD(ID_MMFR3, CMAINTVA, 0, 4) 2015 FIELD(ID_MMFR3, CMAINTSW, 4, 4) 2016 FIELD(ID_MMFR3, BPMAINT, 8, 4) 2017 FIELD(ID_MMFR3, MAINTBCST, 12, 4) 2018 FIELD(ID_MMFR3, PAN, 16, 4) 2019 FIELD(ID_MMFR3, COHWALK, 20, 4) 2020 FIELD(ID_MMFR3, CMEMSZ, 24, 4) 2021 FIELD(ID_MMFR3, SUPERSEC, 28, 4) 2022 2023 FIELD(ID_MMFR4, SPECSEI, 0, 4) 2024 FIELD(ID_MMFR4, AC2, 4, 4) 2025 FIELD(ID_MMFR4, XNX, 8, 4) 2026 FIELD(ID_MMFR4, CNP, 12, 4) 2027 FIELD(ID_MMFR4, HPDS, 16, 4) 2028 FIELD(ID_MMFR4, LSM, 20, 4) 2029 FIELD(ID_MMFR4, CCIDX, 24, 4) 2030 FIELD(ID_MMFR4, EVT, 28, 4) 2031 2032 FIELD(ID_MMFR5, ETS, 0, 4) 2033 FIELD(ID_MMFR5, NTLBPA, 4, 4) 2034 2035 FIELD(ID_PFR0, STATE0, 0, 4) 2036 FIELD(ID_PFR0, STATE1, 4, 4) 2037 FIELD(ID_PFR0, STATE2, 8, 4) 2038 FIELD(ID_PFR0, STATE3, 12, 4) 2039 FIELD(ID_PFR0, CSV2, 16, 4) 2040 FIELD(ID_PFR0, AMU, 20, 4) 2041 FIELD(ID_PFR0, DIT, 24, 4) 2042 FIELD(ID_PFR0, RAS, 28, 4) 2043 2044 FIELD(ID_PFR1, PROGMOD, 0, 4) 2045 FIELD(ID_PFR1, SECURITY, 4, 4) 2046 FIELD(ID_PFR1, MPROGMOD, 8, 4) 2047 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) 2048 FIELD(ID_PFR1, GENTIMER, 16, 4) 2049 FIELD(ID_PFR1, SEC_FRAC, 20, 4) 2050 FIELD(ID_PFR1, VIRT_FRAC, 24, 4) 2051 FIELD(ID_PFR1, GIC, 28, 4) 2052 2053 FIELD(ID_PFR2, CSV3, 0, 4) 2054 FIELD(ID_PFR2, SSBS, 4, 4) 2055 FIELD(ID_PFR2, RAS_FRAC, 8, 4) 2056 2057 FIELD(ID_AA64ISAR0, AES, 4, 4) 2058 FIELD(ID_AA64ISAR0, SHA1, 8, 4) 2059 FIELD(ID_AA64ISAR0, SHA2, 12, 4) 2060 FIELD(ID_AA64ISAR0, CRC32, 16, 4) 2061 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) 2062 FIELD(ID_AA64ISAR0, RDM, 28, 4) 2063 FIELD(ID_AA64ISAR0, SHA3, 32, 4) 2064 FIELD(ID_AA64ISAR0, SM3, 36, 4) 2065 FIELD(ID_AA64ISAR0, SM4, 40, 4) 2066 FIELD(ID_AA64ISAR0, DP, 44, 4) 2067 FIELD(ID_AA64ISAR0, FHM, 48, 4) 2068 FIELD(ID_AA64ISAR0, TS, 52, 4) 2069 FIELD(ID_AA64ISAR0, TLB, 56, 4) 2070 FIELD(ID_AA64ISAR0, RNDR, 60, 4) 2071 2072 FIELD(ID_AA64ISAR1, DPB, 0, 4) 2073 FIELD(ID_AA64ISAR1, APA, 4, 4) 2074 FIELD(ID_AA64ISAR1, API, 8, 4) 2075 FIELD(ID_AA64ISAR1, JSCVT, 12, 4) 2076 FIELD(ID_AA64ISAR1, FCMA, 16, 4) 2077 FIELD(ID_AA64ISAR1, LRCPC, 20, 4) 2078 FIELD(ID_AA64ISAR1, GPA, 24, 4) 2079 FIELD(ID_AA64ISAR1, GPI, 28, 4) 2080 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) 2081 FIELD(ID_AA64ISAR1, SB, 36, 4) 2082 FIELD(ID_AA64ISAR1, SPECRES, 40, 4) 2083 FIELD(ID_AA64ISAR1, BF16, 44, 4) 2084 FIELD(ID_AA64ISAR1, DGH, 48, 4) 2085 FIELD(ID_AA64ISAR1, I8MM, 52, 4) 2086 FIELD(ID_AA64ISAR1, XS, 56, 4) 2087 FIELD(ID_AA64ISAR1, LS64, 60, 4) 2088 2089 FIELD(ID_AA64ISAR2, WFXT, 0, 4) 2090 FIELD(ID_AA64ISAR2, RPRES, 4, 4) 2091 FIELD(ID_AA64ISAR2, GPA3, 8, 4) 2092 FIELD(ID_AA64ISAR2, APA3, 12, 4) 2093 FIELD(ID_AA64ISAR2, MOPS, 16, 4) 2094 FIELD(ID_AA64ISAR2, BC, 20, 4) 2095 FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) 2096 2097 FIELD(ID_AA64PFR0, EL0, 0, 4) 2098 FIELD(ID_AA64PFR0, EL1, 4, 4) 2099 FIELD(ID_AA64PFR0, EL2, 8, 4) 2100 FIELD(ID_AA64PFR0, EL3, 12, 4) 2101 FIELD(ID_AA64PFR0, FP, 16, 4) 2102 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) 2103 FIELD(ID_AA64PFR0, GIC, 24, 4) 2104 FIELD(ID_AA64PFR0, RAS, 28, 4) 2105 FIELD(ID_AA64PFR0, SVE, 32, 4) 2106 FIELD(ID_AA64PFR0, SEL2, 36, 4) 2107 FIELD(ID_AA64PFR0, MPAM, 40, 4) 2108 FIELD(ID_AA64PFR0, AMU, 44, 4) 2109 FIELD(ID_AA64PFR0, DIT, 48, 4) 2110 FIELD(ID_AA64PFR0, CSV2, 56, 4) 2111 FIELD(ID_AA64PFR0, CSV3, 60, 4) 2112 2113 FIELD(ID_AA64PFR1, BT, 0, 4) 2114 FIELD(ID_AA64PFR1, SSBS, 4, 4) 2115 FIELD(ID_AA64PFR1, MTE, 8, 4) 2116 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) 2117 FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) 2118 FIELD(ID_AA64PFR1, SME, 24, 4) 2119 FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) 2120 FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) 2121 FIELD(ID_AA64PFR1, NMI, 36, 4) 2122 2123 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) 2124 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) 2125 FIELD(ID_AA64MMFR0, BIGEND, 8, 4) 2126 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) 2127 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) 2128 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) 2129 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) 2130 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) 2131 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) 2132 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) 2133 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) 2134 FIELD(ID_AA64MMFR0, EXS, 44, 4) 2135 FIELD(ID_AA64MMFR0, FGT, 56, 4) 2136 FIELD(ID_AA64MMFR0, ECV, 60, 4) 2137 2138 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) 2139 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) 2140 FIELD(ID_AA64MMFR1, VH, 8, 4) 2141 FIELD(ID_AA64MMFR1, HPDS, 12, 4) 2142 FIELD(ID_AA64MMFR1, LO, 16, 4) 2143 FIELD(ID_AA64MMFR1, PAN, 20, 4) 2144 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) 2145 FIELD(ID_AA64MMFR1, XNX, 28, 4) 2146 FIELD(ID_AA64MMFR1, TWED, 32, 4) 2147 FIELD(ID_AA64MMFR1, ETS, 36, 4) 2148 FIELD(ID_AA64MMFR1, HCX, 40, 4) 2149 FIELD(ID_AA64MMFR1, AFP, 44, 4) 2150 FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) 2151 FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) 2152 FIELD(ID_AA64MMFR1, CMOW, 56, 4) 2153 2154 FIELD(ID_AA64MMFR2, CNP, 0, 4) 2155 FIELD(ID_AA64MMFR2, UAO, 4, 4) 2156 FIELD(ID_AA64MMFR2, LSM, 8, 4) 2157 FIELD(ID_AA64MMFR2, IESB, 12, 4) 2158 FIELD(ID_AA64MMFR2, VARANGE, 16, 4) 2159 FIELD(ID_AA64MMFR2, CCIDX, 20, 4) 2160 FIELD(ID_AA64MMFR2, NV, 24, 4) 2161 FIELD(ID_AA64MMFR2, ST, 28, 4) 2162 FIELD(ID_AA64MMFR2, AT, 32, 4) 2163 FIELD(ID_AA64MMFR2, IDS, 36, 4) 2164 FIELD(ID_AA64MMFR2, FWB, 40, 4) 2165 FIELD(ID_AA64MMFR2, TTL, 48, 4) 2166 FIELD(ID_AA64MMFR2, BBM, 52, 4) 2167 FIELD(ID_AA64MMFR2, EVT, 56, 4) 2168 FIELD(ID_AA64MMFR2, E0PD, 60, 4) 2169 2170 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) 2171 FIELD(ID_AA64DFR0, TRACEVER, 4, 4) 2172 FIELD(ID_AA64DFR0, PMUVER, 8, 4) 2173 FIELD(ID_AA64DFR0, BRPS, 12, 4) 2174 FIELD(ID_AA64DFR0, WRPS, 20, 4) 2175 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) 2176 FIELD(ID_AA64DFR0, PMSVER, 32, 4) 2177 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) 2178 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) 2179 FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) 2180 FIELD(ID_AA64DFR0, MTPMU, 48, 4) 2181 FIELD(ID_AA64DFR0, BRBE, 52, 4) 2182 FIELD(ID_AA64DFR0, HPMN0, 60, 4) 2183 2184 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) 2185 FIELD(ID_AA64ZFR0, AES, 4, 4) 2186 FIELD(ID_AA64ZFR0, BITPERM, 16, 4) 2187 FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) 2188 FIELD(ID_AA64ZFR0, SHA3, 32, 4) 2189 FIELD(ID_AA64ZFR0, SM4, 40, 4) 2190 FIELD(ID_AA64ZFR0, I8MM, 44, 4) 2191 FIELD(ID_AA64ZFR0, F32MM, 52, 4) 2192 FIELD(ID_AA64ZFR0, F64MM, 56, 4) 2193 2194 FIELD(ID_AA64SMFR0, F32F32, 32, 1) 2195 FIELD(ID_AA64SMFR0, B16F32, 34, 1) 2196 FIELD(ID_AA64SMFR0, F16F32, 35, 1) 2197 FIELD(ID_AA64SMFR0, I8I32, 36, 4) 2198 FIELD(ID_AA64SMFR0, F64F64, 48, 1) 2199 FIELD(ID_AA64SMFR0, I16I64, 52, 4) 2200 FIELD(ID_AA64SMFR0, SMEVER, 56, 4) 2201 FIELD(ID_AA64SMFR0, FA64, 63, 1) 2202 2203 FIELD(ID_DFR0, COPDBG, 0, 4) 2204 FIELD(ID_DFR0, COPSDBG, 4, 4) 2205 FIELD(ID_DFR0, MMAPDBG, 8, 4) 2206 FIELD(ID_DFR0, COPTRC, 12, 4) 2207 FIELD(ID_DFR0, MMAPTRC, 16, 4) 2208 FIELD(ID_DFR0, MPROFDBG, 20, 4) 2209 FIELD(ID_DFR0, PERFMON, 24, 4) 2210 FIELD(ID_DFR0, TRACEFILT, 28, 4) 2211 2212 FIELD(ID_DFR1, MTPMU, 0, 4) 2213 FIELD(ID_DFR1, HPMN0, 4, 4) 2214 2215 FIELD(DBGDIDR, SE_IMP, 12, 1) 2216 FIELD(DBGDIDR, NSUHD_IMP, 14, 1) 2217 FIELD(DBGDIDR, VERSION, 16, 4) 2218 FIELD(DBGDIDR, CTX_CMPS, 20, 4) 2219 FIELD(DBGDIDR, BRPS, 24, 4) 2220 FIELD(DBGDIDR, WRPS, 28, 4) 2221 2222 FIELD(MVFR0, SIMDREG, 0, 4) 2223 FIELD(MVFR0, FPSP, 4, 4) 2224 FIELD(MVFR0, FPDP, 8, 4) 2225 FIELD(MVFR0, FPTRAP, 12, 4) 2226 FIELD(MVFR0, FPDIVIDE, 16, 4) 2227 FIELD(MVFR0, FPSQRT, 20, 4) 2228 FIELD(MVFR0, FPSHVEC, 24, 4) 2229 FIELD(MVFR0, FPROUND, 28, 4) 2230 2231 FIELD(MVFR1, FPFTZ, 0, 4) 2232 FIELD(MVFR1, FPDNAN, 4, 4) 2233 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ 2234 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ 2235 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ 2236 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ 2237 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ 2238 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ 2239 FIELD(MVFR1, FPHP, 24, 4) 2240 FIELD(MVFR1, SIMDFMAC, 28, 4) 2241 2242 FIELD(MVFR2, SIMDMISC, 0, 4) 2243 FIELD(MVFR2, FPMISC, 4, 4) 2244 2245 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); 2246 2247 /* If adding a feature bit which corresponds to a Linux ELF 2248 * HWCAP bit, remember to update the feature-bit-to-hwcap 2249 * mapping in linux-user/elfload.c:get_elf_hwcap(). 2250 */ 2251 enum arm_features { 2252 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ 2253 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ 2254 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ 2255 ARM_FEATURE_V6, 2256 ARM_FEATURE_V6K, 2257 ARM_FEATURE_V7, 2258 ARM_FEATURE_THUMB2, 2259 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ 2260 ARM_FEATURE_NEON, 2261 ARM_FEATURE_M, /* Microcontroller profile. */ 2262 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ 2263 ARM_FEATURE_THUMB2EE, 2264 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ 2265 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ 2266 ARM_FEATURE_V4T, 2267 ARM_FEATURE_V5, 2268 ARM_FEATURE_STRONGARM, 2269 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ 2270 ARM_FEATURE_GENERIC_TIMER, 2271 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ 2272 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ 2273 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ 2274 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ 2275 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ 2276 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ 2277 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ 2278 ARM_FEATURE_V8, 2279 ARM_FEATURE_AARCH64, /* supports 64 bit mode */ 2280 ARM_FEATURE_CBAR, /* has cp15 CBAR */ 2281 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ 2282 ARM_FEATURE_EL2, /* has EL2 Virtualization support */ 2283 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ 2284 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ 2285 ARM_FEATURE_PMU, /* has PMU support */ 2286 ARM_FEATURE_VBAR, /* has cp15 VBAR */ 2287 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ 2288 ARM_FEATURE_M_MAIN, /* M profile Main Extension */ 2289 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ 2290 }; 2291 2292 static inline int arm_feature(CPUARMState *env, int feature) 2293 { 2294 return (env->features & (1ULL << feature)) != 0; 2295 } 2296 2297 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); 2298 2299 #if !defined(CONFIG_USER_ONLY) 2300 /* Return true if exception levels below EL3 are in secure state, 2301 * or would be following an exception return to that level. 2302 * Unlike arm_is_secure() (which is always a question about the 2303 * _current_ state of the CPU) this doesn't care about the current 2304 * EL or mode. 2305 */ 2306 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2307 { 2308 if (arm_feature(env, ARM_FEATURE_EL3)) { 2309 return !(env->cp15.scr_el3 & SCR_NS); 2310 } else { 2311 /* If EL3 is not supported then the secure state is implementation 2312 * defined, in which case QEMU defaults to non-secure. 2313 */ 2314 return false; 2315 } 2316 } 2317 2318 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ 2319 static inline bool arm_is_el3_or_mon(CPUARMState *env) 2320 { 2321 if (arm_feature(env, ARM_FEATURE_EL3)) { 2322 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { 2323 /* CPU currently in AArch64 state and EL3 */ 2324 return true; 2325 } else if (!is_a64(env) && 2326 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { 2327 /* CPU currently in AArch32 state and monitor mode */ 2328 return true; 2329 } 2330 } 2331 return false; 2332 } 2333 2334 /* Return true if the processor is in secure state */ 2335 static inline bool arm_is_secure(CPUARMState *env) 2336 { 2337 if (arm_is_el3_or_mon(env)) { 2338 return true; 2339 } 2340 return arm_is_secure_below_el3(env); 2341 } 2342 2343 /* 2344 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. 2345 * This corresponds to the pseudocode EL2Enabled() 2346 */ 2347 static inline bool arm_is_el2_enabled(CPUARMState *env) 2348 { 2349 if (arm_feature(env, ARM_FEATURE_EL2)) { 2350 if (arm_is_secure_below_el3(env)) { 2351 return (env->cp15.scr_el3 & SCR_EEL2) != 0; 2352 } 2353 return true; 2354 } 2355 return false; 2356 } 2357 2358 #else 2359 static inline bool arm_is_secure_below_el3(CPUARMState *env) 2360 { 2361 return false; 2362 } 2363 2364 static inline bool arm_is_secure(CPUARMState *env) 2365 { 2366 return false; 2367 } 2368 2369 static inline bool arm_is_el2_enabled(CPUARMState *env) 2370 { 2371 return false; 2372 } 2373 #endif 2374 2375 /** 2376 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. 2377 * E.g. when in secure state, fields in HCR_EL2 are suppressed, 2378 * "for all purposes other than a direct read or write access of HCR_EL2." 2379 * Not included here is HCR_RW. 2380 */ 2381 uint64_t arm_hcr_el2_eff(CPUARMState *env); 2382 uint64_t arm_hcrx_el2_eff(CPUARMState *env); 2383 2384 /* Return true if the specified exception level is running in AArch64 state. */ 2385 static inline bool arm_el_is_aa64(CPUARMState *env, int el) 2386 { 2387 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, 2388 * and if we're not in EL0 then the state of EL0 isn't well defined.) 2389 */ 2390 assert(el >= 1 && el <= 3); 2391 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); 2392 2393 /* The highest exception level is always at the maximum supported 2394 * register width, and then lower levels have a register width controlled 2395 * by bits in the SCR or HCR registers. 2396 */ 2397 if (el == 3) { 2398 return aa64; 2399 } 2400 2401 if (arm_feature(env, ARM_FEATURE_EL3) && 2402 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) { 2403 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); 2404 } 2405 2406 if (el == 2) { 2407 return aa64; 2408 } 2409 2410 if (arm_is_el2_enabled(env)) { 2411 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); 2412 } 2413 2414 return aa64; 2415 } 2416 2417 /* Function for determing whether guest cp register reads and writes should 2418 * access the secure or non-secure bank of a cp register. When EL3 is 2419 * operating in AArch32 state, the NS-bit determines whether the secure 2420 * instance of a cp register should be used. When EL3 is AArch64 (or if 2421 * it doesn't exist at all) then there is no register banking, and all 2422 * accesses are to the non-secure version. 2423 */ 2424 static inline bool access_secure_reg(CPUARMState *env) 2425 { 2426 bool ret = (arm_feature(env, ARM_FEATURE_EL3) && 2427 !arm_el_is_aa64(env, 3) && 2428 !(env->cp15.scr_el3 & SCR_NS)); 2429 2430 return ret; 2431 } 2432 2433 /* Macros for accessing a specified CP register bank */ 2434 #define A32_BANKED_REG_GET(_env, _regname, _secure) \ 2435 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) 2436 2437 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ 2438 do { \ 2439 if (_secure) { \ 2440 (_env)->cp15._regname##_s = (_val); \ 2441 } else { \ 2442 (_env)->cp15._regname##_ns = (_val); \ 2443 } \ 2444 } while (0) 2445 2446 /* Macros for automatically accessing a specific CP register bank depending on 2447 * the current secure state of the system. These macros are not intended for 2448 * supporting instruction translation reads/writes as these are dependent 2449 * solely on the SCR.NS bit and not the mode. 2450 */ 2451 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ 2452 A32_BANKED_REG_GET((_env), _regname, \ 2453 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) 2454 2455 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ 2456 A32_BANKED_REG_SET((_env), _regname, \ 2457 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ 2458 (_val)) 2459 2460 void arm_cpu_list(void); 2461 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, 2462 uint32_t cur_el, bool secure); 2463 2464 /* Interface between CPU and Interrupt controller. */ 2465 #ifndef CONFIG_USER_ONLY 2466 bool armv7m_nvic_can_take_pending_exception(void *opaque); 2467 #else 2468 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) 2469 { 2470 return true; 2471 } 2472 #endif 2473 /** 2474 * armv7m_nvic_set_pending: mark the specified exception as pending 2475 * @opaque: the NVIC 2476 * @irq: the exception number to mark pending 2477 * @secure: false for non-banked exceptions or for the nonsecure 2478 * version of a banked exception, true for the secure version of a banked 2479 * exception. 2480 * 2481 * Marks the specified exception as pending. Note that we will assert() 2482 * if @secure is true and @irq does not specify one of the fixed set 2483 * of architecturally banked exceptions. 2484 */ 2485 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); 2486 /** 2487 * armv7m_nvic_set_pending_derived: mark this derived exception as pending 2488 * @opaque: the NVIC 2489 * @irq: the exception number to mark pending 2490 * @secure: false for non-banked exceptions or for the nonsecure 2491 * version of a banked exception, true for the secure version of a banked 2492 * exception. 2493 * 2494 * Similar to armv7m_nvic_set_pending(), but specifically for derived 2495 * exceptions (exceptions generated in the course of trying to take 2496 * a different exception). 2497 */ 2498 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); 2499 /** 2500 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending 2501 * @opaque: the NVIC 2502 * @irq: the exception number to mark pending 2503 * @secure: false for non-banked exceptions or for the nonsecure 2504 * version of a banked exception, true for the secure version of a banked 2505 * exception. 2506 * 2507 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions 2508 * generated in the course of lazy stacking of FP registers. 2509 */ 2510 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); 2511 /** 2512 * armv7m_nvic_get_pending_irq_info: return highest priority pending 2513 * exception, and whether it targets Secure state 2514 * @opaque: the NVIC 2515 * @pirq: set to pending exception number 2516 * @ptargets_secure: set to whether pending exception targets Secure 2517 * 2518 * This function writes the number of the highest priority pending 2519 * exception (the one which would be made active by 2520 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure 2521 * to true if the current highest priority pending exception should 2522 * be taken to Secure state, false for NS. 2523 */ 2524 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, 2525 bool *ptargets_secure); 2526 /** 2527 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active 2528 * @opaque: the NVIC 2529 * 2530 * Move the current highest priority pending exception from the pending 2531 * state to the active state, and update v7m.exception to indicate that 2532 * it is the exception currently being handled. 2533 */ 2534 void armv7m_nvic_acknowledge_irq(void *opaque); 2535 /** 2536 * armv7m_nvic_complete_irq: complete specified interrupt or exception 2537 * @opaque: the NVIC 2538 * @irq: the exception number to complete 2539 * @secure: true if this exception was secure 2540 * 2541 * Returns: -1 if the irq was not active 2542 * 1 if completing this irq brought us back to base (no active irqs) 2543 * 0 if there is still an irq active after this one was completed 2544 * (Ignoring -1, this is the same as the RETTOBASE value before completion.) 2545 */ 2546 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); 2547 /** 2548 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) 2549 * @opaque: the NVIC 2550 * @irq: the exception number to mark pending 2551 * @secure: false for non-banked exceptions or for the nonsecure 2552 * version of a banked exception, true for the secure version of a banked 2553 * exception. 2554 * 2555 * Return whether an exception is "ready", i.e. whether the exception is 2556 * enabled and is configured at a priority which would allow it to 2557 * interrupt the current execution priority. This controls whether the 2558 * RDY bit for it in the FPCCR is set. 2559 */ 2560 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); 2561 /** 2562 * armv7m_nvic_raw_execution_priority: return the raw execution priority 2563 * @opaque: the NVIC 2564 * 2565 * Returns: the raw execution priority as defined by the v8M architecture. 2566 * This is the execution priority minus the effects of AIRCR.PRIS, 2567 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. 2568 * (v8M ARM ARM I_PKLD.) 2569 */ 2570 int armv7m_nvic_raw_execution_priority(void *opaque); 2571 /** 2572 * armv7m_nvic_neg_prio_requested: return true if the requested execution 2573 * priority is negative for the specified security state. 2574 * @opaque: the NVIC 2575 * @secure: the security state to test 2576 * This corresponds to the pseudocode IsReqExecPriNeg(). 2577 */ 2578 #ifndef CONFIG_USER_ONLY 2579 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); 2580 #else 2581 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) 2582 { 2583 return false; 2584 } 2585 #endif 2586 2587 /* Interface for defining coprocessor registers. 2588 * Registers are defined in tables of arm_cp_reginfo structs 2589 * which are passed to define_arm_cp_regs(). 2590 */ 2591 2592 /* When looking up a coprocessor register we look for it 2593 * via an integer which encodes all of: 2594 * coprocessor number 2595 * Crn, Crm, opc1, opc2 fields 2596 * 32 or 64 bit register (ie is it accessed via MRC/MCR 2597 * or via MRRC/MCRR?) 2598 * non-secure/secure bank (AArch32 only) 2599 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. 2600 * (In this case crn and opc2 should be zero.) 2601 * For AArch64, there is no 32/64 bit size distinction; 2602 * instead all registers have a 2 bit op0, 3 bit op1 and op2, 2603 * and 4 bit CRn and CRm. The encoding patterns are chosen 2604 * to be easy to convert to and from the KVM encodings, and also 2605 * so that the hashtable can contain both AArch32 and AArch64 2606 * registers (to allow for interprocessing where we might run 2607 * 32 bit code on a 64 bit core). 2608 */ 2609 /* This bit is private to our hashtable cpreg; in KVM register 2610 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 2611 * in the upper bits of the 64 bit ID. 2612 */ 2613 #define CP_REG_AA64_SHIFT 28 2614 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) 2615 2616 /* To enable banking of coprocessor registers depending on ns-bit we 2617 * add a bit to distinguish between secure and non-secure cpregs in the 2618 * hashtable. 2619 */ 2620 #define CP_REG_NS_SHIFT 29 2621 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) 2622 2623 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ 2624 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ 2625 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) 2626 2627 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ 2628 (CP_REG_AA64_MASK | \ 2629 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ 2630 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ 2631 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ 2632 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ 2633 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ 2634 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) 2635 2636 /* Convert a full 64 bit KVM register ID to the truncated 32 bit 2637 * version used as a key for the coprocessor register hashtable 2638 */ 2639 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) 2640 { 2641 uint32_t cpregid = kvmid; 2642 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { 2643 cpregid |= CP_REG_AA64_MASK; 2644 } else { 2645 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { 2646 cpregid |= (1 << 15); 2647 } 2648 2649 /* KVM is always non-secure so add the NS flag on AArch32 register 2650 * entries. 2651 */ 2652 cpregid |= 1 << CP_REG_NS_SHIFT; 2653 } 2654 return cpregid; 2655 } 2656 2657 /* Convert a truncated 32 bit hashtable key into the full 2658 * 64 bit KVM register ID. 2659 */ 2660 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 2661 { 2662 uint64_t kvmid; 2663 2664 if (cpregid & CP_REG_AA64_MASK) { 2665 kvmid = cpregid & ~CP_REG_AA64_MASK; 2666 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; 2667 } else { 2668 kvmid = cpregid & ~(1 << 15); 2669 if (cpregid & (1 << 15)) { 2670 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; 2671 } else { 2672 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; 2673 } 2674 } 2675 return kvmid; 2676 } 2677 2678 /* Return the highest implemented Exception Level */ 2679 static inline int arm_highest_el(CPUARMState *env) 2680 { 2681 if (arm_feature(env, ARM_FEATURE_EL3)) { 2682 return 3; 2683 } 2684 if (arm_feature(env, ARM_FEATURE_EL2)) { 2685 return 2; 2686 } 2687 return 1; 2688 } 2689 2690 /* Return true if a v7M CPU is in Handler mode */ 2691 static inline bool arm_v7m_is_handler_mode(CPUARMState *env) 2692 { 2693 return env->v7m.exception != 0; 2694 } 2695 2696 /* Return the current Exception Level (as per ARMv8; note that this differs 2697 * from the ARMv7 Privilege Level). 2698 */ 2699 static inline int arm_current_el(CPUARMState *env) 2700 { 2701 if (arm_feature(env, ARM_FEATURE_M)) { 2702 return arm_v7m_is_handler_mode(env) || 2703 !(env->v7m.control[env->v7m.secure] & 1); 2704 } 2705 2706 if (is_a64(env)) { 2707 return extract32(env->pstate, 2, 2); 2708 } 2709 2710 switch (env->uncached_cpsr & 0x1f) { 2711 case ARM_CPU_MODE_USR: 2712 return 0; 2713 case ARM_CPU_MODE_HYP: 2714 return 2; 2715 case ARM_CPU_MODE_MON: 2716 return 3; 2717 default: 2718 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { 2719 /* If EL3 is 32-bit then all secure privileged modes run in 2720 * EL3 2721 */ 2722 return 3; 2723 } 2724 2725 return 1; 2726 } 2727 } 2728 2729 /** 2730 * write_list_to_cpustate 2731 * @cpu: ARMCPU 2732 * 2733 * For each register listed in the ARMCPU cpreg_indexes list, write 2734 * its value from the cpreg_values list into the ARMCPUState structure. 2735 * This updates TCG's working data structures from KVM data or 2736 * from incoming migration state. 2737 * 2738 * Returns: true if all register values were updated correctly, 2739 * false if some register was unknown or could not be written. 2740 * Note that we do not stop early on failure -- we will attempt 2741 * writing all registers in the list. 2742 */ 2743 bool write_list_to_cpustate(ARMCPU *cpu); 2744 2745 /** 2746 * write_cpustate_to_list: 2747 * @cpu: ARMCPU 2748 * @kvm_sync: true if this is for syncing back to KVM 2749 * 2750 * For each register listed in the ARMCPU cpreg_indexes list, write 2751 * its value from the ARMCPUState structure into the cpreg_values list. 2752 * This is used to copy info from TCG's working data structures into 2753 * KVM or for outbound migration. 2754 * 2755 * @kvm_sync is true if we are doing this in order to sync the 2756 * register state back to KVM. In this case we will only update 2757 * values in the list if the previous list->cpustate sync actually 2758 * successfully wrote the CPU state. Otherwise we will keep the value 2759 * that is in the list. 2760 * 2761 * Returns: true if all register values were read correctly, 2762 * false if some register was unknown or could not be read. 2763 * Note that we do not stop early on failure -- we will attempt 2764 * reading all registers in the list. 2765 */ 2766 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); 2767 2768 #define ARM_CPUID_TI915T 0x54029152 2769 #define ARM_CPUID_TI925T 0x54029252 2770 2771 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU 2772 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) 2773 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU 2774 2775 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU 2776 2777 #define cpu_list arm_cpu_list 2778 2779 /* ARM has the following "translation regimes" (as the ARM ARM calls them): 2780 * 2781 * If EL3 is 64-bit: 2782 * + NonSecure EL1 & 0 stage 1 2783 * + NonSecure EL1 & 0 stage 2 2784 * + NonSecure EL2 2785 * + NonSecure EL2 & 0 (ARMv8.1-VHE) 2786 * + Secure EL1 & 0 2787 * + Secure EL3 2788 * If EL3 is 32-bit: 2789 * + NonSecure PL1 & 0 stage 1 2790 * + NonSecure PL1 & 0 stage 2 2791 * + NonSecure PL2 2792 * + Secure PL0 2793 * + Secure PL1 2794 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) 2795 * 2796 * For QEMU, an mmu_idx is not quite the same as a translation regime because: 2797 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, 2798 * because they may differ in access permissions even if the VA->PA map is 2799 * the same 2800 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 2801 * translation, which means that we have one mmu_idx that deals with two 2802 * concatenated translation regimes [this sort of combined s1+2 TLB is 2803 * architecturally permitted] 2804 * 3. we don't need to allocate an mmu_idx to translations that we won't be 2805 * handling via the TLB. The only way to do a stage 1 translation without 2806 * the immediate stage 2 translation is via the ATS or AT system insns, 2807 * which can be slow-pathed and always do a page table walk. 2808 * The only use of stage 2 translations is either as part of an s1+2 2809 * lookup or when loading the descriptors during a stage 1 page table walk, 2810 * and in both those cases we don't use the TLB. 2811 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" 2812 * translation regimes, because they map reasonably well to each other 2813 * and they can't both be active at the same time. 2814 * 5. we want to be able to use the TLB for accesses done as part of a 2815 * stage1 page table walk, rather than having to walk the stage2 page 2816 * table over and over. 2817 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access 2818 * Never (PAN) bit within PSTATE. 2819 * 2820 * This gives us the following list of cases: 2821 * 2822 * NS EL0 EL1&0 stage 1+2 (aka NS PL0) 2823 * NS EL1 EL1&0 stage 1+2 (aka NS PL1) 2824 * NS EL1 EL1&0 stage 1+2 +PAN 2825 * NS EL0 EL2&0 2826 * NS EL2 EL2&0 2827 * NS EL2 EL2&0 +PAN 2828 * NS EL2 (aka NS PL2) 2829 * S EL0 EL1&0 (aka S PL0) 2830 * S EL1 EL1&0 (not used if EL3 is 32 bit) 2831 * S EL1 EL1&0 +PAN 2832 * S EL3 (aka S PL1) 2833 * 2834 * for a total of 11 different mmu_idx. 2835 * 2836 * R profile CPUs have an MPU, but can use the same set of MMU indexes 2837 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and 2838 * NS EL2 if we ever model a Cortex-R52). 2839 * 2840 * M profile CPUs are rather different as they do not have a true MMU. 2841 * They have the following different MMU indexes: 2842 * User 2843 * Privileged 2844 * User, execution priority negative (ie the MPU HFNMIENA bit may apply) 2845 * Privileged, execution priority negative (ditto) 2846 * If the CPU supports the v8M Security Extension then there are also: 2847 * Secure User 2848 * Secure Privileged 2849 * Secure User, execution priority negative 2850 * Secure Privileged, execution priority negative 2851 * 2852 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code 2853 * are not quite the same -- different CPU types (most notably M profile 2854 * vs A/R profile) would like to use MMU indexes with different semantics, 2855 * but since we don't ever need to use all of those in a single CPU we 2856 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU 2857 * modes + total number of M profile MMU modes". The lower bits of 2858 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always 2859 * the same for any particular CPU. 2860 * Variables of type ARMMUIdx are always full values, and the core 2861 * index values are in variables of type 'int'. 2862 * 2863 * Our enumeration includes at the end some entries which are not "true" 2864 * mmu_idx values in that they don't have corresponding TLBs and are only 2865 * valid for doing slow path page table walks. 2866 * 2867 * The constant names here are patterned after the general style of the names 2868 * of the AT/ATS operations. 2869 * The values used are carefully arranged to make mmu_idx => EL lookup easy. 2870 * For M profile we arrange them to have a bit for priv, a bit for negpri 2871 * and a bit for secure. 2872 */ 2873 #define ARM_MMU_IDX_A 0x10 /* A profile */ 2874 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ 2875 #define ARM_MMU_IDX_M 0x40 /* M profile */ 2876 2877 /* Meanings of the bits for A profile mmu idx values */ 2878 #define ARM_MMU_IDX_A_NS 0x8 2879 2880 /* Meanings of the bits for M profile mmu idx values */ 2881 #define ARM_MMU_IDX_M_PRIV 0x1 2882 #define ARM_MMU_IDX_M_NEGPRI 0x2 2883 #define ARM_MMU_IDX_M_S 0x4 /* Secure */ 2884 2885 #define ARM_MMU_IDX_TYPE_MASK \ 2886 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) 2887 #define ARM_MMU_IDX_COREIDX_MASK 0xf 2888 2889 typedef enum ARMMMUIdx { 2890 /* 2891 * A-profile. 2892 */ 2893 ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A, 2894 ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A, 2895 ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A, 2896 ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A, 2897 ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A, 2898 ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A, 2899 ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A, 2900 ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, 2901 2902 ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS, 2903 ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS, 2904 ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS, 2905 ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS, 2906 ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS, 2907 ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS, 2908 ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS, 2909 2910 /* 2911 * These are not allocated TLBs and are used only for AT system 2912 * instructions or for the first stage of an S12 page table walk. 2913 */ 2914 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, 2915 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, 2916 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, 2917 ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB, 2918 ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB, 2919 ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB, 2920 /* 2921 * Not allocated a TLB: used only for second stage of an S12 page 2922 * table walk, or for descriptor loads during first stage of an S1 2923 * page table walk. Note that if we ever want to have a TLB for this 2924 * then various TLB flush insns which currently are no-ops or flush 2925 * only stage 1 MMU indexes will need to change to flush stage 2. 2926 */ 2927 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB, 2928 ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB, 2929 2930 /* 2931 * M-profile. 2932 */ 2933 ARMMMUIdx_MUser = ARM_MMU_IDX_M, 2934 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, 2935 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, 2936 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, 2937 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, 2938 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, 2939 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, 2940 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, 2941 } ARMMMUIdx; 2942 2943 /* 2944 * Bit macros for the core-mmu-index values for each index, 2945 * for use when calling tlb_flush_by_mmuidx() and friends. 2946 */ 2947 #define TO_CORE_BIT(NAME) \ 2948 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) 2949 2950 typedef enum ARMMMUIdxBit { 2951 TO_CORE_BIT(E10_0), 2952 TO_CORE_BIT(E20_0), 2953 TO_CORE_BIT(E10_1), 2954 TO_CORE_BIT(E10_1_PAN), 2955 TO_CORE_BIT(E2), 2956 TO_CORE_BIT(E20_2), 2957 TO_CORE_BIT(E20_2_PAN), 2958 TO_CORE_BIT(SE10_0), 2959 TO_CORE_BIT(SE20_0), 2960 TO_CORE_BIT(SE10_1), 2961 TO_CORE_BIT(SE20_2), 2962 TO_CORE_BIT(SE10_1_PAN), 2963 TO_CORE_BIT(SE20_2_PAN), 2964 TO_CORE_BIT(SE2), 2965 TO_CORE_BIT(SE3), 2966 2967 TO_CORE_BIT(MUser), 2968 TO_CORE_BIT(MPriv), 2969 TO_CORE_BIT(MUserNegPri), 2970 TO_CORE_BIT(MPrivNegPri), 2971 TO_CORE_BIT(MSUser), 2972 TO_CORE_BIT(MSPriv), 2973 TO_CORE_BIT(MSUserNegPri), 2974 TO_CORE_BIT(MSPrivNegPri), 2975 } ARMMMUIdxBit; 2976 2977 #undef TO_CORE_BIT 2978 2979 #define MMU_USER_IDX 0 2980 2981 /* Indexes used when registering address spaces with cpu_address_space_init */ 2982 typedef enum ARMASIdx { 2983 ARMASIdx_NS = 0, 2984 ARMASIdx_S = 1, 2985 ARMASIdx_TagNS = 2, 2986 ARMASIdx_TagS = 3, 2987 } ARMASIdx; 2988 2989 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) 2990 { 2991 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and 2992 * CSSELR is RAZ/WI. 2993 */ 2994 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; 2995 } 2996 2997 static inline bool arm_sctlr_b(CPUARMState *env) 2998 { 2999 return 3000 /* We need not implement SCTLR.ITD in user-mode emulation, so 3001 * let linux-user ignore the fact that it conflicts with SCTLR_B. 3002 * This lets people run BE32 binaries with "-cpu any". 3003 */ 3004 #ifndef CONFIG_USER_ONLY 3005 !arm_feature(env, ARM_FEATURE_V7) && 3006 #endif 3007 (env->cp15.sctlr_el[1] & SCTLR_B) != 0; 3008 } 3009 3010 uint64_t arm_sctlr(CPUARMState *env, int el); 3011 3012 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, 3013 bool sctlr_b) 3014 { 3015 #ifdef CONFIG_USER_ONLY 3016 /* 3017 * In system mode, BE32 is modelled in line with the 3018 * architecture (as word-invariant big-endianness), where loads 3019 * and stores are done little endian but from addresses which 3020 * are adjusted by XORing with the appropriate constant. So the 3021 * endianness to use for the raw data access is not affected by 3022 * SCTLR.B. 3023 * In user mode, however, we model BE32 as byte-invariant 3024 * big-endianness (because user-only code cannot tell the 3025 * difference), and so we need to use a data access endianness 3026 * that depends on SCTLR.B. 3027 */ 3028 if (sctlr_b) { 3029 return true; 3030 } 3031 #endif 3032 /* In 32bit endianness is determined by looking at CPSR's E bit */ 3033 return env->uncached_cpsr & CPSR_E; 3034 } 3035 3036 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) 3037 { 3038 return sctlr & (el ? SCTLR_EE : SCTLR_E0E); 3039 } 3040 3041 /* Return true if the processor is in big-endian mode. */ 3042 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) 3043 { 3044 if (!is_a64(env)) { 3045 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); 3046 } else { 3047 int cur_el = arm_current_el(env); 3048 uint64_t sctlr = arm_sctlr(env, cur_el); 3049 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); 3050 } 3051 } 3052 3053 #include "exec/cpu-all.h" 3054 3055 /* 3056 * We have more than 32-bits worth of state per TB, so we split the data 3057 * between tb->flags and tb->cs_base, which is otherwise unused for ARM. 3058 * We collect these two parts in CPUARMTBFlags where they are named 3059 * flags and flags2 respectively. 3060 * 3061 * The flags that are shared between all execution modes, TBFLAG_ANY, 3062 * are stored in flags. The flags that are specific to a given mode 3063 * are stores in flags2. Since cs_base is sized on the configured 3064 * address size, flags2 always has 64-bits for A64, and a minimum of 3065 * 32-bits for A32 and M32. 3066 * 3067 * The bits for 32-bit A-profile and M-profile partially overlap: 3068 * 3069 * 31 23 11 10 0 3070 * +-------------+----------+----------------+ 3071 * | | | TBFLAG_A32 | 3072 * | TBFLAG_AM32 | +-----+----------+ 3073 * | | |TBFLAG_M32| 3074 * +-------------+----------------+----------+ 3075 * 31 23 6 5 0 3076 * 3077 * Unless otherwise noted, these bits are cached in env->hflags. 3078 */ 3079 FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1) 3080 FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1) 3081 FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */ 3082 FIELD(TBFLAG_ANY, BE_DATA, 3, 1) 3083 FIELD(TBFLAG_ANY, MMUIDX, 4, 4) 3084 /* Target EL if we take a floating-point-disabled exception */ 3085 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) 3086 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ 3087 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) 3088 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) 3089 3090 /* 3091 * Bit usage when in AArch32 state, both A- and M-profile. 3092 */ 3093 FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */ 3094 FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */ 3095 3096 /* 3097 * Bit usage when in AArch32 state, for A-profile only. 3098 */ 3099 FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */ 3100 FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */ 3101 /* 3102 * We store the bottom two bits of the CPAR as TB flags and handle 3103 * checks on the other bits at runtime. This shares the same bits as 3104 * VECSTRIDE, which is OK as no XScale CPU has VFP. 3105 * Not cached, because VECLEN+VECSTRIDE are not cached. 3106 */ 3107 FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2) 3108 FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */ 3109 FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */ 3110 FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1) 3111 /* 3112 * Indicates whether cp register reads and writes by guest code should access 3113 * the secure or nonsecure bank of banked registers; note that this is not 3114 * the same thing as the current security state of the processor! 3115 */ 3116 FIELD(TBFLAG_A32, NS, 10, 1) 3117 3118 /* 3119 * Bit usage when in AArch32 state, for M-profile only. 3120 */ 3121 /* Handler (ie not Thread) mode */ 3122 FIELD(TBFLAG_M32, HANDLER, 0, 1) 3123 /* Whether we should generate stack-limit checks */ 3124 FIELD(TBFLAG_M32, STACKCHECK, 1, 1) 3125 /* Set if FPCCR.LSPACT is set */ 3126 FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */ 3127 /* Set if we must create a new FP context */ 3128 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */ 3129 /* Set if FPCCR.S does not match current security state */ 3130 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */ 3131 /* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */ 3132 FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */ 3133 3134 /* 3135 * Bit usage when in AArch64 state 3136 */ 3137 FIELD(TBFLAG_A64, TBII, 0, 2) 3138 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) 3139 /* The current vector length, either NVL or SVL. */ 3140 FIELD(TBFLAG_A64, VL, 4, 4) 3141 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) 3142 FIELD(TBFLAG_A64, BT, 9, 1) 3143 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ 3144 FIELD(TBFLAG_A64, TBID, 12, 2) 3145 FIELD(TBFLAG_A64, UNPRIV, 14, 1) 3146 FIELD(TBFLAG_A64, ATA, 15, 1) 3147 FIELD(TBFLAG_A64, TCMA, 16, 2) 3148 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) 3149 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) 3150 3151 /* 3152 * Helpers for using the above. 3153 */ 3154 #define DP_TBFLAG_ANY(DST, WHICH, VAL) \ 3155 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL)) 3156 #define DP_TBFLAG_A64(DST, WHICH, VAL) \ 3157 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL)) 3158 #define DP_TBFLAG_A32(DST, WHICH, VAL) \ 3159 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL)) 3160 #define DP_TBFLAG_M32(DST, WHICH, VAL) \ 3161 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL)) 3162 #define DP_TBFLAG_AM32(DST, WHICH, VAL) \ 3163 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL)) 3164 3165 #define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH) 3166 #define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH) 3167 #define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH) 3168 #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) 3169 #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) 3170 3171 /** 3172 * cpu_mmu_index: 3173 * @env: The cpu environment 3174 * @ifetch: True for code access, false for data access. 3175 * 3176 * Return the core mmu index for the current translation regime. 3177 * This function is used by generic TCG code paths. 3178 */ 3179 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) 3180 { 3181 return EX_TBFLAG_ANY(env->hflags, MMUIDX); 3182 } 3183 3184 /** 3185 * sve_vq 3186 * @env: the cpu context 3187 * 3188 * Return the VL cached within env->hflags, in units of quadwords. 3189 */ 3190 static inline int sve_vq(CPUARMState *env) 3191 { 3192 return EX_TBFLAG_A64(env->hflags, VL) + 1; 3193 } 3194 3195 static inline bool bswap_code(bool sctlr_b) 3196 { 3197 #ifdef CONFIG_USER_ONLY 3198 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian. 3199 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0 3200 * would also end up as a mixed-endian mode with BE code, LE data. 3201 */ 3202 return 3203 #if TARGET_BIG_ENDIAN 3204 1 ^ 3205 #endif 3206 sctlr_b; 3207 #else 3208 /* All code access in ARM is little endian, and there are no loaders 3209 * doing swaps that need to be reversed 3210 */ 3211 return 0; 3212 #endif 3213 } 3214 3215 #ifdef CONFIG_USER_ONLY 3216 static inline bool arm_cpu_bswap_data(CPUARMState *env) 3217 { 3218 return 3219 #if TARGET_BIG_ENDIAN 3220 1 ^ 3221 #endif 3222 arm_cpu_data_is_big_endian(env); 3223 } 3224 #endif 3225 3226 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, 3227 target_ulong *cs_base, uint32_t *flags); 3228 3229 enum { 3230 QEMU_PSCI_CONDUIT_DISABLED = 0, 3231 QEMU_PSCI_CONDUIT_SMC = 1, 3232 QEMU_PSCI_CONDUIT_HVC = 2, 3233 }; 3234 3235 #ifndef CONFIG_USER_ONLY 3236 /* Return the address space index to use for a memory access */ 3237 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) 3238 { 3239 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; 3240 } 3241 3242 /* Return the AddressSpace to use for a memory access 3243 * (which depends on whether the access is S or NS, and whether 3244 * the board gave us a separate AddressSpace for S accesses). 3245 */ 3246 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) 3247 { 3248 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); 3249 } 3250 #endif 3251 3252 /** 3253 * arm_register_pre_el_change_hook: 3254 * Register a hook function which will be called immediately before this 3255 * CPU changes exception level or mode. The hook function will be 3256 * passed a pointer to the ARMCPU and the opaque data pointer passed 3257 * to this function when the hook was registered. 3258 * 3259 * Note that if a pre-change hook is called, any registered post-change hooks 3260 * are guaranteed to subsequently be called. 3261 */ 3262 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, 3263 void *opaque); 3264 /** 3265 * arm_register_el_change_hook: 3266 * Register a hook function which will be called immediately after this 3267 * CPU changes exception level or mode. The hook function will be 3268 * passed a pointer to the ARMCPU and the opaque data pointer passed 3269 * to this function when the hook was registered. 3270 * 3271 * Note that any registered hooks registered here are guaranteed to be called 3272 * if pre-change hooks have been. 3273 */ 3274 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void 3275 *opaque); 3276 3277 /** 3278 * arm_rebuild_hflags: 3279 * Rebuild the cached TBFLAGS for arbitrary changed processor state. 3280 */ 3281 void arm_rebuild_hflags(CPUARMState *env); 3282 3283 /** 3284 * aa32_vfp_dreg: 3285 * Return a pointer to the Dn register within env in 32-bit mode. 3286 */ 3287 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) 3288 { 3289 return &env->vfp.zregs[regno >> 1].d[regno & 1]; 3290 } 3291 3292 /** 3293 * aa32_vfp_qreg: 3294 * Return a pointer to the Qn register within env in 32-bit mode. 3295 */ 3296 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) 3297 { 3298 return &env->vfp.zregs[regno].d[0]; 3299 } 3300 3301 /** 3302 * aa64_vfp_qreg: 3303 * Return a pointer to the Qn register within env in 64-bit mode. 3304 */ 3305 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) 3306 { 3307 return &env->vfp.zregs[regno].d[0]; 3308 } 3309 3310 /* Shared between translate-sve.c and sve_helper.c. */ 3311 extern const uint64_t pred_esz_masks[4]; 3312 3313 /* Helper for the macros below, validating the argument type. */ 3314 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) 3315 { 3316 return x; 3317 } 3318 3319 /* 3320 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. 3321 * Using these should be a bit more self-documenting than using the 3322 * generic target bits directly. 3323 */ 3324 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) 3325 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) 3326 3327 /* 3328 * AArch64 usage of the PAGE_TARGET_* bits for linux-user. 3329 */ 3330 #define PAGE_BTI PAGE_TARGET_1 3331 #define PAGE_MTE PAGE_TARGET_2 3332 3333 #ifdef TARGET_TAGGED_ADDRESSES 3334 /** 3335 * cpu_untagged_addr: 3336 * @cs: CPU context 3337 * @x: tagged address 3338 * 3339 * Remove any address tag from @x. This is explicitly related to the 3340 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general. 3341 * 3342 * There should be a better place to put this, but we need this in 3343 * include/exec/cpu_ldst.h, and not some place linux-user specific. 3344 */ 3345 static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) 3346 { 3347 ARMCPU *cpu = ARM_CPU(cs); 3348 if (cpu->env.tagged_addr_enable) { 3349 /* 3350 * TBI is enabled for userspace but not kernelspace addresses. 3351 * Only clear the tag if bit 55 is clear. 3352 */ 3353 x &= sextract64(x, 0, 56); 3354 } 3355 return x; 3356 } 3357 #endif 3358 3359 /* 3360 * Naming convention for isar_feature functions: 3361 * Functions which test 32-bit ID registers should have _aa32_ in 3362 * their name. Functions which test 64-bit ID registers should have 3363 * _aa64_ in their name. These must only be used in code where we 3364 * know for certain that the CPU has AArch32 or AArch64 respectively 3365 * or where the correct answer for a CPU which doesn't implement that 3366 * CPU state is "false" (eg when generating A32 or A64 code, if adding 3367 * system registers that are specific to that CPU state, for "should 3368 * we let this system register bit be set" tests where the 32-bit 3369 * flavour of the register doesn't have the bit, and so on). 3370 * Functions which simply ask "does this feature exist at all" have 3371 * _any_ in their name, and always return the logical OR of the _aa64_ 3372 * and the _aa32_ function. 3373 */ 3374 3375 /* 3376 * 32-bit feature tests via id registers. 3377 */ 3378 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) 3379 { 3380 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; 3381 } 3382 3383 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) 3384 { 3385 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; 3386 } 3387 3388 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) 3389 { 3390 /* (M-profile) low-overhead loops and branch future */ 3391 return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; 3392 } 3393 3394 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) 3395 { 3396 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; 3397 } 3398 3399 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) 3400 { 3401 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; 3402 } 3403 3404 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) 3405 { 3406 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; 3407 } 3408 3409 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) 3410 { 3411 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; 3412 } 3413 3414 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) 3415 { 3416 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; 3417 } 3418 3419 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) 3420 { 3421 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; 3422 } 3423 3424 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) 3425 { 3426 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; 3427 } 3428 3429 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) 3430 { 3431 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; 3432 } 3433 3434 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) 3435 { 3436 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; 3437 } 3438 3439 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) 3440 { 3441 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; 3442 } 3443 3444 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 3445 { 3446 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; 3447 } 3448 3449 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 3450 { 3451 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; 3452 } 3453 3454 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) 3455 { 3456 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; 3457 } 3458 3459 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) 3460 { 3461 return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; 3462 } 3463 3464 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) 3465 { 3466 return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; 3467 } 3468 3469 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) 3470 { 3471 return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; 3472 } 3473 3474 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) 3475 { 3476 return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; 3477 } 3478 3479 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) 3480 { 3481 /* 3482 * Return true if M-profile state handling insns 3483 * (VSCCLRM, CLRM, FPCTX access insns) are implemented 3484 */ 3485 return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; 3486 } 3487 3488 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) 3489 { 3490 /* Sadly this is encoded differently for A-profile and M-profile */ 3491 if (isar_feature_aa32_mprofile(id)) { 3492 return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; 3493 } else { 3494 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; 3495 } 3496 } 3497 3498 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) 3499 { 3500 /* 3501 * Return true if MVE is supported (either integer or floating point). 3502 * We must check for M-profile as the MVFR1 field means something 3503 * else for A-profile. 3504 */ 3505 return isar_feature_aa32_mprofile(id) && 3506 FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; 3507 } 3508 3509 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) 3510 { 3511 /* 3512 * Return true if MVE is supported (either integer or floating point). 3513 * We must check for M-profile as the MVFR1 field means something 3514 * else for A-profile. 3515 */ 3516 return isar_feature_aa32_mprofile(id) && 3517 FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; 3518 } 3519 3520 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) 3521 { 3522 /* 3523 * Return true if either VFP or SIMD is implemented. 3524 * In this case, a minimum of VFP w/ D0-D15. 3525 */ 3526 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; 3527 } 3528 3529 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) 3530 { 3531 /* Return true if D16-D31 are implemented */ 3532 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; 3533 } 3534 3535 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) 3536 { 3537 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; 3538 } 3539 3540 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) 3541 { 3542 /* Return true if CPU supports single precision floating point, VFPv2 */ 3543 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; 3544 } 3545 3546 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) 3547 { 3548 /* Return true if CPU supports single precision floating point, VFPv3 */ 3549 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; 3550 } 3551 3552 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) 3553 { 3554 /* Return true if CPU supports double precision floating point, VFPv2 */ 3555 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; 3556 } 3557 3558 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) 3559 { 3560 /* Return true if CPU supports double precision floating point, VFPv3 */ 3561 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; 3562 } 3563 3564 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) 3565 { 3566 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); 3567 } 3568 3569 /* 3570 * We always set the FP and SIMD FP16 fields to indicate identical 3571 * levels of support (assuming SIMD is implemented at all), so 3572 * we only need one set of accessors. 3573 */ 3574 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) 3575 { 3576 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; 3577 } 3578 3579 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) 3580 { 3581 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; 3582 } 3583 3584 /* 3585 * Note that this ID register field covers both VFP and Neon FMAC, 3586 * so should usually be tested in combination with some other 3587 * check that confirms the presence of whichever of VFP or Neon is 3588 * relevant, to avoid accidentally enabling a Neon feature on 3589 * a VFP-no-Neon core or vice-versa. 3590 */ 3591 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) 3592 { 3593 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; 3594 } 3595 3596 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) 3597 { 3598 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; 3599 } 3600 3601 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) 3602 { 3603 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; 3604 } 3605 3606 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) 3607 { 3608 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; 3609 } 3610 3611 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) 3612 { 3613 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; 3614 } 3615 3616 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) 3617 { 3618 return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; 3619 } 3620 3621 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) 3622 { 3623 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; 3624 } 3625 3626 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) 3627 { 3628 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; 3629 } 3630 3631 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) 3632 { 3633 /* 0xf means "non-standard IMPDEF PMU" */ 3634 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && 3635 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3636 } 3637 3638 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) 3639 { 3640 /* 0xf means "non-standard IMPDEF PMU" */ 3641 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && 3642 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; 3643 } 3644 3645 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) 3646 { 3647 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; 3648 } 3649 3650 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) 3651 { 3652 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; 3653 } 3654 3655 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) 3656 { 3657 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; 3658 } 3659 3660 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) 3661 { 3662 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; 3663 } 3664 3665 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) 3666 { 3667 return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; 3668 } 3669 3670 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) 3671 { 3672 return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; 3673 } 3674 3675 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) 3676 { 3677 return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; 3678 } 3679 3680 /* 3681 * 64-bit feature tests via id registers. 3682 */ 3683 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) 3684 { 3685 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; 3686 } 3687 3688 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) 3689 { 3690 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; 3691 } 3692 3693 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) 3694 { 3695 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; 3696 } 3697 3698 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) 3699 { 3700 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; 3701 } 3702 3703 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) 3704 { 3705 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; 3706 } 3707 3708 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) 3709 { 3710 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; 3711 } 3712 3713 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) 3714 { 3715 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; 3716 } 3717 3718 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) 3719 { 3720 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; 3721 } 3722 3723 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) 3724 { 3725 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; 3726 } 3727 3728 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) 3729 { 3730 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; 3731 } 3732 3733 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) 3734 { 3735 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; 3736 } 3737 3738 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) 3739 { 3740 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; 3741 } 3742 3743 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 3744 { 3745 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; 3746 } 3747 3748 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 3749 { 3750 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; 3751 } 3752 3753 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) 3754 { 3755 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; 3756 } 3757 3758 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) 3759 { 3760 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; 3761 } 3762 3763 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) 3764 { 3765 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; 3766 } 3767 3768 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) 3769 { 3770 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; 3771 } 3772 3773 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 3774 { 3775 /* 3776 * Return true if any form of pauth is enabled, as this 3777 * predicate controls migration of the 128-bit keys. 3778 */ 3779 return (id->id_aa64isar1 & 3780 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | 3781 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | 3782 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | 3783 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; 3784 } 3785 3786 static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) 3787 { 3788 /* 3789 * Return true if pauth is enabled with the architected QARMA algorithm. 3790 * QEMU will always set APA+GPA to the same value. 3791 */ 3792 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; 3793 } 3794 3795 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) 3796 { 3797 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; 3798 } 3799 3800 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) 3801 { 3802 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; 3803 } 3804 3805 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 3806 { 3807 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; 3808 } 3809 3810 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) 3811 { 3812 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; 3813 } 3814 3815 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) 3816 { 3817 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; 3818 } 3819 3820 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) 3821 { 3822 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; 3823 } 3824 3825 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) 3826 { 3827 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; 3828 } 3829 3830 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) 3831 { 3832 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; 3833 } 3834 3835 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) 3836 { 3837 /* We always set the AdvSIMD and FP fields identically. */ 3838 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; 3839 } 3840 3841 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) 3842 { 3843 /* We always set the AdvSIMD and FP fields identically wrt FP16. */ 3844 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; 3845 } 3846 3847 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) 3848 { 3849 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; 3850 } 3851 3852 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) 3853 { 3854 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; 3855 } 3856 3857 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) 3858 { 3859 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; 3860 } 3861 3862 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) 3863 { 3864 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; 3865 } 3866 3867 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) 3868 { 3869 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; 3870 } 3871 3872 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) 3873 { 3874 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; 3875 } 3876 3877 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) 3878 { 3879 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; 3880 } 3881 3882 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) 3883 { 3884 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; 3885 } 3886 3887 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) 3888 { 3889 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; 3890 } 3891 3892 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) 3893 { 3894 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; 3895 } 3896 3897 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) 3898 { 3899 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; 3900 } 3901 3902 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) 3903 { 3904 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; 3905 } 3906 3907 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) 3908 { 3909 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; 3910 } 3911 3912 static inline bool isar_feature_aa64_st(const ARMISARegisters *id) 3913 { 3914 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; 3915 } 3916 3917 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) 3918 { 3919 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; 3920 } 3921 3922 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) 3923 { 3924 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; 3925 } 3926 3927 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) 3928 { 3929 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; 3930 } 3931 3932 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) 3933 { 3934 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; 3935 } 3936 3937 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) 3938 { 3939 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; 3940 } 3941 3942 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) 3943 { 3944 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; 3945 } 3946 3947 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) 3948 { 3949 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && 3950 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3951 } 3952 3953 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) 3954 { 3955 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && 3956 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; 3957 } 3958 3959 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) 3960 { 3961 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; 3962 } 3963 3964 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) 3965 { 3966 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; 3967 } 3968 3969 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) 3970 { 3971 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; 3972 } 3973 3974 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) 3975 { 3976 return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; 3977 } 3978 3979 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) 3980 { 3981 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); 3982 return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); 3983 } 3984 3985 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) 3986 { 3987 return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; 3988 } 3989 3990 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) 3991 { 3992 unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); 3993 return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); 3994 } 3995 3996 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) 3997 { 3998 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; 3999 } 4000 4001 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) 4002 { 4003 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; 4004 } 4005 4006 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) 4007 { 4008 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; 4009 } 4010 4011 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) 4012 { 4013 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; 4014 } 4015 4016 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) 4017 { 4018 int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); 4019 if (key >= 2) { 4020 return true; /* FEAT_CSV2_2 */ 4021 } 4022 if (key == 1) { 4023 key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); 4024 return key >= 2; /* FEAT_CSV2_1p2 */ 4025 } 4026 return false; 4027 } 4028 4029 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) 4030 { 4031 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; 4032 } 4033 4034 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) 4035 { 4036 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; 4037 } 4038 4039 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) 4040 { 4041 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; 4042 } 4043 4044 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) 4045 { 4046 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; 4047 } 4048 4049 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) 4050 { 4051 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; 4052 } 4053 4054 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) 4055 { 4056 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; 4057 } 4058 4059 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) 4060 { 4061 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; 4062 } 4063 4064 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) 4065 { 4066 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; 4067 } 4068 4069 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) 4070 { 4071 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; 4072 } 4073 4074 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) 4075 { 4076 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; 4077 } 4078 4079 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) 4080 { 4081 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; 4082 } 4083 4084 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) 4085 { 4086 return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; 4087 } 4088 4089 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) 4090 { 4091 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); 4092 } 4093 4094 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) 4095 { 4096 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; 4097 } 4098 4099 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) 4100 { 4101 return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); 4102 } 4103 4104 /* 4105 * Feature tests for "does this exist in either 32-bit or 64-bit?" 4106 */ 4107 static inline bool isar_feature_any_fp16(const ARMISARegisters *id) 4108 { 4109 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); 4110 } 4111 4112 static inline bool isar_feature_any_predinv(const ARMISARegisters *id) 4113 { 4114 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); 4115 } 4116 4117 static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) 4118 { 4119 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); 4120 } 4121 4122 static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) 4123 { 4124 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); 4125 } 4126 4127 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) 4128 { 4129 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); 4130 } 4131 4132 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) 4133 { 4134 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); 4135 } 4136 4137 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) 4138 { 4139 return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); 4140 } 4141 4142 static inline bool isar_feature_any_ras(const ARMISARegisters *id) 4143 { 4144 return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); 4145 } 4146 4147 /* 4148 * Forward to the above feature tests given an ARMCPU pointer. 4149 */ 4150 #define cpu_isar_feature(name, cpu) \ 4151 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) 4152 4153 #endif 4154