1671efad1SFabiano Rosas /* 2671efad1SFabiano Rosas * ARM hflags 3671efad1SFabiano Rosas * 4671efad1SFabiano Rosas * This code is licensed under the GNU GPL v2 or later. 5671efad1SFabiano Rosas * 6671efad1SFabiano Rosas * SPDX-License-Identifier: GPL-2.0-or-later 7671efad1SFabiano Rosas */ 8671efad1SFabiano Rosas #include "qemu/osdep.h" 9671efad1SFabiano Rosas #include "cpu.h" 10671efad1SFabiano Rosas #include "internals.h" 115a534314SPeter Maydell #include "cpu-features.h" 12671efad1SFabiano Rosas #include "exec/helper-proto.h" 13671efad1SFabiano Rosas #include "cpregs.h" 14671efad1SFabiano Rosas 15671efad1SFabiano Rosas static inline bool fgt_svc(CPUARMState *env, int el) 16671efad1SFabiano Rosas { 17671efad1SFabiano Rosas /* 18671efad1SFabiano Rosas * Assuming fine-grained-traps are active, return true if we 19671efad1SFabiano Rosas * should be trapping on SVC instructions. Only AArch64 can 20671efad1SFabiano Rosas * trap on an SVC at EL1, but we don't need to special-case this 21671efad1SFabiano Rosas * because if this is AArch32 EL1 then arm_fgt_active() is false. 22671efad1SFabiano Rosas * We also know el is 0 or 1. 23671efad1SFabiano Rosas */ 24671efad1SFabiano Rosas return el == 0 ? 25671efad1SFabiano Rosas FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : 26671efad1SFabiano Rosas FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); 27671efad1SFabiano Rosas } 28671efad1SFabiano Rosas 29671efad1SFabiano Rosas static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, 30671efad1SFabiano Rosas ARMMMUIdx mmu_idx, 31671efad1SFabiano Rosas CPUARMTBFlags flags) 32671efad1SFabiano Rosas { 33671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); 34671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); 35671efad1SFabiano Rosas 36671efad1SFabiano Rosas if (arm_singlestep_active(env)) { 37671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); 38671efad1SFabiano Rosas } 39671efad1SFabiano Rosas 40671efad1SFabiano Rosas return flags; 41671efad1SFabiano Rosas } 42671efad1SFabiano Rosas 43671efad1SFabiano Rosas static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, 44671efad1SFabiano Rosas ARMMMUIdx mmu_idx, 45671efad1SFabiano Rosas CPUARMTBFlags flags) 46671efad1SFabiano Rosas { 47671efad1SFabiano Rosas bool sctlr_b = arm_sctlr_b(env); 48671efad1SFabiano Rosas 49671efad1SFabiano Rosas if (sctlr_b) { 50671efad1SFabiano Rosas DP_TBFLAG_A32(flags, SCTLR__B, 1); 51671efad1SFabiano Rosas } 52671efad1SFabiano Rosas if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { 53671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, BE_DATA, 1); 54671efad1SFabiano Rosas } 55671efad1SFabiano Rosas DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); 56671efad1SFabiano Rosas 57671efad1SFabiano Rosas return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 58671efad1SFabiano Rosas } 59671efad1SFabiano Rosas 60671efad1SFabiano Rosas static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, 61671efad1SFabiano Rosas ARMMMUIdx mmu_idx) 62671efad1SFabiano Rosas { 63671efad1SFabiano Rosas CPUARMTBFlags flags = {}; 64671efad1SFabiano Rosas uint32_t ccr = env->v7m.ccr[env->v7m.secure]; 65671efad1SFabiano Rosas 66671efad1SFabiano Rosas /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ 67671efad1SFabiano Rosas if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { 68671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 69671efad1SFabiano Rosas } 70671efad1SFabiano Rosas 71671efad1SFabiano Rosas if (arm_v7m_is_handler_mode(env)) { 72671efad1SFabiano Rosas DP_TBFLAG_M32(flags, HANDLER, 1); 73671efad1SFabiano Rosas } 74671efad1SFabiano Rosas 75671efad1SFabiano Rosas /* 76671efad1SFabiano Rosas * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN 77671efad1SFabiano Rosas * is suppressing them because the requested execution priority 78671efad1SFabiano Rosas * is less than 0. 79671efad1SFabiano Rosas */ 80671efad1SFabiano Rosas if (arm_feature(env, ARM_FEATURE_V8) && 81671efad1SFabiano Rosas !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && 82671efad1SFabiano Rosas (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { 83671efad1SFabiano Rosas DP_TBFLAG_M32(flags, STACKCHECK, 1); 84671efad1SFabiano Rosas } 85671efad1SFabiano Rosas 86671efad1SFabiano Rosas if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { 87671efad1SFabiano Rosas DP_TBFLAG_M32(flags, SECURE, 1); 88671efad1SFabiano Rosas } 89671efad1SFabiano Rosas 90671efad1SFabiano Rosas return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 91671efad1SFabiano Rosas } 92671efad1SFabiano Rosas 93671efad1SFabiano Rosas /* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ 94671efad1SFabiano Rosas static bool sme_fa64(CPUARMState *env, int el) 95671efad1SFabiano Rosas { 96671efad1SFabiano Rosas if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { 97671efad1SFabiano Rosas return false; 98671efad1SFabiano Rosas } 99671efad1SFabiano Rosas 100671efad1SFabiano Rosas if (el <= 1 && !el_is_in_host(env, el)) { 101671efad1SFabiano Rosas if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { 102671efad1SFabiano Rosas return false; 103671efad1SFabiano Rosas } 104671efad1SFabiano Rosas } 105671efad1SFabiano Rosas if (el <= 2 && arm_is_el2_enabled(env)) { 106671efad1SFabiano Rosas if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { 107671efad1SFabiano Rosas return false; 108671efad1SFabiano Rosas } 109671efad1SFabiano Rosas } 110671efad1SFabiano Rosas if (arm_feature(env, ARM_FEATURE_EL3)) { 111671efad1SFabiano Rosas if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { 112671efad1SFabiano Rosas return false; 113671efad1SFabiano Rosas } 114671efad1SFabiano Rosas } 115671efad1SFabiano Rosas 116671efad1SFabiano Rosas return true; 117671efad1SFabiano Rosas } 118671efad1SFabiano Rosas 119671efad1SFabiano Rosas static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, 120671efad1SFabiano Rosas ARMMMUIdx mmu_idx) 121671efad1SFabiano Rosas { 122671efad1SFabiano Rosas CPUARMTBFlags flags = {}; 123671efad1SFabiano Rosas int el = arm_current_el(env); 124671efad1SFabiano Rosas 125671efad1SFabiano Rosas if (arm_sctlr(env, el) & SCTLR_A) { 126671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 127671efad1SFabiano Rosas } 128671efad1SFabiano Rosas 129671efad1SFabiano Rosas if (arm_el_is_aa64(env, 1)) { 130671efad1SFabiano Rosas DP_TBFLAG_A32(flags, VFPEN, 1); 131671efad1SFabiano Rosas } 132671efad1SFabiano Rosas 133671efad1SFabiano Rosas if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && 134671efad1SFabiano Rosas (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { 135671efad1SFabiano Rosas DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); 136671efad1SFabiano Rosas } 137671efad1SFabiano Rosas 138671efad1SFabiano Rosas if (arm_fgt_active(env, el)) { 139671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); 140671efad1SFabiano Rosas if (fgt_svc(env, el)) { 141671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, FGT_SVC, 1); 142671efad1SFabiano Rosas } 143671efad1SFabiano Rosas } 144671efad1SFabiano Rosas 145671efad1SFabiano Rosas if (env->uncached_cpsr & CPSR_IL) { 146671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 147671efad1SFabiano Rosas } 148671efad1SFabiano Rosas 149671efad1SFabiano Rosas /* 150671efad1SFabiano Rosas * The SME exception we are testing for is raised via 151671efad1SFabiano Rosas * AArch64.CheckFPAdvSIMDEnabled(), as called from 152671efad1SFabiano Rosas * AArch32.CheckAdvSIMDOrFPEnabled(). 153671efad1SFabiano Rosas */ 154671efad1SFabiano Rosas if (el == 0 155671efad1SFabiano Rosas && FIELD_EX64(env->svcr, SVCR, SM) 156671efad1SFabiano Rosas && (!arm_is_el2_enabled(env) 157671efad1SFabiano Rosas || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) 158671efad1SFabiano Rosas && arm_el_is_aa64(env, 1) 159671efad1SFabiano Rosas && !sme_fa64(env, el)) { 160671efad1SFabiano Rosas DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); 161671efad1SFabiano Rosas } 162671efad1SFabiano Rosas 163671efad1SFabiano Rosas return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); 164671efad1SFabiano Rosas } 165671efad1SFabiano Rosas 166671efad1SFabiano Rosas static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, 167671efad1SFabiano Rosas ARMMMUIdx mmu_idx) 168671efad1SFabiano Rosas { 169671efad1SFabiano Rosas CPUARMTBFlags flags = {}; 170671efad1SFabiano Rosas ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); 171671efad1SFabiano Rosas uint64_t tcr = regime_tcr(env, mmu_idx); 172e37e98b7SPeter Maydell uint64_t hcr = arm_hcr_el2_eff(env); 173671efad1SFabiano Rosas uint64_t sctlr; 174671efad1SFabiano Rosas int tbii, tbid; 175671efad1SFabiano Rosas 176671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); 177671efad1SFabiano Rosas 178671efad1SFabiano Rosas /* Get control bits for tagged addresses. */ 179671efad1SFabiano Rosas tbid = aa64_va_parameter_tbi(tcr, mmu_idx); 180671efad1SFabiano Rosas tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); 181671efad1SFabiano Rosas 182671efad1SFabiano Rosas DP_TBFLAG_A64(flags, TBII, tbii); 183671efad1SFabiano Rosas DP_TBFLAG_A64(flags, TBID, tbid); 184671efad1SFabiano Rosas 185671efad1SFabiano Rosas if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { 186671efad1SFabiano Rosas int sve_el = sve_exception_el(env, el); 187671efad1SFabiano Rosas 188671efad1SFabiano Rosas /* 189671efad1SFabiano Rosas * If either FP or SVE are disabled, translator does not need len. 190671efad1SFabiano Rosas * If SVE EL > FP EL, FP exception has precedence, and translator 191671efad1SFabiano Rosas * does not need SVE EL. Save potential re-translations by forcing 192671efad1SFabiano Rosas * the unneeded data to zero. 193671efad1SFabiano Rosas */ 194671efad1SFabiano Rosas if (fp_el != 0) { 195671efad1SFabiano Rosas if (sve_el > fp_el) { 196671efad1SFabiano Rosas sve_el = 0; 197671efad1SFabiano Rosas } 198671efad1SFabiano Rosas } else if (sve_el == 0) { 199671efad1SFabiano Rosas DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); 200671efad1SFabiano Rosas } 201671efad1SFabiano Rosas DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); 202671efad1SFabiano Rosas } 203671efad1SFabiano Rosas if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { 204671efad1SFabiano Rosas int sme_el = sme_exception_el(env, el); 205671efad1SFabiano Rosas bool sm = FIELD_EX64(env->svcr, SVCR, SM); 206671efad1SFabiano Rosas 207671efad1SFabiano Rosas DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); 208671efad1SFabiano Rosas if (sme_el == 0) { 209671efad1SFabiano Rosas /* Similarly, do not compute SVL if SME is disabled. */ 210671efad1SFabiano Rosas int svl = sve_vqm1_for_el_sm(env, el, true); 211671efad1SFabiano Rosas DP_TBFLAG_A64(flags, SVL, svl); 212671efad1SFabiano Rosas if (sm) { 213671efad1SFabiano Rosas /* If SVE is disabled, we will not have set VL above. */ 214671efad1SFabiano Rosas DP_TBFLAG_A64(flags, VL, svl); 215671efad1SFabiano Rosas } 216671efad1SFabiano Rosas } 217671efad1SFabiano Rosas if (sm) { 218671efad1SFabiano Rosas DP_TBFLAG_A64(flags, PSTATE_SM, 1); 219671efad1SFabiano Rosas DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); 220671efad1SFabiano Rosas } 221671efad1SFabiano Rosas DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); 222671efad1SFabiano Rosas } 223671efad1SFabiano Rosas 224671efad1SFabiano Rosas sctlr = regime_sctlr(env, stage1); 225671efad1SFabiano Rosas 226671efad1SFabiano Rosas if (sctlr & SCTLR_A) { 227671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); 228671efad1SFabiano Rosas } 229671efad1SFabiano Rosas 230671efad1SFabiano Rosas if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { 231671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, BE_DATA, 1); 232671efad1SFabiano Rosas } 233671efad1SFabiano Rosas 234671efad1SFabiano Rosas if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { 235671efad1SFabiano Rosas /* 236671efad1SFabiano Rosas * In order to save space in flags, we record only whether 237671efad1SFabiano Rosas * pauth is "inactive", meaning all insns are implemented as 238671efad1SFabiano Rosas * a nop, or "active" when some action must be performed. 239671efad1SFabiano Rosas * The decision of which action to take is left to a helper. 240671efad1SFabiano Rosas */ 241671efad1SFabiano Rosas if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { 242671efad1SFabiano Rosas DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); 243671efad1SFabiano Rosas } 244671efad1SFabiano Rosas } 245671efad1SFabiano Rosas 246671efad1SFabiano Rosas if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { 247671efad1SFabiano Rosas /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ 248671efad1SFabiano Rosas if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { 249671efad1SFabiano Rosas DP_TBFLAG_A64(flags, BT, 1); 250671efad1SFabiano Rosas } 251671efad1SFabiano Rosas } 252671efad1SFabiano Rosas 25383f624d9SRichard Henderson if (cpu_isar_feature(aa64_lse2, env_archcpu(env))) { 25483f624d9SRichard Henderson if (sctlr & SCTLR_nAA) { 25583f624d9SRichard Henderson DP_TBFLAG_A64(flags, NAA, 1); 25683f624d9SRichard Henderson } 25783f624d9SRichard Henderson } 25883f624d9SRichard Henderson 259671efad1SFabiano Rosas /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ 260671efad1SFabiano Rosas if (!(env->pstate & PSTATE_UAO)) { 261671efad1SFabiano Rosas switch (mmu_idx) { 262671efad1SFabiano Rosas case ARMMMUIdx_E10_1: 263671efad1SFabiano Rosas case ARMMMUIdx_E10_1_PAN: 264671efad1SFabiano Rosas /* TODO: ARMv8.3-NV */ 265671efad1SFabiano Rosas DP_TBFLAG_A64(flags, UNPRIV, 1); 266671efad1SFabiano Rosas break; 267671efad1SFabiano Rosas case ARMMMUIdx_E20_2: 268671efad1SFabiano Rosas case ARMMMUIdx_E20_2_PAN: 269671efad1SFabiano Rosas /* 270671efad1SFabiano Rosas * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is 271671efad1SFabiano Rosas * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. 272671efad1SFabiano Rosas */ 273671efad1SFabiano Rosas if (env->cp15.hcr_el2 & HCR_TGE) { 274671efad1SFabiano Rosas DP_TBFLAG_A64(flags, UNPRIV, 1); 275671efad1SFabiano Rosas } 276671efad1SFabiano Rosas break; 277671efad1SFabiano Rosas default: 278671efad1SFabiano Rosas break; 279671efad1SFabiano Rosas } 280671efad1SFabiano Rosas } 281671efad1SFabiano Rosas 282671efad1SFabiano Rosas if (env->pstate & PSTATE_IL) { 283671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, PSTATE__IL, 1); 284671efad1SFabiano Rosas } 285671efad1SFabiano Rosas 286671efad1SFabiano Rosas if (arm_fgt_active(env, el)) { 287671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); 288671efad1SFabiano Rosas if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { 289e37e98b7SPeter Maydell DP_TBFLAG_A64(flags, TRAP_ERET, 1); 290671efad1SFabiano Rosas } 291671efad1SFabiano Rosas if (fgt_svc(env, el)) { 292671efad1SFabiano Rosas DP_TBFLAG_ANY(flags, FGT_SVC, 1); 293671efad1SFabiano Rosas } 294671efad1SFabiano Rosas } 295671efad1SFabiano Rosas 296e37e98b7SPeter Maydell /* 297e37e98b7SPeter Maydell * ERET can also be trapped for FEAT_NV. arm_hcr_el2_eff() takes care 298e37e98b7SPeter Maydell * of "is EL2 enabled" and the NV bit can only be set if FEAT_NV is present. 299e37e98b7SPeter Maydell */ 300e37e98b7SPeter Maydell if (el == 1 && (hcr & HCR_NV)) { 301e37e98b7SPeter Maydell DP_TBFLAG_A64(flags, TRAP_ERET, 1); 302e37e98b7SPeter Maydell } 303e37e98b7SPeter Maydell 304671efad1SFabiano Rosas if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { 305671efad1SFabiano Rosas /* 306671efad1SFabiano Rosas * Set MTE_ACTIVE if any access may be Checked, and leave clear 307671efad1SFabiano Rosas * if all accesses must be Unchecked: 308671efad1SFabiano Rosas * 1) If no TBI, then there are no tags in the address to check, 309671efad1SFabiano Rosas * 2) If Tag Check Override, then all accesses are Unchecked, 310671efad1SFabiano Rosas * 3) If Tag Check Fail == 0, then Checked access have no effect, 311671efad1SFabiano Rosas * 4) If no Allocation Tag Access, then all accesses are Unchecked. 312671efad1SFabiano Rosas */ 313671efad1SFabiano Rosas if (allocation_tag_access_enabled(env, el, sctlr)) { 314671efad1SFabiano Rosas DP_TBFLAG_A64(flags, ATA, 1); 315671efad1SFabiano Rosas if (tbid 316671efad1SFabiano Rosas && !(env->pstate & PSTATE_TCO) 317671efad1SFabiano Rosas && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { 318671efad1SFabiano Rosas DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); 319903dbefcSPeter Maydell if (!EX_TBFLAG_A64(flags, UNPRIV)) { 320903dbefcSPeter Maydell /* 321903dbefcSPeter Maydell * In non-unpriv contexts (eg EL0), unpriv load/stores 322903dbefcSPeter Maydell * act like normal ones; duplicate the MTE info to 323903dbefcSPeter Maydell * avoid translate-a64.c having to check UNPRIV to see 324903dbefcSPeter Maydell * whether it is OK to index into MTE_ACTIVE[]. 325903dbefcSPeter Maydell */ 326903dbefcSPeter Maydell DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); 327903dbefcSPeter Maydell } 328671efad1SFabiano Rosas } 329671efad1SFabiano Rosas } 330671efad1SFabiano Rosas /* And again for unprivileged accesses, if required. */ 331671efad1SFabiano Rosas if (EX_TBFLAG_A64(flags, UNPRIV) 332671efad1SFabiano Rosas && tbid 333671efad1SFabiano Rosas && !(env->pstate & PSTATE_TCO) 334671efad1SFabiano Rosas && (sctlr & SCTLR_TCF0) 335671efad1SFabiano Rosas && allocation_tag_access_enabled(env, 0, sctlr)) { 336671efad1SFabiano Rosas DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); 337671efad1SFabiano Rosas } 338179e9a3bSPeter Maydell /* 33951464c56SMichael Tokarev * For unpriv tag-setting accesses we also need ATA0. Again, in 340179e9a3bSPeter Maydell * contexts where unpriv and normal insns are the same we 341179e9a3bSPeter Maydell * duplicate the ATA bit to save effort for translate-a64.c. 342179e9a3bSPeter Maydell */ 343179e9a3bSPeter Maydell if (EX_TBFLAG_A64(flags, UNPRIV)) { 344179e9a3bSPeter Maydell if (allocation_tag_access_enabled(env, 0, sctlr)) { 345179e9a3bSPeter Maydell DP_TBFLAG_A64(flags, ATA0, 1); 346179e9a3bSPeter Maydell } 347179e9a3bSPeter Maydell } else { 348179e9a3bSPeter Maydell DP_TBFLAG_A64(flags, ATA0, EX_TBFLAG_A64(flags, ATA)); 349179e9a3bSPeter Maydell } 350671efad1SFabiano Rosas /* Cache TCMA as well as TBI. */ 351671efad1SFabiano Rosas DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); 352671efad1SFabiano Rosas } 353671efad1SFabiano Rosas 354671efad1SFabiano Rosas return rebuild_hflags_common(env, fp_el, mmu_idx, flags); 355671efad1SFabiano Rosas } 356671efad1SFabiano Rosas 357671efad1SFabiano Rosas static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) 358671efad1SFabiano Rosas { 359671efad1SFabiano Rosas int el = arm_current_el(env); 360671efad1SFabiano Rosas int fp_el = fp_exception_el(env, el); 361671efad1SFabiano Rosas ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 362671efad1SFabiano Rosas 363671efad1SFabiano Rosas if (is_a64(env)) { 364671efad1SFabiano Rosas return rebuild_hflags_a64(env, el, fp_el, mmu_idx); 365671efad1SFabiano Rosas } else if (arm_feature(env, ARM_FEATURE_M)) { 366671efad1SFabiano Rosas return rebuild_hflags_m32(env, fp_el, mmu_idx); 367671efad1SFabiano Rosas } else { 368671efad1SFabiano Rosas return rebuild_hflags_a32(env, fp_el, mmu_idx); 369671efad1SFabiano Rosas } 370671efad1SFabiano Rosas } 371671efad1SFabiano Rosas 372671efad1SFabiano Rosas void arm_rebuild_hflags(CPUARMState *env) 373671efad1SFabiano Rosas { 374671efad1SFabiano Rosas env->hflags = rebuild_hflags_internal(env); 375671efad1SFabiano Rosas } 376671efad1SFabiano Rosas 377671efad1SFabiano Rosas /* 378671efad1SFabiano Rosas * If we have triggered a EL state change we can't rely on the 379671efad1SFabiano Rosas * translator having passed it to us, we need to recompute. 380671efad1SFabiano Rosas */ 381671efad1SFabiano Rosas void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) 382671efad1SFabiano Rosas { 383671efad1SFabiano Rosas int el = arm_current_el(env); 384671efad1SFabiano Rosas int fp_el = fp_exception_el(env, el); 385671efad1SFabiano Rosas ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 386671efad1SFabiano Rosas 387671efad1SFabiano Rosas env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 388671efad1SFabiano Rosas } 389671efad1SFabiano Rosas 390671efad1SFabiano Rosas void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) 391671efad1SFabiano Rosas { 392671efad1SFabiano Rosas int fp_el = fp_exception_el(env, el); 393671efad1SFabiano Rosas ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 394671efad1SFabiano Rosas 395671efad1SFabiano Rosas env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); 396671efad1SFabiano Rosas } 397671efad1SFabiano Rosas 398671efad1SFabiano Rosas /* 399671efad1SFabiano Rosas * If we have triggered a EL state change we can't rely on the 400671efad1SFabiano Rosas * translator having passed it to us, we need to recompute. 401671efad1SFabiano Rosas */ 402671efad1SFabiano Rosas void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) 403671efad1SFabiano Rosas { 404671efad1SFabiano Rosas int el = arm_current_el(env); 405671efad1SFabiano Rosas int fp_el = fp_exception_el(env, el); 406671efad1SFabiano Rosas ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 407671efad1SFabiano Rosas env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 408671efad1SFabiano Rosas } 409671efad1SFabiano Rosas 410671efad1SFabiano Rosas void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) 411671efad1SFabiano Rosas { 412671efad1SFabiano Rosas int fp_el = fp_exception_el(env, el); 413671efad1SFabiano Rosas ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 414671efad1SFabiano Rosas 415671efad1SFabiano Rosas env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); 416671efad1SFabiano Rosas } 417671efad1SFabiano Rosas 418671efad1SFabiano Rosas void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) 419671efad1SFabiano Rosas { 420671efad1SFabiano Rosas int fp_el = fp_exception_el(env, el); 421671efad1SFabiano Rosas ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); 422671efad1SFabiano Rosas 423671efad1SFabiano Rosas env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); 424671efad1SFabiano Rosas } 425671efad1SFabiano Rosas 426671efad1SFabiano Rosas void assert_hflags_rebuild_correctly(CPUARMState *env) 427671efad1SFabiano Rosas { 428671efad1SFabiano Rosas #ifdef CONFIG_DEBUG_TCG 429671efad1SFabiano Rosas CPUARMTBFlags c = env->hflags; 430671efad1SFabiano Rosas CPUARMTBFlags r = rebuild_hflags_internal(env); 431671efad1SFabiano Rosas 432671efad1SFabiano Rosas if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { 433671efad1SFabiano Rosas fprintf(stderr, "TCG hflags mismatch " 434671efad1SFabiano Rosas "(current:(0x%08x,0x" TARGET_FMT_lx ")" 435671efad1SFabiano Rosas " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", 436671efad1SFabiano Rosas c.flags, c.flags2, r.flags, r.flags2); 437671efad1SFabiano Rosas abort(); 438671efad1SFabiano Rosas } 439671efad1SFabiano Rosas #endif 440671efad1SFabiano Rosas } 441