1 /* 2 * ARM VFP floating-point operations 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/helper-proto.h" 23 #include "internals.h" 24 #include "cpu-features.h" 25 #ifdef CONFIG_TCG 26 #include "qemu/log.h" 27 #include "fpu/softfloat.h" 28 #endif 29 30 /* VFP support. We follow the convention used for VFP instructions: 31 Single precision routines have a "s" suffix, double precision a 32 "d" suffix. */ 33 34 #ifdef CONFIG_TCG 35 36 /* Convert host exception flags to vfp form. */ 37 static inline int vfp_exceptbits_from_host(int host_bits) 38 { 39 int target_bits = 0; 40 41 if (host_bits & float_flag_invalid) { 42 target_bits |= 1; 43 } 44 if (host_bits & float_flag_divbyzero) { 45 target_bits |= 2; 46 } 47 if (host_bits & float_flag_overflow) { 48 target_bits |= 4; 49 } 50 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { 51 target_bits |= 8; 52 } 53 if (host_bits & float_flag_inexact) { 54 target_bits |= 0x10; 55 } 56 if (host_bits & float_flag_input_denormal) { 57 target_bits |= 0x80; 58 } 59 return target_bits; 60 } 61 62 /* Convert vfp exception flags to target form. */ 63 static inline int vfp_exceptbits_to_host(int target_bits) 64 { 65 int host_bits = 0; 66 67 if (target_bits & 1) { 68 host_bits |= float_flag_invalid; 69 } 70 if (target_bits & 2) { 71 host_bits |= float_flag_divbyzero; 72 } 73 if (target_bits & 4) { 74 host_bits |= float_flag_overflow; 75 } 76 if (target_bits & 8) { 77 host_bits |= float_flag_underflow; 78 } 79 if (target_bits & 0x10) { 80 host_bits |= float_flag_inexact; 81 } 82 if (target_bits & 0x80) { 83 host_bits |= float_flag_input_denormal; 84 } 85 return host_bits; 86 } 87 88 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) 89 { 90 uint32_t i; 91 92 i = get_float_exception_flags(&env->vfp.fp_status); 93 i |= get_float_exception_flags(&env->vfp.standard_fp_status); 94 /* FZ16 does not generate an input denormal exception. */ 95 i |= (get_float_exception_flags(&env->vfp.fp_status_f16) 96 & ~float_flag_input_denormal); 97 i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16) 98 & ~float_flag_input_denormal); 99 return vfp_exceptbits_from_host(i); 100 } 101 102 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) 103 { 104 int i; 105 uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR]; 106 107 changed ^= val; 108 if (changed & (3 << 22)) { 109 i = (val >> 22) & 3; 110 switch (i) { 111 case FPROUNDING_TIEEVEN: 112 i = float_round_nearest_even; 113 break; 114 case FPROUNDING_POSINF: 115 i = float_round_up; 116 break; 117 case FPROUNDING_NEGINF: 118 i = float_round_down; 119 break; 120 case FPROUNDING_ZERO: 121 i = float_round_to_zero; 122 break; 123 } 124 set_float_rounding_mode(i, &env->vfp.fp_status); 125 set_float_rounding_mode(i, &env->vfp.fp_status_f16); 126 } 127 if (changed & FPCR_FZ16) { 128 bool ftz_enabled = val & FPCR_FZ16; 129 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); 130 set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); 131 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); 132 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); 133 } 134 if (changed & FPCR_FZ) { 135 bool ftz_enabled = val & FPCR_FZ; 136 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); 137 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); 138 } 139 if (changed & FPCR_DN) { 140 bool dnan_enabled = val & FPCR_DN; 141 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); 142 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); 143 } 144 145 /* 146 * The exception flags are ORed together when we read fpscr so we 147 * only need to preserve the current state in one of our 148 * float_status values. 149 */ 150 i = vfp_exceptbits_to_host(val); 151 set_float_exception_flags(i, &env->vfp.fp_status); 152 set_float_exception_flags(0, &env->vfp.fp_status_f16); 153 set_float_exception_flags(0, &env->vfp.standard_fp_status); 154 set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); 155 } 156 157 #else 158 159 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) 160 { 161 return 0; 162 } 163 164 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) 165 { 166 } 167 168 #endif 169 170 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 171 { 172 uint32_t i, fpscr; 173 174 fpscr = env->vfp.xregs[ARM_VFP_FPSCR] 175 | (env->vfp.vec_len << 16) 176 | (env->vfp.vec_stride << 20); 177 178 /* 179 * M-profile LTPSIZE is the same bits [18:16] as A-profile Len; whichever 180 * of the two is not applicable to this CPU will always be zero. 181 */ 182 fpscr |= env->v7m.ltpsize << 16; 183 184 fpscr |= vfp_get_fpscr_from_host(env); 185 186 i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3]; 187 fpscr |= i ? FPCR_QC : 0; 188 189 return fpscr; 190 } 191 192 uint32_t vfp_get_fpscr(CPUARMState *env) 193 { 194 return HELPER(vfp_get_fpscr)(env); 195 } 196 197 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 198 { 199 ARMCPU *cpu = env_archcpu(env); 200 201 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ 202 if (!cpu_isar_feature(any_fp16, cpu)) { 203 val &= ~FPCR_FZ16; 204 } 205 206 vfp_set_fpscr_to_host(env, val); 207 208 if (!arm_feature(env, ARM_FEATURE_M)) { 209 /* 210 * Short-vector length and stride; on M-profile these bits 211 * are used for different purposes. 212 * We can't make this conditional be "if MVFR0.FPShVec != 0", 213 * because in v7A no-short-vector-support cores still had to 214 * allow Stride/Len to be written with the only effect that 215 * some insns are required to UNDEF if the guest sets them. 216 */ 217 env->vfp.vec_len = extract32(val, 16, 3); 218 env->vfp.vec_stride = extract32(val, 20, 2); 219 } else if (cpu_isar_feature(aa32_mve, cpu)) { 220 env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, 221 FPCR_LTPSIZE_LENGTH); 222 } 223 224 if (arm_feature(env, ARM_FEATURE_NEON) || 225 cpu_isar_feature(aa32_mve, cpu)) { 226 /* 227 * The bit we set within fpscr_q is arbitrary; the register as a 228 * whole being zero/non-zero is what counts. 229 */ 230 env->vfp.qc[0] = val & FPCR_QC; 231 env->vfp.qc[1] = 0; 232 env->vfp.qc[2] = 0; 233 env->vfp.qc[3] = 0; 234 } 235 236 /* 237 * We don't implement trapped exception handling, so the 238 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) 239 * 240 * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in 241 * fp_status; QC, Len and Stride are stored separately earlier. 242 * Clear out all of those and the RES0 bits: only NZCV, AHP, DN, 243 * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR]. 244 */ 245 env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000; 246 } 247 248 void vfp_set_fpscr(CPUARMState *env, uint32_t val) 249 { 250 HELPER(vfp_set_fpscr)(env, val); 251 } 252 253 #ifdef CONFIG_TCG 254 255 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 256 257 #define VFP_BINOP(name) \ 258 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \ 259 { \ 260 float_status *fpst = fpstp; \ 261 return float16_ ## name(a, b, fpst); \ 262 } \ 263 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ 264 { \ 265 float_status *fpst = fpstp; \ 266 return float32_ ## name(a, b, fpst); \ 267 } \ 268 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ 269 { \ 270 float_status *fpst = fpstp; \ 271 return float64_ ## name(a, b, fpst); \ 272 } 273 VFP_BINOP(add) 274 VFP_BINOP(sub) 275 VFP_BINOP(mul) 276 VFP_BINOP(div) 277 VFP_BINOP(min) 278 VFP_BINOP(max) 279 VFP_BINOP(minnum) 280 VFP_BINOP(maxnum) 281 #undef VFP_BINOP 282 283 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env) 284 { 285 return float16_sqrt(a, &env->vfp.fp_status_f16); 286 } 287 288 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) 289 { 290 return float32_sqrt(a, &env->vfp.fp_status); 291 } 292 293 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) 294 { 295 return float64_sqrt(a, &env->vfp.fp_status); 296 } 297 298 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp) 299 { 300 uint32_t flags; 301 switch (cmp) { 302 case float_relation_equal: 303 flags = 0x6; 304 break; 305 case float_relation_less: 306 flags = 0x8; 307 break; 308 case float_relation_greater: 309 flags = 0x2; 310 break; 311 case float_relation_unordered: 312 flags = 0x3; 313 break; 314 default: 315 g_assert_not_reached(); 316 } 317 env->vfp.xregs[ARM_VFP_FPSCR] = 318 deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags); 319 } 320 321 /* XXX: check quiet/signaling case */ 322 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \ 323 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 324 { \ 325 softfloat_to_vfp_compare(env, \ 326 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \ 327 } \ 328 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 329 { \ 330 softfloat_to_vfp_compare(env, \ 331 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \ 332 } 333 DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16) 334 DO_VFP_cmp(s, float32, float32, fp_status) 335 DO_VFP_cmp(d, float64, float64, fp_status) 336 #undef DO_VFP_cmp 337 338 /* Integer to float and float to integer conversions */ 339 340 #define CONV_ITOF(name, ftype, fsz, sign) \ 341 ftype HELPER(name)(uint32_t x, void *fpstp) \ 342 { \ 343 float_status *fpst = fpstp; \ 344 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 345 } 346 347 #define CONV_FTOI(name, ftype, fsz, sign, round) \ 348 sign##int32_t HELPER(name)(ftype x, void *fpstp) \ 349 { \ 350 float_status *fpst = fpstp; \ 351 if (float##fsz##_is_any_nan(x)) { \ 352 float_raise(float_flag_invalid, fpst); \ 353 return 0; \ 354 } \ 355 return float##fsz##_to_##sign##int32##round(x, fpst); \ 356 } 357 358 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \ 359 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \ 360 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \ 361 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero) 362 363 FLOAT_CONVS(si, h, uint32_t, 16, ) 364 FLOAT_CONVS(si, s, float32, 32, ) 365 FLOAT_CONVS(si, d, float64, 64, ) 366 FLOAT_CONVS(ui, h, uint32_t, 16, u) 367 FLOAT_CONVS(ui, s, float32, 32, u) 368 FLOAT_CONVS(ui, d, float64, 64, u) 369 370 #undef CONV_ITOF 371 #undef CONV_FTOI 372 #undef FLOAT_CONVS 373 374 /* floating point conversion */ 375 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) 376 { 377 return float32_to_float64(x, &env->vfp.fp_status); 378 } 379 380 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) 381 { 382 return float64_to_float32(x, &env->vfp.fp_status); 383 } 384 385 uint32_t HELPER(bfcvt)(float32 x, void *status) 386 { 387 return float32_to_bfloat16(x, status); 388 } 389 390 uint32_t HELPER(bfcvt_pair)(uint64_t pair, void *status) 391 { 392 bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status); 393 bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status); 394 return deposit32(lo, 16, 16, hi); 395 } 396 397 /* 398 * VFP3 fixed point conversion. The AArch32 versions of fix-to-float 399 * must always round-to-nearest; the AArch64 ones honour the FPSCR 400 * rounding mode. (For AArch32 Neon the standard-FPSCR is set to 401 * round-to-nearest so either helper will work.) AArch32 float-to-fix 402 * must round-to-zero. 403 */ 404 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 405 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 406 void *fpstp) \ 407 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); } 408 409 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ 410 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \ 411 uint32_t shift, \ 412 void *fpstp) \ 413 { \ 414 ftype ret; \ 415 float_status *fpst = fpstp; \ 416 FloatRoundMode oldmode = fpst->float_rounding_mode; \ 417 fpst->float_rounding_mode = float_round_nearest_even; \ 418 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \ 419 fpst->float_rounding_mode = oldmode; \ 420 return ret; \ 421 } 422 423 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \ 424 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \ 425 void *fpst) \ 426 { \ 427 if (unlikely(float##fsz##_is_any_nan(x))) { \ 428 float_raise(float_flag_invalid, fpst); \ 429 return 0; \ 430 } \ 431 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \ 432 } 433 434 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \ 435 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 436 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ 437 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 438 float_round_to_zero, _round_to_zero) \ 439 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 440 get_float_rounding_mode(fpst), ) 441 442 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \ 443 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 444 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 445 get_float_rounding_mode(fpst), ) 446 447 VFP_CONV_FIX(sh, d, 64, float64, 64, int16) 448 VFP_CONV_FIX(sl, d, 64, float64, 64, int32) 449 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64) 450 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16) 451 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32) 452 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64) 453 VFP_CONV_FIX(sh, s, 32, float32, 32, int16) 454 VFP_CONV_FIX(sl, s, 32, float32, 32, int32) 455 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64) 456 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16) 457 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32) 458 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64) 459 VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16) 460 VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32) 461 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64) 462 VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16) 463 VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32) 464 VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64) 465 466 #undef VFP_CONV_FIX 467 #undef VFP_CONV_FIX_FLOAT 468 #undef VFP_CONV_FLOAT_FIX_ROUND 469 #undef VFP_CONV_FIX_A64 470 471 /* Set the current fp rounding mode and return the old one. 472 * The argument is a softfloat float_round_ value. 473 */ 474 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) 475 { 476 float_status *fp_status = fpstp; 477 478 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 479 set_float_rounding_mode(rmode, fp_status); 480 481 return prev_rmode; 482 } 483 484 /* Half precision conversions. */ 485 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode) 486 { 487 /* Squash FZ16 to 0 for the duration of conversion. In this case, 488 * it would affect flushing input denormals. 489 */ 490 float_status *fpst = fpstp; 491 bool save = get_flush_inputs_to_zero(fpst); 492 set_flush_inputs_to_zero(false, fpst); 493 float32 r = float16_to_float32(a, !ahp_mode, fpst); 494 set_flush_inputs_to_zero(save, fpst); 495 return r; 496 } 497 498 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) 499 { 500 /* Squash FZ16 to 0 for the duration of conversion. In this case, 501 * it would affect flushing output denormals. 502 */ 503 float_status *fpst = fpstp; 504 bool save = get_flush_to_zero(fpst); 505 set_flush_to_zero(false, fpst); 506 float16 r = float32_to_float16(a, !ahp_mode, fpst); 507 set_flush_to_zero(save, fpst); 508 return r; 509 } 510 511 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode) 512 { 513 /* Squash FZ16 to 0 for the duration of conversion. In this case, 514 * it would affect flushing input denormals. 515 */ 516 float_status *fpst = fpstp; 517 bool save = get_flush_inputs_to_zero(fpst); 518 set_flush_inputs_to_zero(false, fpst); 519 float64 r = float16_to_float64(a, !ahp_mode, fpst); 520 set_flush_inputs_to_zero(save, fpst); 521 return r; 522 } 523 524 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) 525 { 526 /* Squash FZ16 to 0 for the duration of conversion. In this case, 527 * it would affect flushing output denormals. 528 */ 529 float_status *fpst = fpstp; 530 bool save = get_flush_to_zero(fpst); 531 set_flush_to_zero(false, fpst); 532 float16 r = float64_to_float16(a, !ahp_mode, fpst); 533 set_flush_to_zero(save, fpst); 534 return r; 535 } 536 537 /* NEON helpers. */ 538 539 /* Constants 256 and 512 are used in some helpers; we avoid relying on 540 * int->float conversions at run-time. */ 541 #define float64_256 make_float64(0x4070000000000000LL) 542 #define float64_512 make_float64(0x4080000000000000LL) 543 #define float16_maxnorm make_float16(0x7bff) 544 #define float32_maxnorm make_float32(0x7f7fffff) 545 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 546 547 /* Reciprocal functions 548 * 549 * The algorithm that must be used to calculate the estimate 550 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate 551 */ 552 553 /* See RecipEstimate() 554 * 555 * input is a 9 bit fixed point number 556 * input range 256 .. 511 for a number from 0.5 <= x < 1.0. 557 * result range 256 .. 511 for a number from 1.0 to 511/256. 558 */ 559 560 static int recip_estimate(int input) 561 { 562 int a, b, r; 563 assert(256 <= input && input < 512); 564 a = (input * 2) + 1; 565 b = (1 << 19) / a; 566 r = (b + 1) >> 1; 567 assert(256 <= r && r < 512); 568 return r; 569 } 570 571 /* 572 * Common wrapper to call recip_estimate 573 * 574 * The parameters are exponent and 64 bit fraction (without implicit 575 * bit) where the binary point is nominally at bit 52. Returns a 576 * float64 which can then be rounded to the appropriate size by the 577 * callee. 578 */ 579 580 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac) 581 { 582 uint32_t scaled, estimate; 583 uint64_t result_frac; 584 int result_exp; 585 586 /* Handle sub-normals */ 587 if (*exp == 0) { 588 if (extract64(frac, 51, 1) == 0) { 589 *exp = -1; 590 frac <<= 2; 591 } else { 592 frac <<= 1; 593 } 594 } 595 596 /* scaled = UInt('1':fraction<51:44>) */ 597 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 598 estimate = recip_estimate(scaled); 599 600 result_exp = exp_off - *exp; 601 result_frac = deposit64(0, 44, 8, estimate); 602 if (result_exp == 0) { 603 result_frac = deposit64(result_frac >> 1, 51, 1, 1); 604 } else if (result_exp == -1) { 605 result_frac = deposit64(result_frac >> 2, 50, 2, 1); 606 result_exp = 0; 607 } 608 609 *exp = result_exp; 610 611 return result_frac; 612 } 613 614 static bool round_to_inf(float_status *fpst, bool sign_bit) 615 { 616 switch (fpst->float_rounding_mode) { 617 case float_round_nearest_even: /* Round to Nearest */ 618 return true; 619 case float_round_up: /* Round to +Inf */ 620 return !sign_bit; 621 case float_round_down: /* Round to -Inf */ 622 return sign_bit; 623 case float_round_to_zero: /* Round to Zero */ 624 return false; 625 default: 626 g_assert_not_reached(); 627 } 628 } 629 630 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) 631 { 632 float_status *fpst = fpstp; 633 float16 f16 = float16_squash_input_denormal(input, fpst); 634 uint32_t f16_val = float16_val(f16); 635 uint32_t f16_sign = float16_is_neg(f16); 636 int f16_exp = extract32(f16_val, 10, 5); 637 uint32_t f16_frac = extract32(f16_val, 0, 10); 638 uint64_t f64_frac; 639 640 if (float16_is_any_nan(f16)) { 641 float16 nan = f16; 642 if (float16_is_signaling_nan(f16, fpst)) { 643 float_raise(float_flag_invalid, fpst); 644 if (!fpst->default_nan_mode) { 645 nan = float16_silence_nan(f16, fpst); 646 } 647 } 648 if (fpst->default_nan_mode) { 649 nan = float16_default_nan(fpst); 650 } 651 return nan; 652 } else if (float16_is_infinity(f16)) { 653 return float16_set_sign(float16_zero, float16_is_neg(f16)); 654 } else if (float16_is_zero(f16)) { 655 float_raise(float_flag_divbyzero, fpst); 656 return float16_set_sign(float16_infinity, float16_is_neg(f16)); 657 } else if (float16_abs(f16) < (1 << 8)) { 658 /* Abs(value) < 2.0^-16 */ 659 float_raise(float_flag_overflow | float_flag_inexact, fpst); 660 if (round_to_inf(fpst, f16_sign)) { 661 return float16_set_sign(float16_infinity, f16_sign); 662 } else { 663 return float16_set_sign(float16_maxnorm, f16_sign); 664 } 665 } else if (f16_exp >= 29 && fpst->flush_to_zero) { 666 float_raise(float_flag_underflow, fpst); 667 return float16_set_sign(float16_zero, float16_is_neg(f16)); 668 } 669 670 f64_frac = call_recip_estimate(&f16_exp, 29, 671 ((uint64_t) f16_frac) << (52 - 10)); 672 673 /* result = sign : result_exp<4:0> : fraction<51:42> */ 674 f16_val = deposit32(0, 15, 1, f16_sign); 675 f16_val = deposit32(f16_val, 10, 5, f16_exp); 676 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); 677 return make_float16(f16_val); 678 } 679 680 float32 HELPER(recpe_f32)(float32 input, void *fpstp) 681 { 682 float_status *fpst = fpstp; 683 float32 f32 = float32_squash_input_denormal(input, fpst); 684 uint32_t f32_val = float32_val(f32); 685 bool f32_sign = float32_is_neg(f32); 686 int f32_exp = extract32(f32_val, 23, 8); 687 uint32_t f32_frac = extract32(f32_val, 0, 23); 688 uint64_t f64_frac; 689 690 if (float32_is_any_nan(f32)) { 691 float32 nan = f32; 692 if (float32_is_signaling_nan(f32, fpst)) { 693 float_raise(float_flag_invalid, fpst); 694 if (!fpst->default_nan_mode) { 695 nan = float32_silence_nan(f32, fpst); 696 } 697 } 698 if (fpst->default_nan_mode) { 699 nan = float32_default_nan(fpst); 700 } 701 return nan; 702 } else if (float32_is_infinity(f32)) { 703 return float32_set_sign(float32_zero, float32_is_neg(f32)); 704 } else if (float32_is_zero(f32)) { 705 float_raise(float_flag_divbyzero, fpst); 706 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 707 } else if (float32_abs(f32) < (1ULL << 21)) { 708 /* Abs(value) < 2.0^-128 */ 709 float_raise(float_flag_overflow | float_flag_inexact, fpst); 710 if (round_to_inf(fpst, f32_sign)) { 711 return float32_set_sign(float32_infinity, f32_sign); 712 } else { 713 return float32_set_sign(float32_maxnorm, f32_sign); 714 } 715 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 716 float_raise(float_flag_underflow, fpst); 717 return float32_set_sign(float32_zero, float32_is_neg(f32)); 718 } 719 720 f64_frac = call_recip_estimate(&f32_exp, 253, 721 ((uint64_t) f32_frac) << (52 - 23)); 722 723 /* result = sign : result_exp<7:0> : fraction<51:29> */ 724 f32_val = deposit32(0, 31, 1, f32_sign); 725 f32_val = deposit32(f32_val, 23, 8, f32_exp); 726 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); 727 return make_float32(f32_val); 728 } 729 730 float64 HELPER(recpe_f64)(float64 input, void *fpstp) 731 { 732 float_status *fpst = fpstp; 733 float64 f64 = float64_squash_input_denormal(input, fpst); 734 uint64_t f64_val = float64_val(f64); 735 bool f64_sign = float64_is_neg(f64); 736 int f64_exp = extract64(f64_val, 52, 11); 737 uint64_t f64_frac = extract64(f64_val, 0, 52); 738 739 /* Deal with any special cases */ 740 if (float64_is_any_nan(f64)) { 741 float64 nan = f64; 742 if (float64_is_signaling_nan(f64, fpst)) { 743 float_raise(float_flag_invalid, fpst); 744 if (!fpst->default_nan_mode) { 745 nan = float64_silence_nan(f64, fpst); 746 } 747 } 748 if (fpst->default_nan_mode) { 749 nan = float64_default_nan(fpst); 750 } 751 return nan; 752 } else if (float64_is_infinity(f64)) { 753 return float64_set_sign(float64_zero, float64_is_neg(f64)); 754 } else if (float64_is_zero(f64)) { 755 float_raise(float_flag_divbyzero, fpst); 756 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 757 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 758 /* Abs(value) < 2.0^-1024 */ 759 float_raise(float_flag_overflow | float_flag_inexact, fpst); 760 if (round_to_inf(fpst, f64_sign)) { 761 return float64_set_sign(float64_infinity, f64_sign); 762 } else { 763 return float64_set_sign(float64_maxnorm, f64_sign); 764 } 765 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 766 float_raise(float_flag_underflow, fpst); 767 return float64_set_sign(float64_zero, float64_is_neg(f64)); 768 } 769 770 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac); 771 772 /* result = sign : result_exp<10:0> : fraction<51:0>; */ 773 f64_val = deposit64(0, 63, 1, f64_sign); 774 f64_val = deposit64(f64_val, 52, 11, f64_exp); 775 f64_val = deposit64(f64_val, 0, 52, f64_frac); 776 return make_float64(f64_val); 777 } 778 779 /* The algorithm that must be used to calculate the estimate 780 * is specified by the ARM ARM. 781 */ 782 783 static int do_recip_sqrt_estimate(int a) 784 { 785 int b, estimate; 786 787 assert(128 <= a && a < 512); 788 if (a < 256) { 789 a = a * 2 + 1; 790 } else { 791 a = (a >> 1) << 1; 792 a = (a + 1) * 2; 793 } 794 b = 512; 795 while (a * (b + 1) * (b + 1) < (1 << 28)) { 796 b += 1; 797 } 798 estimate = (b + 1) / 2; 799 assert(256 <= estimate && estimate < 512); 800 801 return estimate; 802 } 803 804 805 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) 806 { 807 int estimate; 808 uint32_t scaled; 809 810 if (*exp == 0) { 811 while (extract64(frac, 51, 1) == 0) { 812 frac = frac << 1; 813 *exp -= 1; 814 } 815 frac = extract64(frac, 0, 51) << 1; 816 } 817 818 if (*exp & 1) { 819 /* scaled = UInt('01':fraction<51:45>) */ 820 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); 821 } else { 822 /* scaled = UInt('1':fraction<51:44>) */ 823 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 824 } 825 estimate = do_recip_sqrt_estimate(scaled); 826 827 *exp = (exp_off - *exp) / 2; 828 return extract64(estimate, 0, 8) << 44; 829 } 830 831 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) 832 { 833 float_status *s = fpstp; 834 float16 f16 = float16_squash_input_denormal(input, s); 835 uint16_t val = float16_val(f16); 836 bool f16_sign = float16_is_neg(f16); 837 int f16_exp = extract32(val, 10, 5); 838 uint16_t f16_frac = extract32(val, 0, 10); 839 uint64_t f64_frac; 840 841 if (float16_is_any_nan(f16)) { 842 float16 nan = f16; 843 if (float16_is_signaling_nan(f16, s)) { 844 float_raise(float_flag_invalid, s); 845 if (!s->default_nan_mode) { 846 nan = float16_silence_nan(f16, fpstp); 847 } 848 } 849 if (s->default_nan_mode) { 850 nan = float16_default_nan(s); 851 } 852 return nan; 853 } else if (float16_is_zero(f16)) { 854 float_raise(float_flag_divbyzero, s); 855 return float16_set_sign(float16_infinity, f16_sign); 856 } else if (f16_sign) { 857 float_raise(float_flag_invalid, s); 858 return float16_default_nan(s); 859 } else if (float16_is_infinity(f16)) { 860 return float16_zero; 861 } 862 863 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 864 * preserving the parity of the exponent. */ 865 866 f64_frac = ((uint64_t) f16_frac) << (52 - 10); 867 868 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac); 869 870 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ 871 val = deposit32(0, 15, 1, f16_sign); 872 val = deposit32(val, 10, 5, f16_exp); 873 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); 874 return make_float16(val); 875 } 876 877 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) 878 { 879 float_status *s = fpstp; 880 float32 f32 = float32_squash_input_denormal(input, s); 881 uint32_t val = float32_val(f32); 882 uint32_t f32_sign = float32_is_neg(f32); 883 int f32_exp = extract32(val, 23, 8); 884 uint32_t f32_frac = extract32(val, 0, 23); 885 uint64_t f64_frac; 886 887 if (float32_is_any_nan(f32)) { 888 float32 nan = f32; 889 if (float32_is_signaling_nan(f32, s)) { 890 float_raise(float_flag_invalid, s); 891 if (!s->default_nan_mode) { 892 nan = float32_silence_nan(f32, fpstp); 893 } 894 } 895 if (s->default_nan_mode) { 896 nan = float32_default_nan(s); 897 } 898 return nan; 899 } else if (float32_is_zero(f32)) { 900 float_raise(float_flag_divbyzero, s); 901 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 902 } else if (float32_is_neg(f32)) { 903 float_raise(float_flag_invalid, s); 904 return float32_default_nan(s); 905 } else if (float32_is_infinity(f32)) { 906 return float32_zero; 907 } 908 909 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 910 * preserving the parity of the exponent. */ 911 912 f64_frac = ((uint64_t) f32_frac) << 29; 913 914 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac); 915 916 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ 917 val = deposit32(0, 31, 1, f32_sign); 918 val = deposit32(val, 23, 8, f32_exp); 919 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); 920 return make_float32(val); 921 } 922 923 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) 924 { 925 float_status *s = fpstp; 926 float64 f64 = float64_squash_input_denormal(input, s); 927 uint64_t val = float64_val(f64); 928 bool f64_sign = float64_is_neg(f64); 929 int f64_exp = extract64(val, 52, 11); 930 uint64_t f64_frac = extract64(val, 0, 52); 931 932 if (float64_is_any_nan(f64)) { 933 float64 nan = f64; 934 if (float64_is_signaling_nan(f64, s)) { 935 float_raise(float_flag_invalid, s); 936 if (!s->default_nan_mode) { 937 nan = float64_silence_nan(f64, fpstp); 938 } 939 } 940 if (s->default_nan_mode) { 941 nan = float64_default_nan(s); 942 } 943 return nan; 944 } else if (float64_is_zero(f64)) { 945 float_raise(float_flag_divbyzero, s); 946 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 947 } else if (float64_is_neg(f64)) { 948 float_raise(float_flag_invalid, s); 949 return float64_default_nan(s); 950 } else if (float64_is_infinity(f64)) { 951 return float64_zero; 952 } 953 954 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac); 955 956 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ 957 val = deposit64(0, 61, 1, f64_sign); 958 val = deposit64(val, 52, 11, f64_exp); 959 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); 960 return make_float64(val); 961 } 962 963 uint32_t HELPER(recpe_u32)(uint32_t a) 964 { 965 int input, estimate; 966 967 if ((a & 0x80000000) == 0) { 968 return 0xffffffff; 969 } 970 971 input = extract32(a, 23, 9); 972 estimate = recip_estimate(input); 973 974 return deposit32(0, (32 - 9), 9, estimate); 975 } 976 977 uint32_t HELPER(rsqrte_u32)(uint32_t a) 978 { 979 int estimate; 980 981 if ((a & 0xc0000000) == 0) { 982 return 0xffffffff; 983 } 984 985 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); 986 987 return deposit32(0, 23, 9, estimate); 988 } 989 990 /* VFPv4 fused multiply-accumulate */ 991 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b, 992 dh_ctype_f16 c, void *fpstp) 993 { 994 float_status *fpst = fpstp; 995 return float16_muladd(a, b, c, 0, fpst); 996 } 997 998 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) 999 { 1000 float_status *fpst = fpstp; 1001 return float32_muladd(a, b, c, 0, fpst); 1002 } 1003 1004 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) 1005 { 1006 float_status *fpst = fpstp; 1007 return float64_muladd(a, b, c, 0, fpst); 1008 } 1009 1010 /* ARMv8 round to integral */ 1011 dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status) 1012 { 1013 return float16_round_to_int(x, fp_status); 1014 } 1015 1016 float32 HELPER(rints_exact)(float32 x, void *fp_status) 1017 { 1018 return float32_round_to_int(x, fp_status); 1019 } 1020 1021 float64 HELPER(rintd_exact)(float64 x, void *fp_status) 1022 { 1023 return float64_round_to_int(x, fp_status); 1024 } 1025 1026 dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status) 1027 { 1028 int old_flags = get_float_exception_flags(fp_status), new_flags; 1029 float16 ret; 1030 1031 ret = float16_round_to_int(x, fp_status); 1032 1033 /* Suppress any inexact exceptions the conversion produced */ 1034 if (!(old_flags & float_flag_inexact)) { 1035 new_flags = get_float_exception_flags(fp_status); 1036 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1037 } 1038 1039 return ret; 1040 } 1041 1042 float32 HELPER(rints)(float32 x, void *fp_status) 1043 { 1044 int old_flags = get_float_exception_flags(fp_status), new_flags; 1045 float32 ret; 1046 1047 ret = float32_round_to_int(x, fp_status); 1048 1049 /* Suppress any inexact exceptions the conversion produced */ 1050 if (!(old_flags & float_flag_inexact)) { 1051 new_flags = get_float_exception_flags(fp_status); 1052 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1053 } 1054 1055 return ret; 1056 } 1057 1058 float64 HELPER(rintd)(float64 x, void *fp_status) 1059 { 1060 int old_flags = get_float_exception_flags(fp_status), new_flags; 1061 float64 ret; 1062 1063 ret = float64_round_to_int(x, fp_status); 1064 1065 new_flags = get_float_exception_flags(fp_status); 1066 1067 /* Suppress any inexact exceptions the conversion produced */ 1068 if (!(old_flags & float_flag_inexact)) { 1069 new_flags = get_float_exception_flags(fp_status); 1070 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1071 } 1072 1073 return ret; 1074 } 1075 1076 /* Convert ARM rounding mode to softfloat */ 1077 const FloatRoundMode arm_rmode_to_sf_map[] = { 1078 [FPROUNDING_TIEEVEN] = float_round_nearest_even, 1079 [FPROUNDING_POSINF] = float_round_up, 1080 [FPROUNDING_NEGINF] = float_round_down, 1081 [FPROUNDING_ZERO] = float_round_to_zero, 1082 [FPROUNDING_TIEAWAY] = float_round_ties_away, 1083 [FPROUNDING_ODD] = float_round_to_odd, 1084 }; 1085 1086 /* 1087 * Implement float64 to int32_t conversion without saturation; 1088 * the result is supplied modulo 2^32. 1089 */ 1090 uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) 1091 { 1092 float_status *status = vstatus; 1093 uint32_t frac, e_old, e_new; 1094 bool inexact; 1095 1096 e_old = get_float_exception_flags(status); 1097 set_float_exception_flags(0, status); 1098 frac = float64_to_int32_modulo(value, float_round_to_zero, status); 1099 e_new = get_float_exception_flags(status); 1100 set_float_exception_flags(e_old | e_new, status); 1101 1102 /* Normal inexact, denormal with flush-to-zero, or overflow or NaN */ 1103 inexact = e_new & (float_flag_inexact | 1104 float_flag_input_denormal | 1105 float_flag_invalid); 1106 1107 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ 1108 inexact |= value == float64_chs(float64_zero); 1109 1110 /* Pack the result and the env->ZF representation of Z together. */ 1111 return deposit64(frac, 32, 32, inexact); 1112 } 1113 1114 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) 1115 { 1116 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status); 1117 uint32_t result = pair; 1118 uint32_t z = (pair >> 32) == 0; 1119 1120 /* Store Z, clear NCV, in FPSCR.NZCV. */ 1121 env->vfp.xregs[ARM_VFP_FPSCR] 1122 = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z); 1123 1124 return result; 1125 } 1126 1127 /* Round a float32 to an integer that fits in int32_t or int64_t. */ 1128 static float32 frint_s(float32 f, float_status *fpst, int intsize) 1129 { 1130 int old_flags = get_float_exception_flags(fpst); 1131 uint32_t exp = extract32(f, 23, 8); 1132 1133 if (unlikely(exp == 0xff)) { 1134 /* NaN or Inf. */ 1135 goto overflow; 1136 } 1137 1138 /* Round and re-extract the exponent. */ 1139 f = float32_round_to_int(f, fpst); 1140 exp = extract32(f, 23, 8); 1141 1142 /* Validate the range of the result. */ 1143 if (exp < 126 + intsize) { 1144 /* abs(F) <= INT{N}_MAX */ 1145 return f; 1146 } 1147 if (exp == 126 + intsize) { 1148 uint32_t sign = extract32(f, 31, 1); 1149 uint32_t frac = extract32(f, 0, 23); 1150 if (sign && frac == 0) { 1151 /* F == INT{N}_MIN */ 1152 return f; 1153 } 1154 } 1155 1156 overflow: 1157 /* 1158 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1159 * inexact exception float32_round_to_int may have raised. 1160 */ 1161 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1162 return (0x100u + 126u + intsize) << 23; 1163 } 1164 1165 float32 HELPER(frint32_s)(float32 f, void *fpst) 1166 { 1167 return frint_s(f, fpst, 32); 1168 } 1169 1170 float32 HELPER(frint64_s)(float32 f, void *fpst) 1171 { 1172 return frint_s(f, fpst, 64); 1173 } 1174 1175 /* Round a float64 to an integer that fits in int32_t or int64_t. */ 1176 static float64 frint_d(float64 f, float_status *fpst, int intsize) 1177 { 1178 int old_flags = get_float_exception_flags(fpst); 1179 uint32_t exp = extract64(f, 52, 11); 1180 1181 if (unlikely(exp == 0x7ff)) { 1182 /* NaN or Inf. */ 1183 goto overflow; 1184 } 1185 1186 /* Round and re-extract the exponent. */ 1187 f = float64_round_to_int(f, fpst); 1188 exp = extract64(f, 52, 11); 1189 1190 /* Validate the range of the result. */ 1191 if (exp < 1022 + intsize) { 1192 /* abs(F) <= INT{N}_MAX */ 1193 return f; 1194 } 1195 if (exp == 1022 + intsize) { 1196 uint64_t sign = extract64(f, 63, 1); 1197 uint64_t frac = extract64(f, 0, 52); 1198 if (sign && frac == 0) { 1199 /* F == INT{N}_MIN */ 1200 return f; 1201 } 1202 } 1203 1204 overflow: 1205 /* 1206 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1207 * inexact exception float64_round_to_int may have raised. 1208 */ 1209 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1210 return (uint64_t)(0x800 + 1022 + intsize) << 52; 1211 } 1212 1213 float64 HELPER(frint32_d)(float64 f, void *fpst) 1214 { 1215 return frint_d(f, fpst, 32); 1216 } 1217 1218 float64 HELPER(frint64_d)(float64 f, void *fpst) 1219 { 1220 return frint_d(f, fpst, 64); 1221 } 1222 1223 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg) 1224 { 1225 uint32_t syndrome; 1226 1227 switch (reg) { 1228 case ARM_VFP_MVFR0: 1229 case ARM_VFP_MVFR1: 1230 case ARM_VFP_MVFR2: 1231 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) { 1232 return; 1233 } 1234 break; 1235 case ARM_VFP_FPSID: 1236 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) { 1237 return; 1238 } 1239 break; 1240 default: 1241 g_assert_not_reached(); 1242 } 1243 1244 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT) 1245 | ARM_EL_IL 1246 | (1 << 24) | (0xe << 20) | (7 << 14) 1247 | (reg << 10) | (rt << 5) | 1); 1248 1249 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); 1250 } 1251 1252 #endif 1253