1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22
23 #include "qemu/int128.h"
24 #include "qemu/cpu-float.h"
25 #include "exec/cpu-defs.h"
26 #include "cpu-qom.h"
27 #include "qom/object.h"
28 #include "hw/registerfields.h"
29
30 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
31
32 #define TARGET_PAGE_BITS_64K 16
33 #define TARGET_PAGE_BITS_16M 24
34
35 #if defined(TARGET_PPC64)
36 #define PPC_ELF_MACHINE EM_PPC64
37 #else
38 #define PPC_ELF_MACHINE EM_PPC
39 #endif
40
41 #define PPC_BIT_NR(bit) (63 - (bit))
42 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
43 #define PPC_BIT32_NR(bit) (31 - (bit))
44 #define PPC_BIT32(bit) (0x80000000 >> (bit))
45 #define PPC_BIT8(bit) (0x80 >> (bit))
46 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
47 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
48 PPC_BIT32(bs))
49 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
50
51 /*
52 * QEMU version of the GETFIELD/SETFIELD macros from skiboot
53 *
54 * It might be better to use the existing extract64() and
55 * deposit64() but this means that all the register definitions will
56 * change and become incompatible with the ones found in skiboot.
57 */
58 #define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
59 #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
60 #define SETFIELD(m, v, val) \
61 (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
62
63 /*****************************************************************************/
64 /* Exception vectors definitions */
65 enum {
66 POWERPC_EXCP_NONE = -1,
67 /* The 64 first entries are used by the PowerPC embedded specification */
68 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
69 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
70 POWERPC_EXCP_DSI = 2, /* Data storage exception */
71 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
72 POWERPC_EXCP_EXTERNAL = 4, /* External input */
73 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
74 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
75 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
76 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
77 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
78 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
79 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
80 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
81 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
82 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
83 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
84 /* Vectors 16 to 31 are reserved */
85 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
86 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
87 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
88 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
89 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
90 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
91 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
92 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
93 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
94 /* Vectors 42 to 63 are reserved */
95 /* Exceptions defined in the PowerPC server specification */
96 POWERPC_EXCP_RESET = 64, /* System reset exception */
97 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
98 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
99 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
100 POWERPC_EXCP_TRACE = 68, /* Trace exception */
101 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
102 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
103 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
104 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
105 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
106 /* 40x specific exceptions */
107 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
108 /* Vectors 75-76 are 601 specific exceptions */
109 /* 602 specific exceptions */
110 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
111 /* 602/603 specific exceptions */
112 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
113 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
114 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
115 /* Exceptions available on most PowerPC */
116 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
117 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
118 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
119 POWERPC_EXCP_SMI = 84, /* System management interrupt */
120 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
121 /* 7xx/74xx specific exceptions */
122 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
123 /* 74xx specific exceptions */
124 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
125 /* 970FX specific exceptions */
126 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
127 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
128 /* Freescale embedded cores specific exceptions */
129 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
130 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
131 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
132 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
133 /* VSX Unavailable (Power ISA 2.06 and later) */
134 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
135 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
136 /* Additional ISA 2.06 and later server exceptions */
137 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
138 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
139 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
140 /* Server doorbell variants */
141 POWERPC_EXCP_SDOOR = 99,
142 POWERPC_EXCP_SDOOR_HV = 100,
143 /* ISA 3.00 additions */
144 POWERPC_EXCP_HVIRT = 101,
145 POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
146 POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
147 POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
148 /* EOL */
149 POWERPC_EXCP_NB = 105,
150 /* QEMU exceptions: special cases we want to stop translation */
151 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
152 };
153
154 /* Exceptions error codes */
155 enum {
156 /* Exception subtypes for POWERPC_EXCP_ALIGN */
157 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
158 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
159 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
160 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
161 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
162 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
163 POWERPC_EXCP_ALIGN_INSN = 0x07, /* Pref. insn x-ing 64-byte boundary */
164 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
165 /* FP exceptions */
166 POWERPC_EXCP_FP = 0x10,
167 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
168 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
169 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
170 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
171 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
172 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
173 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
174 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
175 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
176 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
177 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
178 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
179 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
180 /* Invalid instruction */
181 POWERPC_EXCP_INVAL = 0x20,
182 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
183 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
184 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
185 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
186 /* Privileged instruction */
187 POWERPC_EXCP_PRIV = 0x30,
188 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
189 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
190 /* Trap */
191 POWERPC_EXCP_TRAP = 0x40,
192 };
193
194 /* Exception model */
195 typedef enum powerpc_excp_t {
196 POWERPC_EXCP_UNKNOWN = 0,
197 /* Standard PowerPC exception model */
198 POWERPC_EXCP_STD,
199 /* PowerPC 40x exception model */
200 POWERPC_EXCP_40x,
201 /* PowerPC 603/604/G2 exception model */
202 POWERPC_EXCP_6xx,
203 /* PowerPC 7xx exception model */
204 POWERPC_EXCP_7xx,
205 /* PowerPC 74xx exception model */
206 POWERPC_EXCP_74xx,
207 /* BookE exception model */
208 POWERPC_EXCP_BOOKE,
209 /* PowerPC 970 exception model */
210 POWERPC_EXCP_970,
211 /* POWER7 exception model */
212 POWERPC_EXCP_POWER7,
213 /* POWER8 exception model */
214 POWERPC_EXCP_POWER8,
215 /* POWER9 exception model */
216 POWERPC_EXCP_POWER9,
217 /* POWER10 exception model */
218 POWERPC_EXCP_POWER10,
219 /* POWER11 exception model */
220 POWERPC_EXCP_POWER11,
221 } powerpc_excp_t;
222
223 /*****************************************************************************/
224 /* MMU model */
225 typedef enum powerpc_mmu_t {
226 POWERPC_MMU_UNKNOWN = 0x00000000,
227 /* Standard 32 bits PowerPC MMU */
228 POWERPC_MMU_32B = 0x00000001,
229 /* PowerPC 6xx MMU with software TLB */
230 POWERPC_MMU_SOFT_6xx = 0x00000002,
231 /*
232 * PowerPC 74xx MMU with software TLB (this has been
233 * disabled, see git history for more information.
234 * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
235 */
236 POWERPC_MMU_SOFT_74xx = 0x00000003,
237 /* PowerPC 4xx MMU with software TLB */
238 POWERPC_MMU_SOFT_4xx = 0x00000004,
239 /* PowerPC MMU in real mode only */
240 POWERPC_MMU_REAL = 0x00000006,
241 /* Freescale MPC8xx MMU model */
242 POWERPC_MMU_MPC8xx = 0x00000007,
243 /* BookE MMU model */
244 POWERPC_MMU_BOOKE = 0x00000008,
245 /* BookE 2.06 MMU model */
246 POWERPC_MMU_BOOKE206 = 0x00000009,
247 #define POWERPC_MMU_64 0x00010000
248 /* 64 bits PowerPC MMU */
249 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
250 /* Architecture 2.03 and later (has LPCR) */
251 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
252 /* Architecture 2.06 variant */
253 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
254 /* Architecture 2.07 variant */
255 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
256 /* Architecture 3.00 variant */
257 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
258 } powerpc_mmu_t;
259
mmu_is_64bit(powerpc_mmu_t mmu_model)260 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
261 {
262 return mmu_model & POWERPC_MMU_64;
263 }
264
265 /*****************************************************************************/
266 /* Input pins model */
267 typedef enum powerpc_input_t {
268 PPC_FLAGS_INPUT_UNKNOWN = 0,
269 /* PowerPC 6xx bus */
270 PPC_FLAGS_INPUT_6xx,
271 /* BookE bus */
272 PPC_FLAGS_INPUT_BookE,
273 /* PowerPC 405 bus */
274 PPC_FLAGS_INPUT_405,
275 /* PowerPC 970 bus */
276 PPC_FLAGS_INPUT_970,
277 /* PowerPC POWER7 bus */
278 PPC_FLAGS_INPUT_POWER7,
279 /* PowerPC POWER9 bus */
280 PPC_FLAGS_INPUT_POWER9,
281 /* Freescale RCPU bus */
282 PPC_FLAGS_INPUT_RCPU,
283 } powerpc_input_t;
284
285 #define PPC_INPUT(env) ((env)->bus_model)
286
287 /*****************************************************************************/
288 typedef struct opc_handler_t opc_handler_t;
289
290 /*****************************************************************************/
291 /* Types used to describe some PowerPC registers etc. */
292 typedef struct DisasContext DisasContext;
293 typedef struct ppc_dcr_t ppc_dcr_t;
294 typedef struct ppc_spr_t ppc_spr_t;
295 typedef struct ppc_tb_t ppc_tb_t;
296 typedef union ppc_tlb_t ppc_tlb_t;
297 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
298 typedef struct PPCHash64Options PPCHash64Options;
299
300 typedef struct CPUArchState CPUPPCState;
301
302 /* SPR access micro-ops generations callbacks */
303 struct ppc_spr_t {
304 const char *name;
305 target_ulong default_value;
306 #ifndef CONFIG_USER_ONLY
307 unsigned int gdb_id;
308 #endif
309 #ifdef CONFIG_TCG
310 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
311 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
312 # ifndef CONFIG_USER_ONLY
313 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
314 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
315 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
316 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
317 # endif
318 #endif
319 #ifdef CONFIG_KVM
320 /*
321 * We (ab)use the fact that all the SPRs will have ids for the
322 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
323 * don't sync this
324 */
325 uint64_t one_reg_id;
326 #endif
327 };
328
329 /* VSX/Altivec registers (128 bits) */
330 typedef union _ppc_vsr_t {
331 uint8_t u8[16];
332 uint16_t u16[8];
333 uint32_t u32[4];
334 uint64_t u64[2];
335 int8_t s8[16];
336 int16_t s16[8];
337 int32_t s32[4];
338 int64_t s64[2];
339 float16 f16[8];
340 float32 f32[4];
341 float64 f64[2];
342 float128 f128;
343 #ifdef CONFIG_INT128
344 __uint128_t u128;
345 #endif
346 Int128 s128;
347 } ppc_vsr_t;
348
349 typedef ppc_vsr_t ppc_avr_t;
350 typedef ppc_vsr_t ppc_fprp_t;
351 typedef ppc_vsr_t ppc_acc_t;
352
353 #if !defined(CONFIG_USER_ONLY)
354 /* Software TLB cache */
355 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
356 struct ppc6xx_tlb_t {
357 target_ulong pte0;
358 target_ulong pte1;
359 target_ulong EPN;
360 };
361
362 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
363 struct ppcemb_tlb_t {
364 uint64_t RPN;
365 target_ulong EPN;
366 target_ulong PID;
367 target_ulong size;
368 uint32_t prot;
369 uint32_t attr; /* Storage attributes */
370 };
371
372 typedef struct ppcmas_tlb_t {
373 uint32_t mas8;
374 uint32_t mas1;
375 uint64_t mas2;
376 uint64_t mas7_3;
377 } ppcmas_tlb_t;
378
379 union ppc_tlb_t {
380 ppc6xx_tlb_t *tlb6;
381 ppcemb_tlb_t *tlbe;
382 ppcmas_tlb_t *tlbm;
383 };
384
385 /* possible TLB variants */
386 #define TLB_NONE 0
387 #define TLB_6XX 1
388 #define TLB_EMB 2
389 #define TLB_MAS 3
390 #endif
391
392 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
393
394 typedef struct ppc_slb_t ppc_slb_t;
395 struct ppc_slb_t {
396 uint64_t esid;
397 uint64_t vsid;
398 const PPCHash64SegmentPageSizes *sps;
399 };
400
401 #define MAX_SLB_ENTRIES 64
402 #define SEGMENT_SHIFT_256M 28
403 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
404
405 #define SEGMENT_SHIFT_1T 40
406 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
407
408 typedef struct ppc_v3_pate_t {
409 uint64_t dw0;
410 uint64_t dw1;
411 } ppc_v3_pate_t;
412
413 /* PMU related structs and defines */
414 #define PMU_COUNTERS_NUM 6
415 typedef enum {
416 PMU_EVENT_INVALID = 0,
417 PMU_EVENT_INACTIVE,
418 PMU_EVENT_CYCLES,
419 PMU_EVENT_INSTRUCTIONS,
420 PMU_EVENT_INSN_RUN_LATCH,
421 } PMUEventType;
422
423 /*****************************************************************************/
424 /* Machine state register bits definition */
425 #define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */
426 #define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */
427 #define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */
428 #define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */
429 #define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */
430 #define MSR_TS1 PPC_BIT_NR(30)
431 #define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */
432 #define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */
433 #define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */
434 #define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */
435 #define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
436 #define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */
437 #define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */
438 #define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
439 #define MSR_S PPC_BIT_NR(41) /* Secure state */
440 #define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */
441 #define MSR_POW PPC_BIT_NR(45) /* Power management */
442 #define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */
443 #define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */
444 #define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */
445 #define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
446 #define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */
447 #define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */
448 #define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */
449 #define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */
450 #define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */
451 #define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
452 #define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */
453 #define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */
454 #define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */
455 #define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */
456 #define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */
457 #define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */
458 #define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */
459 #define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */
460 #define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */
461 #define MSR_DR PPC_BIT_NR(59) /* Data relocate */
462 #define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */
463 #define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */
464 #define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */
465 #define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */
466 #define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */
467 #define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
468
469 FIELD(MSR, SF, MSR_SF, 1)
470 FIELD(MSR, TAG, MSR_TAG, 1)
471 FIELD(MSR, ISF, MSR_ISF, 1)
472 #if defined(TARGET_PPC64)
473 FIELD(MSR, HV, MSR_HV, 1)
474 #define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
475 #else
476 #define FIELD_EX64_HV(storage) 0
477 #endif
478 FIELD(MSR, TS0, MSR_TS0, 1)
479 FIELD(MSR, TS1, MSR_TS1, 1)
480 FIELD(MSR, TS, MSR_TS0, 2)
481 FIELD(MSR, TM, MSR_TM, 1)
482 FIELD(MSR, CM, MSR_CM, 1)
483 FIELD(MSR, ICM, MSR_ICM, 1)
484 FIELD(MSR, GS, MSR_GS, 1)
485 FIELD(MSR, UCLE, MSR_UCLE, 1)
486 FIELD(MSR, VR, MSR_VR, 1)
487 FIELD(MSR, SPE, MSR_SPE, 1)
488 FIELD(MSR, VSX, MSR_VSX, 1)
489 FIELD(MSR, S, MSR_S, 1)
490 FIELD(MSR, KEY, MSR_KEY, 1)
491 FIELD(MSR, POW, MSR_POW, 1)
492 FIELD(MSR, WE, MSR_WE, 1)
493 FIELD(MSR, TGPR, MSR_TGPR, 1)
494 FIELD(MSR, CE, MSR_CE, 1)
495 FIELD(MSR, ILE, MSR_ILE, 1)
496 FIELD(MSR, EE, MSR_EE, 1)
497 FIELD(MSR, PR, MSR_PR, 1)
498 FIELD(MSR, FP, MSR_FP, 1)
499 FIELD(MSR, ME, MSR_ME, 1)
500 FIELD(MSR, FE0, MSR_FE0, 1)
501 FIELD(MSR, SE, MSR_SE, 1)
502 FIELD(MSR, DWE, MSR_DWE, 1)
503 FIELD(MSR, UBLE, MSR_UBLE, 1)
504 FIELD(MSR, BE, MSR_BE, 1)
505 FIELD(MSR, DE, MSR_DE, 1)
506 FIELD(MSR, FE1, MSR_FE1, 1)
507 FIELD(MSR, AL, MSR_AL, 1)
508 FIELD(MSR, EP, MSR_EP, 1)
509 FIELD(MSR, IR, MSR_IR, 1)
510 FIELD(MSR, DR, MSR_DR, 1)
511 FIELD(MSR, IS, MSR_IS, 1)
512 FIELD(MSR, DS, MSR_DS, 1)
513 FIELD(MSR, PE, MSR_PE, 1)
514 FIELD(MSR, PX, MSR_PX, 1)
515 FIELD(MSR, PMM, MSR_PMM, 1)
516 FIELD(MSR, RI, MSR_RI, 1)
517 FIELD(MSR, LE, MSR_LE, 1)
518
519 /*
520 * FE0 and FE1 bits are not side-by-side
521 * so we can't combine them using FIELD()
522 */
523 #define FIELD_EX64_FE(msr) \
524 ((FIELD_EX64(msr, MSR, FE0) << 1) | FIELD_EX64(msr, MSR, FE1))
525
526 /* PMU bits */
527 #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
528 #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Occurred */
529 #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */
530 #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */
531 #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */
532 #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */
533 #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */
534 #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */
535 #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */
536 #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */
537 #define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */
538 #define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */
539 #define MMCR0_FCP PPC_BIT(34) /* Freeze Counters/BHRB if PR=1 */
540 #define MMCR0_FCPC PPC_BIT(51) /* Condition for FCP bit */
541 #define MMCR0_BHRBA_NR PPC_BIT_NR(42) /* BHRB Available */
542 /* MMCR0 userspace r/w mask */
543 #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE)
544 /* MMCR2 userspace r/w mask */
545 #define MMCR2_FC1P0 PPC_BIT(1) /* MMCR2 FCnP0 for PMC1 */
546 #define MMCR2_FC2P0 PPC_BIT(10) /* MMCR2 FCnP0 for PMC2 */
547 #define MMCR2_FC3P0 PPC_BIT(19) /* MMCR2 FCnP0 for PMC3 */
548 #define MMCR2_FC4P0 PPC_BIT(28) /* MMCR2 FCnP0 for PMC4 */
549 #define MMCR2_FC5P0 PPC_BIT(37) /* MMCR2 FCnP0 for PMC5 */
550 #define MMCR2_FC6P0 PPC_BIT(46) /* MMCR2 FCnP0 for PMC6 */
551 #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \
552 MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0)
553
554 #define MMCRA_BHRBRD PPC_BIT(26) /* BHRB Recording Disable */
555 #define MMCRA_IFM_MASK PPC_BITMASK(32, 33) /* BHRB Instruction Filtering */
556 #define MMCRA_IFM_SHIFT PPC_BIT_NR(33)
557
558 #define MMCR1_EVT_SIZE 8
559 /* extract64() does a right shift before extracting */
560 #define MMCR1_PMC1SEL_START 32
561 #define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE)
562 #define MMCR1_PMC2SEL_START 40
563 #define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE)
564 #define MMCR1_PMC3SEL_START 48
565 #define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE)
566 #define MMCR1_PMC4SEL_START 56
567 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
568
569 /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
570 #define CTRL_RUN PPC_BIT(63)
571
572 /* EBB/BESCR bits */
573 /* Global Enable */
574 #define BESCR_GE PPC_BIT(0)
575 /* External Event-based Exception Enable */
576 #define BESCR_EE PPC_BIT(30)
577 /* Performance Monitor Event-based Exception Enable */
578 #define BESCR_PME PPC_BIT(31)
579 /* External Event-based Exception Occurred */
580 #define BESCR_EEO PPC_BIT(62)
581 /* Performance Monitor Event-based Exception Occurred */
582 #define BESCR_PMEO PPC_BIT(63)
583 #define BESCR_INVALID PPC_BITMASK(32, 33)
584
585 /* LPCR bits */
586 #define LPCR_VPM0 PPC_BIT(0)
587 #define LPCR_VPM1 PPC_BIT(1)
588 #define LPCR_ISL PPC_BIT(2)
589 #define LPCR_KBV PPC_BIT(3)
590 #define LPCR_DPFD_SHIFT (63 - 11)
591 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
592 #define LPCR_VRMASD_SHIFT (63 - 16)
593 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
594 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
595 #define LPCR_PECE_U_SHIFT (63 - 19)
596 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
597 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
598 #define LPCR_RMLS_SHIFT (63 - 37) /* RMLS (removed in ISA v3.0) */
599 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
600 #define LPCR_HAIL PPC_BIT(37) /* ISA v3.1 HV AIL=3 equivalent */
601 #define LPCR_ILE PPC_BIT(38)
602 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
603 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
604 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
605 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
606 #define LPCR_HR PPC_BIT(43) /* Host Radix */
607 #define LPCR_ONL PPC_BIT(45)
608 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */
609 #define LPCR_P7_PECE0 PPC_BIT(49)
610 #define LPCR_P7_PECE1 PPC_BIT(50)
611 #define LPCR_P7_PECE2 PPC_BIT(51)
612 #define LPCR_P8_PECE0 PPC_BIT(47)
613 #define LPCR_P8_PECE1 PPC_BIT(48)
614 #define LPCR_P8_PECE2 PPC_BIT(49)
615 #define LPCR_P8_PECE3 PPC_BIT(50)
616 #define LPCR_P8_PECE4 PPC_BIT(51)
617 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
618 #define LPCR_PECE_L_SHIFT (63 - 51)
619 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
620 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
621 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
622 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
623 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
624 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
625 #define LPCR_MER PPC_BIT(52)
626 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
627 #define LPCR_TC PPC_BIT(54)
628 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
629 #define LPCR_LPES0 PPC_BIT(60)
630 #define LPCR_LPES1 PPC_BIT(61)
631 #define LPCR_RMI PPC_BIT(62)
632 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
633 #define LPCR_HDICE PPC_BIT(63)
634
635 /* PSSCR bits */
636 #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
637 #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
638
639 /* HFSCR bits */
640 #define HFSCR_MSGP PPC_BIT_NR(53) /* Privileged Message Send Facilities */
641 #define HFSCR_BHRB PPC_BIT_NR(59) /* BHRB Instructions */
642 #define HFSCR_IC_MSGP 0xA
643
644 #define DBCR0_ICMP (1 << 27)
645 #define DBCR0_BRT (1 << 26)
646 #define DBSR_ICMP (1 << 27)
647 #define DBSR_BRT (1 << 26)
648
649 /* Hypervisor bit is more specific */
650 #if defined(TARGET_PPC64)
651 #define MSR_HVB (1ULL << MSR_HV)
652 #else
653 #define MSR_HVB (0ULL)
654 #endif
655
656 /* DSISR */
657 #define DSISR_NOPTE 0x40000000
658 /* Not permitted by access authority of encoded access authority */
659 #define DSISR_PROTFAULT 0x08000000
660 #define DSISR_ISSTORE 0x02000000
661 /* Not permitted by virtual page class key protection */
662 #define DSISR_AMR 0x00200000
663 /* Unsupported Radix Tree Configuration */
664 #define DSISR_R_BADCONFIG 0x00080000
665 #define DSISR_ATOMIC_RC 0x00040000
666 /* Unable to translate address of (guest) pde or process/page table entry */
667 #define DSISR_PRTABLE_FAULT 0x00020000
668
669 /* SRR1 error code fields */
670
671 #define SRR1_NOPTE DSISR_NOPTE
672 /* Not permitted due to no-execute or guard bit set */
673 #define SRR1_NOEXEC_GUARD 0x10000000
674 #define SRR1_PROTFAULT DSISR_PROTFAULT
675 #define SRR1_IAMR DSISR_AMR
676
677 /* SRR1[42:45] wakeup fields for System Reset Interrupt */
678
679 #define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */
680
681 #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
682 #define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */
683 #define SRR1_WAKEEE 0x00200000 /* External interrupt */
684 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
685 #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */
686 #define SRR1_WAKERESET 0x00100000 /* System reset */
687 #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */
688 #define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
689
690 /* SRR1[46:47] power-saving exit mode */
691
692 #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */
693
694 #define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
695 #define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
696 #define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
697
698 /* Facility Status and Control (FSCR) bits */
699 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
700 #define FSCR_TAR (63 - 55) /* Target Address Register */
701 #define FSCR_SCV (63 - 51) /* System call vectored */
702 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
703 #define FSCR_IC_MASK (0xFFULL)
704 #define FSCR_IC_POS (63 - 7)
705 #define FSCR_IC_DSCR_SPR3 2
706 #define FSCR_IC_PMU 3
707 #define FSCR_IC_BHRB 4
708 #define FSCR_IC_TM 5
709 #define FSCR_IC_EBB 7
710 #define FSCR_IC_TAR 8
711 #define FSCR_IC_SCV 12
712
713 /* Exception state register bits definition */
714 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
715 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
716 #define ESR_PTR PPC_BIT(38) /* Trap */
717 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
718 #define ESR_ST PPC_BIT(40) /* Store Operation */
719 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
720 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
721 #define ESR_BO PPC_BIT(46) /* Byte Ordering */
722 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */
723 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
724 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
725 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
726 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
727 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */
728 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */
729 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
730
731 /* Transaction EXception And Summary Register bits */
732 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
733 #define TEXASR_DISALLOWED (63 - 8)
734 #define TEXASR_NESTING_OVERFLOW (63 - 9)
735 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
736 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
737 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
738 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
739 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
740 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
741 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
742 #define TEXASR_ABORT (63 - 31)
743 #define TEXASR_SUSPENDED (63 - 32)
744 #define TEXASR_PRIVILEGE_HV (63 - 34)
745 #define TEXASR_PRIVILEGE_PR (63 - 35)
746 #define TEXASR_FAILURE_SUMMARY (63 - 36)
747 #define TEXASR_TFIAR_EXACT (63 - 37)
748 #define TEXASR_ROT (63 - 38)
749 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
750
751 enum {
752 POWERPC_FLAG_NONE = 0x00000000,
753 /* Flag for MSR bit 25 signification (VRE/SPE) */
754 POWERPC_FLAG_SPE = 0x00000001,
755 POWERPC_FLAG_VRE = 0x00000002,
756 /* Flag for MSR bit 17 signification (TGPR/CE) */
757 POWERPC_FLAG_TGPR = 0x00000004,
758 POWERPC_FLAG_CE = 0x00000008,
759 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
760 POWERPC_FLAG_SE = 0x00000010,
761 POWERPC_FLAG_DWE = 0x00000020,
762 POWERPC_FLAG_UBLE = 0x00000040,
763 /* Flag for MSR bit 9 signification (BE/DE) */
764 POWERPC_FLAG_BE = 0x00000080,
765 POWERPC_FLAG_DE = 0x00000100,
766 /* Flag for MSR bit 2 signification (PX/PMM) */
767 POWERPC_FLAG_PX = 0x00000200,
768 POWERPC_FLAG_PMM = 0x00000400,
769 /* Flag for special features */
770 /* Decrementer clock */
771 POWERPC_FLAG_BUS_CLK = 0x00020000,
772 /* Has CFAR */
773 POWERPC_FLAG_CFAR = 0x00040000,
774 /* Has VSX */
775 POWERPC_FLAG_VSX = 0x00080000,
776 /* Has Transaction Memory (ISA 2.07) */
777 POWERPC_FLAG_TM = 0x00100000,
778 /* Has SCV (ISA 3.00) */
779 POWERPC_FLAG_SCV = 0x00200000,
780 /* Has >1 thread per core */
781 POWERPC_FLAG_SMT = 0x00400000,
782 /* Using "LPAR per core" mode (as opposed to per-thread) */
783 POWERPC_FLAG_SMT_1LPAR = 0x00800000,
784 /* Has BHRB */
785 POWERPC_FLAG_BHRB = 0x01000000,
786 };
787
788 /*
789 * Bits for env->hflags.
790 *
791 * Most of these bits overlap with corresponding bits in MSR,
792 * but some come from other sources. Those that do come from
793 * the MSR are validated in hreg_compute_hflags.
794 */
795 enum {
796 HFLAGS_LE = 0, /* MSR_LE */
797 HFLAGS_HV = 1, /* computed from MSR_HV and other state */
798 HFLAGS_64 = 2, /* computed from MSR_CE and MSR_SF */
799 HFLAGS_GTSE = 3, /* computed from SPR_LPCR[GTSE] */
800 HFLAGS_DR = 4, /* MSR_DR */
801 HFLAGS_HR = 5, /* computed from SPR_LPCR[HR] */
802 HFLAGS_SPE = 6, /* from MSR_SPE if cpu has SPE; avoid overlap w/ MSR_VR */
803 HFLAGS_TM = 8, /* computed from MSR_TM */
804 HFLAGS_BE = 9, /* MSR_BE -- from elsewhere on embedded ppc */
805 HFLAGS_SE = 10, /* MSR_SE -- from elsewhere on embedded ppc */
806 HFLAGS_FP = 13, /* MSR_FP */
807 HFLAGS_PR = 14, /* MSR_PR */
808 HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */
809 HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */
810 HFLAGS_PMCJCE = 17, /* MMCR0 PMCjCE bit */
811 HFLAGS_PMC_OTHER = 18, /* PMC other than PMC5-6 is enabled */
812 HFLAGS_INSN_CNT = 19, /* PMU instruction count enabled */
813 HFLAGS_BHRB_ENABLE = 20, /* Summary flag for enabling BHRB */
814 HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */
815 HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */
816
817 HFLAGS_IMMU_IDX = 26, /* 26..28 -- the composite immu_idx */
818 HFLAGS_DMMU_IDX = 29, /* 29..31 -- the composite dmmu_idx */
819 };
820
821 /*****************************************************************************/
822 /* Floating point status and control register */
823 #define FPSCR_DRN2 PPC_BIT_NR(29) /* Decimal Floating-Point rounding ctrl. */
824 #define FPSCR_DRN1 PPC_BIT_NR(30) /* Decimal Floating-Point rounding ctrl. */
825 #define FPSCR_DRN0 PPC_BIT_NR(31) /* Decimal Floating-Point rounding ctrl. */
826 #define FPSCR_FX PPC_BIT_NR(32) /* Floating-point exception summary */
827 #define FPSCR_FEX PPC_BIT_NR(33) /* Floating-point enabled exception summ.*/
828 #define FPSCR_VX PPC_BIT_NR(34) /* Floating-point invalid op. excp. summ.*/
829 #define FPSCR_OX PPC_BIT_NR(35) /* Floating-point overflow exception */
830 #define FPSCR_UX PPC_BIT_NR(36) /* Floating-point underflow exception */
831 #define FPSCR_ZX PPC_BIT_NR(37) /* Floating-point zero divide exception */
832 #define FPSCR_XX PPC_BIT_NR(38) /* Floating-point inexact exception */
833 #define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp (sNan)*/
834 #define FPSCR_VXISI PPC_BIT_NR(40) /* Floating-point invalid op. excp (inf) */
835 #define FPSCR_VXIDI PPC_BIT_NR(41) /* Floating-point invalid op. excp (inf) */
836 #define FPSCR_VXZDZ PPC_BIT_NR(42) /* Floating-point invalid op. excp (zero)*/
837 #define FPSCR_VXIMZ PPC_BIT_NR(43) /* Floating-point invalid op. excp (inf) */
838 #define FPSCR_VXVC PPC_BIT_NR(44) /* Floating-point invalid op. excp (comp)*/
839 #define FPSCR_FR PPC_BIT_NR(45) /* Floating-point fraction rounded */
840 #define FPSCR_FI PPC_BIT_NR(46) /* Floating-point fraction inexact */
841 #define FPSCR_C PPC_BIT_NR(47) /* Floating-point result class descriptor*/
842 #define FPSCR_FL PPC_BIT_NR(48) /* Floating-point less than or negative */
843 #define FPSCR_FG PPC_BIT_NR(49) /* Floating-point greater than or neg. */
844 #define FPSCR_FE PPC_BIT_NR(50) /* Floating-point equal or zero */
845 #define FPSCR_FU PPC_BIT_NR(51) /* Floating-point unordered or NaN */
846 #define FPSCR_FPCC PPC_BIT_NR(51) /* Floating-point condition code */
847 #define FPSCR_FPRF PPC_BIT_NR(51) /* Floating-point result flags */
848 #define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp (soft)*/
849 #define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp (sqrt)*/
850 #define FPSCR_VXCVI PPC_BIT_NR(55) /* Floating-point invalid op. excp (int) */
851 #define FPSCR_VE PPC_BIT_NR(56) /* Floating-point invalid op. excp enable*/
852 #define FPSCR_OE PPC_BIT_NR(57) /* Floating-point overflow excp. enable */
853 #define FPSCR_UE PPC_BIT_NR(58) /* Floating-point underflow excp. enable */
854 #define FPSCR_ZE PPC_BIT_NR(59) /* Floating-point zero divide excp enable*/
855 #define FPSCR_XE PPC_BIT_NR(60) /* Floating-point inexact excp. enable */
856 #define FPSCR_NI PPC_BIT_NR(61) /* Floating-point non-IEEE mode */
857 #define FPSCR_RN1 PPC_BIT_NR(62)
858 #define FPSCR_RN0 PPC_BIT_NR(63) /* Floating-point rounding control */
859 /* Invalid operation exception summary */
860 #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
861 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
862 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
863 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
864 (1 << FPSCR_VXCVI))
865
866 FIELD(FPSCR, FI, FPSCR_FI, 1)
867
868 #define FP_DRN2 (1ull << FPSCR_DRN2)
869 #define FP_DRN1 (1ull << FPSCR_DRN1)
870 #define FP_DRN0 (1ull << FPSCR_DRN0)
871 #define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
872 #define FP_FX (1ull << FPSCR_FX)
873 #define FP_FEX (1ull << FPSCR_FEX)
874 #define FP_VX (1ull << FPSCR_VX)
875 #define FP_OX (1ull << FPSCR_OX)
876 #define FP_UX (1ull << FPSCR_UX)
877 #define FP_ZX (1ull << FPSCR_ZX)
878 #define FP_XX (1ull << FPSCR_XX)
879 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
880 #define FP_VXISI (1ull << FPSCR_VXISI)
881 #define FP_VXIDI (1ull << FPSCR_VXIDI)
882 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
883 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
884 #define FP_VXVC (1ull << FPSCR_VXVC)
885 #define FP_FR (1ull << FPSCR_FR)
886 #define FP_FI (1ull << FPSCR_FI)
887 #define FP_C (1ull << FPSCR_C)
888 #define FP_FL (1ull << FPSCR_FL)
889 #define FP_FG (1ull << FPSCR_FG)
890 #define FP_FE (1ull << FPSCR_FE)
891 #define FP_FU (1ull << FPSCR_FU)
892 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
893 #define FP_FPRF (FP_C | FP_FPCC)
894 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
895 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
896 #define FP_VXCVI (1ull << FPSCR_VXCVI)
897 #define FP_VE (1ull << FPSCR_VE)
898 #define FP_OE (1ull << FPSCR_OE)
899 #define FP_UE (1ull << FPSCR_UE)
900 #define FP_ZE (1ull << FPSCR_ZE)
901 #define FP_XE (1ull << FPSCR_XE)
902 #define FP_NI (1ull << FPSCR_NI)
903 #define FP_RN1 (1ull << FPSCR_RN1)
904 #define FP_RN0 (1ull << FPSCR_RN0)
905 #define FP_RN (FP_RN1 | FP_RN0)
906
907 #define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
908 #define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
909
910 /* the exception bits which can be cleared by mcrfs - includes FX */
911 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
912 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
913 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
914 FP_VXSQRT | FP_VXCVI)
915
916 /* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
917 #define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \
918 FP_FEX | FP_VX | PPC_BIT(52)))
919
920 /*****************************************************************************/
921 /* Vector status and control register */
922 #define VSCR_NJ 16 /* Vector non-java */
923 #define VSCR_SAT 0 /* Vector saturation */
924
925 /*****************************************************************************/
926 /* BookE e500 MMU registers */
927
928 #define MAS0_NV_SHIFT 0
929 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
930
931 #define MAS0_WQ_SHIFT 12
932 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
933 /* Write TLB entry regardless of reservation */
934 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
935 /* Write TLB entry only already in use */
936 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
937 /* Clear TLB entry */
938 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
939
940 #define MAS0_HES_SHIFT 14
941 #define MAS0_HES (1 << MAS0_HES_SHIFT)
942
943 #define MAS0_ESEL_SHIFT 16
944 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
945
946 #define MAS0_TLBSEL_SHIFT 28
947 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
948 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
949 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
950 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
951 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
952
953 #define MAS0_ATSEL_SHIFT 31
954 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
955 #define MAS0_ATSEL_TLB 0
956 #define MAS0_ATSEL_LRAT MAS0_ATSEL
957
958 #define MAS1_TSIZE_SHIFT 7
959 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
960
961 #define MAS1_TS_SHIFT 12
962 #define MAS1_TS (1 << MAS1_TS_SHIFT)
963
964 #define MAS1_IND_SHIFT 13
965 #define MAS1_IND (1 << MAS1_IND_SHIFT)
966
967 #define MAS1_TID_SHIFT 16
968 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
969
970 #define MAS1_IPROT_SHIFT 30
971 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
972
973 #define MAS1_VALID_SHIFT 31
974 #define MAS1_VALID 0x80000000
975
976 #define MAS2_EPN_SHIFT 12
977 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
978
979 #define MAS2_ACM_SHIFT 6
980 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
981
982 #define MAS2_VLE_SHIFT 5
983 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
984
985 #define MAS2_W_SHIFT 4
986 #define MAS2_W (1 << MAS2_W_SHIFT)
987
988 #define MAS2_I_SHIFT 3
989 #define MAS2_I (1 << MAS2_I_SHIFT)
990
991 #define MAS2_M_SHIFT 2
992 #define MAS2_M (1 << MAS2_M_SHIFT)
993
994 #define MAS2_G_SHIFT 1
995 #define MAS2_G (1 << MAS2_G_SHIFT)
996
997 #define MAS2_E_SHIFT 0
998 #define MAS2_E (1 << MAS2_E_SHIFT)
999
1000 #define MAS3_RPN_SHIFT 12
1001 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
1002
1003 #define MAS3_U0 0x00000200
1004 #define MAS3_U1 0x00000100
1005 #define MAS3_U2 0x00000080
1006 #define MAS3_U3 0x00000040
1007 #define MAS3_UX 0x00000020
1008 #define MAS3_SX 0x00000010
1009 #define MAS3_UW 0x00000008
1010 #define MAS3_SW 0x00000004
1011 #define MAS3_UR 0x00000002
1012 #define MAS3_SR 0x00000001
1013 #define MAS3_SPSIZE_SHIFT 1
1014 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
1015
1016 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
1017 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
1018 #define MAS4_TIDSELD_MASK 0x00030000
1019 #define MAS4_TIDSELD_PID0 0x00000000
1020 #define MAS4_TIDSELD_PID1 0x00010000
1021 #define MAS4_TIDSELD_PID2 0x00020000
1022 #define MAS4_TIDSELD_PIDZ 0x00030000
1023 #define MAS4_INDD 0x00008000 /* Default IND */
1024 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
1025 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
1026 #define MAS4_ACMD 0x00000040
1027 #define MAS4_VLED 0x00000020
1028 #define MAS4_WD 0x00000010
1029 #define MAS4_ID 0x00000008
1030 #define MAS4_MD 0x00000004
1031 #define MAS4_GD 0x00000002
1032 #define MAS4_ED 0x00000001
1033 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
1034 #define MAS4_WIMGED_SHIFT 0
1035
1036 #define MAS5_SGS 0x80000000
1037 #define MAS5_SLPID_MASK 0x00000fff
1038
1039 #define MAS6_SPID0 0x3fff0000
1040 #define MAS6_SPID1 0x00007ffe
1041 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
1042 #define MAS6_SAS 0x00000001
1043 #define MAS6_SPID MAS6_SPID0
1044 #define MAS6_SIND 0x00000002 /* Indirect page */
1045 #define MAS6_SIND_SHIFT 1
1046 #define MAS6_SPID_MASK 0x3fff0000
1047 #define MAS6_SPID_SHIFT 16
1048 #define MAS6_ISIZE_MASK 0x00000f80
1049 #define MAS6_ISIZE_SHIFT 7
1050
1051 #define MAS7_RPN 0xffffffff
1052
1053 #define MAS8_TGS 0x80000000
1054 #define MAS8_VF 0x40000000
1055 #define MAS8_TLBPID 0x00000fff
1056
1057 /* Bit definitions for MMUCFG */
1058 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
1059 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
1060 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
1061 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
1062 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
1063 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
1064 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
1065 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
1066 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
1067
1068 /* Bit definitions for MMUCSR0 */
1069 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
1070 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
1071 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
1072 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
1073 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
1074 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
1075 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
1076 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
1077 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
1078 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
1079
1080 /* TLBnCFG encoding */
1081 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
1082 #define TLBnCFG_HES 0x00002000 /* HW select supported */
1083 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
1084 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
1085 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
1086 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
1087 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
1088 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
1089 #define TLBnCFG_MINSIZE_SHIFT 20
1090 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
1091 #define TLBnCFG_MAXSIZE_SHIFT 16
1092 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
1093 #define TLBnCFG_ASSOC_SHIFT 24
1094
1095 /* TLBnPS encoding */
1096 #define TLBnPS_4K 0x00000004
1097 #define TLBnPS_8K 0x00000008
1098 #define TLBnPS_16K 0x00000010
1099 #define TLBnPS_32K 0x00000020
1100 #define TLBnPS_64K 0x00000040
1101 #define TLBnPS_128K 0x00000080
1102 #define TLBnPS_256K 0x00000100
1103 #define TLBnPS_512K 0x00000200
1104 #define TLBnPS_1M 0x00000400
1105 #define TLBnPS_2M 0x00000800
1106 #define TLBnPS_4M 0x00001000
1107 #define TLBnPS_8M 0x00002000
1108 #define TLBnPS_16M 0x00004000
1109 #define TLBnPS_32M 0x00008000
1110 #define TLBnPS_64M 0x00010000
1111 #define TLBnPS_128M 0x00020000
1112 #define TLBnPS_256M 0x00040000
1113 #define TLBnPS_512M 0x00080000
1114 #define TLBnPS_1G 0x00100000
1115 #define TLBnPS_2G 0x00200000
1116 #define TLBnPS_4G 0x00400000
1117 #define TLBnPS_8G 0x00800000
1118 #define TLBnPS_16G 0x01000000
1119 #define TLBnPS_32G 0x02000000
1120 #define TLBnPS_64G 0x04000000
1121 #define TLBnPS_128G 0x08000000
1122 #define TLBnPS_256G 0x10000000
1123
1124 /* tlbilx action encoding */
1125 #define TLBILX_T_ALL 0
1126 #define TLBILX_T_TID 1
1127 #define TLBILX_T_FULLMATCH 3
1128 #define TLBILX_T_CLASS0 4
1129 #define TLBILX_T_CLASS1 5
1130 #define TLBILX_T_CLASS2 6
1131 #define TLBILX_T_CLASS3 7
1132
1133 /* BookE 2.06 helper defines */
1134
1135 #define BOOKE206_FLUSH_TLB0 (1 << 0)
1136 #define BOOKE206_FLUSH_TLB1 (1 << 1)
1137 #define BOOKE206_FLUSH_TLB2 (1 << 2)
1138 #define BOOKE206_FLUSH_TLB3 (1 << 3)
1139
1140 /* number of possible TLBs */
1141 #define BOOKE206_MAX_TLBN 4
1142
1143 #define EPID_EPID_SHIFT 0x0
1144 #define EPID_EPID 0xFF
1145 #define EPID_ELPID_SHIFT 0x10
1146 #define EPID_ELPID 0x3F0000
1147 #define EPID_EGS 0x20000000
1148 #define EPID_EGS_SHIFT 29
1149 #define EPID_EAS 0x40000000
1150 #define EPID_EAS_SHIFT 30
1151 #define EPID_EPR 0x80000000
1152 #define EPID_EPR_SHIFT 31
1153 /* We don't support EGS and ELPID */
1154 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
1155
1156 /*****************************************************************************/
1157 /* Server and Embedded Processor Control */
1158
1159 #define DBELL_TYPE_SHIFT 27
1160 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
1161 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
1162 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
1163 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
1164 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
1165 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
1166
1167 #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
1168
1169 #define DBELL_BRDCAST_MASK PPC_BITMASK(37, 38)
1170 #define DBELL_BRDCAST_SHIFT 25
1171 #define DBELL_BRDCAST_SUBPROC (0x1 << DBELL_BRDCAST_SHIFT)
1172 #define DBELL_BRDCAST_CORE (0x2 << DBELL_BRDCAST_SHIFT)
1173
1174 #define DBELL_LPIDTAG_SHIFT 14
1175 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
1176 #define DBELL_PIRTAG_MASK 0x3fff
1177
1178 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
1179
1180 #define PPC_PAGE_SIZES_MAX_SZ 8
1181
1182 struct ppc_radix_page_info {
1183 uint32_t count;
1184 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
1185 };
1186
1187 /*****************************************************************************/
1188 /* Dynamic Execution Control Register */
1189
1190 #define DEXCR_ASPECT(name, num) \
1191 FIELD(DEXCR, PNH_##name, PPC_BIT_NR(num), 1) \
1192 FIELD(DEXCR, PRO_##name, PPC_BIT_NR(num + 32), 1) \
1193 FIELD(HDEXCR, HNU_##name, PPC_BIT_NR(num), 1) \
1194 FIELD(HDEXCR, ENF_##name, PPC_BIT_NR(num + 32), 1) \
1195
1196 DEXCR_ASPECT(SBHE, 0)
1197 DEXCR_ASPECT(IBRTPD, 1)
1198 DEXCR_ASPECT(SRAPD, 4)
1199 DEXCR_ASPECT(NPHIE, 5)
1200 DEXCR_ASPECT(PHIE, 6)
1201
1202 /*****************************************************************************/
1203 /* The whole PowerPC CPU context */
1204
1205 /*
1206 * PowerPC needs eight modes for different hypervisor/supervisor/guest
1207 * + real/paged mode combinations. The other two modes are for
1208 * external PID load/store.
1209 */
1210 #define PPC_TLB_EPID_LOAD 8
1211 #define PPC_TLB_EPID_STORE 9
1212
1213 #define PPC_CPU_OPCODES_LEN 0x40
1214 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1215
1216 #define BHRB_MAX_NUM_ENTRIES_LOG2 (5)
1217 #define BHRB_MAX_NUM_ENTRIES (1 << BHRB_MAX_NUM_ENTRIES_LOG2)
1218
1219 struct CPUArchState {
1220 /* Most commonly used resources during translated code execution first */
1221 target_ulong gpr[32]; /* general purpose registers */
1222 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
1223 target_ulong lr;
1224 target_ulong ctr;
1225 uint32_t crf[8]; /* condition register */
1226 #if defined(TARGET_PPC64)
1227 target_ulong cfar;
1228 #endif
1229 target_ulong xer; /* XER (with SO, OV, CA split out) */
1230 target_ulong so;
1231 target_ulong ov;
1232 target_ulong ca;
1233 target_ulong ov32;
1234 target_ulong ca32;
1235
1236 target_ulong reserve_addr; /* Reservation address */
1237 target_ulong reserve_length; /* Reservation larx op size (bytes) */
1238 target_ulong reserve_val; /* Reservation value */
1239 #if defined(TARGET_PPC64)
1240 target_ulong reserve_val2;
1241 #endif
1242
1243 /* These are used in supervisor mode only */
1244 target_ulong msr; /* machine state register */
1245 target_ulong tgpr[4]; /* temporary general purpose registers, */
1246 /* used to speed-up TLB assist handlers */
1247
1248 target_ulong nip; /* next instruction pointer */
1249
1250 /* when a memory exception occurs, the access type is stored here */
1251 int access_type;
1252
1253 /* For SMT processors */
1254 bool has_smt_siblings;
1255 int core_index;
1256
1257 #if !defined(CONFIG_USER_ONLY)
1258 /* MMU context, only relevant for full system emulation */
1259 #if defined(TARGET_PPC64)
1260 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
1261 struct CPUBreakpoint *ciabr_breakpoint;
1262 struct CPUWatchpoint *dawr0_watchpoint;
1263 #endif
1264 target_ulong sr[32]; /* segment registers */
1265 uint32_t nb_BATs; /* number of BATs */
1266 target_ulong DBAT[2][8];
1267 target_ulong IBAT[2][8];
1268 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1269 int32_t nb_tlb; /* Total number of TLB */
1270 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1271 int nb_ways; /* Number of ways in the TLB set */
1272 int last_way; /* Last used way used to allocate TLB in a LRU way */
1273 int nb_pids; /* Number of available PID registers */
1274 int tlb_type; /* Type of TLB we're dealing with */
1275 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1276 #ifdef CONFIG_KVM
1277 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1278 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1279 #endif /* CONFIG_KVM */
1280 uint32_t tlb_need_flush; /* Delayed flush needed */
1281 #define TLB_NEED_LOCAL_FLUSH 0x1
1282 #define TLB_NEED_GLOBAL_FLUSH 0x2
1283 #endif
1284
1285 /* Other registers */
1286 target_ulong spr[1024]; /* special purpose registers */
1287 ppc_spr_t spr_cb[1024];
1288 /* Composite status for PMC[1-6] enabled and counting insns or cycles. */
1289 uint8_t pmc_ins_cnt;
1290 uint8_t pmc_cyc_cnt;
1291 /* Vector status and control register, minus VSCR_SAT */
1292 uint32_t vscr;
1293 /* VSX registers (including FP and AVR) */
1294 ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1295 /* Non-zero if and only if VSCR_SAT should be set */
1296 ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1297 /* SPE registers */
1298 uint64_t spe_acc;
1299 uint32_t spe_fscr;
1300 /* SPE and Altivec share status as they'll never be used simultaneously */
1301 float_status vec_status;
1302 float_status fp_status; /* Floating point execution context */
1303 target_ulong fpscr; /* Floating point status and control register */
1304
1305 /* Internal devices resources */
1306 ppc_tb_t *tb_env; /* Time base and decrementer */
1307 ppc_dcr_t *dcr_env; /* Device control registers */
1308
1309 int dcache_line_size;
1310 int icache_line_size;
1311
1312 #ifdef TARGET_PPC64
1313 /* Branch History Rolling Buffer (BHRB) resources */
1314 target_ulong bhrb_num_entries;
1315 intptr_t bhrb_base;
1316 target_ulong bhrb_filter;
1317 target_ulong bhrb_offset;
1318 target_ulong bhrb_offset_mask;
1319 uint64_t bhrb[BHRB_MAX_NUM_ENTRIES];
1320 #endif
1321
1322 /* These resources are used during exception processing */
1323 /* CPU model definition */
1324 target_ulong msr_mask;
1325 powerpc_mmu_t mmu_model;
1326 powerpc_excp_t excp_model;
1327 powerpc_input_t bus_model;
1328 int bfd_mach;
1329 uint32_t flags;
1330 uint64_t insns_flags;
1331 uint64_t insns_flags2;
1332
1333 int error_code;
1334 uint32_t pending_interrupts;
1335 #if !defined(CONFIG_USER_ONLY)
1336 uint64_t excp_stats[POWERPC_EXCP_NB];
1337 /*
1338 * This is the IRQ controller, which is implementation dependent and only
1339 * relevant when emulating a complete machine. Note that this isn't used
1340 * by recent Book3s compatible CPUs (POWER7 and newer).
1341 */
1342 uint32_t irq_input_state;
1343
1344 target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1345 target_ulong excp_prefix;
1346 target_ulong ivor_mask;
1347 target_ulong ivpr_mask;
1348 target_ulong hreset_vector;
1349 hwaddr mpic_iack;
1350 bool mpic_proxy; /* true if the external proxy facility mode is enabled */
1351 bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1352 /* instructions and SPRs are diallowed if MSR:HV is 0 */
1353 /*
1354 * On P7/P8/P9, set when in PM state so we need to handle resume in a
1355 * special way (such as routing some resume causes to 0x100, i.e. sreset).
1356 */
1357 bool resume_as_sreset;
1358 #endif
1359
1360 /* These resources are used only in TCG */
1361 uint32_t hflags;
1362 target_ulong hflags_compat_nmsr; /* for migration compatibility */
1363
1364 /* Power management */
1365 int (*check_pow)(CPUPPCState *env);
1366
1367 /* attn instruction enable */
1368 int (*check_attn)(CPUPPCState *env);
1369
1370 #if !defined(CONFIG_USER_ONLY)
1371 void *load_info; /* holds boot loading state */
1372 #endif
1373
1374 /* booke timers */
1375
1376 /*
1377 * Specifies bit locations of the Time Base used to signal a fixed timer
1378 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1379 *
1380 * 0 selects the least significant bit, 63 selects the most significant bit
1381 */
1382 uint8_t fit_period[4];
1383 uint8_t wdt_period[4];
1384
1385 /* Transactional memory state */
1386 target_ulong tm_gpr[32];
1387 ppc_avr_t tm_vsr[64];
1388 uint64_t tm_cr;
1389 uint64_t tm_lr;
1390 uint64_t tm_ctr;
1391 uint64_t tm_fpscr;
1392 uint64_t tm_amr;
1393 uint64_t tm_ppr;
1394 uint64_t tm_vrsave;
1395 uint32_t tm_vscr;
1396 uint64_t tm_dscr;
1397 uint64_t tm_tar;
1398
1399 /*
1400 * Timers used to fire performance monitor alerts
1401 * when counting cycles.
1402 */
1403 QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM];
1404
1405 /*
1406 * PMU base time value used by the PMU to calculate
1407 * running cycles.
1408 */
1409 uint64_t pmu_base_time;
1410 };
1411
1412 #define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
1413 CPU_FOREACH(cs_sibling) \
1414 if (POWERPC_CPU(cs)->env.core_index == \
1415 POWERPC_CPU(cs_sibling)->env.core_index)
1416
1417 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1418 do { \
1419 env->fit_period[0] = (a_); \
1420 env->fit_period[1] = (b_); \
1421 env->fit_period[2] = (c_); \
1422 env->fit_period[3] = (d_); \
1423 } while (0)
1424
1425 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1426 do { \
1427 env->wdt_period[0] = (a_); \
1428 env->wdt_period[1] = (b_); \
1429 env->wdt_period[2] = (c_); \
1430 env->wdt_period[3] = (d_); \
1431 } while (0)
1432
1433 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1434 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1435
1436 /**
1437 * PowerPCCPU:
1438 * @env: #CPUPPCState
1439 * @vcpu_id: vCPU identifier given to KVM
1440 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1441 *
1442 * A PowerPC CPU.
1443 */
1444 struct ArchCPU {
1445 CPUState parent_obj;
1446
1447 CPUPPCState env;
1448
1449 int vcpu_id;
1450 uint32_t compat_pvr;
1451 PPCVirtualHypervisor *vhyp;
1452 PPCVirtualHypervisorClass *vhyp_class;
1453 void *machine_data;
1454 int32_t node_id; /* NUMA node this CPU belongs to */
1455 PPCHash64Options *hash64_opts;
1456
1457 /* Those resources are used only during code translation */
1458 /* opcode handlers */
1459 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1460 };
1461
1462 /**
1463 * PowerPCCPUClass:
1464 * @parent_realize: The parent class' realize handler.
1465 * @parent_phases: The parent class' reset phase handlers.
1466 *
1467 * A PowerPC CPU model.
1468 */
1469 struct PowerPCCPUClass {
1470 CPUClass parent_class;
1471
1472 DeviceRealize parent_realize;
1473 DeviceUnrealize parent_unrealize;
1474 ResettablePhases parent_phases;
1475 void (*parent_parse_features)(const char *type, char *str, Error **errp);
1476
1477 uint32_t pvr;
1478 uint32_t spapr_logical_pvr;
1479 /*
1480 * If @best is false, match if pcc is in the family of pvr
1481 * Else match only if pcc is the best match for pvr in this family.
1482 */
1483 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr, bool best);
1484 uint64_t pcr_mask; /* Available bits in PCR register */
1485 uint64_t pcr_supported; /* Bits for supported PowerISA versions */
1486 uint32_t svr;
1487 uint64_t insns_flags;
1488 uint64_t insns_flags2;
1489 uint64_t msr_mask;
1490 uint64_t lpcr_mask; /* Available bits in the LPCR */
1491 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
1492 powerpc_mmu_t mmu_model;
1493 powerpc_excp_t excp_model;
1494 powerpc_input_t bus_model;
1495 uint32_t flags;
1496 int bfd_mach;
1497 uint32_t l1_dcache_size, l1_icache_size;
1498 #ifndef CONFIG_USER_ONLY
1499 GDBFeature gdb_spr;
1500 #endif
1501 const PPCHash64Options *hash64_opts;
1502 struct ppc_radix_page_info *radix_page_info;
1503 uint32_t lrg_decr_bits;
1504 int n_host_threads;
1505 void (*init_proc)(CPUPPCState *env);
1506 int (*check_pow)(CPUPPCState *env);
1507 int (*check_attn)(CPUPPCState *env);
1508 };
1509
ppc_cpu_core_single_threaded(CPUState * cs)1510 static inline bool ppc_cpu_core_single_threaded(CPUState *cs)
1511 {
1512 return !POWERPC_CPU(cs)->env.has_smt_siblings;
1513 }
1514
ppc_cpu_lpar_single_threaded(CPUState * cs)1515 static inline bool ppc_cpu_lpar_single_threaded(CPUState *cs)
1516 {
1517 return !(POWERPC_CPU(cs)->env.flags & POWERPC_FLAG_SMT_1LPAR) ||
1518 ppc_cpu_core_single_threaded(cs);
1519 }
1520
1521 ObjectClass *ppc_cpu_class_by_name(const char *name);
1522 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1523 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1524 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1525
1526 #ifndef CONFIG_USER_ONLY
1527 struct PPCVirtualHypervisorClass {
1528 InterfaceClass parent;
1529 bool (*cpu_in_nested)(PowerPCCPU *cpu);
1530 void (*deliver_hv_excp)(PowerPCCPU *cpu, int excp);
1531 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1532 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1533 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1534 hwaddr ptex, int n);
1535 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1536 const ppc_hash_pte64_t *hptes,
1537 hwaddr ptex, int n);
1538 void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1539 void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1540 bool (*get_pate)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
1541 target_ulong lpid, ppc_v3_pate_t *entry);
1542 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1543 void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1544 void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1545 };
1546
1547 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor,PPCVirtualHypervisorClass,PPC_VIRTUAL_HYPERVISOR,TYPE_PPC_VIRTUAL_HYPERVISOR)1548 DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
1549 PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
1550
1551 static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
1552 {
1553 return cpu->vhyp_class->cpu_in_nested(cpu);
1554 }
1555 #endif /* CONFIG_USER_ONLY */
1556
1557 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1558 int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1559 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1560 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1561 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1562 #ifndef CONFIG_USER_ONLY
1563 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1564 #endif
1565 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1566 int cpuid, DumpState *s);
1567 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1568 int cpuid, DumpState *s);
1569 #ifndef CONFIG_USER_ONLY
1570 void ppc_maybe_interrupt(CPUPPCState *env);
1571 void ppc_cpu_do_interrupt(CPUState *cpu);
1572 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1573 void ppc_cpu_do_system_reset(CPUState *cs);
1574 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1575 extern const VMStateDescription vmstate_ppc_cpu;
1576 #endif
1577
1578 /*****************************************************************************/
1579 void ppc_translate_init(void);
1580
1581 #if !defined(CONFIG_USER_ONLY)
1582 void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1583 void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
1584 void ppc_update_ciabr(CPUPPCState *env);
1585 void ppc_store_ciabr(CPUPPCState *env, target_ulong value);
1586 void ppc_update_daw0(CPUPPCState *env);
1587 void ppc_store_dawr0(CPUPPCState *env, target_ulong value);
1588 void ppc_store_dawrx0(CPUPPCState *env, uint32_t value);
1589 #endif /* !defined(CONFIG_USER_ONLY) */
1590 void ppc_store_msr(CPUPPCState *env, target_ulong value);
1591
1592 void ppc_cpu_list(void);
1593
1594 /* Time-base and decrementer management */
1595 uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1596 uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1597 void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1598 void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1599 uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1600 uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1601 void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1602 void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1603 void cpu_ppc_increase_tb_by_offset(CPUPPCState *env, int64_t offset);
1604 void cpu_ppc_decrease_tb_by_offset(CPUPPCState *env, int64_t offset);
1605 uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1606 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1607 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1608 target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1609 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1610 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1611 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1612 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1613 uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1614 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1615 #if !defined(CONFIG_USER_ONLY)
1616 target_ulong load_40x_pit(CPUPPCState *env);
1617 void store_40x_pit(CPUPPCState *env, target_ulong val);
1618 void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1619 void store_40x_sler(CPUPPCState *env, uint32_t val);
1620 void store_40x_tcr(CPUPPCState *env, target_ulong val);
1621 void store_40x_tsr(CPUPPCState *env, target_ulong val);
1622 void store_booke_tcr(CPUPPCState *env, target_ulong val);
1623 void store_booke_tsr(CPUPPCState *env, target_ulong val);
1624 void ppc_tlb_invalidate_all(CPUPPCState *env);
1625 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1626 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1627 void cpu_ppc_set_1lpar(PowerPCCPU *cpu);
1628 #endif
1629
1630 void ppc_store_fpscr(CPUPPCState *env, target_ulong val);
1631 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1632 const char *caller, uint32_t cause);
1633
ppc_dump_gpr(CPUPPCState * env,int gprn)1634 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1635 {
1636 uint64_t gprv;
1637
1638 gprv = env->gpr[gprn];
1639 if (env->flags & POWERPC_FLAG_SPE) {
1640 /*
1641 * If the CPU implements the SPE extension, we have to get the
1642 * high bits of the GPR from the gprh storage area
1643 */
1644 gprv &= 0xFFFFFFFFULL;
1645 gprv |= (uint64_t)env->gprh[gprn] << 32;
1646 }
1647
1648 return gprv;
1649 }
1650
1651 /* Device control registers */
1652 int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1653 int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1654
1655 #define cpu_list ppc_cpu_list
1656
1657 /* MMU modes definitions */
1658 #define MMU_USER_IDX 0
ppc_env_mmu_index(CPUPPCState * env,bool ifetch)1659 static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch)
1660 {
1661 #ifdef CONFIG_USER_ONLY
1662 return MMU_USER_IDX;
1663 #else
1664 return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
1665 #endif
1666 }
1667
1668 /* Compatibility modes */
1669 #if defined(TARGET_PPC64)
1670 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1671 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1672 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1673 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1674
1675 int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1676
1677 #if !defined(CONFIG_USER_ONLY)
1678 int ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1679 int ppc_init_compat_all(uint32_t compat_pvr, Error **errp);
1680 #endif
1681 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1682 void ppc_compat_add_property(Object *obj, const char *name,
1683 uint32_t *compat_pvr, const char *basedesc);
1684 #endif /* defined(TARGET_PPC64) */
1685
1686 #include "exec/cpu-all.h"
1687
1688 /*****************************************************************************/
1689 /* CRF definitions */
1690 #define CRF_LT_BIT 3
1691 #define CRF_GT_BIT 2
1692 #define CRF_EQ_BIT 1
1693 #define CRF_SO_BIT 0
1694 #define CRF_LT (1 << CRF_LT_BIT)
1695 #define CRF_GT (1 << CRF_GT_BIT)
1696 #define CRF_EQ (1 << CRF_EQ_BIT)
1697 #define CRF_SO (1 << CRF_SO_BIT)
1698 /* For SPE extensions */
1699 #define CRF_CH (1 << CRF_LT_BIT)
1700 #define CRF_CL (1 << CRF_GT_BIT)
1701 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1702 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1703
1704 /* XER definitions */
1705 #define XER_SO 31
1706 #define XER_OV 30
1707 #define XER_CA 29
1708 #define XER_OV32 19
1709 #define XER_CA32 18
1710 #define XER_CMP 8
1711 #define XER_BC 0
1712 #define xer_so (env->so)
1713 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1714 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1715
1716 /* SPR definitions */
1717 #define SPR_MQ (0x000)
1718 #define SPR_XER (0x001)
1719 #define SPR_LR (0x008)
1720 #define SPR_CTR (0x009)
1721 #define SPR_UAMR (0x00D)
1722 #define SPR_DSCR (0x011)
1723 #define SPR_DSISR (0x012)
1724 #define SPR_DAR (0x013)
1725 #define SPR_DECR (0x016)
1726 #define SPR_SDR1 (0x019)
1727 #define SPR_SRR0 (0x01A)
1728 #define SPR_SRR1 (0x01B)
1729 #define SPR_CFAR (0x01C)
1730 #define SPR_AMR (0x01D)
1731 #define SPR_ACOP (0x01F)
1732 #define SPR_BOOKE_PID (0x030)
1733 #define SPR_BOOKS_PID (0x030)
1734 #define SPR_BOOKE_DECAR (0x036)
1735 #define SPR_BOOKE_CSRR0 (0x03A)
1736 #define SPR_BOOKE_CSRR1 (0x03B)
1737 #define SPR_BOOKE_DEAR (0x03D)
1738 #define SPR_IAMR (0x03D)
1739 #define SPR_BOOKE_ESR (0x03E)
1740 #define SPR_BOOKE_IVPR (0x03F)
1741 #define SPR_MPC_EIE (0x050)
1742 #define SPR_MPC_EID (0x051)
1743 #define SPR_MPC_NRI (0x052)
1744 #define SPR_TFHAR (0x080)
1745 #define SPR_TFIAR (0x081)
1746 #define SPR_TEXASR (0x082)
1747 #define SPR_TEXASRU (0x083)
1748 #define SPR_UCTRL (0x088)
1749 #define SPR_TIDR (0x090)
1750 #define SPR_MPC_CMPA (0x090)
1751 #define SPR_MPC_CMPB (0x091)
1752 #define SPR_MPC_CMPC (0x092)
1753 #define SPR_MPC_CMPD (0x093)
1754 #define SPR_MPC_ECR (0x094)
1755 #define SPR_MPC_DER (0x095)
1756 #define SPR_MPC_COUNTA (0x096)
1757 #define SPR_MPC_COUNTB (0x097)
1758 #define SPR_CTRL (0x098)
1759 #define SPR_MPC_CMPE (0x098)
1760 #define SPR_MPC_CMPF (0x099)
1761 #define SPR_FSCR (0x099)
1762 #define SPR_MPC_CMPG (0x09A)
1763 #define SPR_MPC_CMPH (0x09B)
1764 #define SPR_MPC_LCTRL1 (0x09C)
1765 #define SPR_MPC_LCTRL2 (0x09D)
1766 #define SPR_UAMOR (0x09D)
1767 #define SPR_MPC_ICTRL (0x09E)
1768 #define SPR_MPC_BAR (0x09F)
1769 #define SPR_PSPB (0x09F)
1770 #define SPR_DPDES (0x0B0)
1771 #define SPR_DAWR0 (0x0B4)
1772 #define SPR_DAWR1 (0x0B5)
1773 #define SPR_RPR (0x0BA)
1774 #define SPR_CIABR (0x0BB)
1775 #define SPR_DAWRX0 (0x0BC)
1776 #define SPR_DAWRX1 (0x0BD)
1777 #define SPR_HFSCR (0x0BE)
1778 #define SPR_VRSAVE (0x100)
1779 #define SPR_USPRG0 (0x100)
1780 #define SPR_USPRG1 (0x101)
1781 #define SPR_USPRG2 (0x102)
1782 #define SPR_USPRG3 (0x103)
1783 #define SPR_USPRG4 (0x104)
1784 #define SPR_USPRG5 (0x105)
1785 #define SPR_USPRG6 (0x106)
1786 #define SPR_USPRG7 (0x107)
1787 #define SPR_TBL (0x10C)
1788 #define SPR_TBU (0x10D)
1789 #define SPR_SPRG0 (0x110)
1790 #define SPR_SPRG1 (0x111)
1791 #define SPR_SPRG2 (0x112)
1792 #define SPR_SPRG3 (0x113)
1793 #define SPR_SPRG4 (0x114)
1794 #define SPR_POWER_SPRC (0x114)
1795 #define SPR_SPRG5 (0x115)
1796 #define SPR_POWER_SPRD (0x115)
1797 #define SPR_SPRG6 (0x116)
1798 #define SPR_SPRG7 (0x117)
1799 #define SPR_ASR (0x118)
1800 #define SPR_EAR (0x11A)
1801 #define SPR_WR_TBL (0x11C)
1802 #define SPR_WR_TBU (0x11D)
1803 #define SPR_TBU40 (0x11E)
1804 #define SPR_SVR (0x11E)
1805 #define SPR_BOOKE_PIR (0x11E)
1806 #define SPR_PVR (0x11F)
1807 #define SPR_HSPRG0 (0x130)
1808 #define SPR_BOOKE_DBSR (0x130)
1809 #define SPR_HSPRG1 (0x131)
1810 #define SPR_HDSISR (0x132)
1811 #define SPR_HDAR (0x133)
1812 #define SPR_BOOKE_EPCR (0x133)
1813 #define SPR_SPURR (0x134)
1814 #define SPR_BOOKE_DBCR0 (0x134)
1815 #define SPR_IBCR (0x135)
1816 #define SPR_PURR (0x135)
1817 #define SPR_BOOKE_DBCR1 (0x135)
1818 #define SPR_DBCR (0x136)
1819 #define SPR_HDEC (0x136)
1820 #define SPR_BOOKE_DBCR2 (0x136)
1821 #define SPR_HIOR (0x137)
1822 #define SPR_MBAR (0x137)
1823 #define SPR_RMOR (0x138)
1824 #define SPR_BOOKE_IAC1 (0x138)
1825 #define SPR_HRMOR (0x139)
1826 #define SPR_BOOKE_IAC2 (0x139)
1827 #define SPR_HSRR0 (0x13A)
1828 #define SPR_BOOKE_IAC3 (0x13A)
1829 #define SPR_HSRR1 (0x13B)
1830 #define SPR_BOOKE_IAC4 (0x13B)
1831 #define SPR_BOOKE_DAC1 (0x13C)
1832 #define SPR_MMCRH (0x13C)
1833 #define SPR_DABR2 (0x13D)
1834 #define SPR_BOOKE_DAC2 (0x13D)
1835 #define SPR_TFMR (0x13D)
1836 #define SPR_BOOKE_DVC1 (0x13E)
1837 #define SPR_LPCR (0x13E)
1838 #define SPR_BOOKE_DVC2 (0x13F)
1839 #define SPR_LPIDR (0x13F)
1840 #define SPR_BOOKE_TSR (0x150)
1841 #define SPR_HMER (0x150)
1842 #define SPR_HMEER (0x151)
1843 #define SPR_PCR (0x152)
1844 #define SPR_HEIR (0x153)
1845 #define SPR_BOOKE_LPIDR (0x152)
1846 #define SPR_BOOKE_TCR (0x154)
1847 #define SPR_BOOKE_TLB0PS (0x158)
1848 #define SPR_BOOKE_TLB1PS (0x159)
1849 #define SPR_BOOKE_TLB2PS (0x15A)
1850 #define SPR_BOOKE_TLB3PS (0x15B)
1851 #define SPR_AMOR (0x15D)
1852 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1853 #define SPR_BOOKE_IVOR0 (0x190)
1854 #define SPR_BOOKE_IVOR1 (0x191)
1855 #define SPR_BOOKE_IVOR2 (0x192)
1856 #define SPR_BOOKE_IVOR3 (0x193)
1857 #define SPR_BOOKE_IVOR4 (0x194)
1858 #define SPR_BOOKE_IVOR5 (0x195)
1859 #define SPR_BOOKE_IVOR6 (0x196)
1860 #define SPR_BOOKE_IVOR7 (0x197)
1861 #define SPR_BOOKE_IVOR8 (0x198)
1862 #define SPR_BOOKE_IVOR9 (0x199)
1863 #define SPR_BOOKE_IVOR10 (0x19A)
1864 #define SPR_BOOKE_IVOR11 (0x19B)
1865 #define SPR_BOOKE_IVOR12 (0x19C)
1866 #define SPR_BOOKE_IVOR13 (0x19D)
1867 #define SPR_BOOKE_IVOR14 (0x19E)
1868 #define SPR_BOOKE_IVOR15 (0x19F)
1869 #define SPR_BOOKE_IVOR38 (0x1B0)
1870 #define SPR_BOOKE_IVOR39 (0x1B1)
1871 #define SPR_BOOKE_IVOR40 (0x1B2)
1872 #define SPR_BOOKE_IVOR41 (0x1B3)
1873 #define SPR_BOOKE_IVOR42 (0x1B4)
1874 #define SPR_BOOKE_GIVOR2 (0x1B8)
1875 #define SPR_BOOKE_GIVOR3 (0x1B9)
1876 #define SPR_BOOKE_GIVOR4 (0x1BA)
1877 #define SPR_BOOKE_GIVOR8 (0x1BB)
1878 #define SPR_BOOKE_GIVOR13 (0x1BC)
1879 #define SPR_BOOKE_GIVOR14 (0x1BD)
1880 #define SPR_TIR (0x1BE)
1881 #define SPR_UHDEXCR (0x1C7)
1882 #define SPR_PTCR (0x1D0)
1883 #define SPR_HASHKEYR (0x1D4)
1884 #define SPR_HASHPKEYR (0x1D5)
1885 #define SPR_HDEXCR (0x1D7)
1886 #define SPR_BOOKE_SPEFSCR (0x200)
1887 #define SPR_Exxx_BBEAR (0x201)
1888 #define SPR_Exxx_BBTAR (0x202)
1889 #define SPR_Exxx_L1CFG0 (0x203)
1890 #define SPR_Exxx_L1CFG1 (0x204)
1891 #define SPR_Exxx_NPIDR (0x205)
1892 #define SPR_ATBL (0x20E)
1893 #define SPR_ATBU (0x20F)
1894 #define SPR_IBAT0U (0x210)
1895 #define SPR_BOOKE_IVOR32 (0x210)
1896 #define SPR_RCPU_MI_GRA (0x210)
1897 #define SPR_IBAT0L (0x211)
1898 #define SPR_BOOKE_IVOR33 (0x211)
1899 #define SPR_IBAT1U (0x212)
1900 #define SPR_BOOKE_IVOR34 (0x212)
1901 #define SPR_IBAT1L (0x213)
1902 #define SPR_BOOKE_IVOR35 (0x213)
1903 #define SPR_IBAT2U (0x214)
1904 #define SPR_BOOKE_IVOR36 (0x214)
1905 #define SPR_IBAT2L (0x215)
1906 #define SPR_BOOKE_IVOR37 (0x215)
1907 #define SPR_IBAT3U (0x216)
1908 #define SPR_IBAT3L (0x217)
1909 #define SPR_DBAT0U (0x218)
1910 #define SPR_RCPU_L2U_GRA (0x218)
1911 #define SPR_DBAT0L (0x219)
1912 #define SPR_DBAT1U (0x21A)
1913 #define SPR_DBAT1L (0x21B)
1914 #define SPR_DBAT2U (0x21C)
1915 #define SPR_DBAT2L (0x21D)
1916 #define SPR_DBAT3U (0x21E)
1917 #define SPR_DBAT3L (0x21F)
1918 #define SPR_IBAT4U (0x230)
1919 #define SPR_RPCU_BBCMCR (0x230)
1920 #define SPR_MPC_IC_CST (0x230)
1921 #define SPR_Exxx_CTXCR (0x230)
1922 #define SPR_IBAT4L (0x231)
1923 #define SPR_MPC_IC_ADR (0x231)
1924 #define SPR_Exxx_DBCR3 (0x231)
1925 #define SPR_IBAT5U (0x232)
1926 #define SPR_MPC_IC_DAT (0x232)
1927 #define SPR_Exxx_DBCNT (0x232)
1928 #define SPR_IBAT5L (0x233)
1929 #define SPR_IBAT6U (0x234)
1930 #define SPR_IBAT6L (0x235)
1931 #define SPR_IBAT7U (0x236)
1932 #define SPR_IBAT7L (0x237)
1933 #define SPR_DBAT4U (0x238)
1934 #define SPR_RCPU_L2U_MCR (0x238)
1935 #define SPR_MPC_DC_CST (0x238)
1936 #define SPR_Exxx_ALTCTXCR (0x238)
1937 #define SPR_DBAT4L (0x239)
1938 #define SPR_MPC_DC_ADR (0x239)
1939 #define SPR_DBAT5U (0x23A)
1940 #define SPR_BOOKE_MCSRR0 (0x23A)
1941 #define SPR_MPC_DC_DAT (0x23A)
1942 #define SPR_DBAT5L (0x23B)
1943 #define SPR_BOOKE_MCSRR1 (0x23B)
1944 #define SPR_DBAT6U (0x23C)
1945 #define SPR_BOOKE_MCSR (0x23C)
1946 #define SPR_DBAT6L (0x23D)
1947 #define SPR_Exxx_MCAR (0x23D)
1948 #define SPR_DBAT7U (0x23E)
1949 #define SPR_BOOKE_DSRR0 (0x23E)
1950 #define SPR_DBAT7L (0x23F)
1951 #define SPR_BOOKE_DSRR1 (0x23F)
1952 #define SPR_BOOKE_SPRG8 (0x25C)
1953 #define SPR_BOOKE_SPRG9 (0x25D)
1954 #define SPR_BOOKE_MAS0 (0x270)
1955 #define SPR_BOOKE_MAS1 (0x271)
1956 #define SPR_BOOKE_MAS2 (0x272)
1957 #define SPR_BOOKE_MAS3 (0x273)
1958 #define SPR_BOOKE_MAS4 (0x274)
1959 #define SPR_BOOKE_MAS5 (0x275)
1960 #define SPR_BOOKE_MAS6 (0x276)
1961 #define SPR_BOOKE_PID1 (0x279)
1962 #define SPR_BOOKE_PID2 (0x27A)
1963 #define SPR_MPC_DPDR (0x280)
1964 #define SPR_MPC_IMMR (0x288)
1965 #define SPR_BOOKE_TLB0CFG (0x2B0)
1966 #define SPR_BOOKE_TLB1CFG (0x2B1)
1967 #define SPR_BOOKE_TLB2CFG (0x2B2)
1968 #define SPR_BOOKE_TLB3CFG (0x2B3)
1969 #define SPR_BOOKE_EPR (0x2BE)
1970 #define SPR_POWER_USIER2 (0x2E0)
1971 #define SPR_POWER_USIER3 (0x2E1)
1972 #define SPR_POWER_UMMCR3 (0x2E2)
1973 #define SPR_POWER_SIER2 (0x2F0)
1974 #define SPR_POWER_SIER3 (0x2F1)
1975 #define SPR_POWER_MMCR3 (0x2F2)
1976 #define SPR_PERF0 (0x300)
1977 #define SPR_RCPU_MI_RBA0 (0x300)
1978 #define SPR_MPC_MI_CTR (0x300)
1979 #define SPR_POWER_USIER (0x300)
1980 #define SPR_PERF1 (0x301)
1981 #define SPR_RCPU_MI_RBA1 (0x301)
1982 #define SPR_POWER_UMMCR2 (0x301)
1983 #define SPR_PERF2 (0x302)
1984 #define SPR_RCPU_MI_RBA2 (0x302)
1985 #define SPR_MPC_MI_AP (0x302)
1986 #define SPR_POWER_UMMCRA (0x302)
1987 #define SPR_PERF3 (0x303)
1988 #define SPR_RCPU_MI_RBA3 (0x303)
1989 #define SPR_MPC_MI_EPN (0x303)
1990 #define SPR_POWER_UPMC1 (0x303)
1991 #define SPR_PERF4 (0x304)
1992 #define SPR_POWER_UPMC2 (0x304)
1993 #define SPR_PERF5 (0x305)
1994 #define SPR_MPC_MI_TWC (0x305)
1995 #define SPR_POWER_UPMC3 (0x305)
1996 #define SPR_PERF6 (0x306)
1997 #define SPR_MPC_MI_RPN (0x306)
1998 #define SPR_POWER_UPMC4 (0x306)
1999 #define SPR_PERF7 (0x307)
2000 #define SPR_POWER_UPMC5 (0x307)
2001 #define SPR_PERF8 (0x308)
2002 #define SPR_RCPU_L2U_RBA0 (0x308)
2003 #define SPR_MPC_MD_CTR (0x308)
2004 #define SPR_POWER_UPMC6 (0x308)
2005 #define SPR_PERF9 (0x309)
2006 #define SPR_RCPU_L2U_RBA1 (0x309)
2007 #define SPR_MPC_MD_CASID (0x309)
2008 #define SPR_970_UPMC7 (0X309)
2009 #define SPR_PERFA (0x30A)
2010 #define SPR_RCPU_L2U_RBA2 (0x30A)
2011 #define SPR_MPC_MD_AP (0x30A)
2012 #define SPR_970_UPMC8 (0X30A)
2013 #define SPR_PERFB (0x30B)
2014 #define SPR_RCPU_L2U_RBA3 (0x30B)
2015 #define SPR_MPC_MD_EPN (0x30B)
2016 #define SPR_POWER_UMMCR0 (0X30B)
2017 #define SPR_PERFC (0x30C)
2018 #define SPR_MPC_MD_TWB (0x30C)
2019 #define SPR_POWER_USIAR (0X30C)
2020 #define SPR_PERFD (0x30D)
2021 #define SPR_MPC_MD_TWC (0x30D)
2022 #define SPR_POWER_USDAR (0X30D)
2023 #define SPR_PERFE (0x30E)
2024 #define SPR_MPC_MD_RPN (0x30E)
2025 #define SPR_POWER_UMMCR1 (0X30E)
2026 #define SPR_PERFF (0x30F)
2027 #define SPR_MPC_MD_TW (0x30F)
2028 #define SPR_UPERF0 (0x310)
2029 #define SPR_POWER_SIER (0x310)
2030 #define SPR_UPERF1 (0x311)
2031 #define SPR_POWER_MMCR2 (0x311)
2032 #define SPR_UPERF2 (0x312)
2033 #define SPR_POWER_MMCRA (0X312)
2034 #define SPR_UPERF3 (0x313)
2035 #define SPR_POWER_PMC1 (0X313)
2036 #define SPR_UPERF4 (0x314)
2037 #define SPR_POWER_PMC2 (0X314)
2038 #define SPR_UPERF5 (0x315)
2039 #define SPR_POWER_PMC3 (0X315)
2040 #define SPR_UPERF6 (0x316)
2041 #define SPR_POWER_PMC4 (0X316)
2042 #define SPR_UPERF7 (0x317)
2043 #define SPR_POWER_PMC5 (0X317)
2044 #define SPR_UPERF8 (0x318)
2045 #define SPR_POWER_PMC6 (0X318)
2046 #define SPR_UPERF9 (0x319)
2047 #define SPR_970_PMC7 (0X319)
2048 #define SPR_UPERFA (0x31A)
2049 #define SPR_970_PMC8 (0X31A)
2050 #define SPR_UPERFB (0x31B)
2051 #define SPR_POWER_MMCR0 (0X31B)
2052 #define SPR_UPERFC (0x31C)
2053 #define SPR_POWER_SIAR (0X31C)
2054 #define SPR_UPERFD (0x31D)
2055 #define SPR_POWER_SDAR (0X31D)
2056 #define SPR_UPERFE (0x31E)
2057 #define SPR_POWER_MMCR1 (0X31E)
2058 #define SPR_UPERFF (0x31F)
2059 #define SPR_RCPU_MI_RA0 (0x320)
2060 #define SPR_MPC_MI_DBCAM (0x320)
2061 #define SPR_BESCRS (0x320)
2062 #define SPR_RCPU_MI_RA1 (0x321)
2063 #define SPR_MPC_MI_DBRAM0 (0x321)
2064 #define SPR_BESCRSU (0x321)
2065 #define SPR_RCPU_MI_RA2 (0x322)
2066 #define SPR_MPC_MI_DBRAM1 (0x322)
2067 #define SPR_BESCRR (0x322)
2068 #define SPR_RCPU_MI_RA3 (0x323)
2069 #define SPR_BESCRRU (0x323)
2070 #define SPR_EBBHR (0x324)
2071 #define SPR_EBBRR (0x325)
2072 #define SPR_BESCR (0x326)
2073 #define SPR_RCPU_L2U_RA0 (0x328)
2074 #define SPR_MPC_MD_DBCAM (0x328)
2075 #define SPR_RCPU_L2U_RA1 (0x329)
2076 #define SPR_MPC_MD_DBRAM0 (0x329)
2077 #define SPR_RCPU_L2U_RA2 (0x32A)
2078 #define SPR_MPC_MD_DBRAM1 (0x32A)
2079 #define SPR_RCPU_L2U_RA3 (0x32B)
2080 #define SPR_UDEXCR (0x32C)
2081 #define SPR_TAR (0x32F)
2082 #define SPR_ASDR (0x330)
2083 #define SPR_DEXCR (0x33C)
2084 #define SPR_IC (0x350)
2085 #define SPR_VTB (0x351)
2086 #define SPR_LDBAR (0x352)
2087 #define SPR_MMCRC (0x353)
2088 #define SPR_PSSCR (0x357)
2089 #define SPR_440_INV0 (0x370)
2090 #define SPR_440_INV1 (0x371)
2091 #define SPR_TRIG1 (0x371)
2092 #define SPR_440_INV2 (0x372)
2093 #define SPR_TRIG2 (0x372)
2094 #define SPR_440_INV3 (0x373)
2095 #define SPR_440_ITV0 (0x374)
2096 #define SPR_440_ITV1 (0x375)
2097 #define SPR_440_ITV2 (0x376)
2098 #define SPR_440_ITV3 (0x377)
2099 #define SPR_440_CCR1 (0x378)
2100 #define SPR_TACR (0x378)
2101 #define SPR_TCSCR (0x379)
2102 #define SPR_CSIGR (0x37a)
2103 #define SPR_DCRIPR (0x37B)
2104 #define SPR_POWER_SPMC1 (0x37C)
2105 #define SPR_POWER_SPMC2 (0x37D)
2106 #define SPR_POWER_MMCRS (0x37E)
2107 #define SPR_WORT (0x37F)
2108 #define SPR_PPR (0x380)
2109 #define SPR_PPR32 (0x382)
2110 #define SPR_750_GQR0 (0x390)
2111 #define SPR_440_DNV0 (0x390)
2112 #define SPR_750_GQR1 (0x391)
2113 #define SPR_440_DNV1 (0x391)
2114 #define SPR_750_GQR2 (0x392)
2115 #define SPR_440_DNV2 (0x392)
2116 #define SPR_750_GQR3 (0x393)
2117 #define SPR_440_DNV3 (0x393)
2118 #define SPR_750_GQR4 (0x394)
2119 #define SPR_440_DTV0 (0x394)
2120 #define SPR_750_GQR5 (0x395)
2121 #define SPR_440_DTV1 (0x395)
2122 #define SPR_750_GQR6 (0x396)
2123 #define SPR_440_DTV2 (0x396)
2124 #define SPR_750_GQR7 (0x397)
2125 #define SPR_440_DTV3 (0x397)
2126 #define SPR_750_THRM4 (0x398)
2127 #define SPR_750CL_HID2 (0x398)
2128 #define SPR_440_DVLIM (0x398)
2129 #define SPR_750_WPAR (0x399)
2130 #define SPR_440_IVLIM (0x399)
2131 #define SPR_TSCR (0x399)
2132 #define SPR_750_DMAU (0x39A)
2133 #define SPR_POWER_TTR (0x39A)
2134 #define SPR_750_DMAL (0x39B)
2135 #define SPR_440_RSTCFG (0x39B)
2136 #define SPR_BOOKE_DCDBTRL (0x39C)
2137 #define SPR_BOOKE_DCDBTRH (0x39D)
2138 #define SPR_BOOKE_ICDBTRL (0x39E)
2139 #define SPR_BOOKE_ICDBTRH (0x39F)
2140 #define SPR_74XX_UMMCR2 (0x3A0)
2141 #define SPR_7XX_UPMC5 (0x3A1)
2142 #define SPR_7XX_UPMC6 (0x3A2)
2143 #define SPR_UBAMR (0x3A7)
2144 #define SPR_7XX_UMMCR0 (0x3A8)
2145 #define SPR_7XX_UPMC1 (0x3A9)
2146 #define SPR_7XX_UPMC2 (0x3AA)
2147 #define SPR_7XX_USIAR (0x3AB)
2148 #define SPR_7XX_UMMCR1 (0x3AC)
2149 #define SPR_7XX_UPMC3 (0x3AD)
2150 #define SPR_7XX_UPMC4 (0x3AE)
2151 #define SPR_USDA (0x3AF)
2152 #define SPR_40x_ZPR (0x3B0)
2153 #define SPR_BOOKE_MAS7 (0x3B0)
2154 #define SPR_74XX_MMCR2 (0x3B0)
2155 #define SPR_7XX_PMC5 (0x3B1)
2156 #define SPR_40x_PID (0x3B1)
2157 #define SPR_7XX_PMC6 (0x3B2)
2158 #define SPR_440_MMUCR (0x3B2)
2159 #define SPR_4xx_CCR0 (0x3B3)
2160 #define SPR_BOOKE_EPLC (0x3B3)
2161 #define SPR_405_IAC3 (0x3B4)
2162 #define SPR_BOOKE_EPSC (0x3B4)
2163 #define SPR_405_IAC4 (0x3B5)
2164 #define SPR_405_DVC1 (0x3B6)
2165 #define SPR_405_DVC2 (0x3B7)
2166 #define SPR_BAMR (0x3B7)
2167 #define SPR_7XX_MMCR0 (0x3B8)
2168 #define SPR_7XX_PMC1 (0x3B9)
2169 #define SPR_40x_SGR (0x3B9)
2170 #define SPR_7XX_PMC2 (0x3BA)
2171 #define SPR_40x_DCWR (0x3BA)
2172 #define SPR_7XX_SIAR (0x3BB)
2173 #define SPR_405_SLER (0x3BB)
2174 #define SPR_7XX_MMCR1 (0x3BC)
2175 #define SPR_405_SU0R (0x3BC)
2176 #define SPR_401_SKR (0x3BC)
2177 #define SPR_7XX_PMC3 (0x3BD)
2178 #define SPR_405_DBCR1 (0x3BD)
2179 #define SPR_7XX_PMC4 (0x3BE)
2180 #define SPR_SDA (0x3BF)
2181 #define SPR_403_VTBL (0x3CC)
2182 #define SPR_403_VTBU (0x3CD)
2183 #define SPR_DMISS (0x3D0)
2184 #define SPR_DCMP (0x3D1)
2185 #define SPR_HASH1 (0x3D2)
2186 #define SPR_HASH2 (0x3D3)
2187 #define SPR_BOOKE_ICDBDR (0x3D3)
2188 #define SPR_TLBMISS (0x3D4)
2189 #define SPR_IMISS (0x3D4)
2190 #define SPR_40x_ESR (0x3D4)
2191 #define SPR_PTEHI (0x3D5)
2192 #define SPR_ICMP (0x3D5)
2193 #define SPR_40x_DEAR (0x3D5)
2194 #define SPR_PTELO (0x3D6)
2195 #define SPR_RPA (0x3D6)
2196 #define SPR_40x_EVPR (0x3D6)
2197 #define SPR_L3PM (0x3D7)
2198 #define SPR_403_CDBCR (0x3D7)
2199 #define SPR_L3ITCR0 (0x3D8)
2200 #define SPR_TCR (0x3D8)
2201 #define SPR_40x_TSR (0x3D8)
2202 #define SPR_IBR (0x3DA)
2203 #define SPR_40x_TCR (0x3DA)
2204 #define SPR_ESASRR (0x3DB)
2205 #define SPR_40x_PIT (0x3DB)
2206 #define SPR_403_TBL (0x3DC)
2207 #define SPR_403_TBU (0x3DD)
2208 #define SPR_SEBR (0x3DE)
2209 #define SPR_40x_SRR2 (0x3DE)
2210 #define SPR_SER (0x3DF)
2211 #define SPR_40x_SRR3 (0x3DF)
2212 #define SPR_L3OHCR (0x3E8)
2213 #define SPR_L3ITCR1 (0x3E9)
2214 #define SPR_L3ITCR2 (0x3EA)
2215 #define SPR_L3ITCR3 (0x3EB)
2216 #define SPR_HID0 (0x3F0)
2217 #define SPR_40x_DBSR (0x3F0)
2218 #define SPR_HID1 (0x3F1)
2219 #define SPR_IABR (0x3F2)
2220 #define SPR_40x_DBCR0 (0x3F2)
2221 #define SPR_Exxx_L1CSR0 (0x3F2)
2222 #define SPR_ICTRL (0x3F3)
2223 #define SPR_HID2 (0x3F3)
2224 #define SPR_750CL_HID4 (0x3F3)
2225 #define SPR_Exxx_L1CSR1 (0x3F3)
2226 #define SPR_440_DBDR (0x3F3)
2227 #define SPR_LDSTDB (0x3F4)
2228 #define SPR_750_TDCL (0x3F4)
2229 #define SPR_40x_IAC1 (0x3F4)
2230 #define SPR_MMUCSR0 (0x3F4)
2231 #define SPR_970_HID4 (0x3F4)
2232 #define SPR_DABR (0x3F5)
2233 #define DABR_MASK (~(target_ulong)0x7)
2234 #define SPR_Exxx_BUCSR (0x3F5)
2235 #define SPR_40x_IAC2 (0x3F5)
2236 #define SPR_40x_DAC1 (0x3F6)
2237 #define SPR_MSSCR0 (0x3F6)
2238 #define SPR_970_HID5 (0x3F6)
2239 #define SPR_MSSSR0 (0x3F7)
2240 #define SPR_MSSCR1 (0x3F7)
2241 #define SPR_DABRX (0x3F7)
2242 #define SPR_40x_DAC2 (0x3F7)
2243 #define SPR_MMUCFG (0x3F7)
2244 #define SPR_LDSTCR (0x3F8)
2245 #define SPR_L2PMCR (0x3F8)
2246 #define SPR_750FX_HID2 (0x3F8)
2247 #define SPR_Exxx_L1FINV0 (0x3F8)
2248 #define SPR_L2CR (0x3F9)
2249 #define SPR_Exxx_L2CSR0 (0x3F9)
2250 #define SPR_L3CR (0x3FA)
2251 #define SPR_750_TDCH (0x3FA)
2252 #define SPR_IABR2 (0x3FA)
2253 #define SPR_40x_DCCR (0x3FA)
2254 #define SPR_ICTC (0x3FB)
2255 #define SPR_40x_ICCR (0x3FB)
2256 #define SPR_THRM1 (0x3FC)
2257 #define SPR_403_PBL1 (0x3FC)
2258 #define SPR_SP (0x3FD)
2259 #define SPR_THRM2 (0x3FD)
2260 #define SPR_403_PBU1 (0x3FD)
2261 #define SPR_604_HID13 (0x3FD)
2262 #define SPR_LT (0x3FE)
2263 #define SPR_THRM3 (0x3FE)
2264 #define SPR_RCPU_FPECR (0x3FE)
2265 #define SPR_403_PBL2 (0x3FE)
2266 #define SPR_PIR (0x3FF)
2267 #define SPR_403_PBU2 (0x3FF)
2268 #define SPR_604_HID15 (0x3FF)
2269 #define SPR_E500_SVR (0x3FF)
2270
2271 /* Disable MAS Interrupt Updates for Hypervisor */
2272 #define EPCR_DMIUH (1 << 22)
2273 /* Disable Guest TLB Management Instructions */
2274 #define EPCR_DGTMI (1 << 23)
2275 /* Guest Interrupt Computation Mode */
2276 #define EPCR_GICM (1 << 24)
2277 /* Interrupt Computation Mode */
2278 #define EPCR_ICM (1 << 25)
2279 /* Disable Embedded Hypervisor Debug */
2280 #define EPCR_DUVD (1 << 26)
2281 /* Instruction Storage Interrupt Directed to Guest State */
2282 #define EPCR_ISIGS (1 << 27)
2283 /* Data Storage Interrupt Directed to Guest State */
2284 #define EPCR_DSIGS (1 << 28)
2285 /* Instruction TLB Error Interrupt Directed to Guest State */
2286 #define EPCR_ITLBGS (1 << 29)
2287 /* Data TLB Error Interrupt Directed to Guest State */
2288 #define EPCR_DTLBGS (1 << 30)
2289 /* External Input Interrupt Directed to Guest State */
2290 #define EPCR_EXTGS (1 << 31)
2291
2292 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
2293 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
2294 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
2295 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
2296 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
2297
2298 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
2299 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
2300 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
2301 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
2302 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
2303
2304 /* E500 L2CSR0 */
2305 #define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */
2306 #define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */
2307 #define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */
2308
2309 /* HID0 bits */
2310 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2311 #define HID0_DOZE (1 << 23) /* pre-2.06 */
2312 #define HID0_NAP (1 << 22) /* pre-2.06 */
2313 #define HID0_HILE PPC_BIT(19) /* POWER8 */
2314 #define HID0_POWER9_HILE PPC_BIT(4)
2315 #define HID0_ENABLE_ATTN PPC_BIT(31) /* POWER8 */
2316 #define HID0_POWER9_ENABLE_ATTN PPC_BIT(3)
2317
2318 /*****************************************************************************/
2319 /* PowerPC Instructions types definitions */
2320 enum {
2321 PPC_NONE = 0x0000000000000000ULL,
2322 /* PowerPC base instructions set */
2323 PPC_INSNS_BASE = 0x0000000000000001ULL,
2324 /* integer operations instructions */
2325 #define PPC_INTEGER PPC_INSNS_BASE
2326 /* flow control instructions */
2327 #define PPC_FLOW PPC_INSNS_BASE
2328 /* virtual memory instructions */
2329 #define PPC_MEM PPC_INSNS_BASE
2330 /* ld/st with reservation instructions */
2331 #define PPC_RES PPC_INSNS_BASE
2332 /* spr/msr access instructions */
2333 #define PPC_MISC PPC_INSNS_BASE
2334 /* 64 bits PowerPC instruction set */
2335 PPC_64B = 0x0000000000000020ULL,
2336 /* New 64 bits extensions (PowerPC 2.0x) */
2337 PPC_64BX = 0x0000000000000040ULL,
2338 /* 64 bits hypervisor extensions */
2339 PPC_64H = 0x0000000000000080ULL,
2340 /* New wait instruction (PowerPC 2.0x) */
2341 PPC_WAIT = 0x0000000000000100ULL,
2342 /* Time base mftb instruction */
2343 PPC_MFTB = 0x0000000000000200ULL,
2344
2345 /* Fixed-point unit extensions */
2346 /* isel instruction */
2347 PPC_ISEL = 0x0000000000000800ULL,
2348 /* popcntb instruction */
2349 PPC_POPCNTB = 0x0000000000001000ULL,
2350 /* string load / store */
2351 PPC_STRING = 0x0000000000002000ULL,
2352 /* real mode cache inhibited load / store */
2353 PPC_CILDST = 0x0000000000004000ULL,
2354
2355 /* Floating-point unit extensions */
2356 /* Optional floating point instructions */
2357 PPC_FLOAT = 0x0000000000010000ULL,
2358 /* New floating-point extensions (PowerPC 2.0x) */
2359 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2360 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2361 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2362 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2363 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2364 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2365 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2366
2367 /* Vector/SIMD extensions */
2368 /* Altivec support */
2369 PPC_ALTIVEC = 0x0000000001000000ULL,
2370 /* PowerPC 2.03 SPE extension */
2371 PPC_SPE = 0x0000000002000000ULL,
2372 /* PowerPC 2.03 SPE single-precision floating-point extension */
2373 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2374 /* PowerPC 2.03 SPE double-precision floating-point extension */
2375 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2376
2377 /* Optional memory control instructions */
2378 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2379 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2380 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2381 /* sync instruction */
2382 PPC_MEM_SYNC = 0x0000000080000000ULL,
2383 /* eieio instruction */
2384 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2385
2386 /* Cache control instructions */
2387 PPC_CACHE = 0x0000000200000000ULL,
2388 /* icbi instruction */
2389 PPC_CACHE_ICBI = 0x0000000400000000ULL,
2390 /* dcbz instruction */
2391 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2392 /* dcba instruction */
2393 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2394 /* Freescale cache locking instructions */
2395 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2396
2397 /* MMU related extensions */
2398 /* external control instructions */
2399 PPC_EXTERN = 0x0000010000000000ULL,
2400 /* segment register access instructions */
2401 PPC_SEGMENT = 0x0000020000000000ULL,
2402 /* PowerPC 6xx TLB management instructions */
2403 PPC_6xx_TLB = 0x0000040000000000ULL,
2404 /* PowerPC 40x TLB management instructions */
2405 PPC_40x_TLB = 0x0000100000000000ULL,
2406 /* segment register access instructions for PowerPC 64 "bridge" */
2407 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2408 /* SLB management */
2409 PPC_SLBI = 0x0000400000000000ULL,
2410
2411 /* Embedded PowerPC dedicated instructions */
2412 PPC_WRTEE = 0x0001000000000000ULL,
2413 /* PowerPC 40x exception model */
2414 PPC_40x_EXCP = 0x0002000000000000ULL,
2415 /* PowerPC 405 Mac instructions */
2416 PPC_405_MAC = 0x0004000000000000ULL,
2417 /* PowerPC 440 specific instructions */
2418 PPC_440_SPEC = 0x0008000000000000ULL,
2419 /* BookE (embedded) PowerPC specification */
2420 PPC_BOOKE = 0x0010000000000000ULL,
2421 /* mfapidi instruction */
2422 PPC_MFAPIDI = 0x0020000000000000ULL,
2423 /* tlbiva instruction */
2424 PPC_TLBIVA = 0x0040000000000000ULL,
2425 /* tlbivax instruction */
2426 PPC_TLBIVAX = 0x0080000000000000ULL,
2427 /* PowerPC 4xx dedicated instructions */
2428 PPC_4xx_COMMON = 0x0100000000000000ULL,
2429 /* PowerPC 40x ibct instructions */
2430 PPC_40x_ICBT = 0x0200000000000000ULL,
2431 /* rfmci is not implemented in all BookE PowerPC */
2432 PPC_RFMCI = 0x0400000000000000ULL,
2433 /* rfdi instruction */
2434 PPC_RFDI = 0x0800000000000000ULL,
2435 /* DCR accesses */
2436 PPC_DCR = 0x1000000000000000ULL,
2437 /* DCR extended accesse */
2438 PPC_DCRX = 0x2000000000000000ULL,
2439 /* popcntw and popcntd instructions */
2440 PPC_POPCNTWD = 0x8000000000000000ULL,
2441
2442 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_64B \
2443 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2444 | PPC_ISEL | PPC_POPCNTB \
2445 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2446 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2447 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2448 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2449 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2450 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2451 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2452 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2453 | PPC_CACHE | PPC_CACHE_ICBI \
2454 | PPC_CACHE_DCBZ \
2455 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2456 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2457 | PPC_40x_TLB | PPC_SEGMENT_64B \
2458 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2459 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2460 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2461 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2462 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_POPCNTWD \
2463 | PPC_CILDST)
2464
2465 /* extended type values */
2466
2467 /* BookE 2.06 PowerPC specification */
2468 PPC2_BOOKE206 = 0x0000000000000001ULL,
2469 /* VSX (extensions to Altivec / VMX) */
2470 PPC2_VSX = 0x0000000000000002ULL,
2471 /* Decimal Floating Point (DFP) */
2472 PPC2_DFP = 0x0000000000000004ULL,
2473 /* Embedded.Processor Control */
2474 PPC2_PRCNTL = 0x0000000000000008ULL,
2475 /* Byte-reversed, indexed, double-word load and store */
2476 PPC2_DBRX = 0x0000000000000010ULL,
2477 /* Book I 2.05 PowerPC specification */
2478 PPC2_ISA205 = 0x0000000000000020ULL,
2479 /* VSX additions in ISA 2.07 */
2480 PPC2_VSX207 = 0x0000000000000040ULL,
2481 /* ISA 2.06B bpermd */
2482 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2483 /* ISA 2.06B divide extended variants */
2484 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2485 /* ISA 2.06B larx/stcx. instructions */
2486 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2487 /* ISA 2.06B floating point integer conversion */
2488 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2489 /* ISA 2.06B floating point test instructions */
2490 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2491 /* ISA 2.07 bctar instruction */
2492 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2493 /* ISA 2.07 load/store quadword */
2494 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2495 /* ISA 2.07 Altivec */
2496 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2497 /* PowerISA 2.07 Book3s specification */
2498 PPC2_ISA207S = 0x0000000000008000ULL,
2499 /* Double precision floating point conversion for signed integer 64 */
2500 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2501 /* Transactional Memory (ISA 2.07, Book II) */
2502 PPC2_TM = 0x0000000000020000ULL,
2503 /* Server PM instructgions (ISA 2.06, Book III) */
2504 PPC2_PM_ISA206 = 0x0000000000040000ULL,
2505 /* POWER ISA 3.0 */
2506 PPC2_ISA300 = 0x0000000000080000ULL,
2507 /* POWER ISA 3.1 */
2508 PPC2_ISA310 = 0x0000000000100000ULL,
2509 /* lwsync instruction */
2510 PPC2_MEM_LWSYNC = 0x0000000000200000ULL,
2511 /* ISA 2.06 BCD assist instructions */
2512 PPC2_BCDA_ISA206 = 0x0000000000400000ULL,
2513
2514 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2515 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2516 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2517 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2518 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2519 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2520 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2521 PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
2522 PPC2_BCDA_ISA206)
2523 };
2524
2525 /*****************************************************************************/
2526 /*
2527 * Memory access type :
2528 * may be needed for precise access rights control and precise exceptions.
2529 */
2530 enum {
2531 /* Type of instruction that generated the access */
2532 ACCESS_CODE = 0x10, /* Code fetch access */
2533 ACCESS_INT = 0x20, /* Integer load/store access */
2534 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2535 ACCESS_RES = 0x40, /* load/store with reservation */
2536 ACCESS_EXT = 0x50, /* external access */
2537 ACCESS_CACHE = 0x60, /* Cache manipulation */
2538 };
2539
2540 /*
2541 * Hardware interrupt sources:
2542 * all those exception can be raised simulteaneously
2543 */
2544 /* Input pins definitions */
2545 enum {
2546 /* 6xx bus input pins */
2547 PPC6xx_INPUT_HRESET = 0,
2548 PPC6xx_INPUT_SRESET = 1,
2549 PPC6xx_INPUT_CKSTP_IN = 2,
2550 PPC6xx_INPUT_MCP = 3,
2551 PPC6xx_INPUT_SMI = 4,
2552 PPC6xx_INPUT_INT = 5,
2553 PPC6xx_INPUT_TBEN = 6,
2554 PPC6xx_INPUT_WAKEUP = 7,
2555 PPC6xx_INPUT_NB,
2556 };
2557
2558 enum {
2559 /* Embedded PowerPC input pins */
2560 PPCBookE_INPUT_HRESET = 0,
2561 PPCBookE_INPUT_SRESET = 1,
2562 PPCBookE_INPUT_CKSTP_IN = 2,
2563 PPCBookE_INPUT_MCP = 3,
2564 PPCBookE_INPUT_SMI = 4,
2565 PPCBookE_INPUT_INT = 5,
2566 PPCBookE_INPUT_CINT = 6,
2567 PPCBookE_INPUT_NB,
2568 };
2569
2570 enum {
2571 /* PowerPC E500 input pins */
2572 PPCE500_INPUT_RESET_CORE = 0,
2573 PPCE500_INPUT_MCK = 1,
2574 PPCE500_INPUT_CINT = 3,
2575 PPCE500_INPUT_INT = 4,
2576 PPCE500_INPUT_DEBUG = 6,
2577 PPCE500_INPUT_NB,
2578 };
2579
2580 enum {
2581 /* PowerPC 40x input pins */
2582 PPC40x_INPUT_RESET_CORE = 0,
2583 PPC40x_INPUT_RESET_CHIP = 1,
2584 PPC40x_INPUT_RESET_SYS = 2,
2585 PPC40x_INPUT_CINT = 3,
2586 PPC40x_INPUT_INT = 4,
2587 PPC40x_INPUT_HALT = 5,
2588 PPC40x_INPUT_DEBUG = 6,
2589 PPC40x_INPUT_NB,
2590 };
2591
2592 enum {
2593 /* RCPU input pins */
2594 PPCRCPU_INPUT_PORESET = 0,
2595 PPCRCPU_INPUT_HRESET = 1,
2596 PPCRCPU_INPUT_SRESET = 2,
2597 PPCRCPU_INPUT_IRQ0 = 3,
2598 PPCRCPU_INPUT_IRQ1 = 4,
2599 PPCRCPU_INPUT_IRQ2 = 5,
2600 PPCRCPU_INPUT_IRQ3 = 6,
2601 PPCRCPU_INPUT_IRQ4 = 7,
2602 PPCRCPU_INPUT_IRQ5 = 8,
2603 PPCRCPU_INPUT_IRQ6 = 9,
2604 PPCRCPU_INPUT_IRQ7 = 10,
2605 PPCRCPU_INPUT_NB,
2606 };
2607
2608 #if defined(TARGET_PPC64)
2609 enum {
2610 /* PowerPC 970 input pins */
2611 PPC970_INPUT_HRESET = 0,
2612 PPC970_INPUT_SRESET = 1,
2613 PPC970_INPUT_CKSTP = 2,
2614 PPC970_INPUT_TBEN = 3,
2615 PPC970_INPUT_MCP = 4,
2616 PPC970_INPUT_INT = 5,
2617 PPC970_INPUT_THINT = 6,
2618 PPC970_INPUT_NB,
2619 };
2620
2621 enum {
2622 /* POWER7 input pins */
2623 POWER7_INPUT_INT = 0,
2624 /*
2625 * POWER7 probably has other inputs, but we don't care about them
2626 * for any existing machine. We can wire these up when we need
2627 * them
2628 */
2629 POWER7_INPUT_NB,
2630 };
2631
2632 enum {
2633 /* POWER9 input pins */
2634 POWER9_INPUT_INT = 0,
2635 POWER9_INPUT_HINT = 1,
2636 POWER9_INPUT_NB,
2637 };
2638 #endif
2639
2640 /* Hardware exceptions definitions */
2641 enum {
2642 /* External hardware exception sources */
2643 PPC_INTERRUPT_RESET = 0x00001, /* Reset exception */
2644 PPC_INTERRUPT_WAKEUP = 0x00002, /* Wakeup exception */
2645 PPC_INTERRUPT_MCK = 0x00004, /* Machine check exception */
2646 PPC_INTERRUPT_EXT = 0x00008, /* External interrupt */
2647 PPC_INTERRUPT_SMI = 0x00010, /* System management interrupt */
2648 PPC_INTERRUPT_CEXT = 0x00020, /* Critical external interrupt */
2649 PPC_INTERRUPT_DEBUG = 0x00040, /* External debug exception */
2650 PPC_INTERRUPT_THERM = 0x00080, /* Thermal exception */
2651 /* Internal hardware exception sources */
2652 PPC_INTERRUPT_DECR = 0x00100, /* Decrementer exception */
2653 PPC_INTERRUPT_HDECR = 0x00200, /* Hypervisor decrementer exception */
2654 PPC_INTERRUPT_PIT = 0x00400, /* Programmable interval timer int. */
2655 PPC_INTERRUPT_FIT = 0x00800, /* Fixed interval timer interrupt */
2656 PPC_INTERRUPT_WDT = 0x01000, /* Watchdog timer interrupt */
2657 PPC_INTERRUPT_CDOORBELL = 0x02000, /* Critical doorbell interrupt */
2658 PPC_INTERRUPT_DOORBELL = 0x04000, /* Doorbell interrupt */
2659 PPC_INTERRUPT_PERFM = 0x08000, /* Performance monitor interrupt */
2660 PPC_INTERRUPT_HMI = 0x10000, /* Hypervisor Maintenance interrupt */
2661 PPC_INTERRUPT_HDOORBELL = 0x20000, /* Hypervisor Doorbell interrupt */
2662 PPC_INTERRUPT_HVIRT = 0x40000, /* Hypervisor virtualization interrupt */
2663 PPC_INTERRUPT_EBB = 0x80000, /* Event-based Branch exception */
2664 };
2665
2666 /* Processor Compatibility mask (PCR) */
2667 enum {
2668 PCR_COMPAT_2_05 = PPC_BIT(62),
2669 PCR_COMPAT_2_06 = PPC_BIT(61),
2670 PCR_COMPAT_2_07 = PPC_BIT(60),
2671 PCR_COMPAT_3_00 = PPC_BIT(59),
2672 PCR_COMPAT_3_10 = PPC_BIT(58),
2673 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2674 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2675 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2676 };
2677
2678 /* HMER/HMEER */
2679 enum {
2680 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2681 HMER_PROC_RECV_DONE = PPC_BIT(2),
2682 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2683 HMER_TFAC_ERROR = PPC_BIT(4),
2684 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2685 HMER_XSCOM_FAIL = PPC_BIT(8),
2686 HMER_XSCOM_DONE = PPC_BIT(9),
2687 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2688 HMER_WARN_RISE = PPC_BIT(14),
2689 HMER_WARN_FALL = PPC_BIT(15),
2690 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2691 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2692 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2693 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2694 };
2695
2696 /* TFMR */
2697 enum {
2698 TFMR_CONTROL_MASK = PPC_BITMASK(0, 24),
2699 TFMR_MASK_HMI = PPC_BIT(10),
2700 TFMR_TB_ECLIPZ = PPC_BIT(14),
2701 TFMR_LOAD_TOD_MOD = PPC_BIT(16),
2702 TFMR_MOVE_CHIP_TOD_TO_TB = PPC_BIT(18),
2703 TFMR_CLEAR_TB_ERRORS = PPC_BIT(24),
2704 TFMR_STATUS_MASK = PPC_BITMASK(25, 63),
2705 TFMR_TBST_ENCODED = PPC_BITMASK(28, 31), /* TBST = TB State */
2706 TFMR_TBST_LAST = PPC_BITMASK(32, 35), /* Previous TBST */
2707 TFMR_TB_ENABLED = PPC_BIT(40),
2708 TFMR_TB_VALID = PPC_BIT(41),
2709 TFMR_TB_SYNC_OCCURED = PPC_BIT(42),
2710 TFMR_FIRMWARE_CONTROL_ERROR = PPC_BIT(46),
2711 };
2712
2713 /* TFMR TBST (Time Base State Machine). */
2714 enum {
2715 TBST_RESET = 0x0,
2716 TBST_SEND_TOD_MOD = 0x1,
2717 TBST_NOT_SET = 0x2,
2718 TBST_SYNC_WAIT = 0x6,
2719 TBST_GET_TOD = 0x7,
2720 TBST_TB_RUNNING = 0x8,
2721 TBST_TB_ERROR = 0x9,
2722 };
2723
2724 /*****************************************************************************/
2725
2726 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2727 target_ulong cpu_read_xer(const CPUPPCState *env);
2728 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2729
2730 /*
2731 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2732 * have PPC_SEGMENT_64B.
2733 */
2734 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2735
2736 #ifdef CONFIG_DEBUG_TCG
2737 void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2738 uint64_t *cs_base, uint32_t *flags);
2739 #else
cpu_get_tb_cpu_state(CPUPPCState * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)2740 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
2741 uint64_t *cs_base, uint32_t *flags)
2742 {
2743 *pc = env->nip;
2744 *cs_base = 0;
2745 *flags = env->hflags;
2746 }
2747 #endif
2748
2749 G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
2750 G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
2751 uintptr_t raddr);
2752 G_NORETURN void raise_exception_err(CPUPPCState *env, uint32_t exception,
2753 uint32_t error_code);
2754 G_NORETURN void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2755 uint32_t error_code, uintptr_t raddr);
2756
2757 /* PERFM EBB helper*/
2758 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2759 void raise_ebb_perfm_exception(CPUPPCState *env);
2760 #endif
2761
2762 #if !defined(CONFIG_USER_ONLY)
booke206_tlbm_id(CPUPPCState * env,ppcmas_tlb_t * tlbm)2763 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2764 {
2765 uintptr_t tlbml = (uintptr_t)tlbm;
2766 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2767
2768 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2769 }
2770
booke206_tlb_size(CPUPPCState * env,int tlbn)2771 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2772 {
2773 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2774 int r = tlbncfg & TLBnCFG_N_ENTRY;
2775 return r;
2776 }
2777
booke206_tlb_ways(CPUPPCState * env,int tlbn)2778 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2779 {
2780 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2781 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2782 return r;
2783 }
2784
booke206_tlbm_to_tlbn(CPUPPCState * env,ppcmas_tlb_t * tlbm)2785 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2786 {
2787 int id = booke206_tlbm_id(env, tlbm);
2788 int end = 0;
2789 int i;
2790
2791 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2792 end += booke206_tlb_size(env, i);
2793 if (id < end) {
2794 return i;
2795 }
2796 }
2797
2798 cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2799 return 0;
2800 }
2801
booke206_tlbm_to_way(CPUPPCState * env,ppcmas_tlb_t * tlb)2802 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2803 {
2804 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2805 int tlbid = booke206_tlbm_id(env, tlb);
2806 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2807 }
2808
booke206_get_tlbm(CPUPPCState * env,const int tlbn,target_ulong ea,int way)2809 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2810 target_ulong ea, int way)
2811 {
2812 int r;
2813 uint32_t ways = booke206_tlb_ways(env, tlbn);
2814 int ways_bits = ctz32(ways);
2815 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2816 int i;
2817
2818 way &= ways - 1;
2819 ea >>= MAS2_EPN_SHIFT;
2820 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2821 r = (ea << ways_bits) | way;
2822
2823 if (r >= booke206_tlb_size(env, tlbn)) {
2824 return NULL;
2825 }
2826
2827 /* bump up to tlbn index */
2828 for (i = 0; i < tlbn; i++) {
2829 r += booke206_tlb_size(env, i);
2830 }
2831
2832 return &env->tlb.tlbm[r];
2833 }
2834
2835 /* returns bitmap of supported page sizes for a given TLB */
booke206_tlbnps(CPUPPCState * env,const int tlbn)2836 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2837 {
2838 uint32_t ret = 0;
2839
2840 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2841 /* MAV2 */
2842 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2843 } else {
2844 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2845 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2846 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2847 int i;
2848 for (i = min; i <= max; i++) {
2849 ret |= (1 << (i << 1));
2850 }
2851 }
2852
2853 return ret;
2854 }
2855
booke206_fixed_size_tlbn(CPUPPCState * env,const int tlbn,ppcmas_tlb_t * tlb)2856 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2857 ppcmas_tlb_t *tlb)
2858 {
2859 uint8_t i;
2860 int32_t tsize = -1;
2861
2862 for (i = 0; i < 32; i++) {
2863 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2864 if (tsize == -1) {
2865 tsize = i;
2866 } else {
2867 return;
2868 }
2869 }
2870 }
2871
2872 /* TLBnPS unimplemented? Odd.. */
2873 assert(tsize != -1);
2874 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2875 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2876 }
2877
ppc_is_split_tlb(PowerPCCPU * cpu)2878 static inline bool ppc_is_split_tlb(PowerPCCPU *cpu)
2879 {
2880 return cpu->env.tlb_type == TLB_6XX;
2881 }
2882 #endif
2883
msr_is_64bit(CPUPPCState * env,target_ulong msr)2884 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2885 {
2886 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2887 return msr & (1ULL << MSR_CM);
2888 }
2889
2890 return msr & (1ULL << MSR_SF);
2891 }
2892
2893 /**
2894 * Check whether register rx is in the range between start and
2895 * start + nregs (as needed by the LSWX and LSWI instructions)
2896 */
lsw_reg_in_range(int start,int nregs,int rx)2897 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2898 {
2899 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2900 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2901 }
2902
2903 /* Accessors for FP, VMX and VSX registers */
2904 #if HOST_BIG_ENDIAN
2905 #define VsrB(i) u8[i]
2906 #define VsrSB(i) s8[i]
2907 #define VsrH(i) u16[i]
2908 #define VsrSH(i) s16[i]
2909 #define VsrW(i) u32[i]
2910 #define VsrSW(i) s32[i]
2911 #define VsrD(i) u64[i]
2912 #define VsrSD(i) s64[i]
2913 #define VsrHF(i) f16[i]
2914 #define VsrSF(i) f32[i]
2915 #define VsrDF(i) f64[i]
2916 #else
2917 #define VsrB(i) u8[15 - (i)]
2918 #define VsrSB(i) s8[15 - (i)]
2919 #define VsrH(i) u16[7 - (i)]
2920 #define VsrSH(i) s16[7 - (i)]
2921 #define VsrW(i) u32[3 - (i)]
2922 #define VsrSW(i) s32[3 - (i)]
2923 #define VsrD(i) u64[1 - (i)]
2924 #define VsrSD(i) s64[1 - (i)]
2925 #define VsrHF(i) f16[7 - (i)]
2926 #define VsrSF(i) f32[3 - (i)]
2927 #define VsrDF(i) f64[1 - (i)]
2928 #endif
2929
vsr64_offset(int i,bool high)2930 static inline int vsr64_offset(int i, bool high)
2931 {
2932 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2933 }
2934
vsr_full_offset(int i)2935 static inline int vsr_full_offset(int i)
2936 {
2937 return offsetof(CPUPPCState, vsr[i].u64[0]);
2938 }
2939
acc_full_offset(int i)2940 static inline int acc_full_offset(int i)
2941 {
2942 return vsr_full_offset(i * 4);
2943 }
2944
fpr_offset(int i)2945 static inline int fpr_offset(int i)
2946 {
2947 return vsr64_offset(i, true);
2948 }
2949
cpu_fpr_ptr(CPUPPCState * env,int i)2950 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2951 {
2952 return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2953 }
2954
cpu_vsrl_ptr(CPUPPCState * env,int i)2955 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2956 {
2957 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2958 }
2959
avr64_offset(int i,bool high)2960 static inline long avr64_offset(int i, bool high)
2961 {
2962 return vsr64_offset(i + 32, high);
2963 }
2964
avr_full_offset(int i)2965 static inline int avr_full_offset(int i)
2966 {
2967 return vsr_full_offset(i + 32);
2968 }
2969
cpu_avr_ptr(CPUPPCState * env,int i)2970 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2971 {
2972 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2973 }
2974
ppc_has_spr(PowerPCCPU * cpu,int spr)2975 static inline bool ppc_has_spr(PowerPCCPU *cpu, int spr)
2976 {
2977 /* We can test whether the SPR is defined by checking for a valid name */
2978 return cpu->env.spr_cb[spr].name != NULL;
2979 }
2980
2981 #if !defined(CONFIG_USER_ONLY)
2982 /* Sort out endianness of interrupt. Depends on the CPU, HV mode, etc. */
ppc_interrupts_little_endian(PowerPCCPU * cpu,bool hv)2983 static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
2984 {
2985 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2986 CPUPPCState *env = &cpu->env;
2987 bool ile;
2988
2989 if (hv && env->has_hv_mode) {
2990 if (is_isa300(pcc)) {
2991 ile = !!(env->spr[SPR_HID0] & HID0_POWER9_HILE);
2992 } else {
2993 ile = !!(env->spr[SPR_HID0] & HID0_HILE);
2994 }
2995
2996 } else if (pcc->lpcr_mask & LPCR_ILE) {
2997 ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
2998 } else {
2999 ile = FIELD_EX64(env->msr, MSR, ILE);
3000 }
3001
3002 return ile;
3003 }
3004 #endif
3005
3006 void dump_mmu(CPUPPCState *env);
3007
3008 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
3009 void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
3010 uint32_t ppc_get_vscr(CPUPPCState *env);
3011 void ppc_set_cr(CPUPPCState *env, uint64_t cr);
3012 uint64_t ppc_get_cr(const CPUPPCState *env);
3013
3014 /*****************************************************************************/
3015 /* Power management enable checks */
check_pow_none(CPUPPCState * env)3016 static inline int check_pow_none(CPUPPCState *env)
3017 {
3018 return 0;
3019 }
3020
check_pow_nocheck(CPUPPCState * env)3021 static inline int check_pow_nocheck(CPUPPCState *env)
3022 {
3023 return 1;
3024 }
3025
3026 /* attn enable check */
check_attn_none(CPUPPCState * env)3027 static inline int check_attn_none(CPUPPCState *env)
3028 {
3029 return 0;
3030 }
3031
3032 /*****************************************************************************/
3033 /* PowerPC implementations definitions */
3034
3035 #define POWERPC_FAMILY(_name) \
3036 static void \
3037 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3038 \
3039 static const TypeInfo \
3040 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3041 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3042 .parent = TYPE_POWERPC_CPU, \
3043 .abstract = true, \
3044 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3045 }; \
3046 \
3047 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3048 { \
3049 type_register_static( \
3050 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3051 } \
3052 \
3053 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3054 \
3055 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3056
3057
3058 #endif /* PPC_CPU_H */
3059