1fcf5ef2aSThomas Huth /*
2fcf5ef2aSThomas Huth * PowerPC floating point and SPE emulation helpers for QEMU.
3fcf5ef2aSThomas Huth *
4fcf5ef2aSThomas Huth * Copyright (c) 2003-2007 Jocelyn Mayer
5fcf5ef2aSThomas Huth *
6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or
7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public
8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either
96bd039cdSChetan Pant * version 2.1 of the License, or (at your option) any later version.
10fcf5ef2aSThomas Huth *
11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful,
12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of
13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14fcf5ef2aSThomas Huth * Lesser General Public License for more details.
15fcf5ef2aSThomas Huth *
16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public
17fcf5ef2aSThomas Huth * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18fcf5ef2aSThomas Huth */
19fcf5ef2aSThomas Huth #include "qemu/osdep.h"
20fcf5ef2aSThomas Huth #include "cpu.h"
21fcf5ef2aSThomas Huth #include "exec/helper-proto.h"
22fcf5ef2aSThomas Huth #include "exec/exec-all.h"
23985e3023SBharata B Rao #include "internal.h"
2424f91e81SAlex Bennée #include "fpu/softfloat.h"
25fcf5ef2aSThomas Huth
float128_snan_to_qnan(float128 x)26e5487803SBharata B Rao static inline float128 float128_snan_to_qnan(float128 x)
27e5487803SBharata B Rao {
28e5487803SBharata B Rao float128 r;
29e5487803SBharata B Rao
30e5487803SBharata B Rao r.high = x.high | 0x0000800000000000;
31e5487803SBharata B Rao r.low = x.low;
32e5487803SBharata B Rao return r;
33e5487803SBharata B Rao }
34e5487803SBharata B Rao
35fcf5ef2aSThomas Huth #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
36fcf5ef2aSThomas Huth #define float32_snan_to_qnan(x) ((x) | 0x00400000)
37f566c047SBharata B Rao #define float16_snan_to_qnan(x) ((x) | 0x0200)
38fcf5ef2aSThomas Huth
bfp32_neg(float32 a)392d9cba74SLucas Mateus Castro (alqotel) static inline float32 bfp32_neg(float32 a)
402d9cba74SLucas Mateus Castro (alqotel) {
412d9cba74SLucas Mateus Castro (alqotel) if (unlikely(float32_is_any_nan(a))) {
422d9cba74SLucas Mateus Castro (alqotel) return a;
432d9cba74SLucas Mateus Castro (alqotel) } else {
442d9cba74SLucas Mateus Castro (alqotel) return float32_chs(a);
452d9cba74SLucas Mateus Castro (alqotel) }
462d9cba74SLucas Mateus Castro (alqotel) }
472d9cba74SLucas Mateus Castro (alqotel)
fp_exceptions_enabled(CPUPPCState * env)48e82c42b7SRichard Henderson static inline bool fp_exceptions_enabled(CPUPPCState *env)
49e82c42b7SRichard Henderson {
50e82c42b7SRichard Henderson #ifdef CONFIG_USER_ONLY
51e82c42b7SRichard Henderson return true;
52e82c42b7SRichard Henderson #else
53e82c42b7SRichard Henderson return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0;
54e82c42b7SRichard Henderson #endif
55e82c42b7SRichard Henderson }
56e82c42b7SRichard Henderson
57fcf5ef2aSThomas Huth /*****************************************************************************/
58fcf5ef2aSThomas Huth /* Floating point operations helpers */
59fcf5ef2aSThomas Huth
6086c0cab1SRichard Henderson /*
6186c0cab1SRichard Henderson * This is the non-arithmatic conversion that happens e.g. on loads.
6286c0cab1SRichard Henderson * In the Power ISA pseudocode, this is called DOUBLE.
6386c0cab1SRichard Henderson */
helper_todouble(uint32_t arg)6486c0cab1SRichard Henderson uint64_t helper_todouble(uint32_t arg)
6586c0cab1SRichard Henderson {
6686c0cab1SRichard Henderson uint32_t abs_arg = arg & 0x7fffffff;
6786c0cab1SRichard Henderson uint64_t ret;
6886c0cab1SRichard Henderson
6986c0cab1SRichard Henderson if (likely(abs_arg >= 0x00800000)) {
70a7b7b983SPaul A. Clarke if (unlikely(extract32(arg, 23, 8) == 0xff)) {
71a7b7b983SPaul A. Clarke /* Inf or NAN. */
72a7b7b983SPaul A. Clarke ret = (uint64_t)extract32(arg, 31, 1) << 63;
73a7b7b983SPaul A. Clarke ret |= (uint64_t)0x7ff << 52;
74a7b7b983SPaul A. Clarke ret |= (uint64_t)extract32(arg, 0, 23) << 29;
75a7b7b983SPaul A. Clarke } else {
76a7b7b983SPaul A. Clarke /* Normalized operand. */
7786c0cab1SRichard Henderson ret = (uint64_t)extract32(arg, 30, 2) << 62;
7886c0cab1SRichard Henderson ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59;
7986c0cab1SRichard Henderson ret |= (uint64_t)extract32(arg, 0, 30) << 29;
80a7b7b983SPaul A. Clarke }
8186c0cab1SRichard Henderson } else {
8286c0cab1SRichard Henderson /* Zero or Denormalized operand. */
8386c0cab1SRichard Henderson ret = (uint64_t)extract32(arg, 31, 1) << 63;
8486c0cab1SRichard Henderson if (unlikely(abs_arg != 0)) {
85c0e6616bSPaul A. Clarke /*
86c0e6616bSPaul A. Clarke * Denormalized operand.
87c0e6616bSPaul A. Clarke * Shift fraction so that the msb is in the implicit bit position.
88c0e6616bSPaul A. Clarke * Thus, shift is in the range [1:23].
89c0e6616bSPaul A. Clarke */
90c0e6616bSPaul A. Clarke int shift = clz32(abs_arg) - 8;
91c0e6616bSPaul A. Clarke /*
92c0e6616bSPaul A. Clarke * The first 3 terms compute the float64 exponent. We then bias
93c0e6616bSPaul A. Clarke * this result by -1 so that we can swallow the implicit bit below.
94c0e6616bSPaul A. Clarke */
95c0e6616bSPaul A. Clarke int exp = -126 - shift + 1023 - 1;
96c0e6616bSPaul A. Clarke
9786c0cab1SRichard Henderson ret |= (uint64_t)exp << 52;
98c0e6616bSPaul A. Clarke ret += (uint64_t)abs_arg << (52 - 23 + shift);
9986c0cab1SRichard Henderson }
10086c0cab1SRichard Henderson }
10186c0cab1SRichard Henderson return ret;
102fcf5ef2aSThomas Huth }
103fcf5ef2aSThomas Huth
10486c0cab1SRichard Henderson /*
10586c0cab1SRichard Henderson * This is the non-arithmatic conversion that happens e.g. on stores.
10686c0cab1SRichard Henderson * In the Power ISA pseudocode, this is called SINGLE.
10786c0cab1SRichard Henderson */
helper_tosingle(uint64_t arg)10886c0cab1SRichard Henderson uint32_t helper_tosingle(uint64_t arg)
109fcf5ef2aSThomas Huth {
11086c0cab1SRichard Henderson int exp = extract64(arg, 52, 11);
11186c0cab1SRichard Henderson uint32_t ret;
112fcf5ef2aSThomas Huth
11386c0cab1SRichard Henderson if (likely(exp > 896)) {
11486c0cab1SRichard Henderson /* No denormalization required (includes Inf, NaN). */
11586c0cab1SRichard Henderson ret = extract64(arg, 62, 2) << 30;
11686c0cab1SRichard Henderson ret |= extract64(arg, 29, 30);
11786c0cab1SRichard Henderson } else {
118fa9ebf8cSDavid Gibson /*
119fa9ebf8cSDavid Gibson * Zero or Denormal result. If the exponent is in bounds for
120fa9ebf8cSDavid Gibson * a single-precision denormal result, extract the proper
121fa9ebf8cSDavid Gibson * bits. If the input is not zero, and the exponent is out of
122fa9ebf8cSDavid Gibson * bounds, then the result is undefined; this underflows to
123fa9ebf8cSDavid Gibson * zero.
12486c0cab1SRichard Henderson */
12586c0cab1SRichard Henderson ret = extract64(arg, 63, 1) << 31;
12686c0cab1SRichard Henderson if (unlikely(exp >= 874)) {
12786c0cab1SRichard Henderson /* Denormal result. */
12886c0cab1SRichard Henderson ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp);
12986c0cab1SRichard Henderson }
13086c0cab1SRichard Henderson }
13186c0cab1SRichard Henderson return ret;
132fcf5ef2aSThomas Huth }
133fcf5ef2aSThomas Huth
ppc_float32_get_unbiased_exp(float32 f)134fcf5ef2aSThomas Huth static inline int ppc_float32_get_unbiased_exp(float32 f)
135fcf5ef2aSThomas Huth {
136fcf5ef2aSThomas Huth return ((f >> 23) & 0xFF) - 127;
137fcf5ef2aSThomas Huth }
138fcf5ef2aSThomas Huth
ppc_float64_get_unbiased_exp(float64 f)139fcf5ef2aSThomas Huth static inline int ppc_float64_get_unbiased_exp(float64 f)
140fcf5ef2aSThomas Huth {
141fcf5ef2aSThomas Huth return ((f >> 52) & 0x7FF) - 1023;
142fcf5ef2aSThomas Huth }
143fcf5ef2aSThomas Huth
144ffc67420SBharata B Rao #define COMPUTE_FPRF(tp) \
145ffc67420SBharata B Rao void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
146ffc67420SBharata B Rao { \
14703ec9d9dSRichard Henderson bool neg = tp##_is_neg(arg); \
14803ec9d9dSRichard Henderson target_ulong fprf; \
14903ec9d9dSRichard Henderson if (likely(tp##_is_normal(arg))) { \
15003ec9d9dSRichard Henderson fprf = neg ? 0x08 << FPSCR_FPRF : 0x04 << FPSCR_FPRF; \
15103ec9d9dSRichard Henderson } else if (tp##_is_zero(arg)) { \
15203ec9d9dSRichard Henderson fprf = neg ? 0x12 << FPSCR_FPRF : 0x02 << FPSCR_FPRF; \
15303ec9d9dSRichard Henderson } else if (tp##_is_zero_or_denormal(arg)) { \
15403ec9d9dSRichard Henderson fprf = neg ? 0x18 << FPSCR_FPRF : 0x14 << FPSCR_FPRF; \
15503ec9d9dSRichard Henderson } else if (tp##_is_infinity(arg)) { \
15603ec9d9dSRichard Henderson fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
15703ec9d9dSRichard Henderson } else { \
15803ec9d9dSRichard Henderson float_status dummy = { }; /* snan_bit_is_one = 0 */ \
15903ec9d9dSRichard Henderson if (tp##_is_signaling_nan(arg, &dummy)) { \
16003ec9d9dSRichard Henderson fprf = 0x00 << FPSCR_FPRF; \
16103ec9d9dSRichard Henderson } else { \
16203ec9d9dSRichard Henderson fprf = 0x11 << FPSCR_FPRF; \
16303ec9d9dSRichard Henderson } \
16403ec9d9dSRichard Henderson } \
16503ec9d9dSRichard Henderson env->fpscr = (env->fpscr & ~FP_FPRF) | fprf; \
166ffc67420SBharata B Rao }
167fcf5ef2aSThomas Huth
168f566c047SBharata B Rao COMPUTE_FPRF(float16)
COMPUTE_FPRF(float32)1699aeae8e1SBharata B Rao COMPUTE_FPRF(float32)
170ffc67420SBharata B Rao COMPUTE_FPRF(float64)
17107bdd247SBharata B Rao COMPUTE_FPRF(float128)
172fcf5ef2aSThomas Huth
173fcf5ef2aSThomas Huth /* Floating-point invalid operations exception */
17413c9115fSRichard Henderson static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
175fcf5ef2aSThomas Huth {
17613c9115fSRichard Henderson /* Update the floating-point invalid operation summary */
1775c94dd38SPaul A. Clarke env->fpscr |= FP_VX;
17813c9115fSRichard Henderson /* Update the floating-point exception summary */
17913c9115fSRichard Henderson env->fpscr |= FP_FX;
180208d8033SVíctor Colombo if (env->fpscr & FP_VE) {
18113c9115fSRichard Henderson /* Update the floating-point enabled exception summary */
1825c94dd38SPaul A. Clarke env->fpscr |= FP_FEX;
18313c9115fSRichard Henderson if (fp_exceptions_enabled(env)) {
18413c9115fSRichard Henderson raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
18513c9115fSRichard Henderson POWERPC_EXCP_FP | op, retaddr);
18613c9115fSRichard Henderson }
18713c9115fSRichard Henderson }
18813c9115fSRichard Henderson }
189fcf5ef2aSThomas Huth
finish_invalid_op_arith(CPUPPCState * env,int op,bool set_fpcc,uintptr_t retaddr)19013c9115fSRichard Henderson static void finish_invalid_op_arith(CPUPPCState *env, int op,
19113c9115fSRichard Henderson bool set_fpcc, uintptr_t retaddr)
19213c9115fSRichard Henderson {
1935c94dd38SPaul A. Clarke env->fpscr &= ~(FP_FR | FP_FI);
194208d8033SVíctor Colombo if (!(env->fpscr & FP_VE)) {
19513c9115fSRichard Henderson if (set_fpcc) {
1965c94dd38SPaul A. Clarke env->fpscr &= ~FP_FPCC;
1975c94dd38SPaul A. Clarke env->fpscr |= (FP_C | FP_FU);
19813c9115fSRichard Henderson }
19913c9115fSRichard Henderson }
20013c9115fSRichard Henderson finish_invalid_op_excp(env, op, retaddr);
20113c9115fSRichard Henderson }
20213c9115fSRichard Henderson
20313c9115fSRichard Henderson /* Signalling NaN */
float_invalid_op_vxsnan(CPUPPCState * env,uintptr_t retaddr)20413c9115fSRichard Henderson static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr)
20513c9115fSRichard Henderson {
2065c94dd38SPaul A. Clarke env->fpscr |= FP_VXSNAN;
20713c9115fSRichard Henderson finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr);
20813c9115fSRichard Henderson }
20913c9115fSRichard Henderson
210fcf5ef2aSThomas Huth /* Magnitude subtraction of infinities */
float_invalid_op_vxisi(CPUPPCState * env,bool set_fpcc,uintptr_t retaddr)21113c9115fSRichard Henderson static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc,
21213c9115fSRichard Henderson uintptr_t retaddr)
21313c9115fSRichard Henderson {
2145c94dd38SPaul A. Clarke env->fpscr |= FP_VXISI;
21513c9115fSRichard Henderson finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr);
21613c9115fSRichard Henderson }
21713c9115fSRichard Henderson
218fcf5ef2aSThomas Huth /* Division of infinity by infinity */
float_invalid_op_vxidi(CPUPPCState * env,bool set_fpcc,uintptr_t retaddr)21913c9115fSRichard Henderson static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc,
22013c9115fSRichard Henderson uintptr_t retaddr)
22113c9115fSRichard Henderson {
2225c94dd38SPaul A. Clarke env->fpscr |= FP_VXIDI;
22313c9115fSRichard Henderson finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIDI, set_fpcc, retaddr);
22413c9115fSRichard Henderson }
22513c9115fSRichard Henderson
226fcf5ef2aSThomas Huth /* Division of zero by zero */
float_invalid_op_vxzdz(CPUPPCState * env,bool set_fpcc,uintptr_t retaddr)22713c9115fSRichard Henderson static void float_invalid_op_vxzdz(CPUPPCState *env, bool set_fpcc,
22813c9115fSRichard Henderson uintptr_t retaddr)
22913c9115fSRichard Henderson {
2305c94dd38SPaul A. Clarke env->fpscr |= FP_VXZDZ;
23113c9115fSRichard Henderson finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXZDZ, set_fpcc, retaddr);
23213c9115fSRichard Henderson }
23313c9115fSRichard Henderson
234fcf5ef2aSThomas Huth /* Multiplication of zero by infinity */
float_invalid_op_vximz(CPUPPCState * env,bool set_fpcc,uintptr_t retaddr)23513c9115fSRichard Henderson static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc,
23613c9115fSRichard Henderson uintptr_t retaddr)
23713c9115fSRichard Henderson {
2385c94dd38SPaul A. Clarke env->fpscr |= FP_VXIMZ;
23913c9115fSRichard Henderson finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr);
24013c9115fSRichard Henderson }
24113c9115fSRichard Henderson
24213c9115fSRichard Henderson /* Square root of a negative number */
float_invalid_op_vxsqrt(CPUPPCState * env,bool set_fpcc,uintptr_t retaddr)24313c9115fSRichard Henderson static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc,
24413c9115fSRichard Henderson uintptr_t retaddr)
24513c9115fSRichard Henderson {
2465c94dd38SPaul A. Clarke env->fpscr |= FP_VXSQRT;
24713c9115fSRichard Henderson finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXSQRT, set_fpcc, retaddr);
24813c9115fSRichard Henderson }
24913c9115fSRichard Henderson
250fcf5ef2aSThomas Huth /* Ordered comparison of NaN */
float_invalid_op_vxvc(CPUPPCState * env,bool set_fpcc,uintptr_t retaddr)25113c9115fSRichard Henderson static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
25213c9115fSRichard Henderson uintptr_t retaddr)
25313c9115fSRichard Henderson {
2545c94dd38SPaul A. Clarke env->fpscr |= FP_VXVC;
255fcf5ef2aSThomas Huth if (set_fpcc) {
2565c94dd38SPaul A. Clarke env->fpscr &= ~FP_FPCC;
2575c94dd38SPaul A. Clarke env->fpscr |= (FP_C | FP_FU);
258fcf5ef2aSThomas Huth }
25913c9115fSRichard Henderson /* Update the floating-point invalid operation summary */
2605c94dd38SPaul A. Clarke env->fpscr |= FP_VX;
26113c9115fSRichard Henderson /* Update the floating-point exception summary */
26213c9115fSRichard Henderson env->fpscr |= FP_FX;
263fcf5ef2aSThomas Huth /* We must update the target FPR before raising the exception */
264208d8033SVíctor Colombo if (env->fpscr & FP_VE) {
265db70b311SRichard Henderson CPUState *cs = env_cpu(env);
26613c9115fSRichard Henderson
267fcf5ef2aSThomas Huth cs->exception_index = POWERPC_EXCP_PROGRAM;
268fcf5ef2aSThomas Huth env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
269fcf5ef2aSThomas Huth /* Update the floating-point enabled exception summary */
2705c94dd38SPaul A. Clarke env->fpscr |= FP_FEX;
27192eeb004SBALATON Zoltan /* Exception is deferred */
272fcf5ef2aSThomas Huth }
273fcf5ef2aSThomas Huth }
27413c9115fSRichard Henderson
275fcf5ef2aSThomas Huth /* Invalid conversion */
float_invalid_op_vxcvi(CPUPPCState * env,bool set_fpcc,uintptr_t retaddr)27613c9115fSRichard Henderson static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
27713c9115fSRichard Henderson uintptr_t retaddr)
27813c9115fSRichard Henderson {
2795c94dd38SPaul A. Clarke env->fpscr |= FP_VXCVI;
2805c94dd38SPaul A. Clarke env->fpscr &= ~(FP_FR | FP_FI);
281208d8033SVíctor Colombo if (!(env->fpscr & FP_VE)) {
282fcf5ef2aSThomas Huth if (set_fpcc) {
2835c94dd38SPaul A. Clarke env->fpscr &= ~FP_FPCC;
2845c94dd38SPaul A. Clarke env->fpscr |= (FP_C | FP_FU);
285fcf5ef2aSThomas Huth }
286fcf5ef2aSThomas Huth }
28713c9115fSRichard Henderson finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, retaddr);
288fcf5ef2aSThomas Huth }
289fcf5ef2aSThomas Huth
float_zero_divide_excp(CPUPPCState * env,uintptr_t raddr)290fcf5ef2aSThomas Huth static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
291fcf5ef2aSThomas Huth {
2925c94dd38SPaul A. Clarke env->fpscr |= FP_ZX;
2935c94dd38SPaul A. Clarke env->fpscr &= ~(FP_FR | FP_FI);
294fcf5ef2aSThomas Huth /* Update the floating-point exception summary */
295fcf5ef2aSThomas Huth env->fpscr |= FP_FX;
296208d8033SVíctor Colombo if (env->fpscr & FP_ZE) {
297fcf5ef2aSThomas Huth /* Update the floating-point enabled exception summary */
2985c94dd38SPaul A. Clarke env->fpscr |= FP_FEX;
299e82c42b7SRichard Henderson if (fp_exceptions_enabled(env)) {
300fcf5ef2aSThomas Huth raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
301fcf5ef2aSThomas Huth POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
302fcf5ef2aSThomas Huth raddr);
303fcf5ef2aSThomas Huth }
304fcf5ef2aSThomas Huth }
305fcf5ef2aSThomas Huth }
306fcf5ef2aSThomas Huth
float_overflow_excp(CPUPPCState * env)307c582a1dbSVíctor Colombo static inline int float_overflow_excp(CPUPPCState *env)
308fcf5ef2aSThomas Huth {
309db70b311SRichard Henderson CPUState *cs = env_cpu(env);
310fcf5ef2aSThomas Huth
3115c94dd38SPaul A. Clarke env->fpscr |= FP_OX;
312fcf5ef2aSThomas Huth /* Update the floating-point exception summary */
313fcf5ef2aSThomas Huth env->fpscr |= FP_FX;
314c582a1dbSVíctor Colombo
315c582a1dbSVíctor Colombo bool overflow_enabled = !!(env->fpscr & FP_OE);
316c582a1dbSVíctor Colombo if (overflow_enabled) {
317fcf5ef2aSThomas Huth /* Update the floating-point enabled exception summary */
3185c94dd38SPaul A. Clarke env->fpscr |= FP_FEX;
319fcf5ef2aSThomas Huth /* We must update the target FPR before raising the exception */
320fcf5ef2aSThomas Huth cs->exception_index = POWERPC_EXCP_PROGRAM;
321fcf5ef2aSThomas Huth env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
322fcf5ef2aSThomas Huth }
323c582a1dbSVíctor Colombo
324c582a1dbSVíctor Colombo return overflow_enabled ? 0 : float_flag_inexact;
325fcf5ef2aSThomas Huth }
326fcf5ef2aSThomas Huth
float_underflow_excp(CPUPPCState * env)327fcf5ef2aSThomas Huth static inline void float_underflow_excp(CPUPPCState *env)
328fcf5ef2aSThomas Huth {
329db70b311SRichard Henderson CPUState *cs = env_cpu(env);
330fcf5ef2aSThomas Huth
3315c94dd38SPaul A. Clarke env->fpscr |= FP_UX;
332fcf5ef2aSThomas Huth /* Update the floating-point exception summary */
333fcf5ef2aSThomas Huth env->fpscr |= FP_FX;
334208d8033SVíctor Colombo if (env->fpscr & FP_UE) {
335fcf5ef2aSThomas Huth /* Update the floating-point enabled exception summary */
3365c94dd38SPaul A. Clarke env->fpscr |= FP_FEX;
337fcf5ef2aSThomas Huth /* We must update the target FPR before raising the exception */
338fcf5ef2aSThomas Huth cs->exception_index = POWERPC_EXCP_PROGRAM;
339fcf5ef2aSThomas Huth env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
340fcf5ef2aSThomas Huth }
341fcf5ef2aSThomas Huth }
342fcf5ef2aSThomas Huth
float_inexact_excp(CPUPPCState * env)343fcf5ef2aSThomas Huth static inline void float_inexact_excp(CPUPPCState *env)
344fcf5ef2aSThomas Huth {
345db70b311SRichard Henderson CPUState *cs = env_cpu(env);
346fcf5ef2aSThomas Huth
3475c94dd38SPaul A. Clarke env->fpscr |= FP_XX;
348fcf5ef2aSThomas Huth /* Update the floating-point exception summary */
349fcf5ef2aSThomas Huth env->fpscr |= FP_FX;
350208d8033SVíctor Colombo if (env->fpscr & FP_XE) {
351fcf5ef2aSThomas Huth /* Update the floating-point enabled exception summary */
3525c94dd38SPaul A. Clarke env->fpscr |= FP_FEX;
353fcf5ef2aSThomas Huth /* We must update the target FPR before raising the exception */
354fcf5ef2aSThomas Huth cs->exception_index = POWERPC_EXCP_PROGRAM;
355fcf5ef2aSThomas Huth env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
356fcf5ef2aSThomas Huth }
357fcf5ef2aSThomas Huth }
358fcf5ef2aSThomas Huth
helper_fpscr_clrbit(CPUPPCState * env,uint32_t bit)359fcf5ef2aSThomas Huth void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
360fcf5ef2aSThomas Huth {
361fe43ba97SBruno Larsen (billionai) uint32_t mask = 1u << bit;
362fe43ba97SBruno Larsen (billionai) if (env->fpscr & mask) {
363fe43ba97SBruno Larsen (billionai) ppc_store_fpscr(env, env->fpscr & ~(target_ulong)mask);
364fcf5ef2aSThomas Huth }
365fcf5ef2aSThomas Huth }
366fcf5ef2aSThomas Huth
helper_fpscr_setbit(CPUPPCState * env,uint32_t bit)367fcf5ef2aSThomas Huth void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
368fcf5ef2aSThomas Huth {
369fe43ba97SBruno Larsen (billionai) uint32_t mask = 1u << bit;
370fe43ba97SBruno Larsen (billionai) if (!(env->fpscr & mask)) {
371fe43ba97SBruno Larsen (billionai) ppc_store_fpscr(env, env->fpscr | mask);
372fcf5ef2aSThomas Huth }
373fcf5ef2aSThomas Huth }
374fcf5ef2aSThomas Huth
helper_store_fpscr(CPUPPCState * env,uint64_t val,uint32_t nibbles)375fe43ba97SBruno Larsen (billionai) void helper_store_fpscr(CPUPPCState *env, uint64_t val, uint32_t nibbles)
376fcf5ef2aSThomas Huth {
377fe43ba97SBruno Larsen (billionai) target_ulong mask = 0;
378fcf5ef2aSThomas Huth int i;
379fcf5ef2aSThomas Huth
380fe43ba97SBruno Larsen (billionai) /* TODO: push this extension back to translation time */
381fcf5ef2aSThomas Huth for (i = 0; i < sizeof(target_ulong) * 2; i++) {
382fe43ba97SBruno Larsen (billionai) if (nibbles & (1 << i)) {
383fe43ba97SBruno Larsen (billionai) mask |= (target_ulong) 0xf << (4 * i);
384fcf5ef2aSThomas Huth }
385fcf5ef2aSThomas Huth }
386fe43ba97SBruno Larsen (billionai) val = (val & mask) | (env->fpscr & ~mask);
387fe43ba97SBruno Larsen (billionai) ppc_store_fpscr(env, val);
388fcf5ef2aSThomas Huth }
389fcf5ef2aSThomas Huth
do_fpscr_check_status(CPUPPCState * env,uintptr_t raddr)390c29018ccSLucas Mateus Castro (alqotel) static void do_fpscr_check_status(CPUPPCState *env, uintptr_t raddr)
391c3a824b0SLucas Mateus Castro (alqotel) {
392c3a824b0SLucas Mateus Castro (alqotel) CPUState *cs = env_cpu(env);
393c3a824b0SLucas Mateus Castro (alqotel) target_ulong fpscr = env->fpscr;
394c3a824b0SLucas Mateus Castro (alqotel) int error = 0;
395c3a824b0SLucas Mateus Castro (alqotel)
396c3a824b0SLucas Mateus Castro (alqotel) if ((fpscr & FP_OX) && (fpscr & FP_OE)) {
397c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_OX;
398c3a824b0SLucas Mateus Castro (alqotel) } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) {
399c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_UX;
400c3a824b0SLucas Mateus Castro (alqotel) } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) {
401c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_XX;
402c3a824b0SLucas Mateus Castro (alqotel) } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) {
403c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_ZX;
404c3a824b0SLucas Mateus Castro (alqotel) } else if (fpscr & FP_VE) {
405c3a824b0SLucas Mateus Castro (alqotel) if (fpscr & FP_VXSOFT) {
406c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_VXSOFT;
407c3a824b0SLucas Mateus Castro (alqotel) } else if (fpscr & FP_VXSNAN) {
408c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_VXSNAN;
409c3a824b0SLucas Mateus Castro (alqotel) } else if (fpscr & FP_VXISI) {
410c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_VXISI;
411c3a824b0SLucas Mateus Castro (alqotel) } else if (fpscr & FP_VXIDI) {
412c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_VXIDI;
413c3a824b0SLucas Mateus Castro (alqotel) } else if (fpscr & FP_VXZDZ) {
414c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_VXZDZ;
415c3a824b0SLucas Mateus Castro (alqotel) } else if (fpscr & FP_VXIMZ) {
416c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_VXIMZ;
417c3a824b0SLucas Mateus Castro (alqotel) } else if (fpscr & FP_VXVC) {
418c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_VXVC;
419c3a824b0SLucas Mateus Castro (alqotel) } else if (fpscr & FP_VXSQRT) {
420c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_VXSQRT;
421c3a824b0SLucas Mateus Castro (alqotel) } else if (fpscr & FP_VXCVI) {
422c3a824b0SLucas Mateus Castro (alqotel) error = POWERPC_EXCP_FP_VXCVI;
423c3a824b0SLucas Mateus Castro (alqotel) } else {
424c3a824b0SLucas Mateus Castro (alqotel) return;
425c3a824b0SLucas Mateus Castro (alqotel) }
426c3a824b0SLucas Mateus Castro (alqotel) } else {
427c3a824b0SLucas Mateus Castro (alqotel) return;
428c3a824b0SLucas Mateus Castro (alqotel) }
429c3a824b0SLucas Mateus Castro (alqotel) cs->exception_index = POWERPC_EXCP_PROGRAM;
430c3a824b0SLucas Mateus Castro (alqotel) env->error_code = error | POWERPC_EXCP_FP;
4315980167eSDaniel Henrique Barboza env->fpscr |= FP_FEX;
432c3a824b0SLucas Mateus Castro (alqotel) /* Deferred floating-point exception after target FPSCR update */
433c3a824b0SLucas Mateus Castro (alqotel) if (fp_exceptions_enabled(env)) {
434c3a824b0SLucas Mateus Castro (alqotel) raise_exception_err_ra(env, cs->exception_index,
435c29018ccSLucas Mateus Castro (alqotel) env->error_code, raddr);
436c3a824b0SLucas Mateus Castro (alqotel) }
437c3a824b0SLucas Mateus Castro (alqotel) }
438c3a824b0SLucas Mateus Castro (alqotel)
helper_fpscr_check_status(CPUPPCState * env)439c29018ccSLucas Mateus Castro (alqotel) void helper_fpscr_check_status(CPUPPCState *env)
440c29018ccSLucas Mateus Castro (alqotel) {
441c29018ccSLucas Mateus Castro (alqotel) do_fpscr_check_status(env, GETPC());
442c29018ccSLucas Mateus Castro (alqotel) }
443c29018ccSLucas Mateus Castro (alqotel)
do_float_check_status(CPUPPCState * env,bool change_fi,uintptr_t raddr)4443278677fSVíctor Colombo static void do_float_check_status(CPUPPCState *env, bool change_fi,
4453278677fSVíctor Colombo uintptr_t raddr)
446fcf5ef2aSThomas Huth {
447db70b311SRichard Henderson CPUState *cs = env_cpu(env);
448fcf5ef2aSThomas Huth int status = get_float_exception_flags(&env->fp_status);
449fcf5ef2aSThomas Huth
450ae13018dSRichard Henderson if (status & float_flag_overflow) {
451c582a1dbSVíctor Colombo status |= float_overflow_excp(env);
452fcf5ef2aSThomas Huth } else if (status & float_flag_underflow) {
453fcf5ef2aSThomas Huth float_underflow_excp(env);
4549e430ca3SJohn Arbuckle }
45516ce2fffSRichard Henderson if (status & float_flag_inexact) {
45616ce2fffSRichard Henderson float_inexact_excp(env);
4573278677fSVíctor Colombo }
4583278677fSVíctor Colombo if (change_fi) {
4593278677fSVíctor Colombo env->fpscr = FIELD_DP64(env->fpscr, FPSCR, FI,
4603278677fSVíctor Colombo !!(status & float_flag_inexact));
461fcf5ef2aSThomas Huth }
462fcf5ef2aSThomas Huth
463fcf5ef2aSThomas Huth if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
464fcf5ef2aSThomas Huth (env->error_code & POWERPC_EXCP_FP)) {
46592eeb004SBALATON Zoltan /* Deferred floating-point exception after target FPR update */
466e82c42b7SRichard Henderson if (fp_exceptions_enabled(env)) {
467fcf5ef2aSThomas Huth raise_exception_err_ra(env, cs->exception_index,
468fcf5ef2aSThomas Huth env->error_code, raddr);
469fcf5ef2aSThomas Huth }
470fcf5ef2aSThomas Huth }
471fcf5ef2aSThomas Huth }
472fcf5ef2aSThomas Huth
helper_float_check_status(CPUPPCState * env)473fcf5ef2aSThomas Huth void helper_float_check_status(CPUPPCState *env)
474fcf5ef2aSThomas Huth {
4753278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
476fcf5ef2aSThomas Huth }
477fcf5ef2aSThomas Huth
helper_reset_fpstatus(CPUPPCState * env)478fcf5ef2aSThomas Huth void helper_reset_fpstatus(CPUPPCState *env)
479fcf5ef2aSThomas Huth {
480fcf5ef2aSThomas Huth set_float_exception_flags(0, &env->fp_status);
481fcf5ef2aSThomas Huth }
482fcf5ef2aSThomas Huth
float_invalid_op_addsub(CPUPPCState * env,int flags,bool set_fpcc,uintptr_t retaddr)483941298ecSRichard Henderson static void float_invalid_op_addsub(CPUPPCState *env, int flags,
484941298ecSRichard Henderson bool set_fpcc, uintptr_t retaddr)
48557483867SRichard Henderson {
486941298ecSRichard Henderson if (flags & float_flag_invalid_isi) {
48757483867SRichard Henderson float_invalid_op_vxisi(env, set_fpcc, retaddr);
488941298ecSRichard Henderson } else if (flags & float_flag_invalid_snan) {
48957483867SRichard Henderson float_invalid_op_vxsnan(env, retaddr);
49057483867SRichard Henderson }
49157483867SRichard Henderson }
49257483867SRichard Henderson
addsub_flags_handler(CPUPPCState * env,int flags,uintptr_t ra)4935747926fSChinmay Rath static inline void addsub_flags_handler(CPUPPCState *env, int flags,
4945747926fSChinmay Rath uintptr_t ra)
495fcf5ef2aSThomas Huth {
496941298ecSRichard Henderson if (unlikely(flags & float_flag_invalid)) {
4975747926fSChinmay Rath float_invalid_op_addsub(env, flags, 1, ra);
498fcf5ef2aSThomas Huth }
499d9e792a1SRichard Henderson }
500d9e792a1SRichard Henderson
float_invalid_op_mul(CPUPPCState * env,int flags,bool set_fprc,uintptr_t retaddr)5014edf5569SRichard Henderson static void float_invalid_op_mul(CPUPPCState *env, int flags,
5024edf5569SRichard Henderson bool set_fprc, uintptr_t retaddr)
5034f0da706SRichard Henderson {
5044edf5569SRichard Henderson if (flags & float_flag_invalid_imz) {
5054f0da706SRichard Henderson float_invalid_op_vximz(env, set_fprc, retaddr);
5064edf5569SRichard Henderson } else if (flags & float_flag_invalid_snan) {
5074f0da706SRichard Henderson float_invalid_op_vxsnan(env, retaddr);
5084f0da706SRichard Henderson }
5094f0da706SRichard Henderson }
5104f0da706SRichard Henderson
mul_flags_handler(CPUPPCState * env,int flags,uintptr_t ra)5115747926fSChinmay Rath static inline void mul_flags_handler(CPUPPCState *env, int flags, uintptr_t ra)
512fcf5ef2aSThomas Huth {
5134edf5569SRichard Henderson if (unlikely(flags & float_flag_invalid)) {
5145747926fSChinmay Rath float_invalid_op_mul(env, flags, 1, ra);
515fcf5ef2aSThomas Huth }
5167f87214eSRichard Henderson }
5177f87214eSRichard Henderson
float_invalid_op_div(CPUPPCState * env,int flags,bool set_fprc,uintptr_t retaddr)518c07f8241SRichard Henderson static void float_invalid_op_div(CPUPPCState *env, int flags,
519c07f8241SRichard Henderson bool set_fprc, uintptr_t retaddr)
520fec59ef3SRichard Henderson {
521c07f8241SRichard Henderson if (flags & float_flag_invalid_idi) {
522fec59ef3SRichard Henderson float_invalid_op_vxidi(env, set_fprc, retaddr);
523c07f8241SRichard Henderson } else if (flags & float_flag_invalid_zdz) {
524fec59ef3SRichard Henderson float_invalid_op_vxzdz(env, set_fprc, retaddr);
525c07f8241SRichard Henderson } else if (flags & float_flag_invalid_snan) {
526fec59ef3SRichard Henderson float_invalid_op_vxsnan(env, retaddr);
527fec59ef3SRichard Henderson }
528fec59ef3SRichard Henderson }
529fec59ef3SRichard Henderson
div_flags_handler(CPUPPCState * env,int flags,uintptr_t ra)5305747926fSChinmay Rath static inline void div_flags_handler(CPUPPCState *env, int flags, uintptr_t ra)
531fcf5ef2aSThomas Huth {
532c07f8241SRichard Henderson if (unlikely(flags & float_flag_invalid)) {
5335747926fSChinmay Rath float_invalid_op_div(env, flags, 1, ra);
534ae13018dSRichard Henderson }
535c07f8241SRichard Henderson if (unlikely(flags & float_flag_divbyzero)) {
5365747926fSChinmay Rath float_zero_divide_excp(env, ra);
537ae13018dSRichard Henderson }
538d9e792a1SRichard Henderson }
539d9e792a1SRichard Henderson
float_invalid_cvt(CPUPPCState * env,int flags,uint64_t ret,uint64_t ret_nan,bool set_fprc,uintptr_t retaddr)540fed12f3bSRichard Henderson static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
541fed12f3bSRichard Henderson uint64_t ret, uint64_t ret_nan,
542353464eaSRichard Henderson bool set_fprc, uintptr_t retaddr)
543a3dec427SRichard Henderson {
544fed12f3bSRichard Henderson /*
545fed12f3bSRichard Henderson * VXCVI is different from most in that it sets two exception bits,
546fed12f3bSRichard Henderson * VXCVI and VXSNAN for an SNaN input.
547fed12f3bSRichard Henderson */
548353464eaSRichard Henderson if (flags & float_flag_invalid_snan) {
549fed12f3bSRichard Henderson env->fpscr |= FP_VXSNAN;
550a3dec427SRichard Henderson }
551fed12f3bSRichard Henderson float_invalid_op_vxcvi(env, set_fprc, retaddr);
552fed12f3bSRichard Henderson
553fed12f3bSRichard Henderson return flags & float_flag_invalid_cvti ? ret : ret_nan;
554a3dec427SRichard Henderson }
555fcf5ef2aSThomas Huth
556fcf5ef2aSThomas Huth #define FPU_FCTI(op, cvt, nanval) \
557a3dec427SRichard Henderson uint64_t helper_##op(CPUPPCState *env, float64 arg) \
558fcf5ef2aSThomas Huth { \
559a3dec427SRichard Henderson uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
560353464eaSRichard Henderson int flags = get_float_exception_flags(&env->fp_status); \
561353464eaSRichard Henderson if (unlikely(flags & float_flag_invalid)) { \
562fed12f3bSRichard Henderson ret = float_invalid_cvt(env, flags, ret, nanval, 1, GETPC()); \
563fcf5ef2aSThomas Huth } \
564a3dec427SRichard Henderson return ret; \
565fcf5ef2aSThomas Huth }
566fcf5ef2aSThomas Huth
567fcf5ef2aSThomas Huth FPU_FCTI(fctiw, int32, 0x80000000U)
568fcf5ef2aSThomas Huth FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
569fcf5ef2aSThomas Huth FPU_FCTI(fctiwu, uint32, 0x00000000U)
570fcf5ef2aSThomas Huth FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
571fcf5ef2aSThomas Huth FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
572fcf5ef2aSThomas Huth FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
573fcf5ef2aSThomas Huth FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
574fcf5ef2aSThomas Huth FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
575fcf5ef2aSThomas Huth
576fcf5ef2aSThomas Huth #define FPU_FCFI(op, cvtr, is_single) \
577fcf5ef2aSThomas Huth uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
578fcf5ef2aSThomas Huth { \
579fcf5ef2aSThomas Huth CPU_DoubleU farg; \
580fcf5ef2aSThomas Huth \
581fcf5ef2aSThomas Huth if (is_single) { \
582fcf5ef2aSThomas Huth float32 tmp = cvtr(arg, &env->fp_status); \
583fcf5ef2aSThomas Huth farg.d = float32_to_float64(tmp, &env->fp_status); \
584fcf5ef2aSThomas Huth } else { \
585fcf5ef2aSThomas Huth farg.d = cvtr(arg, &env->fp_status); \
586fcf5ef2aSThomas Huth } \
5873278677fSVíctor Colombo do_float_check_status(env, true, GETPC()); \
588fcf5ef2aSThomas Huth return farg.ll; \
589fcf5ef2aSThomas Huth }
590fcf5ef2aSThomas Huth
591fcf5ef2aSThomas Huth FPU_FCFI(fcfid, int64_to_float64, 0)
592fcf5ef2aSThomas Huth FPU_FCFI(fcfids, int64_to_float32, 1)
593fcf5ef2aSThomas Huth FPU_FCFI(fcfidu, uint64_to_float64, 0)
594fcf5ef2aSThomas Huth FPU_FCFI(fcfidus, uint64_to_float32, 1)
595fcf5ef2aSThomas Huth
do_fri(CPUPPCState * env,uint64_t arg,FloatRoundMode rounding_mode)596b891757eSRichard Henderson static uint64_t do_fri(CPUPPCState *env, uint64_t arg,
5976bce0777SRichard Henderson FloatRoundMode rounding_mode)
598fcf5ef2aSThomas Huth {
59963d06e90SBruno Larsen (billionai) FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status);
600a4963527SRichard Henderson int flags;
601fcf5ef2aSThomas Huth
602fcf5ef2aSThomas Huth set_float_rounding_mode(rounding_mode, &env->fp_status);
603a4963527SRichard Henderson arg = float64_round_to_int(arg, &env->fp_status);
60463d06e90SBruno Larsen (billionai) set_float_rounding_mode(old_rounding_mode, &env->fp_status);
605fcf5ef2aSThomas Huth
606a4963527SRichard Henderson flags = get_float_exception_flags(&env->fp_status);
607a4963527SRichard Henderson if (flags & float_flag_invalid_snan) {
608a4963527SRichard Henderson float_invalid_op_vxsnan(env, GETPC());
609fcf5ef2aSThomas Huth }
610a4963527SRichard Henderson
611a4963527SRichard Henderson /* fri* does not set FPSCR[XX] */
612a4963527SRichard Henderson set_float_exception_flags(flags & ~float_flag_inexact, &env->fp_status);
6133278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
614a4963527SRichard Henderson
615a4963527SRichard Henderson return arg;
616fcf5ef2aSThomas Huth }
617fcf5ef2aSThomas Huth
helper_frin(CPUPPCState * env,uint64_t arg)618fcf5ef2aSThomas Huth uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
619fcf5ef2aSThomas Huth {
620fcf5ef2aSThomas Huth return do_fri(env, arg, float_round_ties_away);
621fcf5ef2aSThomas Huth }
622fcf5ef2aSThomas Huth
helper_friz(CPUPPCState * env,uint64_t arg)623fcf5ef2aSThomas Huth uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
624fcf5ef2aSThomas Huth {
625fcf5ef2aSThomas Huth return do_fri(env, arg, float_round_to_zero);
626fcf5ef2aSThomas Huth }
627fcf5ef2aSThomas Huth
helper_frip(CPUPPCState * env,uint64_t arg)628fcf5ef2aSThomas Huth uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
629fcf5ef2aSThomas Huth {
630fcf5ef2aSThomas Huth return do_fri(env, arg, float_round_up);
631fcf5ef2aSThomas Huth }
632fcf5ef2aSThomas Huth
helper_frim(CPUPPCState * env,uint64_t arg)633fcf5ef2aSThomas Huth uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
634fcf5ef2aSThomas Huth {
635fcf5ef2aSThomas Huth return do_fri(env, arg, float_round_down);
636fcf5ef2aSThomas Huth }
637fcf5ef2aSThomas Huth
float_invalid_op_madd(CPUPPCState * env,int flags,bool set_fpcc,uintptr_t retaddr)638e4052bb7SRichard Henderson static void float_invalid_op_madd(CPUPPCState *env, int flags,
639e4052bb7SRichard Henderson bool set_fpcc, uintptr_t retaddr)
640e4052bb7SRichard Henderson {
641e4052bb7SRichard Henderson if (flags & float_flag_invalid_imz) {
642e4052bb7SRichard Henderson float_invalid_op_vximz(env, set_fpcc, retaddr);
643e4052bb7SRichard Henderson } else {
644e4052bb7SRichard Henderson float_invalid_op_addsub(env, flags, set_fpcc, retaddr);
645806c9d71SNikunj A Dadhania }
646e4052bb7SRichard Henderson }
647fcf5ef2aSThomas Huth
do_fmadd(CPUPPCState * env,float64 a,float64 b,float64 c,int madd_flags,uintptr_t retaddr)648ffdaff8eSRichard Henderson static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b,
649ffdaff8eSRichard Henderson float64 c, int madd_flags, uintptr_t retaddr)
650ffdaff8eSRichard Henderson {
651ffdaff8eSRichard Henderson float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status);
652ffdaff8eSRichard Henderson int flags = get_float_exception_flags(&env->fp_status);
653ffdaff8eSRichard Henderson
6542125ac18SRichard Henderson if (unlikely(flags & float_flag_invalid)) {
655ffdaff8eSRichard Henderson float_invalid_op_madd(env, flags, 1, retaddr);
656ffdaff8eSRichard Henderson }
657ffdaff8eSRichard Henderson return ret;
658ffdaff8eSRichard Henderson }
659ffdaff8eSRichard Henderson
do_fmadds(CPUPPCState * env,float64 a,float64 b,float64 c,int madd_flags,uintptr_t retaddr)660d04ca895SRichard Henderson static uint64_t do_fmadds(CPUPPCState *env, float64 a, float64 b,
661d04ca895SRichard Henderson float64 c, int madd_flags, uintptr_t retaddr)
662d04ca895SRichard Henderson {
663d04ca895SRichard Henderson float64 ret = float64r32_muladd(a, b, c, madd_flags, &env->fp_status);
664d04ca895SRichard Henderson int flags = get_float_exception_flags(&env->fp_status);
665d04ca895SRichard Henderson
666d04ca895SRichard Henderson if (unlikely(flags & float_flag_invalid)) {
667d04ca895SRichard Henderson float_invalid_op_madd(env, flags, 1, retaddr);
668d04ca895SRichard Henderson }
669d04ca895SRichard Henderson return ret;
670d04ca895SRichard Henderson }
671d04ca895SRichard Henderson
672992d7e97SNikunj A Dadhania #define FPU_FMADD(op, madd_flags) \
673992d7e97SNikunj A Dadhania uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
674992d7e97SNikunj A Dadhania uint64_t arg2, uint64_t arg3) \
675d04ca895SRichard Henderson { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); } \
676177fcc06SChinmay Rath uint64_t helper_##op##S(CPUPPCState *env, uint64_t arg1, \
677d04ca895SRichard Henderson uint64_t arg2, uint64_t arg3) \
678d04ca895SRichard Henderson { return do_fmadds(env, arg1, arg2, arg3, madd_flags, GETPC()); }
679fcf5ef2aSThomas Huth
680992d7e97SNikunj A Dadhania #define MADD_FLGS 0
681992d7e97SNikunj A Dadhania #define MSUB_FLGS float_muladd_negate_c
682992d7e97SNikunj A Dadhania #define NMADD_FLGS float_muladd_negate_result
683992d7e97SNikunj A Dadhania #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
684fcf5ef2aSThomas Huth
FPU_FMADD(FMADD,MADD_FLGS)685177fcc06SChinmay Rath FPU_FMADD(FMADD, MADD_FLGS)
686177fcc06SChinmay Rath FPU_FMADD(FNMADD, NMADD_FLGS)
687177fcc06SChinmay Rath FPU_FMADD(FMSUB, MSUB_FLGS)
688177fcc06SChinmay Rath FPU_FMADD(FNMSUB, NMSUB_FLGS)
689fcf5ef2aSThomas Huth
690fcf5ef2aSThomas Huth /* frsp - frsp. */
6917238e55bSRichard Henderson static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr)
692fcf5ef2aSThomas Huth {
693734cfbd8SRichard Henderson float32 f32 = float64_to_float32(arg, &env->fp_status);
694734cfbd8SRichard Henderson int flags = get_float_exception_flags(&env->fp_status);
695fcf5ef2aSThomas Huth
696734cfbd8SRichard Henderson if (unlikely(flags & float_flag_invalid_snan)) {
6977238e55bSRichard Henderson float_invalid_op_vxsnan(env, retaddr);
698fcf5ef2aSThomas Huth }
69958c7edefSRichard Henderson return helper_todouble(f32);
700fcf5ef2aSThomas Huth }
701fcf5ef2aSThomas Huth
helper_frsp(CPUPPCState * env,uint64_t arg)7027238e55bSRichard Henderson uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
7037238e55bSRichard Henderson {
7047238e55bSRichard Henderson return do_frsp(env, arg, GETPC());
7057238e55bSRichard Henderson }
7067238e55bSRichard Henderson
float_invalid_op_sqrt(CPUPPCState * env,int flags,bool set_fpcc,uintptr_t retaddr)7073d3050ccSRichard Henderson static void float_invalid_op_sqrt(CPUPPCState *env, int flags,
7083d3050ccSRichard Henderson bool set_fpcc, uintptr_t retaddr)
7093d3050ccSRichard Henderson {
7103d3050ccSRichard Henderson if (unlikely(flags & float_flag_invalid_sqrt)) {
7113d3050ccSRichard Henderson float_invalid_op_vxsqrt(env, set_fpcc, retaddr);
7123d3050ccSRichard Henderson } else if (unlikely(flags & float_flag_invalid_snan)) {
7133d3050ccSRichard Henderson float_invalid_op_vxsnan(env, retaddr);
7143d3050ccSRichard Henderson }
7153d3050ccSRichard Henderson }
7163d3050ccSRichard Henderson
71774177ec6SVíctor Colombo #define FPU_FSQRT(name, op) \
71874177ec6SVíctor Colombo float64 helper_##name(CPUPPCState *env, float64 arg) \
71974177ec6SVíctor Colombo { \
72074177ec6SVíctor Colombo float64 ret = op(arg, &env->fp_status); \
72174177ec6SVíctor Colombo int flags = get_float_exception_flags(&env->fp_status); \
72274177ec6SVíctor Colombo \
72374177ec6SVíctor Colombo if (unlikely(flags & float_flag_invalid)) { \
72474177ec6SVíctor Colombo float_invalid_op_sqrt(env, flags, 1, GETPC()); \
72574177ec6SVíctor Colombo } \
72674177ec6SVíctor Colombo \
72774177ec6SVíctor Colombo return ret; \
72849ab52efSRichard Henderson }
72949ab52efSRichard Henderson
FPU_FSQRT(FSQRT,float64_sqrt)73074177ec6SVíctor Colombo FPU_FSQRT(FSQRT, float64_sqrt)
73174177ec6SVíctor Colombo FPU_FSQRT(FSQRTS, float64r32_sqrt)
73241ae890dSRichard Henderson
7335747926fSChinmay Rath #define FPU_FRE(name, op) \
7345747926fSChinmay Rath float64 helper_##name(CPUPPCState *env, float64 arg) \
7355747926fSChinmay Rath { \
7365747926fSChinmay Rath /* "Estimate" the reciprocal with actual division. */ \
7375747926fSChinmay Rath float64 ret = op(float64_one, arg, &env->fp_status); \
7385747926fSChinmay Rath int flags = get_float_exception_flags(&env->fp_status); \
7395747926fSChinmay Rath \
7405747926fSChinmay Rath if (unlikely(flags & float_flag_invalid_snan)) { \
7415747926fSChinmay Rath float_invalid_op_vxsnan(env, GETPC()); \
7425747926fSChinmay Rath } \
7435747926fSChinmay Rath if (unlikely(flags & float_flag_divbyzero)) { \
7445747926fSChinmay Rath float_zero_divide_excp(env, GETPC()); \
7455747926fSChinmay Rath /* For FPSCR.ZE == 0, the result is 1/2. */ \
7465747926fSChinmay Rath ret = float64_set_sign(float64_half, float64_is_neg(arg)); \
7475747926fSChinmay Rath } \
7485747926fSChinmay Rath \
7495747926fSChinmay Rath return ret; \
75038434717SRichard Henderson }
75138434717SRichard Henderson
7525747926fSChinmay Rath #define FPU_FRSQRTE(name, op) \
7535747926fSChinmay Rath float64 helper_##name(CPUPPCState *env, float64 arg) \
7545747926fSChinmay Rath { \
7555747926fSChinmay Rath /* "Estimate" the reciprocal with actual division. */ \
7565747926fSChinmay Rath float64 rets = float64_sqrt(arg, &env->fp_status); \
7575747926fSChinmay Rath float64 retd = op(float64_one, rets, &env->fp_status); \
7585747926fSChinmay Rath int flags = get_float_exception_flags(&env->fp_status); \
7595747926fSChinmay Rath \
7605747926fSChinmay Rath if (unlikely(flags & float_flag_invalid)) { \
7615747926fSChinmay Rath float_invalid_op_sqrt(env, flags, 1, GETPC()); \
7625747926fSChinmay Rath } \
7635747926fSChinmay Rath if (unlikely(flags & float_flag_divbyzero)) { \
7645747926fSChinmay Rath /* Reciprocal of (square root of) zero. */ \
7655747926fSChinmay Rath float_zero_divide_excp(env, GETPC()); \
7665747926fSChinmay Rath } \
7675747926fSChinmay Rath \
7685747926fSChinmay Rath return retd; \
769fcf5ef2aSThomas Huth }
770fcf5ef2aSThomas Huth
7715747926fSChinmay Rath #define FPU_HELPER(name, op, flags_handler) \
7725747926fSChinmay Rath float64 helper_##name(CPUPPCState *env, float64 arg1, float64 arg2) \
7735747926fSChinmay Rath { \
7745747926fSChinmay Rath float64 ret = op(arg1, arg2, &env->fp_status); \
7755747926fSChinmay Rath int flags = get_float_exception_flags(&env->fp_status); \
7765747926fSChinmay Rath uintptr_t ra = GETPC(); \
7775747926fSChinmay Rath flags_handler(env, flags, ra); \
7785747926fSChinmay Rath return ret; \
7797d82ea34SRichard Henderson }
780fcf5ef2aSThomas Huth
781177fcc06SChinmay Rath FPU_FRE(FRE, float64_div)
782177fcc06SChinmay Rath FPU_FRE(FRES, float64r32_div)
783177fcc06SChinmay Rath FPU_FRSQRTE(FRSQRTE, float64_div)
784177fcc06SChinmay Rath FPU_FRSQRTE(FRSQRTES, float64r32_div)
785177fcc06SChinmay Rath FPU_HELPER(FADD, float64_add, addsub_flags_handler)
786177fcc06SChinmay Rath FPU_HELPER(FADDS, float64r32_add, addsub_flags_handler)
787177fcc06SChinmay Rath FPU_HELPER(FSUB, float64_sub, addsub_flags_handler)
788177fcc06SChinmay Rath FPU_HELPER(FSUBS, float64r32_sub, addsub_flags_handler)
789177fcc06SChinmay Rath FPU_HELPER(FMUL, float64_mul, mul_flags_handler)
790177fcc06SChinmay Rath FPU_HELPER(FMULS, float64r32_mul, mul_flags_handler)
791177fcc06SChinmay Rath FPU_HELPER(FDIV, float64_div, div_flags_handler)
792177fcc06SChinmay Rath FPU_HELPER(FDIVS, float64r32_div, div_flags_handler)
793dedbfda7SRichard Henderson
794fcf5ef2aSThomas Huth /* fsel - fsel. */
795eb69a84bSMatheus Ferst uint64_t helper_FSEL(uint64_t a, uint64_t b, uint64_t c)
796fcf5ef2aSThomas Huth {
797eb69a84bSMatheus Ferst CPU_DoubleU fa;
798fcf5ef2aSThomas Huth
799eb69a84bSMatheus Ferst fa.ll = a;
800fcf5ef2aSThomas Huth
801eb69a84bSMatheus Ferst if ((!float64_is_neg(fa.d) || float64_is_zero(fa.d)) &&
802eb69a84bSMatheus Ferst !float64_is_any_nan(fa.d)) {
803eb69a84bSMatheus Ferst return c;
804fcf5ef2aSThomas Huth } else {
805eb69a84bSMatheus Ferst return b;
806fcf5ef2aSThomas Huth }
807fcf5ef2aSThomas Huth }
808fcf5ef2aSThomas Huth
helper_FTDIV(uint64_t fra,uint64_t frb)809177fcc06SChinmay Rath uint32_t helper_FTDIV(uint64_t fra, uint64_t frb)
810fcf5ef2aSThomas Huth {
811fcf5ef2aSThomas Huth int fe_flag = 0;
812fcf5ef2aSThomas Huth int fg_flag = 0;
813fcf5ef2aSThomas Huth
814fcf5ef2aSThomas Huth if (unlikely(float64_is_infinity(fra) ||
815fcf5ef2aSThomas Huth float64_is_infinity(frb) ||
816fcf5ef2aSThomas Huth float64_is_zero(frb))) {
817fcf5ef2aSThomas Huth fe_flag = 1;
818fcf5ef2aSThomas Huth fg_flag = 1;
819fcf5ef2aSThomas Huth } else {
820fcf5ef2aSThomas Huth int e_a = ppc_float64_get_unbiased_exp(fra);
821fcf5ef2aSThomas Huth int e_b = ppc_float64_get_unbiased_exp(frb);
822fcf5ef2aSThomas Huth
823fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(fra) ||
824fcf5ef2aSThomas Huth float64_is_any_nan(frb))) {
825fcf5ef2aSThomas Huth fe_flag = 1;
826fcf5ef2aSThomas Huth } else if ((e_b <= -1022) || (e_b >= 1021)) {
827fcf5ef2aSThomas Huth fe_flag = 1;
828fcf5ef2aSThomas Huth } else if (!float64_is_zero(fra) &&
829fcf5ef2aSThomas Huth (((e_a - e_b) >= 1023) ||
830fcf5ef2aSThomas Huth ((e_a - e_b) <= -1021) ||
831fcf5ef2aSThomas Huth (e_a <= -970))) {
832fcf5ef2aSThomas Huth fe_flag = 1;
833fcf5ef2aSThomas Huth }
834fcf5ef2aSThomas Huth
835fcf5ef2aSThomas Huth if (unlikely(float64_is_zero_or_denormal(frb))) {
836fcf5ef2aSThomas Huth /* XB is not zero because of the above check and */
837fcf5ef2aSThomas Huth /* so must be denormalized. */
838fcf5ef2aSThomas Huth fg_flag = 1;
839fcf5ef2aSThomas Huth }
840fcf5ef2aSThomas Huth }
841fcf5ef2aSThomas Huth
842fcf5ef2aSThomas Huth return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
843fcf5ef2aSThomas Huth }
844fcf5ef2aSThomas Huth
helper_FTSQRT(uint64_t frb)845177fcc06SChinmay Rath uint32_t helper_FTSQRT(uint64_t frb)
846fcf5ef2aSThomas Huth {
847fcf5ef2aSThomas Huth int fe_flag = 0;
848fcf5ef2aSThomas Huth int fg_flag = 0;
849fcf5ef2aSThomas Huth
850fcf5ef2aSThomas Huth if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
851fcf5ef2aSThomas Huth fe_flag = 1;
852fcf5ef2aSThomas Huth fg_flag = 1;
853fcf5ef2aSThomas Huth } else {
854fcf5ef2aSThomas Huth int e_b = ppc_float64_get_unbiased_exp(frb);
855fcf5ef2aSThomas Huth
856fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(frb))) {
857fcf5ef2aSThomas Huth fe_flag = 1;
858fcf5ef2aSThomas Huth } else if (unlikely(float64_is_zero(frb))) {
859fcf5ef2aSThomas Huth fe_flag = 1;
860fcf5ef2aSThomas Huth } else if (unlikely(float64_is_neg(frb))) {
861fcf5ef2aSThomas Huth fe_flag = 1;
862fcf5ef2aSThomas Huth } else if (!float64_is_zero(frb) && (e_b <= (-1022 + 52))) {
863fcf5ef2aSThomas Huth fe_flag = 1;
864fcf5ef2aSThomas Huth }
865fcf5ef2aSThomas Huth
866fcf5ef2aSThomas Huth if (unlikely(float64_is_zero_or_denormal(frb))) {
867fcf5ef2aSThomas Huth /* XB is not zero because of the above check and */
868fcf5ef2aSThomas Huth /* therefore must be denormalized. */
869fcf5ef2aSThomas Huth fg_flag = 1;
870fcf5ef2aSThomas Huth }
871fcf5ef2aSThomas Huth }
872fcf5ef2aSThomas Huth
873fcf5ef2aSThomas Huth return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
874fcf5ef2aSThomas Huth }
875fcf5ef2aSThomas Huth
helper_fcmpu(CPUPPCState * env,uint64_t arg1,uint64_t arg2,uint32_t crfD)876fcf5ef2aSThomas Huth void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
877fcf5ef2aSThomas Huth uint32_t crfD)
878fcf5ef2aSThomas Huth {
879fcf5ef2aSThomas Huth CPU_DoubleU farg1, farg2;
880fcf5ef2aSThomas Huth uint32_t ret = 0;
881fcf5ef2aSThomas Huth
882fcf5ef2aSThomas Huth farg1.ll = arg1;
883fcf5ef2aSThomas Huth farg2.ll = arg2;
884fcf5ef2aSThomas Huth
885fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(farg1.d) ||
886fcf5ef2aSThomas Huth float64_is_any_nan(farg2.d))) {
887fcf5ef2aSThomas Huth ret = 0x01UL;
888fcf5ef2aSThomas Huth } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
889fcf5ef2aSThomas Huth ret = 0x08UL;
890fcf5ef2aSThomas Huth } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
891fcf5ef2aSThomas Huth ret = 0x04UL;
892fcf5ef2aSThomas Huth } else {
893fcf5ef2aSThomas Huth ret = 0x02UL;
894fcf5ef2aSThomas Huth }
895fcf5ef2aSThomas Huth
8965c94dd38SPaul A. Clarke env->fpscr &= ~FP_FPCC;
8975c94dd38SPaul A. Clarke env->fpscr |= ret << FPSCR_FPCC;
898fcf5ef2aSThomas Huth env->crf[crfD] = ret;
899fcf5ef2aSThomas Huth if (unlikely(ret == 0x01UL
900fcf5ef2aSThomas Huth && (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
901fcf5ef2aSThomas Huth float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
902fcf5ef2aSThomas Huth /* sNaN comparison */
90313c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC());
904fcf5ef2aSThomas Huth }
905fcf5ef2aSThomas Huth }
906fcf5ef2aSThomas Huth
helper_fcmpo(CPUPPCState * env,uint64_t arg1,uint64_t arg2,uint32_t crfD)907fcf5ef2aSThomas Huth void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
908fcf5ef2aSThomas Huth uint32_t crfD)
909fcf5ef2aSThomas Huth {
910fcf5ef2aSThomas Huth CPU_DoubleU farg1, farg2;
911fcf5ef2aSThomas Huth uint32_t ret = 0;
912fcf5ef2aSThomas Huth
913fcf5ef2aSThomas Huth farg1.ll = arg1;
914fcf5ef2aSThomas Huth farg2.ll = arg2;
915fcf5ef2aSThomas Huth
916fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(farg1.d) ||
917fcf5ef2aSThomas Huth float64_is_any_nan(farg2.d))) {
918fcf5ef2aSThomas Huth ret = 0x01UL;
919fcf5ef2aSThomas Huth } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
920fcf5ef2aSThomas Huth ret = 0x08UL;
921fcf5ef2aSThomas Huth } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
922fcf5ef2aSThomas Huth ret = 0x04UL;
923fcf5ef2aSThomas Huth } else {
924fcf5ef2aSThomas Huth ret = 0x02UL;
925fcf5ef2aSThomas Huth }
926fcf5ef2aSThomas Huth
9275c94dd38SPaul A. Clarke env->fpscr &= ~FP_FPCC;
9285c94dd38SPaul A. Clarke env->fpscr |= ret << FPSCR_FPCC;
9295c94dd38SPaul A. Clarke env->crf[crfD] = (uint32_t) ret;
930fcf5ef2aSThomas Huth if (unlikely(ret == 0x01UL)) {
93113c9115fSRichard Henderson float_invalid_op_vxvc(env, 1, GETPC());
932fcf5ef2aSThomas Huth if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
933fcf5ef2aSThomas Huth float64_is_signaling_nan(farg2.d, &env->fp_status)) {
934fcf5ef2aSThomas Huth /* sNaN comparison */
93513c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC());
936fcf5ef2aSThomas Huth }
937fcf5ef2aSThomas Huth }
938fcf5ef2aSThomas Huth }
939fcf5ef2aSThomas Huth
940fcf5ef2aSThomas Huth /* Single-precision floating-point conversions */
efscfsi(CPUPPCState * env,uint32_t val)941fcf5ef2aSThomas Huth static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
942fcf5ef2aSThomas Huth {
943fcf5ef2aSThomas Huth CPU_FloatU u;
944fcf5ef2aSThomas Huth
945fcf5ef2aSThomas Huth u.f = int32_to_float32(val, &env->vec_status);
946fcf5ef2aSThomas Huth
947fcf5ef2aSThomas Huth return u.l;
948fcf5ef2aSThomas Huth }
949fcf5ef2aSThomas Huth
efscfui(CPUPPCState * env,uint32_t val)950fcf5ef2aSThomas Huth static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
951fcf5ef2aSThomas Huth {
952fcf5ef2aSThomas Huth CPU_FloatU u;
953fcf5ef2aSThomas Huth
954fcf5ef2aSThomas Huth u.f = uint32_to_float32(val, &env->vec_status);
955fcf5ef2aSThomas Huth
956fcf5ef2aSThomas Huth return u.l;
957fcf5ef2aSThomas Huth }
958fcf5ef2aSThomas Huth
efsctsi(CPUPPCState * env,uint32_t val)959fcf5ef2aSThomas Huth static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
960fcf5ef2aSThomas Huth {
961fcf5ef2aSThomas Huth CPU_FloatU u;
962fcf5ef2aSThomas Huth
963fcf5ef2aSThomas Huth u.l = val;
964fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
965fcf5ef2aSThomas Huth if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
966fcf5ef2aSThomas Huth return 0;
967fcf5ef2aSThomas Huth }
968fcf5ef2aSThomas Huth
969fcf5ef2aSThomas Huth return float32_to_int32(u.f, &env->vec_status);
970fcf5ef2aSThomas Huth }
971fcf5ef2aSThomas Huth
efsctui(CPUPPCState * env,uint32_t val)972fcf5ef2aSThomas Huth static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
973fcf5ef2aSThomas Huth {
974fcf5ef2aSThomas Huth CPU_FloatU u;
975fcf5ef2aSThomas Huth
976fcf5ef2aSThomas Huth u.l = val;
977fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
978fcf5ef2aSThomas Huth if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
979fcf5ef2aSThomas Huth return 0;
980fcf5ef2aSThomas Huth }
981fcf5ef2aSThomas Huth
982fcf5ef2aSThomas Huth return float32_to_uint32(u.f, &env->vec_status);
983fcf5ef2aSThomas Huth }
984fcf5ef2aSThomas Huth
efsctsiz(CPUPPCState * env,uint32_t val)985fcf5ef2aSThomas Huth static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
986fcf5ef2aSThomas Huth {
987fcf5ef2aSThomas Huth CPU_FloatU u;
988fcf5ef2aSThomas Huth
989fcf5ef2aSThomas Huth u.l = val;
990fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
991fcf5ef2aSThomas Huth if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
992fcf5ef2aSThomas Huth return 0;
993fcf5ef2aSThomas Huth }
994fcf5ef2aSThomas Huth
995fcf5ef2aSThomas Huth return float32_to_int32_round_to_zero(u.f, &env->vec_status);
996fcf5ef2aSThomas Huth }
997fcf5ef2aSThomas Huth
efsctuiz(CPUPPCState * env,uint32_t val)998fcf5ef2aSThomas Huth static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
999fcf5ef2aSThomas Huth {
1000fcf5ef2aSThomas Huth CPU_FloatU u;
1001fcf5ef2aSThomas Huth
1002fcf5ef2aSThomas Huth u.l = val;
1003fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1004fcf5ef2aSThomas Huth if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1005fcf5ef2aSThomas Huth return 0;
1006fcf5ef2aSThomas Huth }
1007fcf5ef2aSThomas Huth
1008fcf5ef2aSThomas Huth return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1009fcf5ef2aSThomas Huth }
1010fcf5ef2aSThomas Huth
efscfsf(CPUPPCState * env,uint32_t val)1011fcf5ef2aSThomas Huth static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1012fcf5ef2aSThomas Huth {
1013fcf5ef2aSThomas Huth CPU_FloatU u;
1014fcf5ef2aSThomas Huth float32 tmp;
1015fcf5ef2aSThomas Huth
1016fcf5ef2aSThomas Huth u.f = int32_to_float32(val, &env->vec_status);
1017fcf5ef2aSThomas Huth tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1018fcf5ef2aSThomas Huth u.f = float32_div(u.f, tmp, &env->vec_status);
1019fcf5ef2aSThomas Huth
1020fcf5ef2aSThomas Huth return u.l;
1021fcf5ef2aSThomas Huth }
1022fcf5ef2aSThomas Huth
efscfuf(CPUPPCState * env,uint32_t val)1023fcf5ef2aSThomas Huth static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1024fcf5ef2aSThomas Huth {
1025fcf5ef2aSThomas Huth CPU_FloatU u;
1026fcf5ef2aSThomas Huth float32 tmp;
1027fcf5ef2aSThomas Huth
1028fcf5ef2aSThomas Huth u.f = uint32_to_float32(val, &env->vec_status);
1029fcf5ef2aSThomas Huth tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1030fcf5ef2aSThomas Huth u.f = float32_div(u.f, tmp, &env->vec_status);
1031fcf5ef2aSThomas Huth
1032fcf5ef2aSThomas Huth return u.l;
1033fcf5ef2aSThomas Huth }
1034fcf5ef2aSThomas Huth
efsctsf(CPUPPCState * env,uint32_t val)1035fcf5ef2aSThomas Huth static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1036fcf5ef2aSThomas Huth {
1037fcf5ef2aSThomas Huth CPU_FloatU u;
1038fcf5ef2aSThomas Huth float32 tmp;
1039fcf5ef2aSThomas Huth
1040fcf5ef2aSThomas Huth u.l = val;
1041fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1042fcf5ef2aSThomas Huth if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1043fcf5ef2aSThomas Huth return 0;
1044fcf5ef2aSThomas Huth }
1045fcf5ef2aSThomas Huth tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1046fcf5ef2aSThomas Huth u.f = float32_mul(u.f, tmp, &env->vec_status);
1047fcf5ef2aSThomas Huth
1048fcf5ef2aSThomas Huth return float32_to_int32(u.f, &env->vec_status);
1049fcf5ef2aSThomas Huth }
1050fcf5ef2aSThomas Huth
efsctuf(CPUPPCState * env,uint32_t val)1051fcf5ef2aSThomas Huth static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1052fcf5ef2aSThomas Huth {
1053fcf5ef2aSThomas Huth CPU_FloatU u;
1054fcf5ef2aSThomas Huth float32 tmp;
1055fcf5ef2aSThomas Huth
1056fcf5ef2aSThomas Huth u.l = val;
1057fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1058fcf5ef2aSThomas Huth if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1059fcf5ef2aSThomas Huth return 0;
1060fcf5ef2aSThomas Huth }
1061fcf5ef2aSThomas Huth tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1062fcf5ef2aSThomas Huth u.f = float32_mul(u.f, tmp, &env->vec_status);
1063fcf5ef2aSThomas Huth
1064fcf5ef2aSThomas Huth return float32_to_uint32(u.f, &env->vec_status);
1065fcf5ef2aSThomas Huth }
1066fcf5ef2aSThomas Huth
1067fcf5ef2aSThomas Huth #define HELPER_SPE_SINGLE_CONV(name) \
1068fcf5ef2aSThomas Huth uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1069fcf5ef2aSThomas Huth { \
1070fcf5ef2aSThomas Huth return e##name(env, val); \
1071fcf5ef2aSThomas Huth }
1072fcf5ef2aSThomas Huth /* efscfsi */
1073fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fscfsi);
1074fcf5ef2aSThomas Huth /* efscfui */
1075fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fscfui);
1076fcf5ef2aSThomas Huth /* efscfuf */
1077fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fscfuf);
1078fcf5ef2aSThomas Huth /* efscfsf */
1079fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fscfsf);
1080fcf5ef2aSThomas Huth /* efsctsi */
1081fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fsctsi);
1082fcf5ef2aSThomas Huth /* efsctui */
1083fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fsctui);
1084fcf5ef2aSThomas Huth /* efsctsiz */
1085fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fsctsiz);
1086fcf5ef2aSThomas Huth /* efsctuiz */
1087fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fsctuiz);
1088fcf5ef2aSThomas Huth /* efsctsf */
1089fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fsctsf);
1090fcf5ef2aSThomas Huth /* efsctuf */
1091fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_CONV(fsctuf);
1092fcf5ef2aSThomas Huth
1093fcf5ef2aSThomas Huth #define HELPER_SPE_VECTOR_CONV(name) \
1094fcf5ef2aSThomas Huth uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1095fcf5ef2aSThomas Huth { \
1096fcf5ef2aSThomas Huth return ((uint64_t)e##name(env, val >> 32) << 32) | \
1097fcf5ef2aSThomas Huth (uint64_t)e##name(env, val); \
1098fcf5ef2aSThomas Huth }
1099fcf5ef2aSThomas Huth /* evfscfsi */
1100fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fscfsi);
1101fcf5ef2aSThomas Huth /* evfscfui */
1102fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fscfui);
1103fcf5ef2aSThomas Huth /* evfscfuf */
1104fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fscfuf);
1105fcf5ef2aSThomas Huth /* evfscfsf */
1106fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fscfsf);
1107fcf5ef2aSThomas Huth /* evfsctsi */
1108fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fsctsi);
1109fcf5ef2aSThomas Huth /* evfsctui */
1110fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fsctui);
1111fcf5ef2aSThomas Huth /* evfsctsiz */
1112fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fsctsiz);
1113fcf5ef2aSThomas Huth /* evfsctuiz */
1114fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fsctuiz);
1115fcf5ef2aSThomas Huth /* evfsctsf */
1116fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fsctsf);
1117fcf5ef2aSThomas Huth /* evfsctuf */
1118fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_CONV(fsctuf);
1119fcf5ef2aSThomas Huth
1120fcf5ef2aSThomas Huth /* Single-precision floating-point arithmetic */
efsadd(CPUPPCState * env,uint32_t op1,uint32_t op2)1121fcf5ef2aSThomas Huth static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1122fcf5ef2aSThomas Huth {
1123fcf5ef2aSThomas Huth CPU_FloatU u1, u2;
1124fcf5ef2aSThomas Huth
1125fcf5ef2aSThomas Huth u1.l = op1;
1126fcf5ef2aSThomas Huth u2.l = op2;
1127fcf5ef2aSThomas Huth u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1128fcf5ef2aSThomas Huth return u1.l;
1129fcf5ef2aSThomas Huth }
1130fcf5ef2aSThomas Huth
efssub(CPUPPCState * env,uint32_t op1,uint32_t op2)1131fcf5ef2aSThomas Huth static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1132fcf5ef2aSThomas Huth {
1133fcf5ef2aSThomas Huth CPU_FloatU u1, u2;
1134fcf5ef2aSThomas Huth
1135fcf5ef2aSThomas Huth u1.l = op1;
1136fcf5ef2aSThomas Huth u2.l = op2;
1137fcf5ef2aSThomas Huth u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1138fcf5ef2aSThomas Huth return u1.l;
1139fcf5ef2aSThomas Huth }
1140fcf5ef2aSThomas Huth
efsmul(CPUPPCState * env,uint32_t op1,uint32_t op2)1141fcf5ef2aSThomas Huth static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1142fcf5ef2aSThomas Huth {
1143fcf5ef2aSThomas Huth CPU_FloatU u1, u2;
1144fcf5ef2aSThomas Huth
1145fcf5ef2aSThomas Huth u1.l = op1;
1146fcf5ef2aSThomas Huth u2.l = op2;
1147fcf5ef2aSThomas Huth u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1148fcf5ef2aSThomas Huth return u1.l;
1149fcf5ef2aSThomas Huth }
1150fcf5ef2aSThomas Huth
efsdiv(CPUPPCState * env,uint32_t op1,uint32_t op2)1151fcf5ef2aSThomas Huth static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1152fcf5ef2aSThomas Huth {
1153fcf5ef2aSThomas Huth CPU_FloatU u1, u2;
1154fcf5ef2aSThomas Huth
1155fcf5ef2aSThomas Huth u1.l = op1;
1156fcf5ef2aSThomas Huth u2.l = op2;
1157fcf5ef2aSThomas Huth u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1158fcf5ef2aSThomas Huth return u1.l;
1159fcf5ef2aSThomas Huth }
1160fcf5ef2aSThomas Huth
1161fcf5ef2aSThomas Huth #define HELPER_SPE_SINGLE_ARITH(name) \
1162fcf5ef2aSThomas Huth uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1163fcf5ef2aSThomas Huth { \
1164fcf5ef2aSThomas Huth return e##name(env, op1, op2); \
1165fcf5ef2aSThomas Huth }
1166fcf5ef2aSThomas Huth /* efsadd */
1167fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_ARITH(fsadd);
1168fcf5ef2aSThomas Huth /* efssub */
1169fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_ARITH(fssub);
1170fcf5ef2aSThomas Huth /* efsmul */
1171fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_ARITH(fsmul);
1172fcf5ef2aSThomas Huth /* efsdiv */
1173fcf5ef2aSThomas Huth HELPER_SPE_SINGLE_ARITH(fsdiv);
1174fcf5ef2aSThomas Huth
1175fcf5ef2aSThomas Huth #define HELPER_SPE_VECTOR_ARITH(name) \
1176fcf5ef2aSThomas Huth uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1177fcf5ef2aSThomas Huth { \
1178fcf5ef2aSThomas Huth return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1179fcf5ef2aSThomas Huth (uint64_t)e##name(env, op1, op2); \
1180fcf5ef2aSThomas Huth }
1181fcf5ef2aSThomas Huth /* evfsadd */
1182fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_ARITH(fsadd);
1183fcf5ef2aSThomas Huth /* evfssub */
1184fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_ARITH(fssub);
1185fcf5ef2aSThomas Huth /* evfsmul */
1186fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_ARITH(fsmul);
1187fcf5ef2aSThomas Huth /* evfsdiv */
1188fcf5ef2aSThomas Huth HELPER_SPE_VECTOR_ARITH(fsdiv);
1189fcf5ef2aSThomas Huth
1190fcf5ef2aSThomas Huth /* Single-precision floating-point comparisons */
efscmplt(CPUPPCState * env,uint32_t op1,uint32_t op2)1191fcf5ef2aSThomas Huth static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1192fcf5ef2aSThomas Huth {
1193fcf5ef2aSThomas Huth CPU_FloatU u1, u2;
1194fcf5ef2aSThomas Huth
1195fcf5ef2aSThomas Huth u1.l = op1;
1196fcf5ef2aSThomas Huth u2.l = op2;
1197fcf5ef2aSThomas Huth return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1198fcf5ef2aSThomas Huth }
1199fcf5ef2aSThomas Huth
efscmpgt(CPUPPCState * env,uint32_t op1,uint32_t op2)1200fcf5ef2aSThomas Huth static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1201fcf5ef2aSThomas Huth {
1202fcf5ef2aSThomas Huth CPU_FloatU u1, u2;
1203fcf5ef2aSThomas Huth
1204fcf5ef2aSThomas Huth u1.l = op1;
1205fcf5ef2aSThomas Huth u2.l = op2;
1206fcf5ef2aSThomas Huth return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1207fcf5ef2aSThomas Huth }
1208fcf5ef2aSThomas Huth
efscmpeq(CPUPPCState * env,uint32_t op1,uint32_t op2)1209fcf5ef2aSThomas Huth static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1210fcf5ef2aSThomas Huth {
1211fcf5ef2aSThomas Huth CPU_FloatU u1, u2;
1212fcf5ef2aSThomas Huth
1213fcf5ef2aSThomas Huth u1.l = op1;
1214fcf5ef2aSThomas Huth u2.l = op2;
1215fcf5ef2aSThomas Huth return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1216fcf5ef2aSThomas Huth }
1217fcf5ef2aSThomas Huth
efststlt(CPUPPCState * env,uint32_t op1,uint32_t op2)1218fcf5ef2aSThomas Huth static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1219fcf5ef2aSThomas Huth {
1220fcf5ef2aSThomas Huth /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1221fcf5ef2aSThomas Huth return efscmplt(env, op1, op2);
1222fcf5ef2aSThomas Huth }
1223fcf5ef2aSThomas Huth
efststgt(CPUPPCState * env,uint32_t op1,uint32_t op2)1224fcf5ef2aSThomas Huth static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1225fcf5ef2aSThomas Huth {
1226fcf5ef2aSThomas Huth /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1227fcf5ef2aSThomas Huth return efscmpgt(env, op1, op2);
1228fcf5ef2aSThomas Huth }
1229fcf5ef2aSThomas Huth
efststeq(CPUPPCState * env,uint32_t op1,uint32_t op2)1230fcf5ef2aSThomas Huth static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1231fcf5ef2aSThomas Huth {
1232fcf5ef2aSThomas Huth /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1233fcf5ef2aSThomas Huth return efscmpeq(env, op1, op2);
1234fcf5ef2aSThomas Huth }
1235fcf5ef2aSThomas Huth
1236fcf5ef2aSThomas Huth #define HELPER_SINGLE_SPE_CMP(name) \
1237fcf5ef2aSThomas Huth uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1238fcf5ef2aSThomas Huth { \
1239fcf5ef2aSThomas Huth return e##name(env, op1, op2); \
1240fcf5ef2aSThomas Huth }
1241fcf5ef2aSThomas Huth /* efststlt */
1242fcf5ef2aSThomas Huth HELPER_SINGLE_SPE_CMP(fststlt);
1243fcf5ef2aSThomas Huth /* efststgt */
1244fcf5ef2aSThomas Huth HELPER_SINGLE_SPE_CMP(fststgt);
1245fcf5ef2aSThomas Huth /* efststeq */
1246fcf5ef2aSThomas Huth HELPER_SINGLE_SPE_CMP(fststeq);
1247fcf5ef2aSThomas Huth /* efscmplt */
1248fcf5ef2aSThomas Huth HELPER_SINGLE_SPE_CMP(fscmplt);
1249fcf5ef2aSThomas Huth /* efscmpgt */
1250fcf5ef2aSThomas Huth HELPER_SINGLE_SPE_CMP(fscmpgt);
1251fcf5ef2aSThomas Huth /* efscmpeq */
1252fcf5ef2aSThomas Huth HELPER_SINGLE_SPE_CMP(fscmpeq);
1253fcf5ef2aSThomas Huth
evcmp_merge(int t0,int t1)1254fcf5ef2aSThomas Huth static inline uint32_t evcmp_merge(int t0, int t1)
1255fcf5ef2aSThomas Huth {
1256fcf5ef2aSThomas Huth return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1257fcf5ef2aSThomas Huth }
1258fcf5ef2aSThomas Huth
1259fcf5ef2aSThomas Huth #define HELPER_VECTOR_SPE_CMP(name) \
1260fcf5ef2aSThomas Huth uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1261fcf5ef2aSThomas Huth { \
1262fcf5ef2aSThomas Huth return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1263fcf5ef2aSThomas Huth e##name(env, op1, op2)); \
1264fcf5ef2aSThomas Huth }
1265fcf5ef2aSThomas Huth /* evfststlt */
1266fcf5ef2aSThomas Huth HELPER_VECTOR_SPE_CMP(fststlt);
1267fcf5ef2aSThomas Huth /* evfststgt */
1268fcf5ef2aSThomas Huth HELPER_VECTOR_SPE_CMP(fststgt);
1269fcf5ef2aSThomas Huth /* evfststeq */
1270fcf5ef2aSThomas Huth HELPER_VECTOR_SPE_CMP(fststeq);
1271fcf5ef2aSThomas Huth /* evfscmplt */
1272fcf5ef2aSThomas Huth HELPER_VECTOR_SPE_CMP(fscmplt);
1273fcf5ef2aSThomas Huth /* evfscmpgt */
1274fcf5ef2aSThomas Huth HELPER_VECTOR_SPE_CMP(fscmpgt);
1275fcf5ef2aSThomas Huth /* evfscmpeq */
1276fcf5ef2aSThomas Huth HELPER_VECTOR_SPE_CMP(fscmpeq);
1277fcf5ef2aSThomas Huth
1278fcf5ef2aSThomas Huth /* Double-precision floating-point conversion */
helper_efdcfsi(CPUPPCState * env,uint32_t val)1279fcf5ef2aSThomas Huth uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1280fcf5ef2aSThomas Huth {
1281fcf5ef2aSThomas Huth CPU_DoubleU u;
1282fcf5ef2aSThomas Huth
1283fcf5ef2aSThomas Huth u.d = int32_to_float64(val, &env->vec_status);
1284fcf5ef2aSThomas Huth
1285fcf5ef2aSThomas Huth return u.ll;
1286fcf5ef2aSThomas Huth }
1287fcf5ef2aSThomas Huth
helper_efdcfsid(CPUPPCState * env,uint64_t val)1288fcf5ef2aSThomas Huth uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1289fcf5ef2aSThomas Huth {
1290fcf5ef2aSThomas Huth CPU_DoubleU u;
1291fcf5ef2aSThomas Huth
1292fcf5ef2aSThomas Huth u.d = int64_to_float64(val, &env->vec_status);
1293fcf5ef2aSThomas Huth
1294fcf5ef2aSThomas Huth return u.ll;
1295fcf5ef2aSThomas Huth }
1296fcf5ef2aSThomas Huth
helper_efdcfui(CPUPPCState * env,uint32_t val)1297fcf5ef2aSThomas Huth uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1298fcf5ef2aSThomas Huth {
1299fcf5ef2aSThomas Huth CPU_DoubleU u;
1300fcf5ef2aSThomas Huth
1301fcf5ef2aSThomas Huth u.d = uint32_to_float64(val, &env->vec_status);
1302fcf5ef2aSThomas Huth
1303fcf5ef2aSThomas Huth return u.ll;
1304fcf5ef2aSThomas Huth }
1305fcf5ef2aSThomas Huth
helper_efdcfuid(CPUPPCState * env,uint64_t val)1306fcf5ef2aSThomas Huth uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1307fcf5ef2aSThomas Huth {
1308fcf5ef2aSThomas Huth CPU_DoubleU u;
1309fcf5ef2aSThomas Huth
1310fcf5ef2aSThomas Huth u.d = uint64_to_float64(val, &env->vec_status);
1311fcf5ef2aSThomas Huth
1312fcf5ef2aSThomas Huth return u.ll;
1313fcf5ef2aSThomas Huth }
1314fcf5ef2aSThomas Huth
helper_efdctsi(CPUPPCState * env,uint64_t val)1315fcf5ef2aSThomas Huth uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1316fcf5ef2aSThomas Huth {
1317fcf5ef2aSThomas Huth CPU_DoubleU u;
1318fcf5ef2aSThomas Huth
1319fcf5ef2aSThomas Huth u.ll = val;
1320fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1321fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(u.d))) {
1322fcf5ef2aSThomas Huth return 0;
1323fcf5ef2aSThomas Huth }
1324fcf5ef2aSThomas Huth
1325fcf5ef2aSThomas Huth return float64_to_int32(u.d, &env->vec_status);
1326fcf5ef2aSThomas Huth }
1327fcf5ef2aSThomas Huth
helper_efdctui(CPUPPCState * env,uint64_t val)1328fcf5ef2aSThomas Huth uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1329fcf5ef2aSThomas Huth {
1330fcf5ef2aSThomas Huth CPU_DoubleU u;
1331fcf5ef2aSThomas Huth
1332fcf5ef2aSThomas Huth u.ll = val;
1333fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1334fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(u.d))) {
1335fcf5ef2aSThomas Huth return 0;
1336fcf5ef2aSThomas Huth }
1337fcf5ef2aSThomas Huth
1338fcf5ef2aSThomas Huth return float64_to_uint32(u.d, &env->vec_status);
1339fcf5ef2aSThomas Huth }
1340fcf5ef2aSThomas Huth
helper_efdctsiz(CPUPPCState * env,uint64_t val)1341fcf5ef2aSThomas Huth uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1342fcf5ef2aSThomas Huth {
1343fcf5ef2aSThomas Huth CPU_DoubleU u;
1344fcf5ef2aSThomas Huth
1345fcf5ef2aSThomas Huth u.ll = val;
1346fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1347fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(u.d))) {
1348fcf5ef2aSThomas Huth return 0;
1349fcf5ef2aSThomas Huth }
1350fcf5ef2aSThomas Huth
1351fcf5ef2aSThomas Huth return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1352fcf5ef2aSThomas Huth }
1353fcf5ef2aSThomas Huth
helper_efdctsidz(CPUPPCState * env,uint64_t val)1354fcf5ef2aSThomas Huth uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1355fcf5ef2aSThomas Huth {
1356fcf5ef2aSThomas Huth CPU_DoubleU u;
1357fcf5ef2aSThomas Huth
1358fcf5ef2aSThomas Huth u.ll = val;
1359fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1360fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(u.d))) {
1361fcf5ef2aSThomas Huth return 0;
1362fcf5ef2aSThomas Huth }
1363fcf5ef2aSThomas Huth
1364fcf5ef2aSThomas Huth return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1365fcf5ef2aSThomas Huth }
1366fcf5ef2aSThomas Huth
helper_efdctuiz(CPUPPCState * env,uint64_t val)1367fcf5ef2aSThomas Huth uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1368fcf5ef2aSThomas Huth {
1369fcf5ef2aSThomas Huth CPU_DoubleU u;
1370fcf5ef2aSThomas Huth
1371fcf5ef2aSThomas Huth u.ll = val;
1372fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1373fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(u.d))) {
1374fcf5ef2aSThomas Huth return 0;
1375fcf5ef2aSThomas Huth }
1376fcf5ef2aSThomas Huth
1377fcf5ef2aSThomas Huth return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1378fcf5ef2aSThomas Huth }
1379fcf5ef2aSThomas Huth
helper_efdctuidz(CPUPPCState * env,uint64_t val)1380fcf5ef2aSThomas Huth uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1381fcf5ef2aSThomas Huth {
1382fcf5ef2aSThomas Huth CPU_DoubleU u;
1383fcf5ef2aSThomas Huth
1384fcf5ef2aSThomas Huth u.ll = val;
1385fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1386fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(u.d))) {
1387fcf5ef2aSThomas Huth return 0;
1388fcf5ef2aSThomas Huth }
1389fcf5ef2aSThomas Huth
1390fcf5ef2aSThomas Huth return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1391fcf5ef2aSThomas Huth }
1392fcf5ef2aSThomas Huth
helper_efdcfsf(CPUPPCState * env,uint32_t val)1393fcf5ef2aSThomas Huth uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1394fcf5ef2aSThomas Huth {
1395fcf5ef2aSThomas Huth CPU_DoubleU u;
1396fcf5ef2aSThomas Huth float64 tmp;
1397fcf5ef2aSThomas Huth
1398fcf5ef2aSThomas Huth u.d = int32_to_float64(val, &env->vec_status);
1399fcf5ef2aSThomas Huth tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1400fcf5ef2aSThomas Huth u.d = float64_div(u.d, tmp, &env->vec_status);
1401fcf5ef2aSThomas Huth
1402fcf5ef2aSThomas Huth return u.ll;
1403fcf5ef2aSThomas Huth }
1404fcf5ef2aSThomas Huth
helper_efdcfuf(CPUPPCState * env,uint32_t val)1405fcf5ef2aSThomas Huth uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1406fcf5ef2aSThomas Huth {
1407fcf5ef2aSThomas Huth CPU_DoubleU u;
1408fcf5ef2aSThomas Huth float64 tmp;
1409fcf5ef2aSThomas Huth
1410fcf5ef2aSThomas Huth u.d = uint32_to_float64(val, &env->vec_status);
1411fcf5ef2aSThomas Huth tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1412fcf5ef2aSThomas Huth u.d = float64_div(u.d, tmp, &env->vec_status);
1413fcf5ef2aSThomas Huth
1414fcf5ef2aSThomas Huth return u.ll;
1415fcf5ef2aSThomas Huth }
1416fcf5ef2aSThomas Huth
helper_efdctsf(CPUPPCState * env,uint64_t val)1417fcf5ef2aSThomas Huth uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1418fcf5ef2aSThomas Huth {
1419fcf5ef2aSThomas Huth CPU_DoubleU u;
1420fcf5ef2aSThomas Huth float64 tmp;
1421fcf5ef2aSThomas Huth
1422fcf5ef2aSThomas Huth u.ll = val;
1423fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1424fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(u.d))) {
1425fcf5ef2aSThomas Huth return 0;
1426fcf5ef2aSThomas Huth }
1427fcf5ef2aSThomas Huth tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1428fcf5ef2aSThomas Huth u.d = float64_mul(u.d, tmp, &env->vec_status);
1429fcf5ef2aSThomas Huth
1430fcf5ef2aSThomas Huth return float64_to_int32(u.d, &env->vec_status);
1431fcf5ef2aSThomas Huth }
1432fcf5ef2aSThomas Huth
helper_efdctuf(CPUPPCState * env,uint64_t val)1433fcf5ef2aSThomas Huth uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1434fcf5ef2aSThomas Huth {
1435fcf5ef2aSThomas Huth CPU_DoubleU u;
1436fcf5ef2aSThomas Huth float64 tmp;
1437fcf5ef2aSThomas Huth
1438fcf5ef2aSThomas Huth u.ll = val;
1439fcf5ef2aSThomas Huth /* NaN are not treated the same way IEEE 754 does */
1440fcf5ef2aSThomas Huth if (unlikely(float64_is_any_nan(u.d))) {
1441fcf5ef2aSThomas Huth return 0;
1442fcf5ef2aSThomas Huth }
1443fcf5ef2aSThomas Huth tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1444fcf5ef2aSThomas Huth u.d = float64_mul(u.d, tmp, &env->vec_status);
1445fcf5ef2aSThomas Huth
1446fcf5ef2aSThomas Huth return float64_to_uint32(u.d, &env->vec_status);
1447fcf5ef2aSThomas Huth }
1448fcf5ef2aSThomas Huth
helper_efscfd(CPUPPCState * env,uint64_t val)1449fcf5ef2aSThomas Huth uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1450fcf5ef2aSThomas Huth {
1451fcf5ef2aSThomas Huth CPU_DoubleU u1;
1452fcf5ef2aSThomas Huth CPU_FloatU u2;
1453fcf5ef2aSThomas Huth
1454fcf5ef2aSThomas Huth u1.ll = val;
1455fcf5ef2aSThomas Huth u2.f = float64_to_float32(u1.d, &env->vec_status);
1456fcf5ef2aSThomas Huth
1457fcf5ef2aSThomas Huth return u2.l;
1458fcf5ef2aSThomas Huth }
1459fcf5ef2aSThomas Huth
helper_efdcfs(CPUPPCState * env,uint32_t val)1460fcf5ef2aSThomas Huth uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1461fcf5ef2aSThomas Huth {
1462fcf5ef2aSThomas Huth CPU_DoubleU u2;
1463fcf5ef2aSThomas Huth CPU_FloatU u1;
1464fcf5ef2aSThomas Huth
1465fcf5ef2aSThomas Huth u1.l = val;
1466fcf5ef2aSThomas Huth u2.d = float32_to_float64(u1.f, &env->vec_status);
1467fcf5ef2aSThomas Huth
1468fcf5ef2aSThomas Huth return u2.ll;
1469fcf5ef2aSThomas Huth }
1470fcf5ef2aSThomas Huth
1471fcf5ef2aSThomas Huth /* Double precision fixed-point arithmetic */
helper_efdadd(CPUPPCState * env,uint64_t op1,uint64_t op2)1472fcf5ef2aSThomas Huth uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1473fcf5ef2aSThomas Huth {
1474fcf5ef2aSThomas Huth CPU_DoubleU u1, u2;
1475fcf5ef2aSThomas Huth
1476fcf5ef2aSThomas Huth u1.ll = op1;
1477fcf5ef2aSThomas Huth u2.ll = op2;
1478fcf5ef2aSThomas Huth u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1479fcf5ef2aSThomas Huth return u1.ll;
1480fcf5ef2aSThomas Huth }
1481fcf5ef2aSThomas Huth
helper_efdsub(CPUPPCState * env,uint64_t op1,uint64_t op2)1482fcf5ef2aSThomas Huth uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1483fcf5ef2aSThomas Huth {
1484fcf5ef2aSThomas Huth CPU_DoubleU u1, u2;
1485fcf5ef2aSThomas Huth
1486fcf5ef2aSThomas Huth u1.ll = op1;
1487fcf5ef2aSThomas Huth u2.ll = op2;
1488fcf5ef2aSThomas Huth u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1489fcf5ef2aSThomas Huth return u1.ll;
1490fcf5ef2aSThomas Huth }
1491fcf5ef2aSThomas Huth
helper_efdmul(CPUPPCState * env,uint64_t op1,uint64_t op2)1492fcf5ef2aSThomas Huth uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1493fcf5ef2aSThomas Huth {
1494fcf5ef2aSThomas Huth CPU_DoubleU u1, u2;
1495fcf5ef2aSThomas Huth
1496fcf5ef2aSThomas Huth u1.ll = op1;
1497fcf5ef2aSThomas Huth u2.ll = op2;
1498fcf5ef2aSThomas Huth u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1499fcf5ef2aSThomas Huth return u1.ll;
1500fcf5ef2aSThomas Huth }
1501fcf5ef2aSThomas Huth
helper_efddiv(CPUPPCState * env,uint64_t op1,uint64_t op2)1502fcf5ef2aSThomas Huth uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1503fcf5ef2aSThomas Huth {
1504fcf5ef2aSThomas Huth CPU_DoubleU u1, u2;
1505fcf5ef2aSThomas Huth
1506fcf5ef2aSThomas Huth u1.ll = op1;
1507fcf5ef2aSThomas Huth u2.ll = op2;
1508fcf5ef2aSThomas Huth u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1509fcf5ef2aSThomas Huth return u1.ll;
1510fcf5ef2aSThomas Huth }
1511fcf5ef2aSThomas Huth
1512fcf5ef2aSThomas Huth /* Double precision floating point helpers */
helper_efdtstlt(CPUPPCState * env,uint64_t op1,uint64_t op2)1513fcf5ef2aSThomas Huth uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1514fcf5ef2aSThomas Huth {
1515fcf5ef2aSThomas Huth CPU_DoubleU u1, u2;
1516fcf5ef2aSThomas Huth
1517fcf5ef2aSThomas Huth u1.ll = op1;
1518fcf5ef2aSThomas Huth u2.ll = op2;
1519fcf5ef2aSThomas Huth return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1520fcf5ef2aSThomas Huth }
1521fcf5ef2aSThomas Huth
helper_efdtstgt(CPUPPCState * env,uint64_t op1,uint64_t op2)1522fcf5ef2aSThomas Huth uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1523fcf5ef2aSThomas Huth {
1524fcf5ef2aSThomas Huth CPU_DoubleU u1, u2;
1525fcf5ef2aSThomas Huth
1526fcf5ef2aSThomas Huth u1.ll = op1;
1527fcf5ef2aSThomas Huth u2.ll = op2;
1528fcf5ef2aSThomas Huth return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1529fcf5ef2aSThomas Huth }
1530fcf5ef2aSThomas Huth
helper_efdtsteq(CPUPPCState * env,uint64_t op1,uint64_t op2)1531fcf5ef2aSThomas Huth uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1532fcf5ef2aSThomas Huth {
1533fcf5ef2aSThomas Huth CPU_DoubleU u1, u2;
1534fcf5ef2aSThomas Huth
1535fcf5ef2aSThomas Huth u1.ll = op1;
1536fcf5ef2aSThomas Huth u2.ll = op2;
1537fcf5ef2aSThomas Huth return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1538fcf5ef2aSThomas Huth }
1539fcf5ef2aSThomas Huth
helper_efdcmplt(CPUPPCState * env,uint64_t op1,uint64_t op2)1540fcf5ef2aSThomas Huth uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1541fcf5ef2aSThomas Huth {
1542fcf5ef2aSThomas Huth /* XXX: TODO: test special values (NaN, infinites, ...) */
1543fcf5ef2aSThomas Huth return helper_efdtstlt(env, op1, op2);
1544fcf5ef2aSThomas Huth }
1545fcf5ef2aSThomas Huth
helper_efdcmpgt(CPUPPCState * env,uint64_t op1,uint64_t op2)1546fcf5ef2aSThomas Huth uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1547fcf5ef2aSThomas Huth {
1548fcf5ef2aSThomas Huth /* XXX: TODO: test special values (NaN, infinites, ...) */
1549fcf5ef2aSThomas Huth return helper_efdtstgt(env, op1, op2);
1550fcf5ef2aSThomas Huth }
1551fcf5ef2aSThomas Huth
helper_efdcmpeq(CPUPPCState * env,uint64_t op1,uint64_t op2)1552fcf5ef2aSThomas Huth uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1553fcf5ef2aSThomas Huth {
1554fcf5ef2aSThomas Huth /* XXX: TODO: test special values (NaN, infinites, ...) */
1555fcf5ef2aSThomas Huth return helper_efdtsteq(env, op1, op2);
1556fcf5ef2aSThomas Huth }
1557fcf5ef2aSThomas Huth
1558fcf5ef2aSThomas Huth #define float64_to_float64(x, env) x
1559fcf5ef2aSThomas Huth
1560fcf5ef2aSThomas Huth
1561fa9ebf8cSDavid Gibson /*
1562136fbf65Szhaolichang * VSX_ADD_SUB - VSX floating point add/subtract
1563fcf5ef2aSThomas Huth * name - instruction mnemonic
1564fcf5ef2aSThomas Huth * op - operation (add or sub)
1565fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
1566fcf5ef2aSThomas Huth * tp - type (float32 or float64)
1567fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
1568dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
1569fcf5ef2aSThomas Huth */
1570dd657a35SVíctor Colombo #define VSX_ADD_SUB(name, op, nels, tp, fld, sfifprf, r2sp) \
157199125c74SMark Cave-Ayland void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
157299125c74SMark Cave-Ayland ppc_vsr_t *xa, ppc_vsr_t *xb) \
1573fcf5ef2aSThomas Huth { \
1574205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
1575fcf5ef2aSThomas Huth int i; \
1576fcf5ef2aSThomas Huth \
1577fcf5ef2aSThomas Huth helper_reset_fpstatus(env); \
1578fcf5ef2aSThomas Huth \
1579fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
1580fcf5ef2aSThomas Huth float_status tstat = env->fp_status; \
1581fcf5ef2aSThomas Huth set_float_exception_flags(0, &tstat); \
1582cf3b0334SMark Cave-Ayland t.fld = tp##_##op(xa->fld, xb->fld, &tstat); \
1583fcf5ef2aSThomas Huth env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1584fcf5ef2aSThomas Huth \
1585fcf5ef2aSThomas Huth if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1586941298ecSRichard Henderson float_invalid_op_addsub(env, tstat.float_exception_flags, \
1587dd657a35SVíctor Colombo sfifprf, GETPC()); \
1588fcf5ef2aSThomas Huth } \
1589fcf5ef2aSThomas Huth \
1590fcf5ef2aSThomas Huth if (r2sp) { \
15917238e55bSRichard Henderson t.fld = do_frsp(env, t.fld, GETPC()); \
1592fcf5ef2aSThomas Huth } \
1593fcf5ef2aSThomas Huth \
1594dd657a35SVíctor Colombo if (sfifprf) { \
1595cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.fld); \
1596fcf5ef2aSThomas Huth } \
1597fcf5ef2aSThomas Huth } \
1598cf3b0334SMark Cave-Ayland *xt = t; \
1599dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
1600fcf5ef2aSThomas Huth }
1601fcf5ef2aSThomas Huth
1602638f6d55SChinmay Rath VSX_ADD_SUB(XSADDDP, add, 1, float64, VsrD(0), 1, 0)
1603638f6d55SChinmay Rath VSX_ADD_SUB(XSADDSP, add, 1, float64, VsrD(0), 1, 1)
1604638f6d55SChinmay Rath VSX_ADD_SUB(XVADDDP, add, 2, float64, VsrD(i), 0, 0)
1605638f6d55SChinmay Rath VSX_ADD_SUB(XVADDSP, add, 4, float32, VsrW(i), 0, 0)
1606638f6d55SChinmay Rath VSX_ADD_SUB(XSSUBDP, sub, 1, float64, VsrD(0), 1, 0)
1607638f6d55SChinmay Rath VSX_ADD_SUB(XSSUBSP, sub, 1, float64, VsrD(0), 1, 1)
1608638f6d55SChinmay Rath VSX_ADD_SUB(XVSUBDP, sub, 2, float64, VsrD(i), 0, 0)
1609638f6d55SChinmay Rath VSX_ADD_SUB(XVSUBSP, sub, 4, float32, VsrW(i), 0, 0)
1610fcf5ef2aSThomas Huth
helper_xsaddqp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xt,ppc_vsr_t * xa,ppc_vsr_t * xb)161123d0766bSMark Cave-Ayland void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
161223d0766bSMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
161307bdd247SBharata B Rao {
1614cf3b0334SMark Cave-Ayland ppc_vsr_t t = *xt;
161507bdd247SBharata B Rao float_status tstat;
161607bdd247SBharata B Rao
161707bdd247SBharata B Rao helper_reset_fpstatus(env);
161807bdd247SBharata B Rao
1619a8d411abSBharata B Rao tstat = env->fp_status;
162007bdd247SBharata B Rao if (unlikely(Rc(opcode) != 0)) {
1621a8d411abSBharata B Rao tstat.float_rounding_mode = float_round_to_odd;
162207bdd247SBharata B Rao }
162307bdd247SBharata B Rao
162407bdd247SBharata B Rao set_float_exception_flags(0, &tstat);
1625cf3b0334SMark Cave-Ayland t.f128 = float128_add(xa->f128, xb->f128, &tstat);
162607bdd247SBharata B Rao env->fp_status.float_exception_flags |= tstat.float_exception_flags;
162707bdd247SBharata B Rao
162807bdd247SBharata B Rao if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1629941298ecSRichard Henderson float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
163007bdd247SBharata B Rao }
163107bdd247SBharata B Rao
1632cf3b0334SMark Cave-Ayland helper_compute_fprf_float128(env, t.f128);
163307bdd247SBharata B Rao
1634cf3b0334SMark Cave-Ayland *xt = t;
16353278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
163607bdd247SBharata B Rao }
163707bdd247SBharata B Rao
1638fa9ebf8cSDavid Gibson /*
1639fa9ebf8cSDavid Gibson * VSX_MUL - VSX floating point multiply
1640fcf5ef2aSThomas Huth * op - instruction mnemonic
1641fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
1642fcf5ef2aSThomas Huth * tp - type (float32 or float64)
1643fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
1644dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
1645fcf5ef2aSThomas Huth */
1646dd657a35SVíctor Colombo #define VSX_MUL(op, nels, tp, fld, sfifprf, r2sp) \
164799125c74SMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
164899125c74SMark Cave-Ayland ppc_vsr_t *xa, ppc_vsr_t *xb) \
1649fcf5ef2aSThomas Huth { \
1650205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
1651fcf5ef2aSThomas Huth int i; \
1652fcf5ef2aSThomas Huth \
1653fcf5ef2aSThomas Huth helper_reset_fpstatus(env); \
1654fcf5ef2aSThomas Huth \
1655fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
1656fcf5ef2aSThomas Huth float_status tstat = env->fp_status; \
1657fcf5ef2aSThomas Huth set_float_exception_flags(0, &tstat); \
1658cf3b0334SMark Cave-Ayland t.fld = tp##_mul(xa->fld, xb->fld, &tstat); \
1659fcf5ef2aSThomas Huth env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1660fcf5ef2aSThomas Huth \
1661fcf5ef2aSThomas Huth if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
16624edf5569SRichard Henderson float_invalid_op_mul(env, tstat.float_exception_flags, \
1663dd657a35SVíctor Colombo sfifprf, GETPC()); \
1664fcf5ef2aSThomas Huth } \
1665fcf5ef2aSThomas Huth \
1666fcf5ef2aSThomas Huth if (r2sp) { \
16677238e55bSRichard Henderson t.fld = do_frsp(env, t.fld, GETPC()); \
1668fcf5ef2aSThomas Huth } \
1669fcf5ef2aSThomas Huth \
1670dd657a35SVíctor Colombo if (sfifprf) { \
1671cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.fld); \
1672fcf5ef2aSThomas Huth } \
1673fcf5ef2aSThomas Huth } \
1674fcf5ef2aSThomas Huth \
1675cf3b0334SMark Cave-Ayland *xt = t; \
1676dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
1677fcf5ef2aSThomas Huth }
1678fcf5ef2aSThomas Huth
1679638f6d55SChinmay Rath VSX_MUL(XSMULDP, 1, float64, VsrD(0), 1, 0)
1680638f6d55SChinmay Rath VSX_MUL(XSMULSP, 1, float64, VsrD(0), 1, 1)
1681638f6d55SChinmay Rath VSX_MUL(XVMULDP, 2, float64, VsrD(i), 0, 0)
1682638f6d55SChinmay Rath VSX_MUL(XVMULSP, 4, float32, VsrW(i), 0, 0)
1683fcf5ef2aSThomas Huth
helper_xsmulqp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xt,ppc_vsr_t * xa,ppc_vsr_t * xb)168423d0766bSMark Cave-Ayland void helper_xsmulqp(CPUPPCState *env, uint32_t opcode,
168523d0766bSMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1686a811ec04SBharata B Rao {
1687cf3b0334SMark Cave-Ayland ppc_vsr_t t = *xt;
1688a8d411abSBharata B Rao float_status tstat;
1689a811ec04SBharata B Rao
1690a8d411abSBharata B Rao helper_reset_fpstatus(env);
1691a8d411abSBharata B Rao tstat = env->fp_status;
1692a811ec04SBharata B Rao if (unlikely(Rc(opcode) != 0)) {
1693a8d411abSBharata B Rao tstat.float_rounding_mode = float_round_to_odd;
1694a811ec04SBharata B Rao }
1695a811ec04SBharata B Rao
1696a811ec04SBharata B Rao set_float_exception_flags(0, &tstat);
1697cf3b0334SMark Cave-Ayland t.f128 = float128_mul(xa->f128, xb->f128, &tstat);
1698a811ec04SBharata B Rao env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1699a811ec04SBharata B Rao
1700a811ec04SBharata B Rao if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
17014edf5569SRichard Henderson float_invalid_op_mul(env, tstat.float_exception_flags, 1, GETPC());
1702a811ec04SBharata B Rao }
1703cf3b0334SMark Cave-Ayland helper_compute_fprf_float128(env, t.f128);
1704a811ec04SBharata B Rao
1705cf3b0334SMark Cave-Ayland *xt = t;
17063278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
1707a811ec04SBharata B Rao }
1708a811ec04SBharata B Rao
1709fa9ebf8cSDavid Gibson /*
1710fa9ebf8cSDavid Gibson * VSX_DIV - VSX floating point divide
1711fcf5ef2aSThomas Huth * op - instruction mnemonic
1712fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
1713fcf5ef2aSThomas Huth * tp - type (float32 or float64)
1714fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
1715dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
1716fcf5ef2aSThomas Huth */
1717dd657a35SVíctor Colombo #define VSX_DIV(op, nels, tp, fld, sfifprf, r2sp) \
171899125c74SMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
171999125c74SMark Cave-Ayland ppc_vsr_t *xa, ppc_vsr_t *xb) \
1720fcf5ef2aSThomas Huth { \
1721205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
1722fcf5ef2aSThomas Huth int i; \
1723fcf5ef2aSThomas Huth \
1724fcf5ef2aSThomas Huth helper_reset_fpstatus(env); \
1725fcf5ef2aSThomas Huth \
1726fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
1727fcf5ef2aSThomas Huth float_status tstat = env->fp_status; \
1728fcf5ef2aSThomas Huth set_float_exception_flags(0, &tstat); \
1729cf3b0334SMark Cave-Ayland t.fld = tp##_div(xa->fld, xb->fld, &tstat); \
1730fcf5ef2aSThomas Huth env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1731fcf5ef2aSThomas Huth \
1732fcf5ef2aSThomas Huth if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1733c07f8241SRichard Henderson float_invalid_op_div(env, tstat.float_exception_flags, \
1734dd657a35SVíctor Colombo sfifprf, GETPC()); \
1735fcf5ef2aSThomas Huth } \
1736ae13018dSRichard Henderson if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
1737ae13018dSRichard Henderson float_zero_divide_excp(env, GETPC()); \
1738ae13018dSRichard Henderson } \
1739fcf5ef2aSThomas Huth \
1740fcf5ef2aSThomas Huth if (r2sp) { \
17417238e55bSRichard Henderson t.fld = do_frsp(env, t.fld, GETPC()); \
1742fcf5ef2aSThomas Huth } \
1743fcf5ef2aSThomas Huth \
1744dd657a35SVíctor Colombo if (sfifprf) { \
1745cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.fld); \
1746fcf5ef2aSThomas Huth } \
1747fcf5ef2aSThomas Huth } \
1748fcf5ef2aSThomas Huth \
1749cf3b0334SMark Cave-Ayland *xt = t; \
1750dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
1751fcf5ef2aSThomas Huth }
1752fcf5ef2aSThomas Huth
1753638f6d55SChinmay Rath VSX_DIV(XSDIVDP, 1, float64, VsrD(0), 1, 0)
1754638f6d55SChinmay Rath VSX_DIV(XSDIVSP, 1, float64, VsrD(0), 1, 1)
1755638f6d55SChinmay Rath VSX_DIV(XVDIVDP, 2, float64, VsrD(i), 0, 0)
1756638f6d55SChinmay Rath VSX_DIV(XVDIVSP, 4, float32, VsrW(i), 0, 0)
1757fcf5ef2aSThomas Huth
helper_xsdivqp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xt,ppc_vsr_t * xa,ppc_vsr_t * xb)175823d0766bSMark Cave-Ayland void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
175923d0766bSMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1760314c1163SBharata B Rao {
1761cf3b0334SMark Cave-Ayland ppc_vsr_t t = *xt;
1762a8d411abSBharata B Rao float_status tstat;
1763314c1163SBharata B Rao
1764a8d411abSBharata B Rao helper_reset_fpstatus(env);
1765a8d411abSBharata B Rao tstat = env->fp_status;
1766314c1163SBharata B Rao if (unlikely(Rc(opcode) != 0)) {
1767a8d411abSBharata B Rao tstat.float_rounding_mode = float_round_to_odd;
1768314c1163SBharata B Rao }
1769314c1163SBharata B Rao
1770314c1163SBharata B Rao set_float_exception_flags(0, &tstat);
1771cf3b0334SMark Cave-Ayland t.f128 = float128_div(xa->f128, xb->f128, &tstat);
1772314c1163SBharata B Rao env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1773314c1163SBharata B Rao
1774314c1163SBharata B Rao if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1775c07f8241SRichard Henderson float_invalid_op_div(env, tstat.float_exception_flags, 1, GETPC());
1776314c1163SBharata B Rao }
1777ae13018dSRichard Henderson if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
1778ae13018dSRichard Henderson float_zero_divide_excp(env, GETPC());
1779ae13018dSRichard Henderson }
1780314c1163SBharata B Rao
1781cf3b0334SMark Cave-Ayland helper_compute_fprf_float128(env, t.f128);
1782cf3b0334SMark Cave-Ayland *xt = t;
17833278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
1784314c1163SBharata B Rao }
1785314c1163SBharata B Rao
1786fa9ebf8cSDavid Gibson /*
1787fa9ebf8cSDavid Gibson * VSX_RE - VSX floating point reciprocal estimate
1788fcf5ef2aSThomas Huth * op - instruction mnemonic
1789fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
1790fcf5ef2aSThomas Huth * tp - type (float32 or float64)
1791fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
1792dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
1793fcf5ef2aSThomas Huth */
1794dd657a35SVíctor Colombo #define VSX_RE(op, nels, tp, fld, sfifprf, r2sp) \
179575cf84cbSMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1796fcf5ef2aSThomas Huth { \
1797205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
1798fcf5ef2aSThomas Huth int i; \
1799fcf5ef2aSThomas Huth \
1800fcf5ef2aSThomas Huth helper_reset_fpstatus(env); \
1801fcf5ef2aSThomas Huth \
1802fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
1803cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
180413c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
1805fcf5ef2aSThomas Huth } \
1806cf3b0334SMark Cave-Ayland t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \
1807fcf5ef2aSThomas Huth \
1808fcf5ef2aSThomas Huth if (r2sp) { \
18097238e55bSRichard Henderson t.fld = do_frsp(env, t.fld, GETPC()); \
1810fcf5ef2aSThomas Huth } \
1811fcf5ef2aSThomas Huth \
1812dd657a35SVíctor Colombo if (sfifprf) { \
1813cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.fld); \
1814fcf5ef2aSThomas Huth } \
1815fcf5ef2aSThomas Huth } \
1816fcf5ef2aSThomas Huth \
1817cf3b0334SMark Cave-Ayland *xt = t; \
1818dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
1819fcf5ef2aSThomas Huth }
1820fcf5ef2aSThomas Huth
1821fcf5ef2aSThomas Huth VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
1822fcf5ef2aSThomas Huth VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
1823fcf5ef2aSThomas Huth VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
1824fcf5ef2aSThomas Huth VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
1825fcf5ef2aSThomas Huth
1826fa9ebf8cSDavid Gibson /*
1827fa9ebf8cSDavid Gibson * VSX_SQRT - VSX floating point square root
1828fcf5ef2aSThomas Huth * op - instruction mnemonic
1829fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
1830fcf5ef2aSThomas Huth * tp - type (float32 or float64)
1831fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
1832dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
1833fcf5ef2aSThomas Huth */
1834dd657a35SVíctor Colombo #define VSX_SQRT(op, nels, tp, fld, sfifprf, r2sp) \
183575cf84cbSMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1836fcf5ef2aSThomas Huth { \
1837205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
1838fcf5ef2aSThomas Huth int i; \
1839fcf5ef2aSThomas Huth \
1840fcf5ef2aSThomas Huth helper_reset_fpstatus(env); \
1841fcf5ef2aSThomas Huth \
1842fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
1843fcf5ef2aSThomas Huth float_status tstat = env->fp_status; \
1844fcf5ef2aSThomas Huth set_float_exception_flags(0, &tstat); \
1845cf3b0334SMark Cave-Ayland t.fld = tp##_sqrt(xb->fld, &tstat); \
1846fcf5ef2aSThomas Huth env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1847fcf5ef2aSThomas Huth \
1848fcf5ef2aSThomas Huth if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
18493d3050ccSRichard Henderson float_invalid_op_sqrt(env, tstat.float_exception_flags, \
1850dd657a35SVíctor Colombo sfifprf, GETPC()); \
1851fcf5ef2aSThomas Huth } \
1852fcf5ef2aSThomas Huth \
1853fcf5ef2aSThomas Huth if (r2sp) { \
18547238e55bSRichard Henderson t.fld = do_frsp(env, t.fld, GETPC()); \
1855fcf5ef2aSThomas Huth } \
1856fcf5ef2aSThomas Huth \
1857dd657a35SVíctor Colombo if (sfifprf) { \
1858cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.fld); \
1859fcf5ef2aSThomas Huth } \
1860fcf5ef2aSThomas Huth } \
1861fcf5ef2aSThomas Huth \
1862cf3b0334SMark Cave-Ayland *xt = t; \
1863dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
1864fcf5ef2aSThomas Huth }
1865fcf5ef2aSThomas Huth
1866fcf5ef2aSThomas Huth VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
1867fcf5ef2aSThomas Huth VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
1868fcf5ef2aSThomas Huth VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
1869fcf5ef2aSThomas Huth VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
1870fcf5ef2aSThomas Huth
1871fa9ebf8cSDavid Gibson /*
1872fa9ebf8cSDavid Gibson *VSX_RSQRTE - VSX floating point reciprocal square root estimate
1873fcf5ef2aSThomas Huth * op - instruction mnemonic
1874fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
1875fcf5ef2aSThomas Huth * tp - type (float32 or float64)
1876fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
1877dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
1878fcf5ef2aSThomas Huth */
1879dd657a35SVíctor Colombo #define VSX_RSQRTE(op, nels, tp, fld, sfifprf, r2sp) \
188075cf84cbSMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1881fcf5ef2aSThomas Huth { \
1882205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
1883fcf5ef2aSThomas Huth int i; \
1884fcf5ef2aSThomas Huth \
1885fcf5ef2aSThomas Huth helper_reset_fpstatus(env); \
1886fcf5ef2aSThomas Huth \
1887fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
1888fcf5ef2aSThomas Huth float_status tstat = env->fp_status; \
1889fcf5ef2aSThomas Huth set_float_exception_flags(0, &tstat); \
1890cf3b0334SMark Cave-Ayland t.fld = tp##_sqrt(xb->fld, &tstat); \
1891cf3b0334SMark Cave-Ayland t.fld = tp##_div(tp##_one, t.fld, &tstat); \
1892fcf5ef2aSThomas Huth env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1893fcf5ef2aSThomas Huth if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
18943d3050ccSRichard Henderson float_invalid_op_sqrt(env, tstat.float_exception_flags, \
1895dd657a35SVíctor Colombo sfifprf, GETPC()); \
1896fcf5ef2aSThomas Huth } \
1897fcf5ef2aSThomas Huth if (r2sp) { \
18987238e55bSRichard Henderson t.fld = do_frsp(env, t.fld, GETPC()); \
1899fcf5ef2aSThomas Huth } \
1900fcf5ef2aSThomas Huth \
1901dd657a35SVíctor Colombo if (sfifprf) { \
1902cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.fld); \
1903fcf5ef2aSThomas Huth } \
1904fcf5ef2aSThomas Huth } \
1905fcf5ef2aSThomas Huth \
1906cf3b0334SMark Cave-Ayland *xt = t; \
1907dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
1908fcf5ef2aSThomas Huth }
1909fcf5ef2aSThomas Huth
1910fcf5ef2aSThomas Huth VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
1911fcf5ef2aSThomas Huth VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
1912fcf5ef2aSThomas Huth VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
1913fcf5ef2aSThomas Huth VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
1914fcf5ef2aSThomas Huth
1915fa9ebf8cSDavid Gibson /*
1916fa9ebf8cSDavid Gibson * VSX_TDIV - VSX floating point test for divide
1917fcf5ef2aSThomas Huth * op - instruction mnemonic
1918fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
1919fcf5ef2aSThomas Huth * tp - type (float32 or float64)
1920fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
1921fcf5ef2aSThomas Huth * emin - minimum unbiased exponent
1922fcf5ef2aSThomas Huth * emax - maximum unbiased exponent
1923fcf5ef2aSThomas Huth * nbits - number of fraction bits
1924fcf5ef2aSThomas Huth */
1925fcf5ef2aSThomas Huth #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
1926033e1fcdSMark Cave-Ayland void helper_##op(CPUPPCState *env, uint32_t opcode, \
1927033e1fcdSMark Cave-Ayland ppc_vsr_t *xa, ppc_vsr_t *xb) \
1928fcf5ef2aSThomas Huth { \
1929fcf5ef2aSThomas Huth int i; \
1930fcf5ef2aSThomas Huth int fe_flag = 0; \
1931fcf5ef2aSThomas Huth int fg_flag = 0; \
1932fcf5ef2aSThomas Huth \
1933fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
1934cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_infinity(xa->fld) || \
1935cf3b0334SMark Cave-Ayland tp##_is_infinity(xb->fld) || \
1936cf3b0334SMark Cave-Ayland tp##_is_zero(xb->fld))) { \
1937fcf5ef2aSThomas Huth fe_flag = 1; \
1938fcf5ef2aSThomas Huth fg_flag = 1; \
1939fcf5ef2aSThomas Huth } else { \
1940cf3b0334SMark Cave-Ayland int e_a = ppc_##tp##_get_unbiased_exp(xa->fld); \
1941cf3b0334SMark Cave-Ayland int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
1942fcf5ef2aSThomas Huth \
1943cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_any_nan(xa->fld) || \
1944cf3b0334SMark Cave-Ayland tp##_is_any_nan(xb->fld))) { \
1945fcf5ef2aSThomas Huth fe_flag = 1; \
1946fcf5ef2aSThomas Huth } else if ((e_b <= emin) || (e_b >= (emax - 2))) { \
1947fcf5ef2aSThomas Huth fe_flag = 1; \
1948cf3b0334SMark Cave-Ayland } else if (!tp##_is_zero(xa->fld) && \
1949fcf5ef2aSThomas Huth (((e_a - e_b) >= emax) || \
1950fcf5ef2aSThomas Huth ((e_a - e_b) <= (emin + 1)) || \
1951fcf5ef2aSThomas Huth (e_a <= (emin + nbits)))) { \
1952fcf5ef2aSThomas Huth fe_flag = 1; \
1953fcf5ef2aSThomas Huth } \
1954fcf5ef2aSThomas Huth \
1955cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
1956fa9ebf8cSDavid Gibson /* \
1957fa9ebf8cSDavid Gibson * XB is not zero because of the above check and so \
1958fa9ebf8cSDavid Gibson * must be denormalized. \
1959fa9ebf8cSDavid Gibson */ \
1960fcf5ef2aSThomas Huth fg_flag = 1; \
1961fcf5ef2aSThomas Huth } \
1962fcf5ef2aSThomas Huth } \
1963fcf5ef2aSThomas Huth } \
1964fcf5ef2aSThomas Huth \
1965fcf5ef2aSThomas Huth env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
1966fcf5ef2aSThomas Huth }
1967fcf5ef2aSThomas Huth
1968fcf5ef2aSThomas Huth VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
1969fcf5ef2aSThomas Huth VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
1970fcf5ef2aSThomas Huth VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
1971fcf5ef2aSThomas Huth
1972fa9ebf8cSDavid Gibson /*
1973fa9ebf8cSDavid Gibson * VSX_TSQRT - VSX floating point test for square root
1974fcf5ef2aSThomas Huth * op - instruction mnemonic
1975fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
1976fcf5ef2aSThomas Huth * tp - type (float32 or float64)
1977fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
1978fcf5ef2aSThomas Huth * emin - minimum unbiased exponent
1979fcf5ef2aSThomas Huth * emax - maximum unbiased exponent
1980fcf5ef2aSThomas Huth * nbits - number of fraction bits
1981fcf5ef2aSThomas Huth */
1982fcf5ef2aSThomas Huth #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
19838d830485SMark Cave-Ayland void helper_##op(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) \
1984fcf5ef2aSThomas Huth { \
1985fcf5ef2aSThomas Huth int i; \
1986fcf5ef2aSThomas Huth int fe_flag = 0; \
1987fcf5ef2aSThomas Huth int fg_flag = 0; \
1988fcf5ef2aSThomas Huth \
1989fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
1990cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_infinity(xb->fld) || \
1991cf3b0334SMark Cave-Ayland tp##_is_zero(xb->fld))) { \
1992fcf5ef2aSThomas Huth fe_flag = 1; \
1993fcf5ef2aSThomas Huth fg_flag = 1; \
1994fcf5ef2aSThomas Huth } else { \
1995cf3b0334SMark Cave-Ayland int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
1996fcf5ef2aSThomas Huth \
1997cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_any_nan(xb->fld))) { \
1998fcf5ef2aSThomas Huth fe_flag = 1; \
1999cf3b0334SMark Cave-Ayland } else if (unlikely(tp##_is_zero(xb->fld))) { \
2000fcf5ef2aSThomas Huth fe_flag = 1; \
2001cf3b0334SMark Cave-Ayland } else if (unlikely(tp##_is_neg(xb->fld))) { \
2002fcf5ef2aSThomas Huth fe_flag = 1; \
2003cf3b0334SMark Cave-Ayland } else if (!tp##_is_zero(xb->fld) && \
2004fcf5ef2aSThomas Huth (e_b <= (emin + nbits))) { \
2005fcf5ef2aSThomas Huth fe_flag = 1; \
2006fcf5ef2aSThomas Huth } \
2007fcf5ef2aSThomas Huth \
2008cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
2009fa9ebf8cSDavid Gibson /* \
2010fa9ebf8cSDavid Gibson * XB is not zero because of the above check and \
2011fa9ebf8cSDavid Gibson * therefore must be denormalized. \
2012fa9ebf8cSDavid Gibson */ \
2013fcf5ef2aSThomas Huth fg_flag = 1; \
2014fcf5ef2aSThomas Huth } \
2015fcf5ef2aSThomas Huth } \
2016fcf5ef2aSThomas Huth } \
2017fcf5ef2aSThomas Huth \
2018fcf5ef2aSThomas Huth env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2019fcf5ef2aSThomas Huth }
2020fcf5ef2aSThomas Huth
2021fcf5ef2aSThomas Huth VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2022fcf5ef2aSThomas Huth VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2023fcf5ef2aSThomas Huth VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2024fcf5ef2aSThomas Huth
2025fa9ebf8cSDavid Gibson /*
2026fa9ebf8cSDavid Gibson * VSX_MADD - VSX floating point muliply/add variations
2027fcf5ef2aSThomas Huth * op - instruction mnemonic
2028fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
2029fcf5ef2aSThomas Huth * tp - type (float32 or float64)
2030fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
2031fcf5ef2aSThomas Huth * maddflgs - flags for the float*muladd routine that control the
2032fcf5ef2aSThomas Huth * various forms (madd, msub, nmadd, nmsub)
2033dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
2034fcf5ef2aSThomas Huth */
2035dd657a35SVíctor Colombo #define VSX_MADD(op, nels, tp, fld, maddflgs, sfifprf) \
203699125c74SMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2037e4318ab2SMatheus Ferst ppc_vsr_t *s1, ppc_vsr_t *s2, ppc_vsr_t *s3) \
2038fcf5ef2aSThomas Huth { \
20399f097daaSVíctor Colombo ppc_vsr_t t = { }; \
2040fcf5ef2aSThomas Huth int i; \
2041fcf5ef2aSThomas Huth \
2042fcf5ef2aSThomas Huth helper_reset_fpstatus(env); \
2043fcf5ef2aSThomas Huth \
2044fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
2045fcf5ef2aSThomas Huth float_status tstat = env->fp_status; \
2046fcf5ef2aSThomas Huth set_float_exception_flags(0, &tstat); \
20474e4b5a3eSMatheus Ferst t.fld = tp##_muladd(s1->fld, s3->fld, s2->fld, maddflgs, &tstat); \
2048fcf5ef2aSThomas Huth env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2049fcf5ef2aSThomas Huth \
2050fcf5ef2aSThomas Huth if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2051e4052bb7SRichard Henderson float_invalid_op_madd(env, tstat.float_exception_flags, \
2052dd657a35SVíctor Colombo sfifprf, GETPC()); \
2053fcf5ef2aSThomas Huth } \
2054fcf5ef2aSThomas Huth \
2055dd657a35SVíctor Colombo if (sfifprf) { \
2056cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.fld); \
2057fcf5ef2aSThomas Huth } \
2058fcf5ef2aSThomas Huth } \
2059cf3b0334SMark Cave-Ayland *xt = t; \
2060dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
2061fcf5ef2aSThomas Huth }
2062fcf5ef2aSThomas Huth
20634e4b5a3eSMatheus Ferst VSX_MADD(XSMADDDP, 1, float64, VsrD(0), MADD_FLGS, 1)
20644e4b5a3eSMatheus Ferst VSX_MADD(XSMSUBDP, 1, float64, VsrD(0), MSUB_FLGS, 1)
20654e4b5a3eSMatheus Ferst VSX_MADD(XSNMADDDP, 1, float64, VsrD(0), NMADD_FLGS, 1)
20664e4b5a3eSMatheus Ferst VSX_MADD(XSNMSUBDP, 1, float64, VsrD(0), NMSUB_FLGS, 1)
20674e4b5a3eSMatheus Ferst VSX_MADD(XSMADDSP, 1, float64r32, VsrD(0), MADD_FLGS, 1)
20684e4b5a3eSMatheus Ferst VSX_MADD(XSMSUBSP, 1, float64r32, VsrD(0), MSUB_FLGS, 1)
20694e4b5a3eSMatheus Ferst VSX_MADD(XSNMADDSP, 1, float64r32, VsrD(0), NMADD_FLGS, 1)
20704e4b5a3eSMatheus Ferst VSX_MADD(XSNMSUBSP, 1, float64r32, VsrD(0), NMSUB_FLGS, 1)
2071fcf5ef2aSThomas Huth
20724e4b5a3eSMatheus Ferst VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0)
20734e4b5a3eSMatheus Ferst VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0)
20744e4b5a3eSMatheus Ferst VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0)
20754e4b5a3eSMatheus Ferst VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0)
2076fcf5ef2aSThomas Huth
20774e4b5a3eSMatheus Ferst VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0)
20784e4b5a3eSMatheus Ferst VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0)
20794e4b5a3eSMatheus Ferst VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0)
20804e4b5a3eSMatheus Ferst VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0)
2081fcf5ef2aSThomas Huth
2082fa9ebf8cSDavid Gibson /*
20833bb1aed2SMatheus Ferst * VSX_MADDQ - VSX floating point quad-precision muliply/add
20843bb1aed2SMatheus Ferst * op - instruction mnemonic
20853bb1aed2SMatheus Ferst * maddflgs - flags for the float*muladd routine that control the
20863bb1aed2SMatheus Ferst * various forms (madd, msub, nmadd, nmsub)
20873bb1aed2SMatheus Ferst * ro - round to odd
20883bb1aed2SMatheus Ferst */
20893bb1aed2SMatheus Ferst #define VSX_MADDQ(op, maddflgs, ro) \
20903bb1aed2SMatheus Ferst void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *s1, ppc_vsr_t *s2,\
20913bb1aed2SMatheus Ferst ppc_vsr_t *s3) \
20923bb1aed2SMatheus Ferst { \
20933bb1aed2SMatheus Ferst ppc_vsr_t t = *xt; \
20943bb1aed2SMatheus Ferst \
20953bb1aed2SMatheus Ferst helper_reset_fpstatus(env); \
20963bb1aed2SMatheus Ferst \
20973bb1aed2SMatheus Ferst float_status tstat = env->fp_status; \
20983bb1aed2SMatheus Ferst set_float_exception_flags(0, &tstat); \
20993bb1aed2SMatheus Ferst if (ro) { \
21003bb1aed2SMatheus Ferst tstat.float_rounding_mode = float_round_to_odd; \
21013bb1aed2SMatheus Ferst } \
21023bb1aed2SMatheus Ferst t.f128 = float128_muladd(s1->f128, s3->f128, s2->f128, maddflgs, &tstat); \
21033bb1aed2SMatheus Ferst env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
21043bb1aed2SMatheus Ferst \
21053bb1aed2SMatheus Ferst if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
21063bb1aed2SMatheus Ferst float_invalid_op_madd(env, tstat.float_exception_flags, \
21073bb1aed2SMatheus Ferst false, GETPC()); \
21083bb1aed2SMatheus Ferst } \
21093bb1aed2SMatheus Ferst \
21103bb1aed2SMatheus Ferst helper_compute_fprf_float128(env, t.f128); \
21113bb1aed2SMatheus Ferst *xt = t; \
21123278677fSVíctor Colombo do_float_check_status(env, true, GETPC()); \
21133bb1aed2SMatheus Ferst }
21143bb1aed2SMatheus Ferst
21153bb1aed2SMatheus Ferst VSX_MADDQ(XSMADDQP, MADD_FLGS, 0)
21163bb1aed2SMatheus Ferst VSX_MADDQ(XSMADDQPO, MADD_FLGS, 1)
21173bb1aed2SMatheus Ferst VSX_MADDQ(XSMSUBQP, MSUB_FLGS, 0)
21183bb1aed2SMatheus Ferst VSX_MADDQ(XSMSUBQPO, MSUB_FLGS, 1)
21193bb1aed2SMatheus Ferst VSX_MADDQ(XSNMADDQP, NMADD_FLGS, 0)
21203bb1aed2SMatheus Ferst VSX_MADDQ(XSNMADDQPO, NMADD_FLGS, 1)
21213bb1aed2SMatheus Ferst VSX_MADDQ(XSNMSUBQP, NMSUB_FLGS, 0)
21223bb1aed2SMatheus Ferst VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
21233bb1aed2SMatheus Ferst
21243bb1aed2SMatheus Ferst /*
21254439586aSVíctor Colombo * VSX_SCALAR_CMP - VSX scalar floating point compare
2126fcf5ef2aSThomas Huth * op - instruction mnemonic
21274439586aSVíctor Colombo * tp - type
2128fcf5ef2aSThomas Huth * cmp - comparison operation
21294439586aSVíctor Colombo * fld - vsr_t field
2130fcf5ef2aSThomas Huth * svxvc - set VXVC bit
2131fcf5ef2aSThomas Huth */
21324439586aSVíctor Colombo #define VSX_SCALAR_CMP(op, tp, cmp, fld, svxvc) \
213399125c74SMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
213499125c74SMark Cave-Ayland ppc_vsr_t *xa, ppc_vsr_t *xb) \
2135fcf5ef2aSThomas Huth { \
21364439586aSVíctor Colombo int flags; \
21374439586aSVíctor Colombo bool r, vxvc; \
2138fcf5ef2aSThomas Huth \
21394439586aSVíctor Colombo helper_reset_fpstatus(env); \
21404439586aSVíctor Colombo \
21414439586aSVíctor Colombo if (svxvc) { \
21424439586aSVíctor Colombo r = tp##_##cmp(xb->fld, xa->fld, &env->fp_status); \
21434439586aSVíctor Colombo } else { \
21444439586aSVíctor Colombo r = tp##_##cmp##_quiet(xb->fld, xa->fld, &env->fp_status); \
2145fcf5ef2aSThomas Huth } \
21464439586aSVíctor Colombo \
21474439586aSVíctor Colombo flags = get_float_exception_flags(&env->fp_status); \
21484439586aSVíctor Colombo if (unlikely(flags & float_flag_invalid)) { \
21494439586aSVíctor Colombo vxvc = svxvc; \
21504439586aSVíctor Colombo if (flags & float_flag_invalid_snan) { \
215113c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
2152208d8033SVíctor Colombo vxvc &= !(env->fpscr & FP_VE); \
2153fcf5ef2aSThomas Huth } \
21544439586aSVíctor Colombo if (vxvc) { \
215513c9115fSRichard Henderson float_invalid_op_vxvc(env, 0, GETPC()); \
2156fcf5ef2aSThomas Huth } \
21574439586aSVíctor Colombo } \
2158fcf5ef2aSThomas Huth \
21594439586aSVíctor Colombo memset(xt, 0, sizeof(*xt)); \
21604439586aSVíctor Colombo memset(&xt->fld, -r, sizeof(xt->fld)); \
21613278677fSVíctor Colombo do_float_check_status(env, false, GETPC()); \
2162fcf5ef2aSThomas Huth }
2163fcf5ef2aSThomas Huth
216472d24354SVíctor Colombo VSX_SCALAR_CMP(XSCMPEQDP, float64, eq, VsrD(0), 0)
216572d24354SVíctor Colombo VSX_SCALAR_CMP(XSCMPGEDP, float64, le, VsrD(0), 1)
216672d24354SVíctor Colombo VSX_SCALAR_CMP(XSCMPGTDP, float64, lt, VsrD(0), 1)
2167568e7c4dSVíctor Colombo VSX_SCALAR_CMP(XSCMPEQQP, float128, eq, f128, 0)
2168568e7c4dSVíctor Colombo VSX_SCALAR_CMP(XSCMPGEQP, float128, le, f128, 1)
2169568e7c4dSVíctor Colombo VSX_SCALAR_CMP(XSCMPGTQP, float128, lt, f128, 1)
2170fcf5ef2aSThomas Huth
helper_xscmpexpdp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xa,ppc_vsr_t * xb)2171033e1fcdSMark Cave-Ayland void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
2172033e1fcdSMark Cave-Ayland ppc_vsr_t *xa, ppc_vsr_t *xb)
21733a20d11dSBharata B Rao {
21743a20d11dSBharata B Rao int64_t exp_a, exp_b;
21753a20d11dSBharata B Rao uint32_t cc;
21763a20d11dSBharata B Rao
2177cf3b0334SMark Cave-Ayland exp_a = extract64(xa->VsrD(0), 52, 11);
2178cf3b0334SMark Cave-Ayland exp_b = extract64(xb->VsrD(0), 52, 11);
21793a20d11dSBharata B Rao
2180cf3b0334SMark Cave-Ayland if (unlikely(float64_is_any_nan(xa->VsrD(0)) ||
2181cf3b0334SMark Cave-Ayland float64_is_any_nan(xb->VsrD(0)))) {
21823a20d11dSBharata B Rao cc = CRF_SO;
21833a20d11dSBharata B Rao } else {
21843a20d11dSBharata B Rao if (exp_a < exp_b) {
21853a20d11dSBharata B Rao cc = CRF_LT;
21863a20d11dSBharata B Rao } else if (exp_a > exp_b) {
21873a20d11dSBharata B Rao cc = CRF_GT;
21883a20d11dSBharata B Rao } else {
21893a20d11dSBharata B Rao cc = CRF_EQ;
21903a20d11dSBharata B Rao }
21913a20d11dSBharata B Rao }
21923a20d11dSBharata B Rao
21935c94dd38SPaul A. Clarke env->fpscr &= ~FP_FPCC;
21945c94dd38SPaul A. Clarke env->fpscr |= cc << FPSCR_FPCC;
21953a20d11dSBharata B Rao env->crf[BF(opcode)] = cc;
21963a20d11dSBharata B Rao
21973278677fSVíctor Colombo do_float_check_status(env, false, GETPC());
21983a20d11dSBharata B Rao }
21993a20d11dSBharata B Rao
helper_xscmpexpqp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xa,ppc_vsr_t * xb)22006ae4a57aSMark Cave-Ayland void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode,
22016ae4a57aSMark Cave-Ayland ppc_vsr_t *xa, ppc_vsr_t *xb)
22023a20d11dSBharata B Rao {
22033a20d11dSBharata B Rao int64_t exp_a, exp_b;
22043a20d11dSBharata B Rao uint32_t cc;
22053a20d11dSBharata B Rao
2206cf3b0334SMark Cave-Ayland exp_a = extract64(xa->VsrD(0), 48, 15);
2207cf3b0334SMark Cave-Ayland exp_b = extract64(xb->VsrD(0), 48, 15);
22083a20d11dSBharata B Rao
2209cf3b0334SMark Cave-Ayland if (unlikely(float128_is_any_nan(xa->f128) ||
2210cf3b0334SMark Cave-Ayland float128_is_any_nan(xb->f128))) {
22113a20d11dSBharata B Rao cc = CRF_SO;
22123a20d11dSBharata B Rao } else {
22133a20d11dSBharata B Rao if (exp_a < exp_b) {
22143a20d11dSBharata B Rao cc = CRF_LT;
22153a20d11dSBharata B Rao } else if (exp_a > exp_b) {
22163a20d11dSBharata B Rao cc = CRF_GT;
22173a20d11dSBharata B Rao } else {
22183a20d11dSBharata B Rao cc = CRF_EQ;
22193a20d11dSBharata B Rao }
22203a20d11dSBharata B Rao }
22213a20d11dSBharata B Rao
22225c94dd38SPaul A. Clarke env->fpscr &= ~FP_FPCC;
22235c94dd38SPaul A. Clarke env->fpscr |= cc << FPSCR_FPCC;
22243a20d11dSBharata B Rao env->crf[BF(opcode)] = cc;
22253a20d11dSBharata B Rao
22263278677fSVíctor Colombo do_float_check_status(env, false, GETPC());
22273a20d11dSBharata B Rao }
22283a20d11dSBharata B Rao
do_scalar_cmp(CPUPPCState * env,ppc_vsr_t * xa,ppc_vsr_t * xb,int crf_idx,bool ordered)2229132954a8SGiuseppe Musacchio static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb,
2230132954a8SGiuseppe Musacchio int crf_idx, bool ordered)
2231132954a8SGiuseppe Musacchio {
2232132954a8SGiuseppe Musacchio uint32_t cc;
2233132954a8SGiuseppe Musacchio bool vxsnan_flag = false, vxvc_flag = false;
2234132954a8SGiuseppe Musacchio
2235132954a8SGiuseppe Musacchio helper_reset_fpstatus(env);
2236132954a8SGiuseppe Musacchio
2237132954a8SGiuseppe Musacchio switch (float64_compare(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) {
2238132954a8SGiuseppe Musacchio case float_relation_less:
2239132954a8SGiuseppe Musacchio cc = CRF_LT;
2240132954a8SGiuseppe Musacchio break;
2241132954a8SGiuseppe Musacchio case float_relation_equal:
2242132954a8SGiuseppe Musacchio cc = CRF_EQ;
2243132954a8SGiuseppe Musacchio break;
2244132954a8SGiuseppe Musacchio case float_relation_greater:
2245132954a8SGiuseppe Musacchio cc = CRF_GT;
2246132954a8SGiuseppe Musacchio break;
2247132954a8SGiuseppe Musacchio case float_relation_unordered:
2248132954a8SGiuseppe Musacchio cc = CRF_SO;
2249bc92c260SGiuseppe Musacchio
2250bc92c260SGiuseppe Musacchio if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||
2251bc92c260SGiuseppe Musacchio float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {
2252bc92c260SGiuseppe Musacchio vxsnan_flag = true;
2253208d8033SVíctor Colombo if (!(env->fpscr & FP_VE) && ordered) {
2254bc92c260SGiuseppe Musacchio vxvc_flag = true;
2255bc92c260SGiuseppe Musacchio }
2256bc92c260SGiuseppe Musacchio } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) ||
2257bc92c260SGiuseppe Musacchio float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) {
2258bc92c260SGiuseppe Musacchio if (ordered) {
2259bc92c260SGiuseppe Musacchio vxvc_flag = true;
2260bc92c260SGiuseppe Musacchio }
2261bc92c260SGiuseppe Musacchio }
2262bc92c260SGiuseppe Musacchio
2263132954a8SGiuseppe Musacchio break;
2264132954a8SGiuseppe Musacchio default:
2265132954a8SGiuseppe Musacchio g_assert_not_reached();
2266be0a4fafSBharata B Rao }
2267be0a4fafSBharata B Rao
2268132954a8SGiuseppe Musacchio env->fpscr &= ~FP_FPCC;
2269132954a8SGiuseppe Musacchio env->fpscr |= cc << FPSCR_FPCC;
2270132954a8SGiuseppe Musacchio env->crf[crf_idx] = cc;
2271132954a8SGiuseppe Musacchio
227291699dbfSGiuseppe Musacchio if (vxsnan_flag) {
227391699dbfSGiuseppe Musacchio float_invalid_op_vxsnan(env, GETPC());
227491699dbfSGiuseppe Musacchio }
227591699dbfSGiuseppe Musacchio if (vxvc_flag) {
227691699dbfSGiuseppe Musacchio float_invalid_op_vxvc(env, 0, GETPC());
227791699dbfSGiuseppe Musacchio }
227891699dbfSGiuseppe Musacchio
22793278677fSVíctor Colombo do_float_check_status(env, false, GETPC());
2280132954a8SGiuseppe Musacchio }
2281132954a8SGiuseppe Musacchio
helper_xscmpodp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xa,ppc_vsr_t * xb)2282132954a8SGiuseppe Musacchio void helper_xscmpodp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2283132954a8SGiuseppe Musacchio ppc_vsr_t *xb)
2284132954a8SGiuseppe Musacchio {
2285132954a8SGiuseppe Musacchio do_scalar_cmp(env, xa, xb, BF(opcode), true);
2286132954a8SGiuseppe Musacchio }
2287132954a8SGiuseppe Musacchio
helper_xscmpudp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xa,ppc_vsr_t * xb)2288132954a8SGiuseppe Musacchio void helper_xscmpudp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2289132954a8SGiuseppe Musacchio ppc_vsr_t *xb)
2290132954a8SGiuseppe Musacchio {
2291132954a8SGiuseppe Musacchio do_scalar_cmp(env, xa, xb, BF(opcode), false);
2292132954a8SGiuseppe Musacchio }
2293132954a8SGiuseppe Musacchio
do_scalar_cmpq(CPUPPCState * env,ppc_vsr_t * xa,ppc_vsr_t * xb,int crf_idx,bool ordered)2294132954a8SGiuseppe Musacchio static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa,
2295132954a8SGiuseppe Musacchio ppc_vsr_t *xb, int crf_idx, bool ordered)
2296132954a8SGiuseppe Musacchio {
2297132954a8SGiuseppe Musacchio uint32_t cc;
2298132954a8SGiuseppe Musacchio bool vxsnan_flag = false, vxvc_flag = false;
2299132954a8SGiuseppe Musacchio
2300132954a8SGiuseppe Musacchio helper_reset_fpstatus(env);
2301132954a8SGiuseppe Musacchio
2302132954a8SGiuseppe Musacchio switch (float128_compare(xa->f128, xb->f128, &env->fp_status)) {
2303132954a8SGiuseppe Musacchio case float_relation_less:
2304132954a8SGiuseppe Musacchio cc = CRF_LT;
2305132954a8SGiuseppe Musacchio break;
2306132954a8SGiuseppe Musacchio case float_relation_equal:
2307132954a8SGiuseppe Musacchio cc = CRF_EQ;
2308132954a8SGiuseppe Musacchio break;
2309132954a8SGiuseppe Musacchio case float_relation_greater:
2310132954a8SGiuseppe Musacchio cc = CRF_GT;
2311132954a8SGiuseppe Musacchio break;
2312132954a8SGiuseppe Musacchio case float_relation_unordered:
2313132954a8SGiuseppe Musacchio cc = CRF_SO;
2314bc92c260SGiuseppe Musacchio
2315bc92c260SGiuseppe Musacchio if (float128_is_signaling_nan(xa->f128, &env->fp_status) ||
2316bc92c260SGiuseppe Musacchio float128_is_signaling_nan(xb->f128, &env->fp_status)) {
2317bc92c260SGiuseppe Musacchio vxsnan_flag = true;
2318208d8033SVíctor Colombo if (!(env->fpscr & FP_VE) && ordered) {
2319bc92c260SGiuseppe Musacchio vxvc_flag = true;
2320bc92c260SGiuseppe Musacchio }
2321bc92c260SGiuseppe Musacchio } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) ||
2322bc92c260SGiuseppe Musacchio float128_is_quiet_nan(xb->f128, &env->fp_status)) {
2323bc92c260SGiuseppe Musacchio if (ordered) {
2324bc92c260SGiuseppe Musacchio vxvc_flag = true;
2325bc92c260SGiuseppe Musacchio }
2326bc92c260SGiuseppe Musacchio }
2327bc92c260SGiuseppe Musacchio
2328132954a8SGiuseppe Musacchio break;
2329132954a8SGiuseppe Musacchio default:
2330132954a8SGiuseppe Musacchio g_assert_not_reached();
2331132954a8SGiuseppe Musacchio }
2332132954a8SGiuseppe Musacchio
2333132954a8SGiuseppe Musacchio env->fpscr &= ~FP_FPCC;
2334132954a8SGiuseppe Musacchio env->fpscr |= cc << FPSCR_FPCC;
2335132954a8SGiuseppe Musacchio env->crf[crf_idx] = cc;
2336132954a8SGiuseppe Musacchio
233791699dbfSGiuseppe Musacchio if (vxsnan_flag) {
233891699dbfSGiuseppe Musacchio float_invalid_op_vxsnan(env, GETPC());
233991699dbfSGiuseppe Musacchio }
234091699dbfSGiuseppe Musacchio if (vxvc_flag) {
234191699dbfSGiuseppe Musacchio float_invalid_op_vxvc(env, 0, GETPC());
234291699dbfSGiuseppe Musacchio }
234391699dbfSGiuseppe Musacchio
23443278677fSVíctor Colombo do_float_check_status(env, false, GETPC());
2345132954a8SGiuseppe Musacchio }
2346132954a8SGiuseppe Musacchio
helper_xscmpoqp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xa,ppc_vsr_t * xb)2347132954a8SGiuseppe Musacchio void helper_xscmpoqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2348132954a8SGiuseppe Musacchio ppc_vsr_t *xb)
2349132954a8SGiuseppe Musacchio {
2350132954a8SGiuseppe Musacchio do_scalar_cmpq(env, xa, xb, BF(opcode), true);
2351132954a8SGiuseppe Musacchio }
2352132954a8SGiuseppe Musacchio
helper_xscmpuqp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xa,ppc_vsr_t * xb)2353132954a8SGiuseppe Musacchio void helper_xscmpuqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2354132954a8SGiuseppe Musacchio ppc_vsr_t *xb)
2355132954a8SGiuseppe Musacchio {
2356132954a8SGiuseppe Musacchio do_scalar_cmpq(env, xa, xb, BF(opcode), false);
2357132954a8SGiuseppe Musacchio }
2358be0a4fafSBharata B Rao
2359fa9ebf8cSDavid Gibson /*
2360fa9ebf8cSDavid Gibson * VSX_MAX_MIN - VSX floating point maximum/minimum
2361fcf5ef2aSThomas Huth * name - instruction mnemonic
2362fcf5ef2aSThomas Huth * op - operation (max or min)
2363fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
2364fcf5ef2aSThomas Huth * tp - type (float32 or float64)
2365fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
2366fcf5ef2aSThomas Huth */
2367fcf5ef2aSThomas Huth #define VSX_MAX_MIN(name, op, nels, tp, fld) \
236899125c74SMark Cave-Ayland void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
236999125c74SMark Cave-Ayland ppc_vsr_t *xa, ppc_vsr_t *xb) \
2370fcf5ef2aSThomas Huth { \
2371205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
2372fcf5ef2aSThomas Huth int i; \
2373fcf5ef2aSThomas Huth \
2374fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
2375cf3b0334SMark Cave-Ayland t.fld = tp##_##op(xa->fld, xb->fld, &env->fp_status); \
2376cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2377cf3b0334SMark Cave-Ayland tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
237813c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
2379fcf5ef2aSThomas Huth } \
2380fcf5ef2aSThomas Huth } \
2381fcf5ef2aSThomas Huth \
2382cf3b0334SMark Cave-Ayland *xt = t; \
23833278677fSVíctor Colombo do_float_check_status(env, false, GETPC()); \
2384fcf5ef2aSThomas Huth }
2385fcf5ef2aSThomas Huth
2386638f6d55SChinmay Rath VSX_MAX_MIN(XSMAXDP, maxnum, 1, float64, VsrD(0))
2387638f6d55SChinmay Rath VSX_MAX_MIN(XVMAXDP, maxnum, 2, float64, VsrD(i))
2388638f6d55SChinmay Rath VSX_MAX_MIN(XVMAXSP, maxnum, 4, float32, VsrW(i))
2389638f6d55SChinmay Rath VSX_MAX_MIN(XSMINDP, minnum, 1, float64, VsrD(0))
2390638f6d55SChinmay Rath VSX_MAX_MIN(XVMINDP, minnum, 2, float64, VsrD(i))
2391638f6d55SChinmay Rath VSX_MAX_MIN(XVMINSP, minnum, 4, float32, VsrW(i))
2392fcf5ef2aSThomas Huth
2393da499405SVíctor Colombo #define VSX_MAX_MINC(name, max, tp, fld) \
2394201fc774SVictor Colombo void helper_##name(CPUPPCState *env, \
239523d0766bSMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
23962770deedSBharata B Rao { \
2397205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
2398da499405SVíctor Colombo bool first; \
23992770deedSBharata B Rao \
2400e1428e5bSVíctor Colombo helper_reset_fpstatus(env); \
2401e1428e5bSVíctor Colombo \
2402da499405SVíctor Colombo if (max) { \
2403da499405SVíctor Colombo first = tp##_le_quiet(xb->fld, xa->fld, &env->fp_status); \
24042770deedSBharata B Rao } else { \
2405da499405SVíctor Colombo first = tp##_lt_quiet(xa->fld, xb->fld, &env->fp_status); \
24062770deedSBharata B Rao } \
24072770deedSBharata B Rao \
2408da499405SVíctor Colombo if (first) { \
2409da499405SVíctor Colombo t.fld = xa->fld; \
2410da499405SVíctor Colombo } else { \
2411da499405SVíctor Colombo t.fld = xb->fld; \
2412da499405SVíctor Colombo if (env->fp_status.float_exception_flags & float_flag_invalid_snan) { \
241313c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
24142770deedSBharata B Rao } \
2415da499405SVíctor Colombo } \
2416da499405SVíctor Colombo \
2417cf3b0334SMark Cave-Ayland *xt = t; \
2418da499405SVíctor Colombo }
24192770deedSBharata B Rao
2420da499405SVíctor Colombo VSX_MAX_MINC(XSMAXCDP, true, float64, VsrD(0));
2421da499405SVíctor Colombo VSX_MAX_MINC(XSMINCDP, false, float64, VsrD(0));
24227b8d6e3eSVíctor Colombo VSX_MAX_MINC(XSMAXCQP, true, float128, f128);
24237b8d6e3eSVíctor Colombo VSX_MAX_MINC(XSMINCQP, false, float128, f128);
24242770deedSBharata B Rao
2425d4ccd87eSBharata B Rao #define VSX_MAX_MINJ(name, max) \
2426201fc774SVictor Colombo void helper_##name(CPUPPCState *env, \
242723d0766bSMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2428d4ccd87eSBharata B Rao { \
2429205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
2430d4ccd87eSBharata B Rao bool vxsnan_flag = false, vex_flag = false; \
2431d4ccd87eSBharata B Rao \
2432cf3b0334SMark Cave-Ayland if (unlikely(float64_is_any_nan(xa->VsrD(0)))) { \
2433cf3b0334SMark Cave-Ayland if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status)) { \
2434d4ccd87eSBharata B Rao vxsnan_flag = true; \
2435d4ccd87eSBharata B Rao } \
2436cf3b0334SMark Cave-Ayland t.VsrD(0) = xa->VsrD(0); \
2437cf3b0334SMark Cave-Ayland } else if (unlikely(float64_is_any_nan(xb->VsrD(0)))) { \
2438cf3b0334SMark Cave-Ayland if (float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2439d4ccd87eSBharata B Rao vxsnan_flag = true; \
2440d4ccd87eSBharata B Rao } \
2441cf3b0334SMark Cave-Ayland t.VsrD(0) = xb->VsrD(0); \
2442cf3b0334SMark Cave-Ayland } else if (float64_is_zero(xa->VsrD(0)) && \
2443cf3b0334SMark Cave-Ayland float64_is_zero(xb->VsrD(0))) { \
2444d4ccd87eSBharata B Rao if (max) { \
2445cf3b0334SMark Cave-Ayland if (!float64_is_neg(xa->VsrD(0)) || \
2446cf3b0334SMark Cave-Ayland !float64_is_neg(xb->VsrD(0))) { \
2447cf3b0334SMark Cave-Ayland t.VsrD(0) = 0ULL; \
2448d4ccd87eSBharata B Rao } else { \
2449cf3b0334SMark Cave-Ayland t.VsrD(0) = 0x8000000000000000ULL; \
2450d4ccd87eSBharata B Rao } \
2451d4ccd87eSBharata B Rao } else { \
2452cf3b0334SMark Cave-Ayland if (float64_is_neg(xa->VsrD(0)) || \
2453cf3b0334SMark Cave-Ayland float64_is_neg(xb->VsrD(0))) { \
2454cf3b0334SMark Cave-Ayland t.VsrD(0) = 0x8000000000000000ULL; \
2455d4ccd87eSBharata B Rao } else { \
2456cf3b0334SMark Cave-Ayland t.VsrD(0) = 0ULL; \
2457d4ccd87eSBharata B Rao } \
2458d4ccd87eSBharata B Rao } \
2459d4ccd87eSBharata B Rao } else if ((max && \
2460cf3b0334SMark Cave-Ayland !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2461d4ccd87eSBharata B Rao (!max && \
2462cf3b0334SMark Cave-Ayland float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2463cf3b0334SMark Cave-Ayland t.VsrD(0) = xa->VsrD(0); \
2464d4ccd87eSBharata B Rao } else { \
2465cf3b0334SMark Cave-Ayland t.VsrD(0) = xb->VsrD(0); \
2466d4ccd87eSBharata B Rao } \
2467d4ccd87eSBharata B Rao \
2468208d8033SVíctor Colombo vex_flag = (env->fpscr & FP_VE) && vxsnan_flag; \
2469d4ccd87eSBharata B Rao if (vxsnan_flag) { \
247013c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
2471d4ccd87eSBharata B Rao } \
2472d4ccd87eSBharata B Rao if (!vex_flag) { \
2473cf3b0334SMark Cave-Ayland *xt = t; \
2474d4ccd87eSBharata B Rao } \
2475d4ccd87eSBharata B Rao } \
2476d4ccd87eSBharata B Rao
24775307df8fSVíctor Colombo VSX_MAX_MINJ(XSMAXJDP, 1);
24785307df8fSVíctor Colombo VSX_MAX_MINJ(XSMINJDP, 0);
2479d4ccd87eSBharata B Rao
2480fa9ebf8cSDavid Gibson /*
2481fa9ebf8cSDavid Gibson * VSX_CMP - VSX floating point compare
2482fcf5ef2aSThomas Huth * op - instruction mnemonic
2483fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
2484fcf5ef2aSThomas Huth * tp - type (float32 or float64)
2485fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
2486fcf5ef2aSThomas Huth * cmp - comparison operation
2487fcf5ef2aSThomas Huth * svxvc - set VXVC bit
2488fcf5ef2aSThomas Huth * exp - expected result of comparison
2489fcf5ef2aSThomas Huth */
2490fcf5ef2aSThomas Huth #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \
249100084a25SMark Cave-Ayland uint32_t helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
249200084a25SMark Cave-Ayland ppc_vsr_t *xa, ppc_vsr_t *xb) \
2493fcf5ef2aSThomas Huth { \
2494cf3b0334SMark Cave-Ayland ppc_vsr_t t = *xt; \
249500084a25SMark Cave-Ayland uint32_t crf6 = 0; \
2496fcf5ef2aSThomas Huth int i; \
2497fcf5ef2aSThomas Huth int all_true = 1; \
2498fcf5ef2aSThomas Huth int all_false = 1; \
2499fcf5ef2aSThomas Huth \
2500c3f24257SVíctor Colombo helper_reset_fpstatus(env); \
2501c3f24257SVíctor Colombo \
2502fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
2503cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_any_nan(xa->fld) || \
2504cf3b0334SMark Cave-Ayland tp##_is_any_nan(xb->fld))) { \
2505cf3b0334SMark Cave-Ayland if (tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2506cf3b0334SMark Cave-Ayland tp##_is_signaling_nan(xb->fld, &env->fp_status)) { \
250713c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
2508fcf5ef2aSThomas Huth } \
2509fcf5ef2aSThomas Huth if (svxvc) { \
251013c9115fSRichard Henderson float_invalid_op_vxvc(env, 0, GETPC()); \
2511fcf5ef2aSThomas Huth } \
2512cf3b0334SMark Cave-Ayland t.fld = 0; \
2513fcf5ef2aSThomas Huth all_true = 0; \
2514fcf5ef2aSThomas Huth } else { \
2515cf3b0334SMark Cave-Ayland if (tp##_##cmp(xb->fld, xa->fld, &env->fp_status) == exp) { \
2516cf3b0334SMark Cave-Ayland t.fld = -1; \
2517fcf5ef2aSThomas Huth all_false = 0; \
2518fcf5ef2aSThomas Huth } else { \
2519cf3b0334SMark Cave-Ayland t.fld = 0; \
2520fcf5ef2aSThomas Huth all_true = 0; \
2521fcf5ef2aSThomas Huth } \
2522fcf5ef2aSThomas Huth } \
2523fcf5ef2aSThomas Huth } \
2524fcf5ef2aSThomas Huth \
2525cf3b0334SMark Cave-Ayland *xt = t; \
252600084a25SMark Cave-Ayland crf6 = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
252700084a25SMark Cave-Ayland return crf6; \
2528fcf5ef2aSThomas Huth }
2529fcf5ef2aSThomas Huth
2530*e77d736dSChinmay Rath VSX_CMP(XVCMPEQDP, 2, float64, VsrD(i), eq, 0, 1)
2531*e77d736dSChinmay Rath VSX_CMP(XVCMPGEDP, 2, float64, VsrD(i), le, 1, 1)
2532*e77d736dSChinmay Rath VSX_CMP(XVCMPGTDP, 2, float64, VsrD(i), lt, 1, 1)
2533*e77d736dSChinmay Rath VSX_CMP(XVCMPNEDP, 2, float64, VsrD(i), eq, 0, 0)
2534*e77d736dSChinmay Rath VSX_CMP(XVCMPEQSP, 4, float32, VsrW(i), eq, 0, 1)
2535*e77d736dSChinmay Rath VSX_CMP(XVCMPGESP, 4, float32, VsrW(i), le, 1, 1)
2536*e77d736dSChinmay Rath VSX_CMP(XVCMPGTSP, 4, float32, VsrW(i), lt, 1, 1)
2537*e77d736dSChinmay Rath VSX_CMP(XVCMPNESP, 4, float32, VsrW(i), eq, 0, 0)
2538fcf5ef2aSThomas Huth
2539fa9ebf8cSDavid Gibson /*
2540fa9ebf8cSDavid Gibson * VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2541fcf5ef2aSThomas Huth * op - instruction mnemonic
2542fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
2543fcf5ef2aSThomas Huth * stp - source type (float32 or float64)
2544fcf5ef2aSThomas Huth * ttp - target type (float32 or float64)
2545fcf5ef2aSThomas Huth * sfld - source vsr_t field
2546fcf5ef2aSThomas Huth * tfld - target vsr_t field (f32 or f64)
2547dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
2548fcf5ef2aSThomas Huth */
2549dd657a35SVíctor Colombo #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfifprf) \
255075cf84cbSMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2551fcf5ef2aSThomas Huth { \
2552205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
2553fcf5ef2aSThomas Huth int i; \
2554fcf5ef2aSThomas Huth \
2555c3f24257SVíctor Colombo helper_reset_fpstatus(env); \
2556c3f24257SVíctor Colombo \
2557fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
2558cf3b0334SMark Cave-Ayland t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2559cf3b0334SMark Cave-Ayland if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2560fcf5ef2aSThomas Huth &env->fp_status))) { \
256113c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
2562cf3b0334SMark Cave-Ayland t.tfld = ttp##_snan_to_qnan(t.tfld); \
2563fcf5ef2aSThomas Huth } \
2564dd657a35SVíctor Colombo if (sfifprf) { \
2565cf3b0334SMark Cave-Ayland helper_compute_fprf_##ttp(env, t.tfld); \
2566fcf5ef2aSThomas Huth } \
2567fcf5ef2aSThomas Huth } \
2568fcf5ef2aSThomas Huth \
2569cf3b0334SMark Cave-Ayland *xt = t; \
2570dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
2571fcf5ef2aSThomas Huth }
2572fcf5ef2aSThomas Huth
2573fcf5ef2aSThomas Huth VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2574fcf5ef2aSThomas Huth VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
2575fcf5ef2aSThomas Huth
2576dd657a35SVíctor Colombo #define VSX_CVT_FP_TO_FP2(op, nels, stp, ttp, sfifprf) \
25773515553bSLucas Coutinho void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
25783515553bSLucas Coutinho { \
25793515553bSLucas Coutinho ppc_vsr_t t = { }; \
25803515553bSLucas Coutinho int i; \
25813515553bSLucas Coutinho \
2582c3f24257SVíctor Colombo helper_reset_fpstatus(env); \
2583c3f24257SVíctor Colombo \
25843515553bSLucas Coutinho for (i = 0; i < nels; i++) { \
25853515553bSLucas Coutinho t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \
25863515553bSLucas Coutinho if (unlikely(stp##_is_signaling_nan(xb->VsrD(i), \
25873515553bSLucas Coutinho &env->fp_status))) { \
25883515553bSLucas Coutinho float_invalid_op_vxsnan(env, GETPC()); \
25893515553bSLucas Coutinho t.VsrW(2 * i) = ttp##_snan_to_qnan(t.VsrW(2 * i)); \
25903515553bSLucas Coutinho } \
2591dd657a35SVíctor Colombo if (sfifprf) { \
25923515553bSLucas Coutinho helper_compute_fprf_##ttp(env, t.VsrW(2 * i)); \
25933515553bSLucas Coutinho } \
25943515553bSLucas Coutinho t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
25953515553bSLucas Coutinho } \
25963515553bSLucas Coutinho \
25973515553bSLucas Coutinho *xt = t; \
2598dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
25993515553bSLucas Coutinho }
26003515553bSLucas Coutinho
26013515553bSLucas Coutinho VSX_CVT_FP_TO_FP2(xvcvdpsp, 2, float64, float32, 0)
26023515553bSLucas Coutinho VSX_CVT_FP_TO_FP2(xscvdpsp, 1, float64, float32, 1)
26033515553bSLucas Coutinho
2604fa9ebf8cSDavid Gibson /*
2605fa9ebf8cSDavid Gibson * VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
2606e5487803SBharata B Rao * op - instruction mnemonic
2607e5487803SBharata B Rao * nels - number of elements (1, 2 or 4)
2608e5487803SBharata B Rao * stp - source type (float32 or float64)
2609e5487803SBharata B Rao * ttp - target type (float32 or float64)
2610e5487803SBharata B Rao * sfld - source vsr_t field
2611e5487803SBharata B Rao * tfld - target vsr_t field (f32 or f64)
2612e5487803SBharata B Rao * sfprf - set FPRF
2613e5487803SBharata B Rao */
2614e5487803SBharata B Rao #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
261599229620SMark Cave-Ayland void helper_##op(CPUPPCState *env, uint32_t opcode, \
261699229620SMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xb) \
2617e5487803SBharata B Rao { \
2618cf3b0334SMark Cave-Ayland ppc_vsr_t t = *xt; \
2619e5487803SBharata B Rao int i; \
2620e5487803SBharata B Rao \
2621c3f24257SVíctor Colombo helper_reset_fpstatus(env); \
2622c3f24257SVíctor Colombo \
2623e5487803SBharata B Rao for (i = 0; i < nels; i++) { \
2624cf3b0334SMark Cave-Ayland t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2625cf3b0334SMark Cave-Ayland if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2626e5487803SBharata B Rao &env->fp_status))) { \
262713c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
2628cf3b0334SMark Cave-Ayland t.tfld = ttp##_snan_to_qnan(t.tfld); \
2629e5487803SBharata B Rao } \
2630e5487803SBharata B Rao if (sfprf) { \
2631cf3b0334SMark Cave-Ayland helper_compute_fprf_##ttp(env, t.tfld); \
2632e5487803SBharata B Rao } \
2633e5487803SBharata B Rao } \
2634e5487803SBharata B Rao \
2635cf3b0334SMark Cave-Ayland *xt = t; \
26363278677fSVíctor Colombo do_float_check_status(env, true, GETPC()); \
2637e5487803SBharata B Rao }
2638e5487803SBharata B Rao
2639e5487803SBharata B Rao VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
2640e5487803SBharata B Rao
2641fa9ebf8cSDavid Gibson /*
2642fa9ebf8cSDavid Gibson * VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
2643f566c047SBharata B Rao * involving one half precision value
2644f566c047SBharata B Rao * op - instruction mnemonic
26458b920d8aSNikunj A Dadhania * nels - number of elements (1, 2 or 4)
2646f566c047SBharata B Rao * stp - source type
2647f566c047SBharata B Rao * ttp - target type
2648f566c047SBharata B Rao * sfld - source vsr_t field
2649f566c047SBharata B Rao * tfld - target vsr_t field
2650dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
2651f566c047SBharata B Rao */
2652dd657a35SVíctor Colombo #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfifprf) \
265375cf84cbSMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2654f566c047SBharata B Rao { \
2655cf3b0334SMark Cave-Ayland ppc_vsr_t t = { }; \
26568b920d8aSNikunj A Dadhania int i; \
2657f566c047SBharata B Rao \
2658c3f24257SVíctor Colombo helper_reset_fpstatus(env); \
2659c3f24257SVíctor Colombo \
26608b920d8aSNikunj A Dadhania for (i = 0; i < nels; i++) { \
2661cf3b0334SMark Cave-Ayland t.tfld = stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \
2662cf3b0334SMark Cave-Ayland if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2663f566c047SBharata B Rao &env->fp_status))) { \
266413c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
2665cf3b0334SMark Cave-Ayland t.tfld = ttp##_snan_to_qnan(t.tfld); \
2666f566c047SBharata B Rao } \
2667dd657a35SVíctor Colombo if (sfifprf) { \
2668cf3b0334SMark Cave-Ayland helper_compute_fprf_##ttp(env, t.tfld); \
26698b920d8aSNikunj A Dadhania } \
26708b920d8aSNikunj A Dadhania } \
2671f566c047SBharata B Rao \
2672cf3b0334SMark Cave-Ayland *xt = t; \
2673dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
2674f566c047SBharata B Rao }
2675f566c047SBharata B Rao
26768b920d8aSNikunj A Dadhania VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
26778b920d8aSNikunj A Dadhania VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
26788b920d8aSNikunj A Dadhania VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
26798b920d8aSNikunj A Dadhania VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
2680f566c047SBharata B Rao
helper_XVCVSPBF16(CPUPPCState * env,ppc_vsr_t * xt,ppc_vsr_t * xb)26813909ff1fSVíctor Colombo void helper_XVCVSPBF16(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
26823909ff1fSVíctor Colombo {
26833909ff1fSVíctor Colombo ppc_vsr_t t = { };
26843909ff1fSVíctor Colombo int i, status;
26853909ff1fSVíctor Colombo
2686a9eb5037SVíctor Colombo helper_reset_fpstatus(env);
2687a9eb5037SVíctor Colombo
26883909ff1fSVíctor Colombo for (i = 0; i < 4; i++) {
26893909ff1fSVíctor Colombo t.VsrH(2 * i + 1) = float32_to_bfloat16(xb->VsrW(i), &env->fp_status);
26903909ff1fSVíctor Colombo }
26913909ff1fSVíctor Colombo
26923909ff1fSVíctor Colombo status = get_float_exception_flags(&env->fp_status);
26933909ff1fSVíctor Colombo if (unlikely(status & float_flag_invalid_snan)) {
26943909ff1fSVíctor Colombo float_invalid_op_vxsnan(env, GETPC());
26953909ff1fSVíctor Colombo }
26963909ff1fSVíctor Colombo
26973909ff1fSVíctor Colombo *xt = t;
26983278677fSVíctor Colombo do_float_check_status(env, false, GETPC());
26993909ff1fSVíctor Colombo }
27003909ff1fSVíctor Colombo
helper_XSCVQPDP(CPUPPCState * env,uint32_t ro,ppc_vsr_t * xt,ppc_vsr_t * xb)2701caf6f9b5SMatheus Ferst void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt,
2702caf6f9b5SMatheus Ferst ppc_vsr_t *xb)
27032a084dadSBharata B Rao {
2704cf3b0334SMark Cave-Ayland ppc_vsr_t t = { };
2705a8d411abSBharata B Rao float_status tstat;
27062a084dadSBharata B Rao
2707c3f24257SVíctor Colombo helper_reset_fpstatus(env);
2708c3f24257SVíctor Colombo
2709a8d411abSBharata B Rao tstat = env->fp_status;
2710caf6f9b5SMatheus Ferst if (ro != 0) {
2711a8d411abSBharata B Rao tstat.float_rounding_mode = float_round_to_odd;
27122a084dadSBharata B Rao }
27132a084dadSBharata B Rao
2714cf3b0334SMark Cave-Ayland t.VsrD(0) = float128_to_float64(xb->f128, &tstat);
2715a8d411abSBharata B Rao env->fp_status.float_exception_flags |= tstat.float_exception_flags;
2716cf3b0334SMark Cave-Ayland if (unlikely(float128_is_signaling_nan(xb->f128, &tstat))) {
271713c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC());
2718cf3b0334SMark Cave-Ayland t.VsrD(0) = float64_snan_to_qnan(t.VsrD(0));
27192a084dadSBharata B Rao }
2720cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.VsrD(0));
27212a084dadSBharata B Rao
2722cf3b0334SMark Cave-Ayland *xt = t;
27233278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
27242a084dadSBharata B Rao }
27252a084dadSBharata B Rao
helper_xscvdpspn(CPUPPCState * env,uint64_t xb)2726fcf5ef2aSThomas Huth uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2727fcf5ef2aSThomas Huth {
2728fa7d9cb9SPaul A. Clarke uint64_t result, sign, exp, frac;
2729e6f1bfb2SPaul A. Clarke
2730c3f24257SVíctor Colombo helper_reset_fpstatus(env);
2731fcf5ef2aSThomas Huth float_status tstat = env->fp_status;
2732fcf5ef2aSThomas Huth set_float_exception_flags(0, &tstat);
2733fcf5ef2aSThomas Huth
2734fa7d9cb9SPaul A. Clarke sign = extract64(xb, 63, 1);
2735fa7d9cb9SPaul A. Clarke exp = extract64(xb, 52, 11);
2736fa7d9cb9SPaul A. Clarke frac = extract64(xb, 0, 52) | 0x10000000000000ULL;
2737fa7d9cb9SPaul A. Clarke
2738fa7d9cb9SPaul A. Clarke if (unlikely(exp == 0 && extract64(frac, 0, 52) != 0)) {
2739fa7d9cb9SPaul A. Clarke /* DP denormal operand. */
2740fa7d9cb9SPaul A. Clarke /* Exponent override to DP min exp. */
2741fa7d9cb9SPaul A. Clarke exp = 1;
2742fa7d9cb9SPaul A. Clarke /* Implicit bit override to 0. */
2743fa7d9cb9SPaul A. Clarke frac = deposit64(frac, 53, 1, 0);
2744fa7d9cb9SPaul A. Clarke }
2745fa7d9cb9SPaul A. Clarke
2746fa7d9cb9SPaul A. Clarke if (unlikely(exp < 897 && frac != 0)) {
2747fa7d9cb9SPaul A. Clarke /* SP tiny operand. */
2748fa7d9cb9SPaul A. Clarke if (897 - exp > 63) {
2749fa7d9cb9SPaul A. Clarke frac = 0;
2750fa7d9cb9SPaul A. Clarke } else {
2751fa7d9cb9SPaul A. Clarke /* Denormalize until exp = SP min exp. */
2752fa7d9cb9SPaul A. Clarke frac >>= (897 - exp);
2753fa7d9cb9SPaul A. Clarke }
2754fa7d9cb9SPaul A. Clarke /* Exponent override to SP min exp - 1. */
2755fa7d9cb9SPaul A. Clarke exp = 896;
2756fa7d9cb9SPaul A. Clarke }
2757fa7d9cb9SPaul A. Clarke
2758fa7d9cb9SPaul A. Clarke result = sign << 31;
2759fa7d9cb9SPaul A. Clarke result |= extract64(exp, 10, 1) << 30;
2760fa7d9cb9SPaul A. Clarke result |= extract64(exp, 0, 7) << 23;
2761fa7d9cb9SPaul A. Clarke result |= extract64(frac, 29, 23);
2762fa7d9cb9SPaul A. Clarke
2763e6f1bfb2SPaul A. Clarke /* hardware replicates result to both words of the doubleword result. */
2764e6f1bfb2SPaul A. Clarke return (result << 32) | result;
2765fcf5ef2aSThomas Huth }
2766fcf5ef2aSThomas Huth
helper_XSCVSPDPN(uint64_t xb)2767cf862beeSMatheus Ferst uint64_t helper_XSCVSPDPN(uint64_t xb)
2768fcf5ef2aSThomas Huth {
276984ade98eSMatheus Ferst return helper_todouble(xb >> 32);
2770fcf5ef2aSThomas Huth }
2771fcf5ef2aSThomas Huth
2772fa9ebf8cSDavid Gibson /*
2773fa9ebf8cSDavid Gibson * VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2774fcf5ef2aSThomas Huth * op - instruction mnemonic
2775fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
2776fcf5ef2aSThomas Huth * stp - source type (float32 or float64)
2777fcf5ef2aSThomas Huth * ttp - target type (int32, uint32, int64 or uint64)
2778fcf5ef2aSThomas Huth * sfld - source vsr_t field
2779fcf5ef2aSThomas Huth * tfld - target vsr_t field
27803278677fSVíctor Colombo * sfi - set FI
2781fcf5ef2aSThomas Huth * rnan - resulting NaN
2782fcf5ef2aSThomas Huth */
27833278677fSVíctor Colombo #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, sfi, rnan) \
278475cf84cbSMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2785fcf5ef2aSThomas Huth { \
2786d18b0652SJohn Platts int all_flags = 0; \
2787205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
2788c3f24257SVíctor Colombo int i, flags; \
2789c3f24257SVíctor Colombo \
2790fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
2791d18b0652SJohn Platts helper_reset_fpstatus(env); \
2792cf3b0334SMark Cave-Ayland t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2793a3dec427SRichard Henderson flags = env->fp_status.float_exception_flags; \
2794d18b0652SJohn Platts all_flags |= flags; \
2795a3dec427SRichard Henderson if (unlikely(flags & float_flag_invalid)) { \
2796fed12f3bSRichard Henderson t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\
2797fcf5ef2aSThomas Huth } \
2798fcf5ef2aSThomas Huth } \
2799fcf5ef2aSThomas Huth \
2800cf3b0334SMark Cave-Ayland *xt = t; \
2801d18b0652SJohn Platts env->fp_status.float_exception_flags = all_flags; \
28023278677fSVíctor Colombo do_float_check_status(env, sfi, GETPC()); \
2803fcf5ef2aSThomas Huth }
2804fcf5ef2aSThomas Huth
28053278677fSVíctor Colombo VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), true, \
2806fcf5ef2aSThomas Huth 0x8000000000000000ULL)
28073278677fSVíctor Colombo VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), true, 0ULL)
28083278677fSVíctor Colombo VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), false, \
2809fcf5ef2aSThomas Huth 0x8000000000000000ULL)
28103278677fSVíctor Colombo VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), false, \
28113278677fSVíctor Colombo 0ULL)
28123278677fSVíctor Colombo VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), false, \
2813fcf5ef2aSThomas Huth 0x8000000000000000ULL)
28143278677fSVíctor Colombo VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), false, \
28153278677fSVíctor Colombo 0x80000000ULL)
28163278677fSVíctor Colombo VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), \
28173278677fSVíctor Colombo false, 0ULL)
28183278677fSVíctor Colombo VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), false, 0U)
2819fcf5ef2aSThomas Huth
2820b3d45205SMatheus Ferst #define VSX_CVT_FP_TO_INT128(op, tp, rnan) \
2821b3d45205SMatheus Ferst void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2822b3d45205SMatheus Ferst { \
2823b3d45205SMatheus Ferst ppc_vsr_t t; \
2824b3d45205SMatheus Ferst int flags; \
2825b3d45205SMatheus Ferst \
2826b3d45205SMatheus Ferst helper_reset_fpstatus(env); \
2827b3d45205SMatheus Ferst t.s128 = float128_to_##tp##_round_to_zero(xb->f128, &env->fp_status); \
2828b3d45205SMatheus Ferst flags = get_float_exception_flags(&env->fp_status); \
2829b3d45205SMatheus Ferst if (unlikely(flags & float_flag_invalid)) { \
2830b3d45205SMatheus Ferst t.VsrD(0) = float_invalid_cvt(env, flags, t.VsrD(0), rnan, 0, GETPC());\
2831b3d45205SMatheus Ferst t.VsrD(1) = -(t.VsrD(0) & 1); \
2832b3d45205SMatheus Ferst } \
2833b3d45205SMatheus Ferst \
2834b3d45205SMatheus Ferst *xt = t; \
28353278677fSVíctor Colombo do_float_check_status(env, true, GETPC()); \
2836b3d45205SMatheus Ferst }
2837b3d45205SMatheus Ferst
2838b3d45205SMatheus Ferst VSX_CVT_FP_TO_INT128(XSCVQPUQZ, uint128, 0)
2839b3d45205SMatheus Ferst VSX_CVT_FP_TO_INT128(XSCVQPSQZ, int128, 0x8000000000000000ULL);
2840b3d45205SMatheus Ferst
2841fa9ebf8cSDavid Gibson /*
2842217979d3SRichard Henderson * Likewise, except that the result is duplicated into both subwords.
2843217979d3SRichard Henderson * Power ISA v3.1 has Programming Notes for these insns:
2844217979d3SRichard Henderson * Previous versions of the architecture allowed the contents of
2845217979d3SRichard Henderson * word 0 of the result register to be undefined. However, all
2846217979d3SRichard Henderson * processors that support this instruction write the result into
2847217979d3SRichard Henderson * words 0 and 1 (and words 2 and 3) of the result register, as
2848217979d3SRichard Henderson * is required by this version of the architecture.
2849217979d3SRichard Henderson */
28503278677fSVíctor Colombo #define VSX_CVT_FP_TO_INT2(op, nels, stp, ttp, sfi, rnan) \
2851217979d3SRichard Henderson void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2852217979d3SRichard Henderson { \
2853d18b0652SJohn Platts int all_flags = 0; \
2854217979d3SRichard Henderson ppc_vsr_t t = { }; \
2855c3f24257SVíctor Colombo int i, flags; \
2856c3f24257SVíctor Colombo \
2857217979d3SRichard Henderson for (i = 0; i < nels; i++) { \
2858d18b0652SJohn Platts helper_reset_fpstatus(env); \
2859217979d3SRichard Henderson t.VsrW(2 * i) = stp##_to_##ttp##_round_to_zero(xb->VsrD(i), \
2860217979d3SRichard Henderson &env->fp_status); \
2861217979d3SRichard Henderson flags = env->fp_status.float_exception_flags; \
2862d18b0652SJohn Platts all_flags |= flags; \
2863217979d3SRichard Henderson if (unlikely(flags & float_flag_invalid)) { \
2864217979d3SRichard Henderson t.VsrW(2 * i) = float_invalid_cvt(env, flags, t.VsrW(2 * i), \
2865217979d3SRichard Henderson rnan, 0, GETPC()); \
2866217979d3SRichard Henderson } \
2867217979d3SRichard Henderson t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
2868217979d3SRichard Henderson } \
2869217979d3SRichard Henderson \
2870217979d3SRichard Henderson *xt = t; \
2871d18b0652SJohn Platts env->fp_status.float_exception_flags = all_flags; \
28723278677fSVíctor Colombo do_float_check_status(env, sfi, GETPC()); \
2873217979d3SRichard Henderson }
2874217979d3SRichard Henderson
28753278677fSVíctor Colombo VSX_CVT_FP_TO_INT2(xscvdpsxws, 1, float64, int32, true, 0x80000000U)
28763278677fSVíctor Colombo VSX_CVT_FP_TO_INT2(xscvdpuxws, 1, float64, uint32, true, 0U)
28773278677fSVíctor Colombo VSX_CVT_FP_TO_INT2(xvcvdpsxws, 2, float64, int32, false, 0x80000000U)
28783278677fSVíctor Colombo VSX_CVT_FP_TO_INT2(xvcvdpuxws, 2, float64, uint32, false, 0U)
2879217979d3SRichard Henderson
2880217979d3SRichard Henderson /*
2881fa9ebf8cSDavid Gibson * VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
288205590b92SBharata B Rao * op - instruction mnemonic
288305590b92SBharata B Rao * stp - source type (float32 or float64)
288405590b92SBharata B Rao * ttp - target type (int32, uint32, int64 or uint64)
288505590b92SBharata B Rao * sfld - source vsr_t field
288605590b92SBharata B Rao * tfld - target vsr_t field
288705590b92SBharata B Rao * rnan - resulting NaN
288805590b92SBharata B Rao */
288905590b92SBharata B Rao #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) \
289099229620SMark Cave-Ayland void helper_##op(CPUPPCState *env, uint32_t opcode, \
289199229620SMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xb) \
289205590b92SBharata B Rao { \
2893cf3b0334SMark Cave-Ayland ppc_vsr_t t = { }; \
2894353464eaSRichard Henderson int flags; \
289505590b92SBharata B Rao \
2896c3f24257SVíctor Colombo helper_reset_fpstatus(env); \
2897c3f24257SVíctor Colombo \
2898cf3b0334SMark Cave-Ayland t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2899353464eaSRichard Henderson flags = get_float_exception_flags(&env->fp_status); \
2900353464eaSRichard Henderson if (flags & float_flag_invalid) { \
2901fed12f3bSRichard Henderson t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC()); \
290205590b92SBharata B Rao } \
290305590b92SBharata B Rao \
2904cf3b0334SMark Cave-Ayland *xt = t; \
29053278677fSVíctor Colombo do_float_check_status(env, true, GETPC()); \
290605590b92SBharata B Rao }
290705590b92SBharata B Rao
290805590b92SBharata B Rao VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
290905590b92SBharata B Rao 0x8000000000000000ULL)
291005590b92SBharata B Rao VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
291105590b92SBharata B Rao 0xffffffff80000000ULL)
2912e0aee726SBharata B Rao VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
2913e0aee726SBharata B Rao VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
291405590b92SBharata B Rao
2915fa9ebf8cSDavid Gibson /*
2916fa9ebf8cSDavid Gibson * VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2917fcf5ef2aSThomas Huth * op - instruction mnemonic
2918fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
2919fcf5ef2aSThomas Huth * stp - source type (int32, uint32, int64 or uint64)
2920fcf5ef2aSThomas Huth * ttp - target type (float32 or float64)
2921fcf5ef2aSThomas Huth * sfld - source vsr_t field
2922fcf5ef2aSThomas Huth * tfld - target vsr_t field
2923fcf5ef2aSThomas Huth * jdef - definition of the j index (i or 2*i)
2924dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
2925fcf5ef2aSThomas Huth */
2926dd657a35SVíctor Colombo #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfifprf, r2sp)\
292775cf84cbSMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2928fcf5ef2aSThomas Huth { \
2929205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
2930fcf5ef2aSThomas Huth int i; \
2931fcf5ef2aSThomas Huth \
2932c3f24257SVíctor Colombo helper_reset_fpstatus(env); \
2933c3f24257SVíctor Colombo \
2934fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
2935cf3b0334SMark Cave-Ayland t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2936fcf5ef2aSThomas Huth if (r2sp) { \
29377238e55bSRichard Henderson t.tfld = do_frsp(env, t.tfld, GETPC()); \
2938fcf5ef2aSThomas Huth } \
2939dd657a35SVíctor Colombo if (sfifprf) { \
2940cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.tfld); \
2941fcf5ef2aSThomas Huth } \
2942fcf5ef2aSThomas Huth } \
2943fcf5ef2aSThomas Huth \
2944cf3b0334SMark Cave-Ayland *xt = t; \
2945dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
2946fcf5ef2aSThomas Huth }
2947fcf5ef2aSThomas Huth
2948fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
2949fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
2950fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
2951fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
2952fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
2953fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
2954fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
2955fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
2956fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
2957fcf5ef2aSThomas Huth VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
2958fcf5ef2aSThomas Huth
29593515553bSLucas Coutinho #define VSX_CVT_INT_TO_FP2(op, stp, ttp) \
29603515553bSLucas Coutinho void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
29613515553bSLucas Coutinho { \
29623515553bSLucas Coutinho ppc_vsr_t t = { }; \
29633515553bSLucas Coutinho int i; \
29643515553bSLucas Coutinho \
29653515553bSLucas Coutinho for (i = 0; i < 2; i++) { \
29663515553bSLucas Coutinho t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \
29673515553bSLucas Coutinho t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
29683515553bSLucas Coutinho } \
29693515553bSLucas Coutinho \
29703515553bSLucas Coutinho *xt = t; \
29713278677fSVíctor Colombo do_float_check_status(env, false, GETPC()); \
29723515553bSLucas Coutinho }
29733515553bSLucas Coutinho
29743515553bSLucas Coutinho VSX_CVT_INT_TO_FP2(xvcvsxdsp, int64, float32)
29753515553bSLucas Coutinho VSX_CVT_INT_TO_FP2(xvcvuxdsp, uint64, float32)
29763515553bSLucas Coutinho
297767332e07SMatheus Ferst #define VSX_CVT_INT128_TO_FP(op, tp) \
297867332e07SMatheus Ferst void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)\
297967332e07SMatheus Ferst { \
298067332e07SMatheus Ferst helper_reset_fpstatus(env); \
298167332e07SMatheus Ferst xt->f128 = tp##_to_float128(xb->s128, &env->fp_status); \
298267332e07SMatheus Ferst helper_compute_fprf_float128(env, xt->f128); \
29833278677fSVíctor Colombo do_float_check_status(env, true, GETPC()); \
298467332e07SMatheus Ferst }
298567332e07SMatheus Ferst
298667332e07SMatheus Ferst VSX_CVT_INT128_TO_FP(XSCVUQQP, uint128);
298767332e07SMatheus Ferst VSX_CVT_INT128_TO_FP(XSCVSQQP, int128);
298867332e07SMatheus Ferst
2989fa9ebf8cSDavid Gibson /*
2990fa9ebf8cSDavid Gibson * VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
299148ef23cbSBharata B Rao * op - instruction mnemonic
299248ef23cbSBharata B Rao * stp - source type (int32, uint32, int64 or uint64)
299348ef23cbSBharata B Rao * ttp - target type (float32 or float64)
299448ef23cbSBharata B Rao * sfld - source vsr_t field
299548ef23cbSBharata B Rao * tfld - target vsr_t field
299648ef23cbSBharata B Rao */
299748ef23cbSBharata B Rao #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \
299899229620SMark Cave-Ayland void helper_##op(CPUPPCState *env, uint32_t opcode, \
299999229620SMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xb) \
300048ef23cbSBharata B Rao { \
3001cf3b0334SMark Cave-Ayland ppc_vsr_t t = *xt; \
300248ef23cbSBharata B Rao \
3003c3f24257SVíctor Colombo helper_reset_fpstatus(env); \
3004cf3b0334SMark Cave-Ayland t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
3005cf3b0334SMark Cave-Ayland helper_compute_fprf_##ttp(env, t.tfld); \
300648ef23cbSBharata B Rao \
3007cf3b0334SMark Cave-Ayland *xt = t; \
30083278677fSVíctor Colombo do_float_check_status(env, true, GETPC()); \
300948ef23cbSBharata B Rao }
301048ef23cbSBharata B Rao
301148ef23cbSBharata B Rao VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
301248ef23cbSBharata B Rao VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
301348ef23cbSBharata B Rao
3014fa9ebf8cSDavid Gibson /*
3015fa9ebf8cSDavid Gibson * For "use current rounding mode", define a value that will not be
3016fa9ebf8cSDavid Gibson * one of the existing rounding model enums.
3017fcf5ef2aSThomas Huth */
3018fcf5ef2aSThomas Huth #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
3019fcf5ef2aSThomas Huth float_round_up + float_round_to_zero)
3020fcf5ef2aSThomas Huth
3021fa9ebf8cSDavid Gibson /*
3022fa9ebf8cSDavid Gibson * VSX_ROUND - VSX floating point round
3023fcf5ef2aSThomas Huth * op - instruction mnemonic
3024fcf5ef2aSThomas Huth * nels - number of elements (1, 2 or 4)
3025fcf5ef2aSThomas Huth * tp - type (float32 or float64)
3026fcf5ef2aSThomas Huth * fld - vsr_t field (VsrD(*) or VsrW(*))
3027fcf5ef2aSThomas Huth * rmode - rounding mode
3028dd657a35SVíctor Colombo * sfifprf - set FI and FPRF
3029fcf5ef2aSThomas Huth */
3030dd657a35SVíctor Colombo #define VSX_ROUND(op, nels, tp, fld, rmode, sfifprf) \
303175cf84cbSMark Cave-Ayland void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
3032fcf5ef2aSThomas Huth { \
3033205eb5a8SVíctor Colombo ppc_vsr_t t = { }; \
3034fcf5ef2aSThomas Huth int i; \
303563d06e90SBruno Larsen (billionai) FloatRoundMode curr_rounding_mode; \
3036fcf5ef2aSThomas Huth \
3037c3f24257SVíctor Colombo helper_reset_fpstatus(env); \
3038c3f24257SVíctor Colombo \
3039fcf5ef2aSThomas Huth if (rmode != FLOAT_ROUND_CURRENT) { \
304063d06e90SBruno Larsen (billionai) curr_rounding_mode = get_float_rounding_mode(&env->fp_status); \
3041fcf5ef2aSThomas Huth set_float_rounding_mode(rmode, &env->fp_status); \
3042fcf5ef2aSThomas Huth } \
3043fcf5ef2aSThomas Huth \
3044fcf5ef2aSThomas Huth for (i = 0; i < nels; i++) { \
3045cf3b0334SMark Cave-Ayland if (unlikely(tp##_is_signaling_nan(xb->fld, \
3046fcf5ef2aSThomas Huth &env->fp_status))) { \
304713c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC()); \
3048cf3b0334SMark Cave-Ayland t.fld = tp##_snan_to_qnan(xb->fld); \
3049fcf5ef2aSThomas Huth } else { \
3050cf3b0334SMark Cave-Ayland t.fld = tp##_round_to_int(xb->fld, &env->fp_status); \
3051fcf5ef2aSThomas Huth } \
3052dd657a35SVíctor Colombo if (sfifprf) { \
3053cf3b0334SMark Cave-Ayland helper_compute_fprf_float64(env, t.fld); \
3054fcf5ef2aSThomas Huth } \
3055fcf5ef2aSThomas Huth } \
3056fcf5ef2aSThomas Huth \
3057fa9ebf8cSDavid Gibson /* \
3058fa9ebf8cSDavid Gibson * If this is not a "use current rounding mode" instruction, \
3059fcf5ef2aSThomas Huth * then inhibit setting of the XX bit and restore rounding \
3060fa9ebf8cSDavid Gibson * mode from FPSCR \
3061fa9ebf8cSDavid Gibson */ \
3062fcf5ef2aSThomas Huth if (rmode != FLOAT_ROUND_CURRENT) { \
306363d06e90SBruno Larsen (billionai) set_float_rounding_mode(curr_rounding_mode, &env->fp_status); \
3064fcf5ef2aSThomas Huth env->fp_status.float_exception_flags &= ~float_flag_inexact; \
3065fcf5ef2aSThomas Huth } \
3066fcf5ef2aSThomas Huth \
3067cf3b0334SMark Cave-Ayland *xt = t; \
3068dd657a35SVíctor Colombo do_float_check_status(env, sfifprf, GETPC()); \
3069fcf5ef2aSThomas Huth }
3070fcf5ef2aSThomas Huth
3071fcf5ef2aSThomas Huth VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1)
3072fcf5ef2aSThomas Huth VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
3073fcf5ef2aSThomas Huth VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
3074fcf5ef2aSThomas Huth VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
3075fcf5ef2aSThomas Huth VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
3076fcf5ef2aSThomas Huth
3077fcf5ef2aSThomas Huth VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_ties_away, 0)
3078fcf5ef2aSThomas Huth VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
3079fcf5ef2aSThomas Huth VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
3080fcf5ef2aSThomas Huth VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
3081fcf5ef2aSThomas Huth VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
3082fcf5ef2aSThomas Huth
3083fcf5ef2aSThomas Huth VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_ties_away, 0)
3084fcf5ef2aSThomas Huth VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
3085fcf5ef2aSThomas Huth VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
3086fcf5ef2aSThomas Huth VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
3087fcf5ef2aSThomas Huth VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
3088fcf5ef2aSThomas Huth
helper_xsrsp(CPUPPCState * env,uint64_t xb)3089fcf5ef2aSThomas Huth uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
3090fcf5ef2aSThomas Huth {
3091fcf5ef2aSThomas Huth helper_reset_fpstatus(env);
3092fcf5ef2aSThomas Huth
30937238e55bSRichard Henderson uint64_t xt = do_frsp(env, xb, GETPC());
3094fcf5ef2aSThomas Huth
3095ffc67420SBharata B Rao helper_compute_fprf_float64(env, xt);
30963278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
3097fcf5ef2aSThomas Huth return xt;
3098fcf5ef2aSThomas Huth }
3099234068abSBharata B Rao
helper_XVXSIGSP(ppc_vsr_t * xt,ppc_vsr_t * xb)3100c36ab970SMatheus Ferst void helper_XVXSIGSP(ppc_vsr_t *xt, ppc_vsr_t *xb)
3101c5969d2eSNikunj A Dadhania {
3102cf3b0334SMark Cave-Ayland ppc_vsr_t t = { };
3103c5969d2eSNikunj A Dadhania uint32_t exp, i, fraction;
3104c5969d2eSNikunj A Dadhania
3105c5969d2eSNikunj A Dadhania for (i = 0; i < 4; i++) {
3106cf3b0334SMark Cave-Ayland exp = (xb->VsrW(i) >> 23) & 0xFF;
3107cf3b0334SMark Cave-Ayland fraction = xb->VsrW(i) & 0x7FFFFF;
3108c5969d2eSNikunj A Dadhania if (exp != 0 && exp != 255) {
3109cf3b0334SMark Cave-Ayland t.VsrW(i) = fraction | 0x00800000;
3110c5969d2eSNikunj A Dadhania } else {
3111cf3b0334SMark Cave-Ayland t.VsrW(i) = fraction;
3112c5969d2eSNikunj A Dadhania }
3113c5969d2eSNikunj A Dadhania }
3114cf3b0334SMark Cave-Ayland *xt = t;
3115c5969d2eSNikunj A Dadhania }
3116403a884aSNikunj A Dadhania
3117a70a5247SLucas Mateus Castro (alqotel) #define VSX_TSTDC(tp) \
3118a70a5247SLucas Mateus Castro (alqotel) static int32_t tp##_tstdc(tp b, uint32_t dcmx) \
3119a70a5247SLucas Mateus Castro (alqotel) { \
3120a70a5247SLucas Mateus Castro (alqotel) uint32_t match = 0; \
3121a70a5247SLucas Mateus Castro (alqotel) uint32_t sign = tp##_is_neg(b); \
3122a70a5247SLucas Mateus Castro (alqotel) if (tp##_is_any_nan(b)) { \
3123a70a5247SLucas Mateus Castro (alqotel) match = extract32(dcmx, 6, 1); \
3124a70a5247SLucas Mateus Castro (alqotel) } else if (tp##_is_infinity(b)) { \
3125a70a5247SLucas Mateus Castro (alqotel) match = extract32(dcmx, 4 + !sign, 1); \
3126a70a5247SLucas Mateus Castro (alqotel) } else if (tp##_is_zero(b)) { \
3127a70a5247SLucas Mateus Castro (alqotel) match = extract32(dcmx, 2 + !sign, 1); \
3128a70a5247SLucas Mateus Castro (alqotel) } else if (tp##_is_zero_or_denormal(b)) { \
3129a70a5247SLucas Mateus Castro (alqotel) match = extract32(dcmx, 0 + !sign, 1); \
3130a70a5247SLucas Mateus Castro (alqotel) } \
3131a70a5247SLucas Mateus Castro (alqotel) return (match != 0); \
3132a70a5247SLucas Mateus Castro (alqotel) }
3133a70a5247SLucas Mateus Castro (alqotel)
3134a70a5247SLucas Mateus Castro (alqotel) VSX_TSTDC(float32)
VSX_TSTDC(float64)3135a70a5247SLucas Mateus Castro (alqotel) VSX_TSTDC(float64)
3136da3c53baSLucas Mateus Castro (alqotel) VSX_TSTDC(float128)
3137a70a5247SLucas Mateus Castro (alqotel) #undef VSX_TSTDC
3138a70a5247SLucas Mateus Castro (alqotel)
3139a70a5247SLucas Mateus Castro (alqotel) void helper_XVTSTDCDP(ppc_vsr_t *t, ppc_vsr_t *b, uint64_t dcmx, uint32_t v)
3140a70a5247SLucas Mateus Castro (alqotel) {
3141a70a5247SLucas Mateus Castro (alqotel) int i;
3142a70a5247SLucas Mateus Castro (alqotel) for (i = 0; i < 2; i++) {
3143a70a5247SLucas Mateus Castro (alqotel) t->s64[i] = (int64_t)-float64_tstdc(b->f64[i], dcmx);
3144a70a5247SLucas Mateus Castro (alqotel) }
3145a70a5247SLucas Mateus Castro (alqotel) }
3146a70a5247SLucas Mateus Castro (alqotel)
helper_XVTSTDCSP(ppc_vsr_t * t,ppc_vsr_t * b,uint64_t dcmx,uint32_t v)3147a70a5247SLucas Mateus Castro (alqotel) void helper_XVTSTDCSP(ppc_vsr_t *t, ppc_vsr_t *b, uint64_t dcmx, uint32_t v)
3148a70a5247SLucas Mateus Castro (alqotel) {
3149a70a5247SLucas Mateus Castro (alqotel) int i;
3150a70a5247SLucas Mateus Castro (alqotel) for (i = 0; i < 4; i++) {
3151a70a5247SLucas Mateus Castro (alqotel) t->s32[i] = (int32_t)-float32_tstdc(b->f32[i], dcmx);
3152a70a5247SLucas Mateus Castro (alqotel) }
3153a70a5247SLucas Mateus Castro (alqotel) }
3154a70a5247SLucas Mateus Castro (alqotel)
not_SP_value(float64 val)3155da3c53baSLucas Mateus Castro (alqotel) static bool not_SP_value(float64 val)
315678241762SNikunj A Dadhania {
3157da3c53baSLucas Mateus Castro (alqotel) return val != helper_todouble(helper_tosingle(val));
315878241762SNikunj A Dadhania }
315978241762SNikunj A Dadhania
3160da3c53baSLucas Mateus Castro (alqotel) /*
3161da3c53baSLucas Mateus Castro (alqotel) * VSX_XS_TSTDC - VSX Scalar Test Data Class
3162da3c53baSLucas Mateus Castro (alqotel) * NAME - instruction name
3163da3c53baSLucas Mateus Castro (alqotel) * FLD - vsr_t field (VsrD(0) or f128)
3164da3c53baSLucas Mateus Castro (alqotel) * TP - type (float64 or float128)
3165da3c53baSLucas Mateus Castro (alqotel) */
3166da3c53baSLucas Mateus Castro (alqotel) #define VSX_XS_TSTDC(NAME, FLD, TP) \
3167da3c53baSLucas Mateus Castro (alqotel) void helper_##NAME(CPUPPCState *env, uint32_t bf, \
3168da3c53baSLucas Mateus Castro (alqotel) uint32_t dcmx, ppc_vsr_t *b) \
3169da3c53baSLucas Mateus Castro (alqotel) { \
3170da3c53baSLucas Mateus Castro (alqotel) uint32_t cc, match, sign = TP##_is_neg(b->FLD); \
3171da3c53baSLucas Mateus Castro (alqotel) match = TP##_tstdc(b->FLD, dcmx); \
3172da3c53baSLucas Mateus Castro (alqotel) cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT; \
3173da3c53baSLucas Mateus Castro (alqotel) env->fpscr &= ~FP_FPCC; \
3174da3c53baSLucas Mateus Castro (alqotel) env->fpscr |= cc << FPSCR_FPCC; \
3175da3c53baSLucas Mateus Castro (alqotel) env->crf[bf] = cc; \
3176da3c53baSLucas Mateus Castro (alqotel) }
317778241762SNikunj A Dadhania
3178da3c53baSLucas Mateus Castro (alqotel) VSX_XS_TSTDC(XSTSTDCDP, VsrD(0), float64)
VSX_XS_TSTDC(XSTSTDCQP,f128,float128)3179da3c53baSLucas Mateus Castro (alqotel) VSX_XS_TSTDC(XSTSTDCQP, f128, float128)
3180da3c53baSLucas Mateus Castro (alqotel) #undef VSX_XS_TSTDC
3181da3c53baSLucas Mateus Castro (alqotel)
3182da3c53baSLucas Mateus Castro (alqotel) void helper_XSTSTDCSP(CPUPPCState *env, uint32_t bf,
3183da3c53baSLucas Mateus Castro (alqotel) uint32_t dcmx, ppc_vsr_t *b)
3184da3c53baSLucas Mateus Castro (alqotel) {
3185da3c53baSLucas Mateus Castro (alqotel) uint32_t cc, match, sign = float64_is_neg(b->VsrD(0));
3186da3c53baSLucas Mateus Castro (alqotel) uint32_t exp = (b->VsrD(0) >> 52) & 0x7FF;
3187da3c53baSLucas Mateus Castro (alqotel) int not_sp = (int)not_SP_value(b->VsrD(0));
3188da3c53baSLucas Mateus Castro (alqotel) match = float64_tstdc(b->VsrD(0), dcmx) || (exp > 0 && exp < 0x381);
318978241762SNikunj A Dadhania cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
31905c94dd38SPaul A. Clarke env->fpscr &= ~FP_FPCC;
31915c94dd38SPaul A. Clarke env->fpscr |= cc << FPSCR_FPCC;
3192da3c53baSLucas Mateus Castro (alqotel) env->crf[bf] = cc;
319378241762SNikunj A Dadhania }
3194be07ad58SJose Ricardo Ziviani
helper_xsrqpi(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xt,ppc_vsr_t * xb)319599229620SMark Cave-Ayland void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
319699229620SMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xb)
3197be07ad58SJose Ricardo Ziviani {
3198cf3b0334SMark Cave-Ayland ppc_vsr_t t = { };
3199be07ad58SJose Ricardo Ziviani uint8_t r = Rrm(opcode);
3200be07ad58SJose Ricardo Ziviani uint8_t ex = Rc(opcode);
3201be07ad58SJose Ricardo Ziviani uint8_t rmc = RMC(opcode);
3202be07ad58SJose Ricardo Ziviani uint8_t rmode = 0;
3203be07ad58SJose Ricardo Ziviani float_status tstat;
3204be07ad58SJose Ricardo Ziviani
3205be07ad58SJose Ricardo Ziviani helper_reset_fpstatus(env);
3206be07ad58SJose Ricardo Ziviani
3207be07ad58SJose Ricardo Ziviani if (r == 0 && rmc == 0) {
3208be07ad58SJose Ricardo Ziviani rmode = float_round_ties_away;
3209be07ad58SJose Ricardo Ziviani } else if (r == 0 && rmc == 0x3) {
3210208d8033SVíctor Colombo rmode = env->fpscr & FP_RN;
3211be07ad58SJose Ricardo Ziviani } else if (r == 1) {
3212be07ad58SJose Ricardo Ziviani switch (rmc) {
3213be07ad58SJose Ricardo Ziviani case 0:
3214be07ad58SJose Ricardo Ziviani rmode = float_round_nearest_even;
3215be07ad58SJose Ricardo Ziviani break;
3216be07ad58SJose Ricardo Ziviani case 1:
3217be07ad58SJose Ricardo Ziviani rmode = float_round_to_zero;
3218be07ad58SJose Ricardo Ziviani break;
3219be07ad58SJose Ricardo Ziviani case 2:
3220be07ad58SJose Ricardo Ziviani rmode = float_round_up;
3221be07ad58SJose Ricardo Ziviani break;
3222be07ad58SJose Ricardo Ziviani case 3:
3223be07ad58SJose Ricardo Ziviani rmode = float_round_down;
3224be07ad58SJose Ricardo Ziviani break;
3225be07ad58SJose Ricardo Ziviani default:
3226be07ad58SJose Ricardo Ziviani abort();
3227be07ad58SJose Ricardo Ziviani }
3228be07ad58SJose Ricardo Ziviani }
3229be07ad58SJose Ricardo Ziviani
3230be07ad58SJose Ricardo Ziviani tstat = env->fp_status;
3231be07ad58SJose Ricardo Ziviani set_float_exception_flags(0, &tstat);
3232be07ad58SJose Ricardo Ziviani set_float_rounding_mode(rmode, &tstat);
3233cf3b0334SMark Cave-Ayland t.f128 = float128_round_to_int(xb->f128, &tstat);
3234be07ad58SJose Ricardo Ziviani env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3235be07ad58SJose Ricardo Ziviani
3236053e23a6SRichard Henderson if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) {
323713c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC());
3238be07ad58SJose Ricardo Ziviani }
3239be07ad58SJose Ricardo Ziviani
3240be07ad58SJose Ricardo Ziviani if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
3241be07ad58SJose Ricardo Ziviani env->fp_status.float_exception_flags &= ~float_flag_inexact;
3242be07ad58SJose Ricardo Ziviani }
3243be07ad58SJose Ricardo Ziviani
3244cf3b0334SMark Cave-Ayland helper_compute_fprf_float128(env, t.f128);
32453278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
3246cf3b0334SMark Cave-Ayland *xt = t;
3247be07ad58SJose Ricardo Ziviani }
3248917950d7SJose Ricardo Ziviani
helper_xsrqpxp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xt,ppc_vsr_t * xb)324999229620SMark Cave-Ayland void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
325099229620SMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xb)
3251917950d7SJose Ricardo Ziviani {
3252cf3b0334SMark Cave-Ayland ppc_vsr_t t = { };
3253917950d7SJose Ricardo Ziviani uint8_t r = Rrm(opcode);
3254917950d7SJose Ricardo Ziviani uint8_t rmc = RMC(opcode);
3255917950d7SJose Ricardo Ziviani uint8_t rmode = 0;
3256917950d7SJose Ricardo Ziviani floatx80 round_res;
3257917950d7SJose Ricardo Ziviani float_status tstat;
3258917950d7SJose Ricardo Ziviani
3259917950d7SJose Ricardo Ziviani helper_reset_fpstatus(env);
3260917950d7SJose Ricardo Ziviani
3261917950d7SJose Ricardo Ziviani if (r == 0 && rmc == 0) {
3262917950d7SJose Ricardo Ziviani rmode = float_round_ties_away;
3263917950d7SJose Ricardo Ziviani } else if (r == 0 && rmc == 0x3) {
3264208d8033SVíctor Colombo rmode = env->fpscr & FP_RN;
3265917950d7SJose Ricardo Ziviani } else if (r == 1) {
3266917950d7SJose Ricardo Ziviani switch (rmc) {
3267917950d7SJose Ricardo Ziviani case 0:
3268917950d7SJose Ricardo Ziviani rmode = float_round_nearest_even;
3269917950d7SJose Ricardo Ziviani break;
3270917950d7SJose Ricardo Ziviani case 1:
3271917950d7SJose Ricardo Ziviani rmode = float_round_to_zero;
3272917950d7SJose Ricardo Ziviani break;
3273917950d7SJose Ricardo Ziviani case 2:
3274917950d7SJose Ricardo Ziviani rmode = float_round_up;
3275917950d7SJose Ricardo Ziviani break;
3276917950d7SJose Ricardo Ziviani case 3:
3277917950d7SJose Ricardo Ziviani rmode = float_round_down;
3278917950d7SJose Ricardo Ziviani break;
3279917950d7SJose Ricardo Ziviani default:
3280917950d7SJose Ricardo Ziviani abort();
3281917950d7SJose Ricardo Ziviani }
3282917950d7SJose Ricardo Ziviani }
3283917950d7SJose Ricardo Ziviani
3284917950d7SJose Ricardo Ziviani tstat = env->fp_status;
3285917950d7SJose Ricardo Ziviani set_float_exception_flags(0, &tstat);
3286917950d7SJose Ricardo Ziviani set_float_rounding_mode(rmode, &tstat);
3287cf3b0334SMark Cave-Ayland round_res = float128_to_floatx80(xb->f128, &tstat);
3288cf3b0334SMark Cave-Ayland t.f128 = floatx80_to_float128(round_res, &tstat);
3289917950d7SJose Ricardo Ziviani env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3290917950d7SJose Ricardo Ziviani
3291053e23a6SRichard Henderson if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) {
329213c9115fSRichard Henderson float_invalid_op_vxsnan(env, GETPC());
3293cf3b0334SMark Cave-Ayland t.f128 = float128_snan_to_qnan(t.f128);
3294917950d7SJose Ricardo Ziviani }
3295917950d7SJose Ricardo Ziviani
3296cf3b0334SMark Cave-Ayland helper_compute_fprf_float128(env, t.f128);
3297cf3b0334SMark Cave-Ayland *xt = t;
32983278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
3299917950d7SJose Ricardo Ziviani }
3300a4a68476SJose Ricardo Ziviani
helper_xssqrtqp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xt,ppc_vsr_t * xb)330199229620SMark Cave-Ayland void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode,
330299229620SMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xb)
3303a4a68476SJose Ricardo Ziviani {
3304cf3b0334SMark Cave-Ayland ppc_vsr_t t = { };
3305a4a68476SJose Ricardo Ziviani float_status tstat;
3306a4a68476SJose Ricardo Ziviani
3307a4a68476SJose Ricardo Ziviani helper_reset_fpstatus(env);
3308a4a68476SJose Ricardo Ziviani
3309a8d411abSBharata B Rao tstat = env->fp_status;
3310a4a68476SJose Ricardo Ziviani if (unlikely(Rc(opcode) != 0)) {
3311a8d411abSBharata B Rao tstat.float_rounding_mode = float_round_to_odd;
3312a4a68476SJose Ricardo Ziviani }
3313a4a68476SJose Ricardo Ziviani
3314a4a68476SJose Ricardo Ziviani set_float_exception_flags(0, &tstat);
3315cf3b0334SMark Cave-Ayland t.f128 = float128_sqrt(xb->f128, &tstat);
3316a4a68476SJose Ricardo Ziviani env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3317a4a68476SJose Ricardo Ziviani
3318a4a68476SJose Ricardo Ziviani if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
33193d3050ccSRichard Henderson float_invalid_op_sqrt(env, tstat.float_exception_flags, 1, GETPC());
3320a4a68476SJose Ricardo Ziviani }
3321a4a68476SJose Ricardo Ziviani
3322cf3b0334SMark Cave-Ayland helper_compute_fprf_float128(env, t.f128);
3323cf3b0334SMark Cave-Ayland *xt = t;
33243278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
3325a4a68476SJose Ricardo Ziviani }
3326f6b99afdSJose Ricardo Ziviani
helper_xssubqp(CPUPPCState * env,uint32_t opcode,ppc_vsr_t * xt,ppc_vsr_t * xa,ppc_vsr_t * xb)332723d0766bSMark Cave-Ayland void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
332823d0766bSMark Cave-Ayland ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
3329f6b99afdSJose Ricardo Ziviani {
3330cf3b0334SMark Cave-Ayland ppc_vsr_t t = *xt;
3331f6b99afdSJose Ricardo Ziviani float_status tstat;
3332f6b99afdSJose Ricardo Ziviani
3333f6b99afdSJose Ricardo Ziviani helper_reset_fpstatus(env);
3334f6b99afdSJose Ricardo Ziviani
3335a8d411abSBharata B Rao tstat = env->fp_status;
3336f6b99afdSJose Ricardo Ziviani if (unlikely(Rc(opcode) != 0)) {
3337a8d411abSBharata B Rao tstat.float_rounding_mode = float_round_to_odd;
3338f6b99afdSJose Ricardo Ziviani }
3339f6b99afdSJose Ricardo Ziviani
3340f6b99afdSJose Ricardo Ziviani set_float_exception_flags(0, &tstat);
3341cf3b0334SMark Cave-Ayland t.f128 = float128_sub(xa->f128, xb->f128, &tstat);
3342f6b99afdSJose Ricardo Ziviani env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3343f6b99afdSJose Ricardo Ziviani
3344f6b99afdSJose Ricardo Ziviani if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3345941298ecSRichard Henderson float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
3346f6b99afdSJose Ricardo Ziviani }
3347f6b99afdSJose Ricardo Ziviani
3348cf3b0334SMark Cave-Ayland helper_compute_fprf_float128(env, t.f128);
3349cf3b0334SMark Cave-Ayland *xt = t;
33503278677fSVíctor Colombo do_float_check_status(env, true, GETPC());
3351f6b99afdSJose Ricardo Ziviani }
3352c29018ccSLucas Mateus Castro (alqotel)
vsxger_excp(CPUPPCState * env,uintptr_t retaddr)3353c29018ccSLucas Mateus Castro (alqotel) static inline void vsxger_excp(CPUPPCState *env, uintptr_t retaddr)
3354c29018ccSLucas Mateus Castro (alqotel) {
3355c29018ccSLucas Mateus Castro (alqotel) /*
3356c29018ccSLucas Mateus Castro (alqotel) * XV*GER instructions execute and set the FPSCR as if exceptions
3357c29018ccSLucas Mateus Castro (alqotel) * are disabled and only at the end throw an exception
3358c29018ccSLucas Mateus Castro (alqotel) */
3359c29018ccSLucas Mateus Castro (alqotel) target_ulong enable;
3360c29018ccSLucas Mateus Castro (alqotel) enable = env->fpscr & (FP_ENABLES | FP_FI | FP_FR);
3361c29018ccSLucas Mateus Castro (alqotel) env->fpscr &= ~(FP_ENABLES | FP_FI | FP_FR);
3362c29018ccSLucas Mateus Castro (alqotel) int status = get_float_exception_flags(&env->fp_status);
3363c29018ccSLucas Mateus Castro (alqotel) if (unlikely(status & float_flag_invalid)) {
3364c29018ccSLucas Mateus Castro (alqotel) if (status & float_flag_invalid_snan) {
3365c29018ccSLucas Mateus Castro (alqotel) float_invalid_op_vxsnan(env, 0);
3366c29018ccSLucas Mateus Castro (alqotel) }
3367c29018ccSLucas Mateus Castro (alqotel) if (status & float_flag_invalid_imz) {
3368c29018ccSLucas Mateus Castro (alqotel) float_invalid_op_vximz(env, false, 0);
3369c29018ccSLucas Mateus Castro (alqotel) }
3370c29018ccSLucas Mateus Castro (alqotel) if (status & float_flag_invalid_isi) {
3371c29018ccSLucas Mateus Castro (alqotel) float_invalid_op_vxisi(env, false, 0);
3372c29018ccSLucas Mateus Castro (alqotel) }
3373c29018ccSLucas Mateus Castro (alqotel) }
3374c29018ccSLucas Mateus Castro (alqotel) do_float_check_status(env, false, retaddr);
3375c29018ccSLucas Mateus Castro (alqotel) env->fpscr |= enable;
3376c29018ccSLucas Mateus Castro (alqotel) do_fpscr_check_status(env, retaddr);
3377c29018ccSLucas Mateus Castro (alqotel) }
3378c29018ccSLucas Mateus Castro (alqotel)
33792d9cba74SLucas Mateus Castro (alqotel) typedef float64 extract_f16(float16, float_status *);
33802d9cba74SLucas Mateus Castro (alqotel)
extract_hf16(float16 in,float_status * fp_status)33812d9cba74SLucas Mateus Castro (alqotel) static float64 extract_hf16(float16 in, float_status *fp_status)
33822d9cba74SLucas Mateus Castro (alqotel) {
33832d9cba74SLucas Mateus Castro (alqotel) return float16_to_float64(in, true, fp_status);
33842d9cba74SLucas Mateus Castro (alqotel) }
33852d9cba74SLucas Mateus Castro (alqotel)
extract_bf16(bfloat16 in,float_status * fp_status)33865724e131SLucas Mateus Castro (alqotel) static float64 extract_bf16(bfloat16 in, float_status *fp_status)
33875724e131SLucas Mateus Castro (alqotel) {
33885724e131SLucas Mateus Castro (alqotel) return bfloat16_to_float64(in, fp_status);
33895724e131SLucas Mateus Castro (alqotel) }
33905724e131SLucas Mateus Castro (alqotel)
vsxger16(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask,bool acc,bool neg_mul,bool neg_acc,extract_f16 extract)33912d9cba74SLucas Mateus Castro (alqotel) static void vsxger16(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
33922d9cba74SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask, bool acc,
33932d9cba74SLucas Mateus Castro (alqotel) bool neg_mul, bool neg_acc, extract_f16 extract)
33942d9cba74SLucas Mateus Castro (alqotel) {
33952d9cba74SLucas Mateus Castro (alqotel) float32 r, aux_acc;
33962d9cba74SLucas Mateus Castro (alqotel) float64 psum, va, vb, vc, vd;
33972d9cba74SLucas Mateus Castro (alqotel) int i, j, xmsk_bit, ymsk_bit;
33982d9cba74SLucas Mateus Castro (alqotel) uint8_t pmsk = FIELD_EX32(mask, GER_MSK, PMSK),
33992d9cba74SLucas Mateus Castro (alqotel) xmsk = FIELD_EX32(mask, GER_MSK, XMSK),
34002d9cba74SLucas Mateus Castro (alqotel) ymsk = FIELD_EX32(mask, GER_MSK, YMSK);
34012d9cba74SLucas Mateus Castro (alqotel) float_status *excp_ptr = &env->fp_status;
34022d9cba74SLucas Mateus Castro (alqotel) for (i = 0, xmsk_bit = 1 << 3; i < 4; i++, xmsk_bit >>= 1) {
34032d9cba74SLucas Mateus Castro (alqotel) for (j = 0, ymsk_bit = 1 << 3; j < 4; j++, ymsk_bit >>= 1) {
34042d9cba74SLucas Mateus Castro (alqotel) if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) {
34052d9cba74SLucas Mateus Castro (alqotel) va = !(pmsk & 2) ? float64_zero :
34062d9cba74SLucas Mateus Castro (alqotel) extract(a->VsrHF(2 * i), excp_ptr);
34072d9cba74SLucas Mateus Castro (alqotel) vb = !(pmsk & 2) ? float64_zero :
34082d9cba74SLucas Mateus Castro (alqotel) extract(b->VsrHF(2 * j), excp_ptr);
34092d9cba74SLucas Mateus Castro (alqotel) vc = !(pmsk & 1) ? float64_zero :
34102d9cba74SLucas Mateus Castro (alqotel) extract(a->VsrHF(2 * i + 1), excp_ptr);
34112d9cba74SLucas Mateus Castro (alqotel) vd = !(pmsk & 1) ? float64_zero :
34122d9cba74SLucas Mateus Castro (alqotel) extract(b->VsrHF(2 * j + 1), excp_ptr);
34132d9cba74SLucas Mateus Castro (alqotel) psum = float64_mul(va, vb, excp_ptr);
34142d9cba74SLucas Mateus Castro (alqotel) psum = float64r32_muladd(vc, vd, psum, 0, excp_ptr);
34152d9cba74SLucas Mateus Castro (alqotel) r = float64_to_float32(psum, excp_ptr);
34162d9cba74SLucas Mateus Castro (alqotel) if (acc) {
34172d9cba74SLucas Mateus Castro (alqotel) aux_acc = at[i].VsrSF(j);
34182d9cba74SLucas Mateus Castro (alqotel) if (neg_mul) {
34192d9cba74SLucas Mateus Castro (alqotel) r = bfp32_neg(r);
34202d9cba74SLucas Mateus Castro (alqotel) }
34212d9cba74SLucas Mateus Castro (alqotel) if (neg_acc) {
34222d9cba74SLucas Mateus Castro (alqotel) aux_acc = bfp32_neg(aux_acc);
34232d9cba74SLucas Mateus Castro (alqotel) }
34242d9cba74SLucas Mateus Castro (alqotel) r = float32_add(r, aux_acc, excp_ptr);
34252d9cba74SLucas Mateus Castro (alqotel) }
34262d9cba74SLucas Mateus Castro (alqotel) at[i].VsrSF(j) = r;
34272d9cba74SLucas Mateus Castro (alqotel) } else {
34282d9cba74SLucas Mateus Castro (alqotel) at[i].VsrSF(j) = float32_zero;
34292d9cba74SLucas Mateus Castro (alqotel) }
34302d9cba74SLucas Mateus Castro (alqotel) }
34312d9cba74SLucas Mateus Castro (alqotel) }
34322d9cba74SLucas Mateus Castro (alqotel) vsxger_excp(env, GETPC());
34332d9cba74SLucas Mateus Castro (alqotel) }
34342d9cba74SLucas Mateus Castro (alqotel)
3435c29018ccSLucas Mateus Castro (alqotel) typedef void vsxger_zero(ppc_vsr_t *at, int, int);
3436c29018ccSLucas Mateus Castro (alqotel)
3437c29018ccSLucas Mateus Castro (alqotel) typedef void vsxger_muladd_f(ppc_vsr_t *, ppc_vsr_t *, ppc_vsr_t *, int, int,
3438c29018ccSLucas Mateus Castro (alqotel) int flags, float_status *s);
3439c29018ccSLucas Mateus Castro (alqotel)
vsxger_muladd32(ppc_vsr_t * at,ppc_vsr_t * a,ppc_vsr_t * b,int i,int j,int flags,float_status * s)3440c29018ccSLucas Mateus Castro (alqotel) static void vsxger_muladd32(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
3441c29018ccSLucas Mateus Castro (alqotel) int j, int flags, float_status *s)
3442c29018ccSLucas Mateus Castro (alqotel) {
3443c29018ccSLucas Mateus Castro (alqotel) at[i].VsrSF(j) = float32_muladd(a->VsrSF(i), b->VsrSF(j),
3444c29018ccSLucas Mateus Castro (alqotel) at[i].VsrSF(j), flags, s);
3445c29018ccSLucas Mateus Castro (alqotel) }
3446c29018ccSLucas Mateus Castro (alqotel)
vsxger_mul32(ppc_vsr_t * at,ppc_vsr_t * a,ppc_vsr_t * b,int i,int j,int flags,float_status * s)3447c29018ccSLucas Mateus Castro (alqotel) static void vsxger_mul32(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
3448c29018ccSLucas Mateus Castro (alqotel) int j, int flags, float_status *s)
3449c29018ccSLucas Mateus Castro (alqotel) {
3450c29018ccSLucas Mateus Castro (alqotel) at[i].VsrSF(j) = float32_mul(a->VsrSF(i), b->VsrSF(j), s);
3451c29018ccSLucas Mateus Castro (alqotel) }
3452c29018ccSLucas Mateus Castro (alqotel)
vsxger_zero32(ppc_vsr_t * at,int i,int j)3453c29018ccSLucas Mateus Castro (alqotel) static void vsxger_zero32(ppc_vsr_t *at, int i, int j)
3454c29018ccSLucas Mateus Castro (alqotel) {
3455c29018ccSLucas Mateus Castro (alqotel) at[i].VsrSF(j) = float32_zero;
3456c29018ccSLucas Mateus Castro (alqotel) }
3457c29018ccSLucas Mateus Castro (alqotel)
vsxger_muladd64(ppc_vsr_t * at,ppc_vsr_t * a,ppc_vsr_t * b,int i,int j,int flags,float_status * s)3458c29018ccSLucas Mateus Castro (alqotel) static void vsxger_muladd64(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
3459c29018ccSLucas Mateus Castro (alqotel) int j, int flags, float_status *s)
3460c29018ccSLucas Mateus Castro (alqotel) {
3461c29018ccSLucas Mateus Castro (alqotel) if (j >= 2) {
3462c29018ccSLucas Mateus Castro (alqotel) j -= 2;
3463c29018ccSLucas Mateus Castro (alqotel) at[i].VsrDF(j) = float64_muladd(a[i / 2].VsrDF(i % 2), b->VsrDF(j),
3464c29018ccSLucas Mateus Castro (alqotel) at[i].VsrDF(j), flags, s);
3465c29018ccSLucas Mateus Castro (alqotel) }
3466c29018ccSLucas Mateus Castro (alqotel) }
3467c29018ccSLucas Mateus Castro (alqotel)
vsxger_mul64(ppc_vsr_t * at,ppc_vsr_t * a,ppc_vsr_t * b,int i,int j,int flags,float_status * s)3468c29018ccSLucas Mateus Castro (alqotel) static void vsxger_mul64(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
3469c29018ccSLucas Mateus Castro (alqotel) int j, int flags, float_status *s)
3470c29018ccSLucas Mateus Castro (alqotel) {
3471c29018ccSLucas Mateus Castro (alqotel) if (j >= 2) {
3472c29018ccSLucas Mateus Castro (alqotel) j -= 2;
3473c29018ccSLucas Mateus Castro (alqotel) at[i].VsrDF(j) = float64_mul(a[i / 2].VsrDF(i % 2), b->VsrDF(j), s);
3474c29018ccSLucas Mateus Castro (alqotel) }
3475c29018ccSLucas Mateus Castro (alqotel) }
3476c29018ccSLucas Mateus Castro (alqotel)
vsxger_zero64(ppc_vsr_t * at,int i,int j)3477c29018ccSLucas Mateus Castro (alqotel) static void vsxger_zero64(ppc_vsr_t *at, int i, int j)
3478c29018ccSLucas Mateus Castro (alqotel) {
3479c29018ccSLucas Mateus Castro (alqotel) if (j >= 2) {
3480c29018ccSLucas Mateus Castro (alqotel) j -= 2;
3481c29018ccSLucas Mateus Castro (alqotel) at[i].VsrDF(j) = float64_zero;
3482c29018ccSLucas Mateus Castro (alqotel) }
3483c29018ccSLucas Mateus Castro (alqotel) }
3484c29018ccSLucas Mateus Castro (alqotel)
vsxger(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask,bool acc,bool neg_mul,bool neg_acc,vsxger_muladd_f mul,vsxger_muladd_f muladd,vsxger_zero zero)3485c29018ccSLucas Mateus Castro (alqotel) static void vsxger(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3486c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask, bool acc, bool neg_mul,
3487c29018ccSLucas Mateus Castro (alqotel) bool neg_acc, vsxger_muladd_f mul, vsxger_muladd_f muladd,
3488c29018ccSLucas Mateus Castro (alqotel) vsxger_zero zero)
3489c29018ccSLucas Mateus Castro (alqotel) {
3490c29018ccSLucas Mateus Castro (alqotel) int i, j, xmsk_bit, ymsk_bit, op_flags;
3491c29018ccSLucas Mateus Castro (alqotel) uint8_t xmsk = mask & 0x0F;
3492c29018ccSLucas Mateus Castro (alqotel) uint8_t ymsk = (mask >> 4) & 0x0F;
3493c29018ccSLucas Mateus Castro (alqotel) float_status *excp_ptr = &env->fp_status;
3494c29018ccSLucas Mateus Castro (alqotel) op_flags = (neg_acc ^ neg_mul) ? float_muladd_negate_c : 0;
3495c29018ccSLucas Mateus Castro (alqotel) op_flags |= (neg_mul) ? float_muladd_negate_result : 0;
3496c29018ccSLucas Mateus Castro (alqotel) helper_reset_fpstatus(env);
3497c29018ccSLucas Mateus Castro (alqotel) for (i = 0, xmsk_bit = 1 << 3; i < 4; i++, xmsk_bit >>= 1) {
3498c29018ccSLucas Mateus Castro (alqotel) for (j = 0, ymsk_bit = 1 << 3; j < 4; j++, ymsk_bit >>= 1) {
3499c29018ccSLucas Mateus Castro (alqotel) if ((xmsk_bit & xmsk) && (ymsk_bit & ymsk)) {
3500c29018ccSLucas Mateus Castro (alqotel) if (acc) {
3501c29018ccSLucas Mateus Castro (alqotel) muladd(at, a, b, i, j, op_flags, excp_ptr);
3502c29018ccSLucas Mateus Castro (alqotel) } else {
3503c29018ccSLucas Mateus Castro (alqotel) mul(at, a, b, i, j, op_flags, excp_ptr);
3504c29018ccSLucas Mateus Castro (alqotel) }
3505c29018ccSLucas Mateus Castro (alqotel) } else {
3506c29018ccSLucas Mateus Castro (alqotel) zero(at, i, j);
3507c29018ccSLucas Mateus Castro (alqotel) }
3508c29018ccSLucas Mateus Castro (alqotel) }
3509c29018ccSLucas Mateus Castro (alqotel) }
3510c29018ccSLucas Mateus Castro (alqotel) vsxger_excp(env, GETPC());
3511c29018ccSLucas Mateus Castro (alqotel) }
3512c29018ccSLucas Mateus Castro (alqotel)
3513c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVBF16GER2(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35145724e131SLucas Mateus Castro (alqotel) void helper_XVBF16GER2(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35155724e131SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35165724e131SLucas Mateus Castro (alqotel) {
35175724e131SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, false, false, false, extract_bf16);
35185724e131SLucas Mateus Castro (alqotel) }
35195724e131SLucas Mateus Castro (alqotel)
35205724e131SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVBF16GER2PP(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35215724e131SLucas Mateus Castro (alqotel) void helper_XVBF16GER2PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35225724e131SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35235724e131SLucas Mateus Castro (alqotel) {
35245724e131SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, true, false, false, extract_bf16);
35255724e131SLucas Mateus Castro (alqotel) }
35265724e131SLucas Mateus Castro (alqotel)
35275724e131SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVBF16GER2PN(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35285724e131SLucas Mateus Castro (alqotel) void helper_XVBF16GER2PN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35295724e131SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35305724e131SLucas Mateus Castro (alqotel) {
35315724e131SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, true, false, true, extract_bf16);
35325724e131SLucas Mateus Castro (alqotel) }
35335724e131SLucas Mateus Castro (alqotel)
35345724e131SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVBF16GER2NP(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35355724e131SLucas Mateus Castro (alqotel) void helper_XVBF16GER2NP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35365724e131SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35375724e131SLucas Mateus Castro (alqotel) {
35385724e131SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, true, true, false, extract_bf16);
35395724e131SLucas Mateus Castro (alqotel) }
35405724e131SLucas Mateus Castro (alqotel)
35415724e131SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVBF16GER2NN(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35425724e131SLucas Mateus Castro (alqotel) void helper_XVBF16GER2NN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35435724e131SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35445724e131SLucas Mateus Castro (alqotel) {
35455724e131SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, true, true, true, extract_bf16);
35465724e131SLucas Mateus Castro (alqotel) }
35475724e131SLucas Mateus Castro (alqotel)
35485724e131SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF16GER2(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35492d9cba74SLucas Mateus Castro (alqotel) void helper_XVF16GER2(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35502d9cba74SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35512d9cba74SLucas Mateus Castro (alqotel) {
35522d9cba74SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, false, false, false, extract_hf16);
35532d9cba74SLucas Mateus Castro (alqotel) }
35542d9cba74SLucas Mateus Castro (alqotel)
35552d9cba74SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF16GER2PP(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35562d9cba74SLucas Mateus Castro (alqotel) void helper_XVF16GER2PP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35572d9cba74SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35582d9cba74SLucas Mateus Castro (alqotel) {
35592d9cba74SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, true, false, false, extract_hf16);
35602d9cba74SLucas Mateus Castro (alqotel) }
35612d9cba74SLucas Mateus Castro (alqotel)
35622d9cba74SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF16GER2PN(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35632d9cba74SLucas Mateus Castro (alqotel) void helper_XVF16GER2PN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35642d9cba74SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35652d9cba74SLucas Mateus Castro (alqotel) {
35662d9cba74SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, true, false, true, extract_hf16);
35672d9cba74SLucas Mateus Castro (alqotel) }
35682d9cba74SLucas Mateus Castro (alqotel)
35692d9cba74SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF16GER2NP(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35702d9cba74SLucas Mateus Castro (alqotel) void helper_XVF16GER2NP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35712d9cba74SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35722d9cba74SLucas Mateus Castro (alqotel) {
35732d9cba74SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, true, true, false, extract_hf16);
35742d9cba74SLucas Mateus Castro (alqotel) }
35752d9cba74SLucas Mateus Castro (alqotel)
35762d9cba74SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF16GER2NN(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)35772d9cba74SLucas Mateus Castro (alqotel) void helper_XVF16GER2NN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
35782d9cba74SLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
35792d9cba74SLucas Mateus Castro (alqotel) {
35802d9cba74SLucas Mateus Castro (alqotel) vsxger16(env, a, b, at, mask, true, true, true, extract_hf16);
35812d9cba74SLucas Mateus Castro (alqotel) }
35822d9cba74SLucas Mateus Castro (alqotel)
35832d9cba74SLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF32GER(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3584c29018ccSLucas Mateus Castro (alqotel) void helper_XVF32GER(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3585c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3586c29018ccSLucas Mateus Castro (alqotel) {
3587c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, false, false, false, vsxger_mul32,
3588c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd32, vsxger_zero32);
3589c29018ccSLucas Mateus Castro (alqotel) }
3590c29018ccSLucas Mateus Castro (alqotel)
3591c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF32GERPP(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3592c29018ccSLucas Mateus Castro (alqotel) void helper_XVF32GERPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3593c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3594c29018ccSLucas Mateus Castro (alqotel) {
3595c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, true, false, false, vsxger_mul32,
3596c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd32, vsxger_zero32);
3597c29018ccSLucas Mateus Castro (alqotel) }
3598c29018ccSLucas Mateus Castro (alqotel)
3599c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF32GERPN(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3600c29018ccSLucas Mateus Castro (alqotel) void helper_XVF32GERPN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3601c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3602c29018ccSLucas Mateus Castro (alqotel) {
3603c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, true, false, true, vsxger_mul32,
3604c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd32, vsxger_zero32);
3605c29018ccSLucas Mateus Castro (alqotel) }
3606c29018ccSLucas Mateus Castro (alqotel)
3607c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF32GERNP(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3608c29018ccSLucas Mateus Castro (alqotel) void helper_XVF32GERNP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3609c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3610c29018ccSLucas Mateus Castro (alqotel) {
3611c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, true, true, false, vsxger_mul32,
3612c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd32, vsxger_zero32);
3613c29018ccSLucas Mateus Castro (alqotel) }
3614c29018ccSLucas Mateus Castro (alqotel)
3615c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF32GERNN(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3616c29018ccSLucas Mateus Castro (alqotel) void helper_XVF32GERNN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3617c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3618c29018ccSLucas Mateus Castro (alqotel) {
3619c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, true, true, true, vsxger_mul32,
3620c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd32, vsxger_zero32);
3621c29018ccSLucas Mateus Castro (alqotel) }
3622c29018ccSLucas Mateus Castro (alqotel)
3623c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF64GER(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3624c29018ccSLucas Mateus Castro (alqotel) void helper_XVF64GER(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3625c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3626c29018ccSLucas Mateus Castro (alqotel) {
3627c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, false, false, false, vsxger_mul64,
3628c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd64, vsxger_zero64);
3629c29018ccSLucas Mateus Castro (alqotel) }
3630c29018ccSLucas Mateus Castro (alqotel)
3631c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF64GERPP(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3632c29018ccSLucas Mateus Castro (alqotel) void helper_XVF64GERPP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3633c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3634c29018ccSLucas Mateus Castro (alqotel) {
3635c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, true, false, false, vsxger_mul64,
3636c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd64, vsxger_zero64);
3637c29018ccSLucas Mateus Castro (alqotel) }
3638c29018ccSLucas Mateus Castro (alqotel)
3639c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF64GERPN(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3640c29018ccSLucas Mateus Castro (alqotel) void helper_XVF64GERPN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3641c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3642c29018ccSLucas Mateus Castro (alqotel) {
3643c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, true, false, true, vsxger_mul64,
3644c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd64, vsxger_zero64);
3645c29018ccSLucas Mateus Castro (alqotel) }
3646c29018ccSLucas Mateus Castro (alqotel)
3647c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF64GERNP(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3648c29018ccSLucas Mateus Castro (alqotel) void helper_XVF64GERNP(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3649c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3650c29018ccSLucas Mateus Castro (alqotel) {
3651c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, true, true, false, vsxger_mul64,
3652c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd64, vsxger_zero64);
3653c29018ccSLucas Mateus Castro (alqotel) }
3654c29018ccSLucas Mateus Castro (alqotel)
3655c29018ccSLucas Mateus Castro (alqotel) QEMU_FLATTEN
helper_XVF64GERNN(CPUPPCState * env,ppc_vsr_t * a,ppc_vsr_t * b,ppc_acc_t * at,uint32_t mask)3656c29018ccSLucas Mateus Castro (alqotel) void helper_XVF64GERNN(CPUPPCState *env, ppc_vsr_t *a, ppc_vsr_t *b,
3657c29018ccSLucas Mateus Castro (alqotel) ppc_acc_t *at, uint32_t mask)
3658c29018ccSLucas Mateus Castro (alqotel) {
3659c29018ccSLucas Mateus Castro (alqotel) vsxger(env, a, b, at, mask, true, true, true, vsxger_mul64,
3660c29018ccSLucas Mateus Castro (alqotel) vsxger_muladd64, vsxger_zero64);
3661c29018ccSLucas Mateus Castro (alqotel) }
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