xref: /qemu/tests/tcg/xtensa/macros.inc (revision 7d6b9f0a)
1c09015ddSAnthony Liguori.macro test_suite name
2c09015ddSAnthony Liguori.data
3c09015ddSAnthony Liguoristatus: .word result
4c09015ddSAnthony Liguoriresult: .space 20
5c09015ddSAnthony Liguori.text
6c09015ddSAnthony Liguori.global main
7c09015ddSAnthony Liguori.align 4
8c09015ddSAnthony Liguorimain:
9c09015ddSAnthony Liguori.endm
10c09015ddSAnthony Liguori
11c09015ddSAnthony Liguori.macro reset_ps
12c09015ddSAnthony Liguori    movi    a2, 0x4000f
13c09015ddSAnthony Liguori    wsr     a2, ps
14c09015ddSAnthony Liguori    isync
15c09015ddSAnthony Liguori.endm
16c09015ddSAnthony Liguori
17c09015ddSAnthony Liguori.macro test_suite_end
18c09015ddSAnthony Liguori    reset_ps
19c09015ddSAnthony Liguori    movi    a0, status
20c09015ddSAnthony Liguori    l32i    a2, a0, 0
21c09015ddSAnthony Liguori    movi    a0, result
22c09015ddSAnthony Liguori    sub     a2, a2, a0
23c09015ddSAnthony Liguori    movi    a3, 0
24c09015ddSAnthony Liguori    loopnez a2, 1f
25c09015ddSAnthony Liguori    l8ui    a2, a0, 0
26c09015ddSAnthony Liguori    or      a3, a3, a2
27c09015ddSAnthony Liguori    addi    a0, a0, 1
28c09015ddSAnthony Liguori1:
29c09015ddSAnthony Liguori    exit
30c09015ddSAnthony Liguori.endm
31c09015ddSAnthony Liguori
32*7d6b9f0aSMax Filippov.macro print text
33*7d6b9f0aSMax Filippov.data
34*7d6b9f0aSMax Filippov97: .ascii "\text\n"
35*7d6b9f0aSMax Filippov98:
36*7d6b9f0aSMax Filippov    .align 4
37*7d6b9f0aSMax Filippov.text
38*7d6b9f0aSMax Filippov    movi    a2, 4
39*7d6b9f0aSMax Filippov    movi    a3, 2
40*7d6b9f0aSMax Filippov    movi    a4, 97b
41*7d6b9f0aSMax Filippov    movi    a5, 98b
42*7d6b9f0aSMax Filippov    sub     a5, a5, a4
43*7d6b9f0aSMax Filippov    simcall
44*7d6b9f0aSMax Filippov.endm
45*7d6b9f0aSMax Filippov
46c09015ddSAnthony Liguori.macro test name
47*7d6b9f0aSMax Filippov    //print test_\name
48*7d6b9f0aSMax Filippovtest_\name:
49*7d6b9f0aSMax Filippov.global test_\name
50c09015ddSAnthony Liguori.endm
51c09015ddSAnthony Liguori
52c09015ddSAnthony Liguori.macro test_end
53c09015ddSAnthony Liguori99:
54c09015ddSAnthony Liguori    reset_ps
55c09015ddSAnthony Liguori    movi    a2, status
56c09015ddSAnthony Liguori    l32i    a3, a2, 0
57c09015ddSAnthony Liguori    addi    a3, a3, 1
58c09015ddSAnthony Liguori    s32i    a3, a2, 0
59c09015ddSAnthony Liguori.endm
60c09015ddSAnthony Liguori
61c09015ddSAnthony Liguori.macro exit
62c09015ddSAnthony Liguori    movi    a2, 1
63c09015ddSAnthony Liguori    simcall
64c09015ddSAnthony Liguori.endm
65c09015ddSAnthony Liguori
66c09015ddSAnthony Liguori.macro test_fail
67c09015ddSAnthony Liguori    movi    a2, status
68c09015ddSAnthony Liguori    l32i    a2, a2, 0
69c09015ddSAnthony Liguori    movi    a3, 1
70c09015ddSAnthony Liguori    s8i     a3, a2, 0
71c09015ddSAnthony Liguori    j       99f
72c09015ddSAnthony Liguori.endm
73c09015ddSAnthony Liguori
74c09015ddSAnthony Liguori.macro assert cond, arg1, arg2
75c09015ddSAnthony Liguori    b\cond  \arg1, \arg2, 90f
76c09015ddSAnthony Liguori    test_fail
77c09015ddSAnthony Liguori90:
78c09015ddSAnthony Liguori    nop
79c09015ddSAnthony Liguori.endm
80c09015ddSAnthony Liguori
81c09015ddSAnthony Liguori.macro set_vector vector, addr
82c09015ddSAnthony Liguori    movi    a2, handler_\vector
83c09015ddSAnthony Liguori    movi    a3, \addr
84c09015ddSAnthony Liguori    s32i    a3, a2, 0
85c09015ddSAnthony Liguori.endm
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