xref: /reactos/boot/armllb/hw/omap3-zoom2/hwlcd.c (revision 9393fc32)
1*c2c66affSColin Finck /*
2*c2c66affSColin Finck  * PROJECT:         ReactOS Boot Loader
3*c2c66affSColin Finck  * LICENSE:         BSD - See COPYING.ARM in the top level directory
4*c2c66affSColin Finck  * FILE:            boot/armllb/hw/omap3-zoom2/hwlcd.c
5*c2c66affSColin Finck  * PURPOSE:         LLB LCD Routines for OMAP3 ZOOM2
6*c2c66affSColin Finck  * PROGRAMMERS:     ReactOS Portable Systems Group
7*c2c66affSColin Finck  */
8*c2c66affSColin Finck 
9*c2c66affSColin Finck #include "precomp.h"
10*c2c66affSColin Finck 
11*c2c66affSColin Finck PUSHORT LlbHwVideoBuffer;
12*c2c66affSColin Finck 
13*c2c66affSColin Finck VOID
14*c2c66affSColin Finck NTAPI
LlbHwOmap3LcdInitialize(VOID)15*c2c66affSColin Finck LlbHwOmap3LcdInitialize(VOID)
16*c2c66affSColin Finck {
17*c2c66affSColin Finck     /*
18*c2c66affSColin Finck      * N.B. The following initialization sequence took about 12 months to figure
19*c2c66affSColin Finck      *      out.
20*c2c66affSColin Finck      *      This means if you are glancing at it and have no idea what on Earth
21*c2c66affSColin Finck      *      could possibly be going on, this is *normal*.
22*c2c66affSColin Finck      *      Just trust that this turns on the LCD.
23*c2c66affSColin Finck      *      And be thankful all you ever have to worry about is Java and HTML.
24*c2c66affSColin Finck      */
25*c2c66affSColin Finck 
26*c2c66affSColin Finck     /* Turn on the functional and interface clocks in the entire PER domain */
27*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48005000, 0x3ffff);  /* Functional clocks */
28*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48005010, 0x3ffff);  /* Interface clocks */
29*c2c66affSColin Finck 
30*c2c66affSColin Finck     /* Now that GPIO Module 3 is on, send a reset to the LCD panel on GPIO 96 */
31*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x49054034, 0);             /* FIXME: Enable all as output */
32*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x49054094, 0xffffffff);    /* FIXME: Output on all gpios */
33*c2c66affSColin Finck 
34*c2c66affSColin Finck     /* Now turn on the functional and interface clocks in the CORE domain */
35*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48004a00, 0x03fffe29); /* Functional clocks */
36*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48004a10, 0x3ffffffb); /* Interface clocks */
37*c2c66affSColin Finck 
38*c2c66affSColin Finck     /* The HS I2C interface is now on, configure it */
39*c2c66affSColin Finck     WRITE_REGISTER_USHORT(0x48070024, 0x0);    /* Disable I2c */
40*c2c66affSColin Finck     WRITE_REGISTER_USHORT(0x48070030, 0x17);   /* Configure clock divider */
41*c2c66affSColin Finck     WRITE_REGISTER_USHORT(0x48070034, 0xd);    /* Configure clock scaler */
42*c2c66affSColin Finck     WRITE_REGISTER_USHORT(0x48070038, 0xf);    /* Configure clock scaler */
43*c2c66affSColin Finck     WRITE_REGISTER_USHORT(0x48070020, 0x215);  /* Configure clocks and idle */
44*c2c66affSColin Finck     WRITE_REGISTER_USHORT(0x4807000c, 0x636f); /* Select wakeup bits */
45*c2c66affSColin Finck     WRITE_REGISTER_USHORT(0x48070014, 0x4343); /* Disable DMA */
46*c2c66affSColin Finck     WRITE_REGISTER_USHORT(0x48070024, 0x8000); /* Enable I2C */
47*c2c66affSColin Finck 
48*c2c66affSColin Finck     /*
49*c2c66affSColin Finck      * Set the VPLL2 to cover all device groups instead of just P3.
50*c2c66affSColin Finck      * This essentially enables the VRRTC to power up the LCD panel.
51*c2c66affSColin Finck      */
52*c2c66affSColin Finck     LlbHwOmap3TwlWrite1(0x4B, 0x8E, 0xE0);
53*c2c66affSColin Finck 
54*c2c66affSColin Finck     /* VPLL2 runs at 1.2V by default, so we need to reprogram to 1.8V for DVI */
55*c2c66affSColin Finck     LlbHwOmap3TwlWrite1(0x4B, 0x91, 0x05);
56*c2c66affSColin Finck 
57*c2c66affSColin Finck     /* Set GPIO pin 7 on the TWL4030 as an output pin */
58*c2c66affSColin Finck     LlbHwOmap3TwlWrite1(0x49, 0x9B, 0x80);
59*c2c66affSColin Finck 
60*c2c66affSColin Finck     /* Set GPIO pin 7 signal on the TWL4030 ON. This powers the LCD backlight */
61*c2c66affSColin Finck     LlbHwOmap3TwlWrite1(0x49, 0xA4, 0x80);
62*c2c66affSColin Finck 
63*c2c66affSColin Finck     /* Now go on the McSPI interface and program it on for the channel */
64*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48098010, 0x15);
65*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48098020, 0x1);
66*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48098028, 0x1);
67*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x4809802c, 0x112fdc);
68*c2c66affSColin Finck 
69*c2c66affSColin Finck     /* Send the reset signal (R2 = 00h) to the NEC WVGA LCD Panel */
70*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48098034, 0x1);
71*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48098038, 0x20100);
72*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48098034, 0x0);
73*c2c66affSColin Finck 
74*c2c66affSColin Finck     /* Turn on the functional and interface clocks in the DSS domain */
75*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48004e00, 0x5);
76*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48004e10, 0x1);
77*c2c66affSColin Finck 
78*c2c66affSColin Finck     /* Reset the Display Controller (DISPC) */
79*c2c66affSColin Finck     WRITE_REGISTER_ULONG(0x48050410, 0x00000005); // DISPC_SYSCONFIG
80*c2c66affSColin Finck 
81*c2c66affSColin Finck     /* Set the frame buffer address */
82*c2c66affSColin Finck 	WRITE_REGISTER_ULONG(0x48050480, 0x800A0000); // DISPC_GFX_BA0
83*c2c66affSColin Finck 
84*c2c66affSColin Finck 	/* Set resolution and RGB16 color mode */
85*c2c66affSColin Finck 	WRITE_REGISTER_ULONG(0x4805048c, 0x01df031f); // DISPC_GFX_SIZE
86*c2c66affSColin Finck 	WRITE_REGISTER_ULONG(0x480504a0, 0x0000000d); // DISPC_GFX_ATTRIBUTES
87*c2c66affSColin Finck 
88*c2c66affSColin Finck     /* Set LCD timings (VSync and HSync), pixel clock, and LCD size */
89*c2c66affSColin Finck 	WRITE_REGISTER_ULONG(0x4805046c, 0x00003000); // DISPC_POL_FREQ
90*c2c66affSColin Finck 	WRITE_REGISTER_ULONG(0x48050470, 0x00010004); // DISPC_DIVISOR
91*c2c66affSColin Finck 	WRITE_REGISTER_ULONG(0x48050464, 0x00300500); // DISPC_TIMING_H
92*c2c66affSColin Finck 	WRITE_REGISTER_ULONG(0x48050468, 0x00400300); // DISPC_TIMING_V
93*c2c66affSColin Finck 	WRITE_REGISTER_ULONG(0x4805047c, 0x01df031f); // DISPC_SIZE_LCD
94*c2c66affSColin Finck 
95*c2c66affSColin Finck     /* Turn the LCD on */
96*c2c66affSColin Finck 	WRITE_REGISTER_ULONG(0x48050440, 0x00018309); // DISPC_CONTROL
97*c2c66affSColin Finck }
98*c2c66affSColin Finck 
99*c2c66affSColin Finck ULONG
100*c2c66affSColin Finck NTAPI
LlbHwGetScreenWidth(VOID)101*c2c66affSColin Finck LlbHwGetScreenWidth(VOID)
102*c2c66affSColin Finck {
103*c2c66affSColin Finck     return 800;
104*c2c66affSColin Finck }
105*c2c66affSColin Finck 
106*c2c66affSColin Finck ULONG
107*c2c66affSColin Finck NTAPI
LlbHwGetScreenHeight(VOID)108*c2c66affSColin Finck LlbHwGetScreenHeight(VOID)
109*c2c66affSColin Finck {
110*c2c66affSColin Finck     return 480;
111*c2c66affSColin Finck }
112*c2c66affSColin Finck 
113*c2c66affSColin Finck PVOID
114*c2c66affSColin Finck NTAPI
LlbHwGetFrameBuffer(VOID)115*c2c66affSColin Finck LlbHwGetFrameBuffer(VOID)
116*c2c66affSColin Finck {
117*c2c66affSColin Finck     return (PVOID)0x800A0000;
118*c2c66affSColin Finck }
119*c2c66affSColin Finck 
120*c2c66affSColin Finck ULONG
121*c2c66affSColin Finck NTAPI
LlbHwVideoCreateColor(IN ULONG Red,IN ULONG Green,IN ULONG Blue)122*c2c66affSColin Finck LlbHwVideoCreateColor(IN ULONG Red,
123*c2c66affSColin Finck                       IN ULONG Green,
124*c2c66affSColin Finck                       IN ULONG Blue)
125*c2c66affSColin Finck {
126*c2c66affSColin Finck     return (((Red >> 3) << 11)| ((Green >> 2) << 5)| ((Blue >> 3) << 0));
127*c2c66affSColin Finck }
128*c2c66affSColin Finck 
129*c2c66affSColin Finck /* EOF */
130