1 /* 2 * PROJECT: ReactOS VGA Miniport Driver 3 * LICENSE: Microsoft NT4 DDK Sample Code License 4 * PURPOSE: Definitions for VGA 5 * PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation 6 * ReactOS Portable Systems Group 7 */ 8 9 #ifndef _BOOTVID_VGA_H_ 10 #define _BOOTVID_VGA_H_ 11 12 #pragma once 13 14 #include "cmdcnst.h" 15 16 // 17 // Base address of VGA memory range. Also used as base address of VGA 18 // memory when loading a font, which is done with the VGA mapped at A0000. 19 // 20 21 #define MEM_VGA 0xA0000 22 #define MEM_VGA_SIZE 0x20000 23 24 // 25 // For memory mapped IO 26 // 27 28 #define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000) 29 30 // 31 // Port definitions for filling the ACCESS_RANGES structure in the miniport 32 // information, defines the range of I/O ports the VGA spans. 33 // There is a break in the IO ports - a few ports are used for the parallel 34 // port. Those cannot be defined in the ACCESS_RANGE, but are still mapped 35 // so all VGA ports are in one address range. 36 // 37 38 #define VGA_BASE_IO_PORT 0x000003B0 39 #define VGA_START_BREAK_PORT 0x000003BB 40 #define VGA_END_BREAK_PORT 0x000003C0 41 #define VGA_MAX_IO_PORT 0x000003DF 42 43 // 44 // VGA register definitions 45 // 46 // eVb: 3.1 [VGA] - Use offsets from the VGA Port Address instead of absolute 47 #define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and 48 #define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode 49 #define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port 50 // in mono mode 51 #define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read 52 // port in mono mode 53 #define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO 54 // Register to read to reset 55 // Attribute Controller index/data 56 57 #define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and 58 #define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port 59 // for writes, but only Address is 60 // readable at 0x3C0 61 #define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is 62 // readable here 63 #define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write 64 // port 65 #define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read 66 // port 67 #define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the 68 // entire VGA subsystem 69 #define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and 70 #define SEQ_DATA_PORT 0x0015 // Data registers 71 #define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg 72 #define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg, 73 // write-only 74 #define DAC_STATE_PORT 0x0017 // DAC state (read/write), 75 // read-only 76 #define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg 77 #define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg 78 #define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port 79 #define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read 80 // port 81 #define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address 82 #define GRAPH_DATA_PORT 0x001F // and Data registers 83 84 #define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and 85 #define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode 86 #define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port 87 #define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read 88 // port in color mode 89 // eVb: 3.2 [END] 90 #define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR 91 // Register to read to reset 92 // Attribute Controller index/data 93 // toggle in color mode 94 95 // 96 // VGA indexed register indexes. 97 // 98 99 #define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start 100 #define IND_CURSOR_END 0x0B // and End registers 101 #define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location 102 #define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers 103 #define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync 104 // End register, which has the bit 105 // that protects/unprotects CRTC 106 // index registers 0-7 107 #define IND_CR2C 0x2C // Nordic LCD Interface Register 108 #define IND_CR2D 0x2D // Nordic LCD Display Control 109 #define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC 110 #define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC 111 #define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr 112 #define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr 113 #define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr 114 #define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr 115 #define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq 116 #define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer 117 #define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq 118 #define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in 119 // CRTC 120 #define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg 121 // in CRTC 122 #define IND_PERF_TUNING 0x16 // index of performance tuning in Seq 123 #define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start 124 // synchronous reset 125 #define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end 126 // synchronous reset 127 128 // 129 // Values for Attribute Controller Index register to turn video off 130 // and on, by setting bit 5 to 0 (off) or 1 (on). 131 // 132 133 #define VIDEO_DISABLE 0 134 #define VIDEO_ENABLE 0x20 135 136 #define INDEX_ENABLE_AUTO_START 0x31 137 138 // Masks to keep only the significant bits of the Graphics Controller and 139 // Sequencer Address registers. Masking is necessary because some VGAs, such 140 // as S3-based ones, don't return unused bits set to 0, and some SVGAs use 141 // these bits if extensions are enabled. 142 // 143 144 #define GRAPH_ADDR_MASK 0x0F 145 #define SEQ_ADDR_MASK 0x07 146 147 // 148 // Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register. 149 // 150 151 #define CHAIN4_MASK 0x08 152 153 // 154 // Value written to the Read Map register when identifying the existence of 155 // a VGA in VgaInitialize. This value must be different from the final test 156 // value written to the Bit Mask in that routine. 157 // 158 159 #define READ_MAP_TEST_SETTING 0x03 160 161 // 162 // Default text mode setting for various registers, used to restore their 163 // states if VGA detection fails after they've been modified. 164 // 165 166 #define MEMORY_MODE_TEXT_DEFAULT 0x02 167 #define BIT_MASK_DEFAULT 0xFF 168 #define READ_MAP_DEFAULT 0x00 169 170 171 // 172 // Palette-related info. 173 // 174 175 // 176 // Highest valid DAC color register index. 177 // 178 179 #define VIDEO_MAX_COLOR_REGISTER 0xFF 180 181 // 182 // Highest valid palette register index 183 // 184 185 #define VIDEO_MAX_PALETTE_REGISTER 0x0F 186 187 // 188 // Mode into which to put the VGA before starting a VDM, so it's a plain 189 // vanilla VGA. (This is the mode's index in ModesVGA[], currently standard 190 // 80x25 text mode.) 191 // 192 193 #define DEFAULT_MODE 0 194 195 // 196 // Number of bytes to save in each plane. 197 // 198 199 #define VGA_PLANE_SIZE 0x10000 200 201 // 202 // Number of each type of indexed register in a standard VGA, used by 203 // validator and state save/restore functions. 204 // 205 // Note: VDMs currently only support basic VGAs only. 206 // 207 208 #define VGA_NUM_SEQUENCER_PORTS 5 209 #define VGA_NUM_CRTC_PORTS 25 210 #define VGA_NUM_GRAPH_CONT_PORTS 9 211 #define VGA_NUM_ATTRIB_CONT_PORTS 21 212 #define VGA_NUM_DAC_ENTRIES 256 213 214 #define EXT_NUM_GRAPH_CONT_PORTS 0 215 #define EXT_NUM_SEQUENCER_PORTS 0 216 #define EXT_NUM_CRTC_PORTS 0 217 #define EXT_NUM_ATTRIB_CONT_PORTS 0 218 #define EXT_NUM_DAC_ENTRIES 0 219 220 #endif /* _BOOTVID_VGA_H_ */ 221