1 /* 2 * PROJECT: PCI IDE bus driver extension 3 * LICENSE: See COPYING in the top level directory 4 * PURPOSE: Common header file 5 * COPYRIGHT: Copyright 2005 Hervé Poussineau <hpoussin@reactos.org> 6 * Copyright 2023 Dmitry Borisov <di.sean@protonmail.com> 7 */ 8 9 #ifndef _PCIIDEX_PCH_ 10 #define _PCIIDEX_PCH_ 11 12 #include <ntddk.h> 13 #include <ntstrsafe.h> 14 #include <ntintsafe.h> 15 #include <initguid.h> 16 #include <wdmguid.h> 17 #include <ide.h> 18 19 #define TAG_PCIIDEX 'XedI' 20 21 #define IS_FDO(p) (((PCOMMON_DEVICE_EXTENSION)(p))->IsFDO) 22 23 #define IS_PRIMARY_CHANNEL(PdoExtension) (PdoExtension->Channel == 0) 24 25 /* 26 * Legacy ranges and interrupts 27 */ 28 #define PCIIDE_LEGACY_RESOURCE_COUNT 3 29 #define PCIIDE_LEGACY_COMMAND_IO_RANGE_LENGTH 8 30 #define PCIIDE_LEGACY_CONTROL_IO_RANGE_LENGTH 1 31 #define PCIIDE_LEGACY_PRIMARY_COMMAND_BASE 0x1F0 32 #define PCIIDE_LEGACY_PRIMARY_CONTROL_BASE 0x3F6 33 #define PCIIDE_LEGACY_PRIMARY_IRQ 14 34 #define PCIIDE_LEGACY_SECONDARY_COMMAND_BASE 0x170 35 #define PCIIDE_LEGACY_SECONDARY_CONTROL_BASE 0x376 36 #define PCIIDE_LEGACY_SECONDARY_IRQ 15 37 38 /* 39 * Programming Interface Register 40 */ 41 #define PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE 0x01 42 #define PCIIDE_PROGIF_PRIMARY_CHANNEL_NATIVE_MODE_CAPABLE 0x02 43 #define PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE 0x04 44 #define PCIIDE_PROGIF_SECONDARY_CHANNEL_NATIVE_MODE_CAPABLE 0x08 45 #define PCIIDE_PROGIF_DMA_CAPABLE 0x80 46 47 #define BM_SECONDARY_CHANNEL_OFFSET 8 48 49 typedef struct _PDO_DEVICE_EXTENSION PDO_DEVICE_EXTENSION, *PPDO_DEVICE_EXTENSION; 50 51 typedef struct _PCIIDEX_DRIVER_EXTENSION 52 { 53 PCONTROLLER_PROPERTIES HwGetControllerProperties; 54 ULONG MiniControllerExtensionSize; 55 } PCIIDEX_DRIVER_EXTENSION, *PPCIIDEX_DRIVER_EXTENSION; 56 57 typedef struct _COMMON_DEVICE_EXTENSION 58 { 59 BOOLEAN IsFDO; 60 PDEVICE_OBJECT Self; 61 62 _Write_guarded_by_(_Global_interlock_) 63 volatile LONG PageFiles; 64 65 _Write_guarded_by_(_Global_interlock_) 66 volatile LONG HibernateFiles; 67 68 _Write_guarded_by_(_Global_interlock_) 69 volatile LONG DumpFiles; 70 } COMMON_DEVICE_EXTENSION, *PCOMMON_DEVICE_EXTENSION; 71 72 typedef struct _FDO_DEVICE_EXTENSION 73 { 74 COMMON_DEVICE_EXTENSION Common; 75 PDEVICE_OBJECT Ldo; 76 77 ULONG ControllerNumber; 78 BOOLEAN InNativeMode; 79 BOOLEAN IoBaseMapped; 80 BOOLEAN MiniportStarted; 81 82 FAST_MUTEX DeviceSyncMutex; 83 _Guarded_by_(DeviceSyncMutex) 84 PPDO_DEVICE_EXTENSION Channels[MAX_IDE_CHANNEL]; 85 86 USHORT VendorId; 87 USHORT DeviceId; 88 PDRIVER_OBJECT DriverObject; 89 PUCHAR BusMasterPortBase; 90 91 KSPIN_LOCK BusDataLock; 92 BUS_INTERFACE_STANDARD BusInterface; 93 94 IDE_CONTROLLER_PROPERTIES Properties; 95 96 /* Must be the last entry */ 97 PUCHAR MiniControllerExtension[0]; 98 } FDO_DEVICE_EXTENSION, *PFDO_DEVICE_EXTENSION; 99 100 typedef struct _PDO_DEVICE_EXTENSION 101 { 102 COMMON_DEVICE_EXTENSION Common; 103 ULONG Channel; 104 PFDO_DEVICE_EXTENSION ParentController; 105 BOOLEAN ReportedMissing; 106 PUCHAR IoBase; 107 } PDO_DEVICE_EXTENSION, *PPDO_DEVICE_EXTENSION; 108 109 CODE_SEG("PAGE") 110 DRIVER_INITIALIZE DriverEntry; 111 112 CODE_SEG("PAGE") 113 DRIVER_UNLOAD PciIdeXUnload; 114 115 CODE_SEG("PAGE") 116 DRIVER_ADD_DEVICE PciIdeXAddDevice; 117 118 _Dispatch_type_(IRP_MJ_PNP) 119 CODE_SEG("PAGE") 120 DRIVER_DISPATCH_PAGED PciIdeXDispatchPnp; 121 122 _Dispatch_type_(IRP_MJ_SYSTEM_CONTROL) 123 CODE_SEG("PAGE") 124 DRIVER_DISPATCH_PAGED PciIdeXDispatchWmi; 125 126 _Dispatch_type_(IRP_MJ_POWER) 127 DRIVER_DISPATCH_RAISED PciIdeXDispatchPower; 128 129 CODE_SEG("PAGE") 130 NTSTATUS 131 PciIdeXFdoDispatchPnp( 132 _In_ PFDO_DEVICE_EXTENSION FdoExtension, 133 _Inout_ PIRP Irp); 134 135 CODE_SEG("PAGE") 136 NTSTATUS 137 PciIdeXStartMiniport( 138 _In_ PFDO_DEVICE_EXTENSION FdoExtension); 139 140 CODE_SEG("PAGE") 141 IDE_CHANNEL_STATE 142 PciIdeXChannelState( 143 _In_ PFDO_DEVICE_EXTENSION FdoExtension, 144 _In_ ULONG Channel); 145 146 #endif /* _PCIIDEX_PCH_ */ 147