1 /* 2 * kernel internal memory management definitions for amd64 3 */ 4 #pragma once 5 6 #define _MI_PAGING_LEVELS 4 7 #define _MI_HAS_NO_EXECUTE 1 8 9 /* Memory layout base addresses (This is based on Vista!) */ 10 #define MI_USER_PROBE_ADDRESS (PVOID)0x000007FFFFFF0000ULL 11 #define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0xFFFF080000000000ULL 12 #define MI_REAL_SYSTEM_RANGE_START 0xFFFF800000000000ULL 13 //#define MI_PAGE_TABLE_BASE 0xFFFFF68000000000ULL // 512 GB page tables 14 #define HYPER_SPACE 0xFFFFF70000000000ULL // 512 GB hyper space [MiVaProcessSpace] 15 #define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL 16 //#define MI_SHARED_SYSTEM_PAGE 0xFFFFF78000000000ULL 17 #define MI_SYSTEM_CACHE_WS_START 0xFFFFF78000001000ULL // 512 GB - 4 KB system cache working set 18 //#define MI_LOADER_MAPPINGS 0xFFFFF80000000000ULL // 512 GB loader mappings aka KSEG0_BASE (NDK) [MiVaBootLoaded] 19 #define MM_SYSTEM_SPACE_START 0xFFFFF88000000000ULL // 128 GB system PTEs [MiVaSystemPtes] 20 #define MI_DEBUG_MAPPING (PVOID)0xFFFFF89FFFFFF000ULL // FIXME should be allocated from System PTEs 21 #define MI_PAGED_POOL_START (PVOID)0xFFFFF8A000000000ULL // 128 GB paged pool [MiVaPagedPool] 22 //#define MI_PAGED_POOL_END 0xFFFFF8BFFFFFFFFFULL 23 //#define MI_SESSION_SPACE_START 0xFFFFF90000000000ULL // 512 GB session space [MiVaSessionSpace] 24 #define MI_SESSION_VIEW_END 0xFFFFF97FFF000000ULL 25 #define MI_SESSION_SPACE_END 0xFFFFF97FFFFFFFFFULL 26 #define MI_SYSTEM_CACHE_START 0xFFFFF98000000000ULL // 1 TB system cache (on Vista+ this is dynamic VA space) [MiVaSystemCache,MiVaSpecialPoolPaged,MiVaSpecialPoolNonPaged] 27 #define MI_SYSTEM_CACHE_END 0xFFFFFA7FFFFFFFFFULL 28 #define MI_PFN_DATABASE 0xFFFFFA8000000000ULL // up to 5.5 TB PFN database followed by non paged pool [MiVaPfnDatabase/MiVaNonPagedPool] 29 #define MI_NONPAGED_POOL_END (PVOID)0xFFFFFFFFFFBFFFFFULL 30 //#define MM_HAL_VA_START 0xFFFFFFFFFFC00000ULL // 4 MB HAL mappings, defined in NDK [MiVaHal] 31 #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL 32 #define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START) 33 34 /* WOW64 address definitions */ 35 #define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF 36 #define MM_SYSTEM_RANGE_START_WOW64 0x80000000 37 38 /* Misc address definitions */ 39 //#define MI_NON_PAGED_SYSTEM_START_MIN MM_SYSTEM_SPACE_START // FIXME 40 //#define MI_SYSTEM_PTE_START MM_SYSTEM_SPACE_START 41 //#define MI_SYSTEM_PTE_END (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1) 42 #define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(KSEG0_BASE) 43 #define MM_HIGHEST_VAD_ADDRESS (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE)) 44 #define MI_MAPPING_RANGE_START HYPER_SPACE 45 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE) 46 #define MI_DUMMY_PTE (MI_MAPPING_RANGE_END + PAGE_SIZE) 47 #define MI_VAD_BITMAP (MI_DUMMY_PTE + PAGE_SIZE) 48 #define MI_WORKING_SET_LIST (MI_VAD_BITMAP + PAGE_SIZE) 49 50 /* Memory sizes */ 51 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT) 52 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT) 53 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT) 54 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT) 55 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB) 56 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) 57 #define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024) 58 #define MI_SYSTEM_VIEW_SIZE (16 * _1MB) 59 #define MI_SESSION_VIEW_SIZE (20 * _1MB) 60 #define MI_SESSION_POOL_SIZE (16 * _1MB) 61 #define MI_SESSION_IMAGE_SIZE (8 * _1MB) 62 #define MI_SESSION_WORKING_SET_SIZE (4 * _1MB) 63 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \ 64 MI_SESSION_POOL_SIZE + \ 65 MI_SESSION_IMAGE_SIZE + \ 66 MI_SESSION_WORKING_SET_SIZE) 67 #define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB) 68 #define MI_ALLOCATION_FRAGMENT (64 * _1KB) 69 #define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB) 70 71 /* Misc constants */ 72 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5 73 #define MI_MIN_SECONDARY_COLORS 8 74 #define MI_SECONDARY_COLORS 64 75 #define MI_MAX_SECONDARY_COLORS 1024 76 #define MI_NUMBER_SYSTEM_PTES 22000 77 #define MI_MAX_FREE_PAGE_LISTS 4 78 #define MI_HYPERSPACE_PTES (256 - 1) 79 #define MI_ZERO_PTES (32) 80 #define MI_MAX_ZERO_BITS 53 81 #define SESSION_POOL_LOOKASIDES 21 82 83 /* MMPTE related defines */ 84 #define MM_EMPTY_PTE_LIST ((ULONG64)0xFFFFFFFF) 85 #define MM_EMPTY_LIST ((ULONG_PTR)-1) 86 87 88 /* Easy accessing PFN in PTE */ 89 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber) 90 #define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber) 91 #define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber) 92 #define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber) 93 94 /* Macros for portable PTE modification */ 95 #define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1) 96 #define MI_MAKE_CLEAN_PAGE(x) ((x)->u.Hard.Dirty = 0) 97 #define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1) 98 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1) 99 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1) 100 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0) 101 #define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1) 102 #if !defined(CONFIG_SMP) 103 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1) 104 #else 105 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1) 106 #endif 107 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1) 108 #define MI_IS_PAGE_EXECUTABLE(x) ((x)->u.Hard.NoExecute == 0) 109 #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1) 110 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1) 111 #if !defined(CONFIG_SMP) 112 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1) 113 #else 114 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1) 115 #endif 116 117 /* Macros to identify the page fault reason from the error code */ 118 #define MI_IS_NOT_PRESENT_FAULT(FaultCode) !BooleanFlagOn(FaultCode, 0x1) 119 #define MI_IS_WRITE_ACCESS(FaultCode) BooleanFlagOn(FaultCode, 0x2) 120 #define MI_IS_INSTRUCTION_FETCH(FaultCode) BooleanFlagOn(FaultCode, 0x10) 121 122 /* On x64, these are the same */ 123 #define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE 124 #define ValidKernelPpe ValidKernelPde 125 126 /* Convert an address to a corresponding PTE */ 127 FORCEINLINE 128 PMMPTE 129 _MiAddressToPte(PVOID Address) 130 { 131 ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3); 132 Offset &= 0xFFFFFFFFFULL << 3; 133 return (PMMPTE)(PTE_BASE + Offset); 134 } 135 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x)) 136 137 /* Convert an address to a corresponding PDE */ 138 FORCEINLINE 139 PMMPTE 140 _MiAddressToPde(PVOID Address) 141 { 142 ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3); 143 Offset &= 0x7FFFFFF << 3; 144 return (PMMPTE)(PDE_BASE + Offset); 145 } 146 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x)) 147 148 /* Convert an address to a corresponding PPE */ 149 FORCEINLINE 150 PMMPTE 151 MiAddressToPpe(PVOID Address) 152 { 153 ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3); 154 Offset &= 0x3FFFF << 3; 155 return (PMMPTE)(PPE_BASE + Offset); 156 } 157 158 /* Convert an address to a corresponding PXE */ 159 FORCEINLINE 160 PMMPTE 161 MiAddressToPxe(PVOID Address) 162 { 163 ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3); 164 Offset &= PXI_MASK << 3; 165 return (PMMPTE)(PXE_BASE + Offset); 166 } 167 168 /* Convert an address to a corresponding PTE offset/index */ 169 FORCEINLINE 170 ULONG 171 MiAddressToPti(PVOID Address) 172 { 173 return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF); 174 } 175 #define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name 176 177 /* Convert an address to a corresponding PDE offset/index */ 178 FORCEINLINE 179 ULONG 180 MiAddressToPdi(PVOID Address) 181 { 182 return ((((ULONG64)Address) >> PDI_SHIFT) & 0x1FF); 183 } 184 #define MiAddressToPdeOffset(x) MiAddressToPdi(x) 185 #define MiGetPdeOffset(x) MiAddressToPdi(x) 186 187 /* Convert an address to a corresponding PXE offset/index */ 188 FORCEINLINE 189 ULONG 190 MiAddressToPxi(PVOID Address) 191 { 192 return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF); 193 } 194 195 /* Convert a PTE into a corresponding address */ 196 FORCEINLINE 197 PVOID 198 MiPteToAddress(PMMPTE PointerPte) 199 { 200 /* Use signed math */ 201 return (PVOID)(((LONG64)PointerPte << 25) >> 16); 202 } 203 204 /* Convert a PDE into a corresponding address */ 205 FORCEINLINE 206 PVOID 207 MiPdeToAddress(PMMPTE PointerPde) 208 { 209 /* Use signed math */ 210 return (PVOID)(((LONG64)PointerPde << 34) >> 16); 211 } 212 213 /* Convert a PPE into a corresponding address */ 214 FORCEINLINE 215 PVOID 216 MiPpeToAddress(PMMPTE PointerPpe) 217 { 218 /* Use signed math */ 219 return (PVOID)(((LONG64)PointerPpe << 43) >> 16); 220 } 221 222 /* Convert a PXE into a corresponding address */ 223 FORCEINLINE 224 PVOID 225 MiPxeToAddress(PMMPTE PointerPxe) 226 { 227 /* Use signed math */ 228 return (PVOID)(((LONG64)PointerPxe << 52) >> 16); 229 } 230 231 /* Translate between P*Es */ 232 #define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde)) 233 #define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte)) 234 #define MiPdeToPpe(_Pde) ((PMMPPE)MiAddressToPte(_Pde)) 235 236 /* Check P*E boundaries */ 237 #define MiIsPteOnPdeBoundary(PointerPte) \ 238 ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0) 239 #define MiIsPteOnPpeBoundary(PointerPte) \ 240 ((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0) 241 #define MiIsPteOnPxeBoundary(PointerPte) \ 242 ((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0) 243 244 // 245 // Decodes a Prototype PTE into the underlying PTE 246 // 247 #define MiProtoPteToPte(x) \ 248 (PMMPTE)(((LONG64)(x)->u.Long) >> 16) /* Sign extend 48 bits */ 249 250 // 251 // Decodes a Prototype PTE into the underlying PTE 252 // 253 #define MiSubsectionPteToSubsection(x) \ 254 (PMMPTE)((x)->u.Subsect.SubsectionAddress >> 16) 255 256 FORCEINLINE 257 VOID 258 MI_MAKE_SUBSECTION_PTE( 259 _Out_ PMMPTE NewPte, 260 _In_ PVOID Segment) 261 { 262 /* Mark this as a prototype */ 263 NewPte->u.Long = 0; 264 NewPte->u.Subsect.Prototype = 1; 265 266 /* Store the lower 48 bits of the Segment address */ 267 NewPte->u.Subsect.SubsectionAddress = ((ULONG_PTR)Segment & 0x0000FFFFFFFFFFFF); 268 } 269 270 FORCEINLINE 271 VOID 272 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte, 273 IN PMMPTE PointerPte) 274 { 275 /* Store the Address */ 276 NewPte->u.Long = (ULONG64)PointerPte << 16; 277 278 /* Mark this as a prototype PTE */ 279 NewPte->u.Proto.Prototype = 1; 280 281 ASSERT(MiProtoPteToPte(NewPte) == PointerPte); 282 } 283 284 FORCEINLINE 285 BOOLEAN 286 MI_IS_MAPPED_PTE(PMMPTE PointerPte) 287 { 288 /// FIXME 289 __debugbreak(); 290 return ((PointerPte->u.Long & 0xFFFFFC01) != 0); 291 } 292 293 INIT_FUNCTION 294 FORCEINLINE 295 VOID 296 MmInitGlobalKernelPageDirectory(VOID) 297 { 298 /* Nothing to do */ 299 } 300 301 FORCEINLINE 302 BOOLEAN 303 MiIsPdeForAddressValid(PVOID Address) 304 { 305 return ((MiAddressToPxe(Address)->u.Hard.Valid) && 306 (MiAddressToPpe(Address)->u.Hard.Valid) && 307 (MiAddressToPde(Address)->u.Hard.Valid)); 308 } 309 310