1 /* 2 * See MultiProcessor Specification Version 1.[14]. 3 * 4 */ 5 6 struct mp { /* floating pointer */ 7 uchar signature[4]; /* "_MP_" */ 8 void* physaddr; /* physical address of MP configuration table */ 9 uchar length; /* 1 */ 10 uchar specrev; /* [14] */ 11 uchar checksum; /* all bytes must add up to 0 */ 12 uchar type; /* MP system configuration type */ 13 uchar imcrp; 14 uchar reserved[3]; 15 }; 16 17 struct mpctb { /* configuration table header */ 18 uchar signature[4]; /* "PCMP" */ 19 ushort length; /* total table length */ 20 uchar version; /* [14] */ 21 uchar checksum; /* all bytes must add up to 0 */ 22 uchar product[20]; /* product id */ 23 uint * oemtable; /* OEM table pointer */ 24 ushort oemlength; /* OEM table length */ 25 ushort entry; /* entry count */ 26 uint * lapicaddr; /* address of local APIC */ 27 ushort xlength; /* extended table length */ 28 uchar xchecksum; /* extended table checksum */ 29 uchar reserved; 30 }; 31 32 struct mppe { /* processor table entry */ 33 uchar type; /* entry type (0) */ 34 uchar apicid; /* local APIC id */ 35 uchar version; /* local APIC verison */ 36 uchar flags; /* CPU flags */ 37 uchar signature[4]; /* CPU signature */ 38 uint feature; /* feature flags from CPUID instruction */ 39 uchar reserved[8]; 40 }; 41 42 struct mpbe { /* bus table entry */ 43 uchar type; /* entry type (1) */ 44 uchar busno; /* bus id */ 45 char string[6]; /* bus type string */ 46 }; 47 48 struct mpioapic { /* I/O APIC table entry */ 49 uchar type; /* entry type (2) */ 50 uchar apicno; /* I/O APIC id */ 51 uchar version; /* I/O APIC version */ 52 uchar flags; /* I/O APIC flags */ 53 uint * addr; /* I/O APIC address */ 54 }; 55 56 struct mpie { /* interrupt table entry */ 57 uchar type; /* entry type ([34]) */ 58 uchar intr; /* interrupt type */ 59 ushort flags; /* interrupt flag */ 60 uchar busno; /* source bus id */ 61 uchar irq; /* source bus irq */ 62 uchar apicno; /* destination APIC id */ 63 uchar intin; /* destination APIC [L]INTIN# */ 64 }; 65 66 enum { /* table entry types */ 67 MPPROCESSOR = 0x00, /* one entry per processor */ 68 MPBUS = 0x01, /* one entry per bus */ 69 MPIOAPIC = 0x02, /* one entry per I/O APIC */ 70 MPIOINTR = 0x03, /* one entry per bus interrupt source */ 71 MPLINTR = 0x04, /* one entry per system interrupt source */ 72 73 MPSASM = 0x80, 74 MPHIERARCHY = 0x81, 75 MPCBASM = 0x82, 76 77 /* PCMPprocessor and PCMPioapic flags */ 78 MPEN = 0x01, /* enabled */ 79 MPBP = 0x02, /* bootstrap processor */ 80 81 /* PCMPiointr and PCMPlintr flags */ 82 MPPOMASK = 0x03, /* polarity conforms to specifications of bus */ 83 MPHIGH = 0x01, /* active high */ 84 MPLOW = 0x03, /* active low */ 85 MPELMASK = 0x0C, /* trigger mode of APIC input signals */ 86 MPEDGE = 0x04, /* edge-triggered */ 87 MPLEVEL = 0x0C, /* level-triggered */ 88 89 /* PCMPiointr and PCMPlintr interrupt type */ 90 MPINT = 0x00, /* vectored interrupt from APIC Rdt */ 91 MPNMI = 0x01, /* non-maskable interrupt */ 92 MPSMI = 0x02, /* system management interrupt */ 93 MPExtINT = 0x03, /* vectored interrupt from external PIC */ 94 }; 95 96 /* 97 * Common bits for 98 * I/O APIC Redirection Table Entry; 99 * Local APIC Local Interrupt Vector Table; 100 * Local APIC Inter-Processor Interrupt; 101 * Local APIC Timer Vector Table. 102 */ 103 enum { 104 APIC_FIXED = 0x00000000, /* [10:8] Delivery Mode */ 105 APIC_LOWEST = 0x00000100, /* Lowest priority */ 106 APIC_SMI = 0x00000200, /* System Management Interrupt */ 107 APIC_RR = 0x00000300, /* Remote Read */ 108 APIC_NMI = 0x00000400, 109 APIC_INIT = 0x00000500, /* INIT/RESET */ 110 APIC_STARTUP = 0x00000600, /* Startup IPI */ 111 APIC_EXTINT = 0x00000700, 112 113 APIC_PHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */ 114 APIC_LOGICAL = 0x00000800, 115 116 APIC_DELIVS = 0x00001000, /* [12] Delivery Status (RO) */ 117 APIC_HIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */ 118 APIC_LOW = 0x00002000, 119 APIC_REMOTEIRR = 0x00004000, /* [14] Remote IRR (RO) */ 120 APIC_EDGE = 0x00000000, /* [15] Trigger Mode (RW) */ 121 APIC_LEVEL = 0x00008000, 122 APIC_IMASK = 0x00010000, /* [16] Interrupt Mask */ 123 }; 124