1 /* Author: Mike Tierney <floyd@eng.umd.edu> */ 2 3 /** 4 ** register definitions for WD90C31 hardware accelerator 5 **/ 6 7 /* $XFree86: mit/server/ddx/x386/vga256/drivers/pvga1/paradise.h,v 2.0 1993/09/21 15:24:53 dawes Exp $ */ 8 9 /** BITBLT Control Part 1, Index 1 **/ 10 #define BLIT_CNTRL1 0x0000 /* blit index 0 */ 11 #define BLT_ACT_STAT 0x0800 /* activation/status bit */ 12 #define BLT_DIRECT 0x0400 /* blit direction 0-top->bottom,left->right */ 13 /* 1-bottom->top,right->left */ 14 #define BLT_PLANAR 0x0000 /* planar mode */ 15 #define BLT_PACKED 0x0100 /* packed mode, text and 256-color */ 16 #define BLT_DLINEAR 0x0080 /* blit is dest linear, 0 - blit is rectangular */ 17 #define BLT_SLINEAR 0x0040 /* blit is source linear, 0 - blit is rectangular */ 18 #define BLT_DST_SCR 0x0000 /* blit dest is screen memory */ 19 #define BLT_DST_SYS 0x0020 /* blit dest is system IO location */ 20 #define BLT_SRC_COLR 0x0000 /* color source format */ 21 #define BLT_SRC_MONC 0x0004 /* source format is mono from color comparators */ 22 #define BLT_SRC_FCOL 0x0008 /* source format is fixed color (filled rect) */ 23 #define BLT_SRC_MONH 0x000C /* source format is mono from host */ 24 #define BLT_SRC_SCR 0x0000 /* blit source is screen memory */ 25 #define BLT_SRC_SYS 0x0002 /* blit source is system IO location */ 26 27 /** BITBLT Control Part 2, Index 1 **/ 28 #define BLIT_CNTRL2 0x1000 /* blit index 0 */ 29 #define BLT_IENABLE 0X0400 /* interrupt enable when blt completes */ 30 #define BLT_QSTART 0X0080 /* quick start when dest reg written to */ 31 #define BLT_UPDST 0x0040 /* update dest on completion of blit */ 32 #define BLT_NOPAT 0x0000 /* no pattern */ 33 #define BLT_8x8PAT 0x0010 /* 8x8 pattern used for source */ 34 #define BLT_MTRNS 0x0008 /* monochrome transparency enable */ 35 #define BLT_PTRNS 0x0004 /* matching pixels are 1-opaque 0-transparent */ 36 #define BLT_TENABLE 0x0001 /* destination transparency enable */ 37 38 /** BITBLT SOURCE Low, Index 2 */ 39 #define BLIT_SRC_LOW 0x2000 40 41 /** BITBLT SOURCE High, Index 3 */ 42 #define BLIT_SRC_HGH 0x3000 43 44 /** BITBLT DEST LOW, Index 4 */ 45 #define BLIT_DST_LOW 0x4000 46 47 /** BITBLT DEST LOW, Index 5 */ 48 #define BLIT_DST_HGH 0x5000 49 50 /** BITBLT Dim X, Index 6 **/ 51 #define BLIT_DIM_X 0x6000 52 53 /** BITBLT Dim Y, Index 7 **/ 54 #define BLIT_DIM_Y 0x7000 55 56 /** BITBLT Row Pitch, Index 8 **/ 57 #define BLIT_ROW_PTCH 0x8000 58 59 /** BITBLT Raster Op, Index 9 **/ 60 #define BLIT_RAS_OP 0x9000 61 #define ROP_ZERO 0x0000 62 #define ROP_AND 0x0100 63 #define ROP_SAND 0x0200 64 #define ROP_SRC 0x0300 65 #define ROP_NSAD 0x0400 66 #define ROP_DST 0x0500 67 #define ROP_XOR 0x0600 68 #define ROP_OR 0x0700 69 #define ROP_NOR 0x0800 70 #define ROP_XNOR 0x0900 71 #define ROP_NDEST 0x0A00 72 #define ROP_SOND 0x0B00 73 #define ROP_NSRC 0x0C00 74 #define ROP_NSOD 0x0D00 75 #define ROP_NAND 0x0E00 76 #define ROP_ONE 0x0F00 77 78 /** BLT Forground Color, Index 10 **/ 79 #define BLIT_FOR_COLR 0xA000 80 81 /** BLT Background Color, Index 11 **/ 82 #define BLIT_BCK_COLR 0xB000 83 84 /** BLT Transparency Color, Index 12 **/ 85 #define BLIT_TRN_COLR 0xC000 86 87 /** BLT Transparency Mask, Index 13 **/ 88 #define BLIT_TRN_MASK 0xD000 89 90 /** BLT MASK, Index 14 **/ 91 #define BLIT_MASK 0xE000 92 93 /** wait for current blit operation to finish **/ 94 #define WAIT_BLIT outw(0x23C0, 0x1 | (0x10 << 8)); \ 95 while (inw(0x23C2) & BLT_ACT_STAT); 96 97 /** wait finite time for current blit operation to finish **/ 98 #define WAIT_BLIT_FINITE \ 99 { int count = 0; \ 100 do { outw(0x23C0, 0x1 | (0x10 << 8)); \ 101 fprintf (fp, "waiting...\n"); \ 102 } while ((inw(0x23C2) & BLT_ACT_STAT) && count++ < 100); \ 103 if (count >= 200) {vgaCloseScreen(); exit(-1);}\ 104 } 105 106 107 /** 108 ** used to save off default functions 109 ** sometimes the speedup routines need to bow out to the default funtion 110 ** most of the speedups only work if the operation is screen->screen 111 **/ 112 113 extern void (*pvga1_stdcfbFillRectSolidCopy)(); 114 extern int (*pvga1_stdcfbDoBitbltCopy)(); 115 extern void (*pvga1_stdcfbBitblt)(); 116 extern void (*pvga1_stdcfbFillBoxSolid)(); 117 118 119 /** 120 ** these variables hold the current known state of the accel registers 121 ** that way, time isn't wasted outputing a value to a port that already 122 ** has that value. 123 **/ 124 125 extern unsigned int pvga1_blt_cntrl2; 126 extern unsigned int pvga1_blt_src_low; 127 extern unsigned int pvga1_blt_src_hgh; 128 extern unsigned int pvga1_blt_dim_x; 129 extern unsigned int pvga1_blt_dim_y; 130 extern unsigned int pvga1_blt_row_pitch; 131 extern unsigned int pvga1_blt_rop; 132 extern unsigned int pvga1_blt_for_color; 133 extern unsigned int pvga1_blt_bck_color; 134 extern unsigned int pvga1_blt_trns_color; 135 extern unsigned int pvga1_blt_trns_mask; 136 extern unsigned int pvga1_blt_planemask; 137 138 139 /** 140 ** macros to set each hardware register 141 **/ 142 143 #define SELECT_BLT_REG outb (0x23C0, 0x1); 144 145 #define SET_BLT_CNTRL1(value) outw(0x23C2, BLIT_CNTRL1 | value); 146 147 #define SET_BLT_CNTRL2(value) \ 148 if (pvga1_blt_cntrl2 != (value)) \ 149 outw(0x23C2, (BLIT_CNTRL2 | value)); \ 150 pvga1_blt_cntrl2 = value; 151 152 #define SET_BLT_DST_LOW(value) \ 153 outw (0x23C2, BLIT_DST_LOW | value); 154 155 #define SET_BLT_DST_HGH(value) \ 156 outw (0x23C2, BLIT_DST_HGH | value); 157 158 #define SET_BLT_SRC_LOW(value) \ 159 if (pvga1_blt_src_low != (value)) \ 160 outw (0x23C2, BLIT_SRC_LOW | value); \ 161 pvga1_blt_src_low = value; 162 163 #define SET_BLT_SRC_HGH(value) \ 164 if (pvga1_blt_src_hgh != (value)) \ 165 outw (0x23C2, BLIT_SRC_HGH | value); \ 166 pvga1_blt_src_hgh = value; 167 168 #define SET_BLT_DIM_X(value) \ 169 if (pvga1_blt_dim_x != (value)) \ 170 outw (0x23C2, BLIT_DIM_X | value); \ 171 pvga1_blt_dim_x = value; 172 173 #define SET_BLT_DIM_Y(value) \ 174 if (pvga1_blt_dim_y != (value)) \ 175 outw (0x23C2, BLIT_DIM_Y | value); \ 176 pvga1_blt_dim_y = value; 177 178 #define SET_BLT_ROW_PTCH(value) \ 179 if (pvga1_blt_row_pitch != (value)) \ 180 outw (0x23C2, BLIT_ROW_PTCH | value); \ 181 pvga1_blt_row_pitch = value; 182 183 #define SET_BLT_RAS_OP(value) \ 184 if (pvga1_blt_rop != (value)) \ 185 outw (0x23C2, BLIT_RAS_OP | value); \ 186 pvga1_blt_rop = value; 187 188 #define SET_BLT_FOR_COLR(value) \ 189 if (pvga1_blt_for_color != (value)) \ 190 outw (0x23C2, BLIT_FOR_COLR | value); \ 191 pvga1_blt_for_color = value; 192 193 #define SET_BLT_BCK_COLR(value) \ 194 if (pvga1_blt_bck_color != (value)) \ 195 outw (0x23C2, BLIT_BCK_COLR | value); \ 196 pvga1_blt_bck_color = value; 197 198 #define SET_BLT_TRN_COLR(value) \ 199 if (pvga1_blt_trns_color != (value)) \ 200 outw (0x23C2, BLIT_TRN_COLR | value); \ 201 pvga1_blt_trns_color = value; 202 203 #define SET_BLT_TRN_MASK(value) \ 204 if (pvga1_blt_trn_mask != (value)) \ 205 outw (0x23C2, BLIT_TRN_MASK | value); \ 206 pvga1_blt_trn_mask = value; 207 208 #define SET_BLT_MASK(value) \ 209 if (pvga1_blt_planemask != (value)) \ 210 outw (0x23C2, BLIT_MASK | value); \ 211 pvga1_blt_planemask = value; 212