1 /* 2 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 3 * adapters. By David Greenman, 29-April-1993 4 * 5 * Copyright (C) 1993, David Greenman. This software may be used, modified, 6 * copied, distributed, and sold, in both source and binary form provided 7 * that the above copyright and these terms are retained. Under no 8 * circumstances is the author responsible for the proper functioning 9 * of this software, nor does the author assume any responsibility 10 * for damages incurred with its use. 11 * 12 * Currently supports the Western Digital/SMC 8003 and 8013 series, 13 * the 3Com 3c503, the NE1000 and NE2000, and a variety of similar 14 * clones. 15 * 16 * David Greenman Id: if_ed.c,v 2.16 1993/11/29 16:55:56 davidg Exp davidg 17 * $Id: ed.c,v 1.4 94/07/07 22:55:18 bill Exp Locker: bill $ 18 */ 19 20 /* null default configuration: (must be added to per host configuration file) */ 21 static char *ed_config = "ed. # ns derivative ethernet $Revision: 1.4 $"; 22 23 #include "sys/param.h" 24 #include "systm.h" 25 #include "sys/errno.h" 26 #include "sys/ioctl.h" 27 #include "mbuf.h" 28 #include "sys/socket.h" 29 #include "sys/syslog.h" 30 #include "esym.h" 31 #include "modconfig.h" 32 33 #include "if.h" 34 #include "if_dl.h" 35 #include "if_types.h" 36 #include "netisr.h" 37 38 #ifdef INET 39 #include "in.h" 40 #include "in_systm.h" 41 #include "in_var.h" 42 #include "ip.h" 43 #include "if_ether.h" 44 #endif 45 46 #ifdef NS 47 #include "ns.h" 48 #include "ns_if.h" 49 #endif 50 51 /* #if NBPFILTER > 0 */ 52 #include "bpf.h" 53 #include "bpfdesc.h" 54 /* #endif*/ 55 56 #include "isa_irq.h" 57 #include "isa_driver.h" 58 #include "machine/icu.h" 59 #include "edreg.h" 60 61 #include "prototypes.h" 62 #include "machine/inline/io.h" 63 64 65 /* For backwards compatibility */ 66 #ifndef IFF_ALTPHYS 67 #define IFF_ALTPHYS IFF_LLC0 68 #endif 69 70 /* 71 * ed_softc: per line info and status 72 */ 73 static 74 struct ed_softc { 75 struct arpcom arpcom; /* ethernet common */ 76 77 char *type_str; /* pointer to type string */ 78 u_char vendor; /* interface vendor */ 79 u_char type; /* interface type code */ 80 81 u_short asic_addr; /* ASIC I/O bus address */ 82 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 83 84 /* 85 * The following 'proto' variable is part of a work-around for 8013EBT asics 86 * being write-only. It's sort of a prototype/shadow of the real thing. 87 */ 88 u_char wd_laar_proto; 89 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 90 int is790; /* set by the probe code if the card is 790 based */ 91 int alive; /* unit exists and was attached */ 92 93 caddr_t bpf; /* BPF "magic cookie" */ 94 caddr_t mem_start; /* NIC memory start address */ 95 caddr_t mem_end; /* NIC memory end address */ 96 u_long mem_size; /* total NIC memory size */ 97 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 98 99 u_char mem_shared; /* NIC memory is shared with host */ 100 u_char xmit_busy; /* transmitter is busy */ 101 u_char txb_cnt; /* number of transmit buffers */ 102 u_char txb_inuse; /* number of TX buffers currently in-use*/ 103 104 u_char txb_new; /* pointer to where new buffer will be added */ 105 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 106 u_short txb_len[8]; /* buffered xmit buffer lengths */ 107 u_char tx_page_start; /* first page of TX buffer area */ 108 u_char rec_page_start; /* first page of RX ring-buffer */ 109 u_char rec_page_stop; /* last page of RX ring-buffer */ 110 u_char next_packet; /* pointer to next unread RX packet */ 111 } *ed_softc; 112 113 static int ned; 114 115 void ed_attach(struct isa_device *); 116 void ed_init(int); 117 void edintr(int); 118 int ed_ioctl(struct ifnet *, int, caddr_t); 119 int ed_probe(struct isa_device *); 120 void ed_start(struct ifnet *); 121 void ed_reset(int, int); 122 void ed_watchdog(int); 123 124 static void ed_get_packet(struct ed_softc *, char *, int /*u_short*/); 125 static void ed_stop(int); 126 127 static inline void ed_rint(); 128 static inline void ed_xmit(); 129 static inline char *ed_ring_copy(); 130 131 void ed_pio_readmem(), ed_pio_writemem(); 132 u_short ed_pio_write_mbufs(); 133 134 135 struct trailer_header { 136 u_short ether_type; 137 u_short ether_residual; 138 }; 139 140 struct isa_driver eddriver = { 141 ed_probe, 142 ed_attach, 143 edintr, 144 "ed", 145 &netmask 146 }; 147 /* 148 * Interrupt conversion table for WD/SMC ASIC 149 * (IRQ* are defined in icu.h) 150 */ 151 static unsigned short ed_intr_mask[] = { 152 IRQ9, 153 IRQ3, 154 IRQ5, 155 IRQ7, 156 IRQ10, 157 IRQ11, 158 IRQ15, 159 IRQ4 160 }; 161 162 /* 163 * Interrupt conversion table for 585/790 Combo 164 */ 165 static unsigned short ed_790_intr_mask[] = { 166 0, 167 IRQ9, 168 IRQ3, 169 IRQ4, 170 IRQ5, 171 IRQ10, 172 IRQ11, 173 IRQ15 174 }; 175 #define ETHER_MIN_LEN 64 176 #define ETHER_MAX_LEN 1518 177 #define ETHER_ADDR_LEN 6 178 #define ETHER_HDR_SIZE 14 179 180 /* 181 * Determine if the device is present 182 * 183 * on entry: 184 * a pointer to an isa_device struct 185 * on exit: 186 * NULL if device not found 187 * or # of i/o addresses used (if found) 188 * (*bogus*, since many clone cards decode inconsistant number, thus 189 * trying to detect conflicts is a "pipe dream" for [E]ISA -wfj) 190 */ 191 int 192 ed_probe(isa_dev) 193 struct isa_device *isa_dev; 194 { 195 struct ed_softc *sc; 196 static lastunit; 197 int nports; 198 199 /* wildcard unit? */ 200 if (isa_dev->id_unit == '?') 201 isa_dev->id_unit = lastunit; 202 if (isa_dev->id_unit >= ned) 203 return (0); 204 sc = &ed_softc[isa_dev->id_unit]; 205 206 while (sc->alive) { 207 if (sc->alive && isa_dev->id_unit > ned) 208 return(0); 209 isa_dev->id_unit++; 210 sc++; 211 } 212 213 if (nports = ed_probe_WD80x3(isa_dev)) { 214 lastunit = isa_dev->id_unit + 1; 215 return (nports); 216 } 217 218 if (nports = ed_probe_3Com(isa_dev)) { 219 lastunit = isa_dev->id_unit + 1; 220 return (nports); 221 } 222 223 if (nports = ed_probe_Novell(isa_dev)) { 224 lastunit = isa_dev->id_unit + 1; 225 return (nports); 226 } 227 return(0); 228 } 229 230 /* 231 * Generic probe routine for testing for the existance of a DS8390. 232 * Must be called after the NIC has just been reset. This routine 233 * works by looking at certain register values that are gauranteed 234 * to be initialized a certain way after power-up or reset. Seems 235 * not to currently work on the 83C690. 236 * 237 * Specifically: 238 * 239 * Register reset bits set bits 240 * Command Register (CR) TXP, STA RD2, STP 241 * Interrupt Status (ISR) RST 242 * Interrupt Mask (IMR) All bits 243 * Data Control (DCR) LAS 244 * Transmit Config. (TCR) LB1, LB0 245 * 246 * We only look at the CR and ISR registers, however, because looking at 247 * the others would require changing register pages (which would be 248 * intrusive if this isn't an 8390). 249 * 250 * Return 1 if 8390 was found, 0 if not. 251 */ 252 253 int 254 ed_probe_generic8390(sc) 255 struct ed_softc *sc; 256 { 257 if ((inb(sc->nic_addr + ED_P0_CR) & 258 (ED_CR_RD2|ED_CR_TXP|ED_CR_STA|ED_CR_STP)) != 259 (ED_CR_RD2|ED_CR_STP)) 260 return (0); 261 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 262 return (0); 263 264 return(1); 265 } 266 267 /* 268 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 269 */ 270 int 271 ed_probe_WD80x3(isa_dev) 272 struct isa_device *isa_dev; 273 { 274 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 275 int i; 276 u_int memsize; 277 u_char iptr, isa16bit, sum; 278 279 sc->asic_addr = isa_dev->id_iobase; 280 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 281 sc->is790 = 0; 282 283 /* 284 * Attempt to do a checksum over the station address PROM. 285 * If it fails, it's probably not a SMC/WD board. There 286 * is a problem with this, though: some clone WD boards 287 * don't pass the checksum test. Danpex boards for one. 288 */ 289 for (sum = 0, i = 0; i < 8; ++i) 290 sum += inb(sc->asic_addr + ED_WD_PROM + i); 291 292 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 293 /* 294 * Checksum is invalid. This often happens with cheap 295 * WD8003E clones. In this case, the checksum byte 296 * (the eighth byte) seems to always be zero. 297 */ 298 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 299 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 300 return(0); 301 } 302 303 /* reset card to force it into a known state. */ 304 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 305 DELAY(100); 306 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 307 /* wait in the case this card is reading it's EEROM */ 308 DELAY(5000); 309 310 sc->vendor = ED_VENDOR_WD_SMC; 311 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 312 313 /* 314 * Set initial values for width/size. 315 */ 316 switch (sc->type) { 317 case ED_TYPE_WD8003S: 318 sc->type_str = "WD8003S"; 319 memsize = 8192; 320 isa16bit = 0; 321 break; 322 case ED_TYPE_WD8003E: 323 sc->type_str = "WD8003E"; 324 memsize = 8192; 325 isa16bit = 0; 326 break; 327 case ED_TYPE_WD8013EBT: 328 sc->type_str = "WD8013EBT"; 329 memsize = 16384; 330 isa16bit = 1; 331 break; 332 case ED_TYPE_WD8013W: 333 sc->type_str = "WD8013W"; 334 memsize = 16384; 335 isa16bit = 1; 336 break; 337 case ED_TYPE_WD8013EP: /* also WD8003EP */ 338 if (inb(sc->asic_addr + ED_WD_ICR) 339 & ED_WD_ICR_16BIT) { 340 isa16bit = 1; 341 memsize = 16384; 342 sc->type_str = "WD8013EP"; 343 } else { 344 isa16bit = 0; 345 memsize = 8192; 346 sc->type_str = "WD8003EP"; 347 } 348 break; 349 case ED_TYPE_WD8013WC: 350 sc->type_str = "WD8013WC"; 351 memsize = 16384; 352 isa16bit = 1; 353 break; 354 case ED_TYPE_WD8013EBP: 355 sc->type_str = "WD8013EBP"; 356 memsize = 16384; 357 isa16bit = 1; 358 break; 359 case ED_TYPE_WD8013EPC: 360 sc->type_str = "WD8013EPC"; 361 memsize = 16384; 362 isa16bit = 1; 363 break; 364 case ED_TYPE_SMC8216C: 365 sc->type_str = "SMC8216/SMC8216C"; 366 memsize = 16384; 367 isa16bit = 1; 368 sc->is790 = 1; 369 break; 370 case ED_TYPE_SMC8216T: 371 sc->type_str = "SMC8216T"; 372 memsize = 16384; 373 isa16bit = 1; 374 sc->is790 = 1; 375 break; 376 default: 377 sc->type_str = ""; 378 memsize = 8192; 379 isa16bit = 0; 380 break; 381 } 382 /* 383 * Make some adjustments to initial values depending on what is 384 * found in the ICR. 385 */ 386 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 387 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 388 isa16bit = 0; 389 memsize = 8192; 390 } 391 392 #if ED_DEBUG 393 printf("type=%s isa16bit=%d memsize=%d id_msize=%d\n", 394 sc->type_str,isa16bit,memsize,isa_dev->id_msize); 395 for (i=0; i<8; i++) 396 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 397 #endif 398 /* 399 * Allow the user to override the autoconfiguration 400 */ 401 if (isa_dev->id_msize) 402 memsize = isa_dev->id_msize; 403 /* 404 * (note that if the user specifies both of the following flags 405 * that '8bit' mode intentionally has precedence) 406 */ 407 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 408 isa16bit = 1; 409 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 410 isa16bit = 0; 411 412 /* 413 * Check 83C584 interrupt configuration register if this board has one 414 * XXX - we could also check the IO address register. But why 415 * bother...if we get past this, it *has* to be correct. 416 */ 417 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 418 /* 419 * Assemble together the encoded interrupt number. 420 */ 421 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 422 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 423 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 424 /* 425 * Translate it using translation table, and check for correctness. 426 */ 427 if (ed_intr_mask[iptr] != isa_dev->id_irq) { 428 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d\n", 429 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_intr_mask[iptr]) - 1); 430 return(0); 431 } 432 /* 433 * Enable the interrupt. 434 */ 435 outb(isa_dev->id_iobase + ED_WD_IRR, 436 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 437 } 438 if (sc->is790) { 439 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) | 0x80); 440 iptr = ((inb(isa_dev->id_iobase + 0x0d) & 0x0c ) >> 2) | 441 ((inb(isa_dev->id_iobase + 0x0d) & 0x40) >> 4); 442 outb(isa_dev->id_iobase + 0x04, inb(isa_dev->id_iobase + 0x04) & ~0x80); 443 444 if (ed_790_intr_mask[iptr] != isa_dev->id_irq) { 445 printf("ed%d: kernel configured irq %d doesn't match board configured irq %d %d\n", 446 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1, ffs(ed_790_intr_mask[iptr]) -1, iptr); 447 return 0; 448 } 449 outb(isa_dev->id_iobase + 0x06, inb(isa_dev->id_iobase + 0x06) | 0x01); 450 } 451 452 sc->isa16bit = isa16bit; 453 454 #ifdef notyet /* XXX - I'm not sure if PIO mode is even possible on WD/SMC boards */ 455 /* 456 * The following allows the WD/SMC boards to be used in Programmed I/O 457 * mode - without mapping the NIC memory shared. ...Not the prefered 458 * way, but it might be the only way. 459 */ 460 if (isa_dev->id_flags & ED_FLAGS_FORCE_PIO) { 461 sc->mem_shared = 0; 462 isa_dev->id_maddr = 0; 463 } else { 464 sc->mem_shared = 1; 465 } 466 #else 467 sc->mem_shared = 1; 468 #endif 469 isa_dev->id_msize = memsize; 470 471 sc->mem_start = (caddr_t)isa_dev->id_maddr; 472 473 /* 474 * allocate one xmit buffer if < 16k, two buffers otherwise 475 */ 476 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 477 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 478 sc->txb_cnt = 1; 479 sc->rec_page_start = ED_TXBUF_SIZE; 480 } else { 481 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE * 2); 482 sc->txb_cnt = 2; 483 sc->rec_page_start = ED_TXBUF_SIZE * 2; 484 } 485 sc->mem_size = memsize; 486 sc->mem_end = sc->mem_start + memsize; 487 sc->rec_page_stop = memsize / ED_PAGE_SIZE; 488 sc->tx_page_start = ED_WD_PAGE_OFFSET; 489 490 /* 491 * Get station address from on-board ROM 492 */ 493 for (i = 0; i < ETHER_ADDR_LEN; ++i) 494 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 495 496 if (sc->mem_shared) { 497 /* 498 * Set address and enable interface shared memory. 499 */ 500 if(!sc->is790) { 501 outb(sc->asic_addr + ED_WD_MSR, ((kmem_phys(sc->mem_start) >> 13) & 502 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 503 } else { 504 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 505 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80)); 506 outb(sc->asic_addr + 0x0b, ((kmem_phys(sc->mem_start) >> 13) & 0x0f) | 507 ((kmem_phys(sc->mem_start) >> 11) & 0x40) | 508 (inb(sc->asic_addr + 0x0b) & 0xb0)); 509 outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80)); 510 } 511 512 /* 513 * Set upper address bits and 8/16 bit access to shared memory 514 */ 515 if (isa16bit) { 516 if (sc->is790) { 517 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 518 outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN); 519 } else { 520 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 521 ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN | 522 ((kmem_phys(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 523 } 524 } else { 525 if ((sc->type & ED_WD_SOFTCONFIG) || (sc->type == ED_TYPE_WD8013EBT) && (!sc->is790)) { 526 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto = 527 ((kmem_phys(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI))); 528 } 529 } 530 531 /* 532 * Now zero memory and verify that it is clear 533 */ 534 memset(sc->mem_start, 0, memsize); 535 536 for (i = 0; i < memsize; ++i) 537 if (sc->mem_start[i]) { 538 printf("ed%d: failed to clear shared memory at %x - check configuration\n", 539 isa_dev->id_unit, kmem_phys(sc->mem_start + i)); 540 541 /* 542 * Disable 16 bit access to shared memory 543 */ 544 if (isa16bit) 545 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 546 ~ED_WD_LAAR_M16EN)); 547 548 return(0); 549 } 550 551 /* 552 * Disable 16bit access to shared memory - we leave it disabled so 553 * that 1) machines reboot properly when the board is set 554 * 16 bit mode and there are conflicting 8bit devices/ROMS 555 * in the same 128k address space as this boards shared 556 * memory. and 2) so that other 8 bit devices with shared 557 * memory can be used in this 128k region, too. 558 */ 559 if (isa16bit) 560 outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &= 561 ~ED_WD_LAAR_M16EN)); 562 563 } 564 565 return (ED_WD_IO_PORTS); 566 } 567 568 /* 569 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 570 */ 571 int 572 ed_probe_3Com(isa_dev) 573 struct isa_device *isa_dev; 574 { 575 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 576 int i; 577 u_int memsize; 578 u_char isa16bit, sum; 579 580 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 581 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 582 583 /* 584 * Verify that the kernel configured I/O address matches the board 585 * configured address 586 */ 587 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 588 case ED_3COM_BCFR_300: 589 if (isa_dev->id_iobase != 0x300) 590 return(0); 591 break; 592 case ED_3COM_BCFR_310: 593 if (isa_dev->id_iobase != 0x310) 594 return(0); 595 break; 596 case ED_3COM_BCFR_330: 597 if (isa_dev->id_iobase != 0x330) 598 return(0); 599 break; 600 case ED_3COM_BCFR_350: 601 if (isa_dev->id_iobase != 0x350) 602 return(0); 603 break; 604 case ED_3COM_BCFR_250: 605 if (isa_dev->id_iobase != 0x250) 606 return(0); 607 break; 608 case ED_3COM_BCFR_280: 609 if (isa_dev->id_iobase != 0x280) 610 return(0); 611 break; 612 case ED_3COM_BCFR_2A0: 613 if (isa_dev->id_iobase != 0x2a0) 614 return(0); 615 break; 616 case ED_3COM_BCFR_2E0: 617 if (isa_dev->id_iobase != 0x2e0) 618 return(0); 619 break; 620 default: 621 return(0); 622 } 623 624 /* 625 * Verify that the kernel shared memory address matches the 626 * board configured address. 627 */ 628 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 629 case ED_3COM_PCFR_DC000: 630 if (kmem_phys(isa_dev->id_maddr) != 0xdc000) 631 return(0); 632 break; 633 case ED_3COM_PCFR_D8000: 634 if (kmem_phys(isa_dev->id_maddr) != 0xd8000) 635 return(0); 636 break; 637 case ED_3COM_PCFR_CC000: 638 if (kmem_phys(isa_dev->id_maddr) != 0xcc000) 639 return(0); 640 break; 641 case ED_3COM_PCFR_C8000: 642 if (kmem_phys(isa_dev->id_maddr) != 0xc8000) 643 return(0); 644 break; 645 default: 646 return(0); 647 } 648 649 650 /* 651 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 652 * sequence because it'll lock up if the cable isn't connected 653 * if we don't. 654 */ 655 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 656 657 /* 658 * Wait for a while, then un-reset it 659 */ 660 DELAY(50); 661 /* 662 * The 3Com ASIC defaults to rather strange settings for the CR after 663 * a reset - it's important to set it again after the following 664 * outb (this is done when we map the PROM below). 665 */ 666 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 667 668 /* 669 * Wait a bit for the NIC to recover from the reset 670 */ 671 DELAY(5000); 672 673 sc->vendor = ED_VENDOR_3COM; 674 sc->type_str = "3c503"; 675 676 sc->mem_shared = 1; 677 678 /* 679 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k 680 * window to it. 681 */ 682 memsize = 8192; 683 684 /* 685 * Get station address from on-board ROM 686 */ 687 /* 688 * First, map ethernet address PROM over the top of where the NIC 689 * registers normally appear. 690 */ 691 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 692 693 for (i = 0; i < ETHER_ADDR_LEN; ++i) 694 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 695 696 /* 697 * Unmap PROM - select NIC registers. The proper setting of the 698 * tranceiver is set in ed_init so that the attach code 699 * is given a chance to set the default based on a compile-time 700 * config option 701 */ 702 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 703 704 /* 705 * Determine if this is an 8bit or 16bit board 706 */ 707 708 /* 709 * select page 0 registers 710 */ 711 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP); 712 713 /* 714 * Attempt to clear WTS bit. If it doesn't clear, then this is a 715 * 16bit board. 716 */ 717 outb(sc->nic_addr + ED_P0_DCR, 0); 718 719 /* 720 * select page 2 registers 721 */ 722 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2|ED_CR_RD2|ED_CR_STP); 723 724 /* 725 * The 3c503 forces the WTS bit to a one if this is a 16bit board 726 */ 727 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 728 isa16bit = 1; 729 else 730 isa16bit = 0; 731 732 /* 733 * select page 0 registers 734 */ 735 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2|ED_CR_STP); 736 737 sc->mem_start = (caddr_t)isa_dev->id_maddr; 738 sc->mem_size = memsize; 739 sc->mem_end = sc->mem_start + memsize; 740 741 /* 742 * We have an entire 8k window to put the transmit buffers on the 743 * 16bit boards. But since the 16bit 3c503's shared memory 744 * is only fast enough to overlap the loading of one full-size 745 * packet, trying to load more than 2 buffers can actually 746 * leave the transmitter idle during the load. So 2 seems 747 * the best value. (Although a mix of variable-sized packets 748 * might change this assumption. Nonetheless, we optimize for 749 * linear transfers of same-size packets.) 750 */ 751 if (isa16bit) { 752 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 753 sc->txb_cnt = 1; 754 else 755 sc->txb_cnt = 2; 756 757 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 758 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 759 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 760 ED_3COM_RX_PAGE_OFFSET_16BIT; 761 sc->mem_ring = sc->mem_start; 762 } else { 763 sc->txb_cnt = 1; 764 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 765 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 766 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 767 ED_3COM_TX_PAGE_OFFSET_8BIT; 768 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 769 } 770 771 sc->isa16bit = isa16bit; 772 773 /* 774 * Initialize GA page start/stop registers. Probably only needed 775 * if doing DMA, but what the hell. 776 */ 777 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 778 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 779 780 /* 781 * Set IRQ. 3c503 only allows a choice of irq 2-5. 782 */ 783 switch (isa_dev->id_irq) { 784 case IRQ2: 785 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 786 break; 787 case IRQ3: 788 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 789 break; 790 case IRQ4: 791 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 792 break; 793 case IRQ5: 794 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 795 break; 796 default: 797 printf("ed%d: Invalid irq configuration (%d) must be 2-5 for 3c503\n", 798 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 799 return(0); 800 } 801 802 /* 803 * Initialize GA configuration register. Set bank and enable shared mem. 804 */ 805 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 806 ED_3COM_GACFR_MBS0); 807 808 /* 809 * Initialize "Vector Pointer" registers. These gawd-awful things 810 * are compared to 20 bits of the address on ISA, and if they 811 * match, the shared memory is disabled. We set them to 812 * 0xffff0...allegedly the reset vector. 813 */ 814 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 815 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 816 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 817 818 /* 819 * Zero memory and verify that it is clear 820 */ 821 memset(sc->mem_start, 0, memsize); 822 823 for (i = 0; i < memsize; ++i) 824 if (sc->mem_start[i]) { 825 printf("ed%d: failed to clear shared memory at %x - check configuration\n", 826 isa_dev->id_unit, kmem_phys(sc->mem_start + i)); 827 return(0); 828 } 829 830 isa_dev->id_msize = memsize; 831 return(ED_3COM_IO_PORTS); 832 } 833 834 /* 835 * Probe and vendor-specific initialization routine for NE1000/2000 boards 836 */ 837 int 838 ed_probe_Novell(isa_dev) 839 struct isa_device *isa_dev; 840 { 841 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 842 u_int memsize, n; 843 u_char romdata[16], isa16bit = 0, tmp; 844 static char test_pattern[32] = "THIS is A memory TEST pattern"; 845 char test_buffer[32]; 846 847 sc->asic_addr = isa_dev->id_iobase + ED_NOVELL_ASIC_OFFSET; 848 sc->nic_addr = isa_dev->id_iobase + ED_NOVELL_NIC_OFFSET; 849 850 /* XXX - do Novell-specific probe here */ 851 852 /* Reset the board */ 853 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 854 855 #if 0 856 /* 857 * This total and completely screwy thing is to work around braindamage 858 * in some NE compatible boards. Why it works, I have *no* idea. 859 * It appears that the boards watch the ISA bus for an outb, and 860 * will lock up the ISA bus if they see an inb first. Weird. 861 */ 862 outb(0x84, 0); 863 #endif 864 865 /* 866 * I don't know if this is necessary; probably cruft leftover from 867 * Clarkson packet driver code. Doesn't do a thing on the boards 868 * I've tested. -DG [note that a outb(0x84, 0) seems to work 869 * here, and is non-invasive...but some boards don't seem to reset 870 * and I don't have complete documentation on what the 'right' 871 * thing to do is...so we do the invasive thing for now. Yuck.] 872 */ 873 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 874 DELAY(5000); 875 876 /* 877 * This is needed because some NE clones apparently don't reset the 878 * NIC properly (or the NIC chip doesn't reset fully on power-up) 879 * XXX - this makes the probe invasive! ...Done against my better 880 * judgement. -DLG 881 */ 882 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP); 883 884 DELAY(5000); 885 886 /* Make sure that we really have an 8390 based board */ 887 if (!ed_probe_generic8390(sc)) 888 return(0); 889 890 sc->vendor = ED_VENDOR_NOVELL; 891 sc->mem_shared = 0; 892 isa_dev->id_maddr = 0; 893 894 /* 895 * Test the ability to read and write to the NIC memory. This has 896 * the side affect of determining if this is an NE1000 or an NE2000. 897 */ 898 899 /* 900 * This prevents packets from being stored in the NIC memory when 901 * the readmem routine turns on the start bit in the CR. 902 */ 903 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 904 905 /* Temporarily initialize DCR for byte operations */ 906 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS); 907 908 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 909 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 910 911 sc->isa16bit = 0; 912 913 /* 914 * Write a test pattern in byte mode. If this fails, then there 915 * probably isn't any memory at 8k - which likely means 916 * that the board is an NE2000. 917 */ 918 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 919 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 920 921 if (memcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 922 /* not an NE1000 - try NE2000 */ 923 924 outb(sc->nic_addr + ED_P0_DCR, 925 ED_DCR_WTS|ED_DCR_FT1|ED_DCR_LS); 926 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 927 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 928 929 sc->isa16bit = 1; 930 /* 931 * Write a test pattern in word mode. If this also fails, then 932 * we don't know what this board is. 933 */ 934 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 935 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 936 937 if (memcmp(test_pattern, test_buffer, sizeof(test_pattern))) 938 return(0); /* not an NE2000 either */ 939 940 sc->type = ED_TYPE_NE2000; 941 sc->type_str = "NE2000"; 942 } else { 943 sc->type = ED_TYPE_NE1000; 944 sc->type_str = "NE1000"; 945 } 946 947 /* 8k of memory plus an additional 8k if 16bit */ 948 memsize = 8192 + sc->isa16bit * 8192; 949 950 #if 0 /* probably not useful - NE boards only come two ways */ 951 /* allow kernel config file overrides */ 952 if (isa_dev->id_msize) 953 memsize = isa_dev->id_msize; 954 #endif 955 956 sc->mem_size = memsize; 957 958 /* NIC memory doesn't start at zero on an NE board */ 959 /* The start address is tied to the bus width */ 960 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 961 sc->mem_end = sc->mem_start + memsize; 962 sc->tx_page_start = memsize / ED_PAGE_SIZE; 963 964 /* 965 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 966 * otherwise). 967 */ 968 if ((memsize < 16384) || (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) 969 sc->txb_cnt = 1; 970 else 971 sc->txb_cnt = 2; 972 973 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 974 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 975 976 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 977 978 ed_pio_readmem(sc, 0, romdata, 16); 979 for (n = 0; n < ETHER_ADDR_LEN; n++) 980 sc->arpcom.ac_enaddr[n] = romdata[n*(sc->isa16bit+1)]; 981 982 /* clear any pending interrupts that might have occurred above */ 983 outb(sc->nic_addr + ED_P0_ISR, 0xff); 984 985 return(ED_NOVELL_IO_PORTS); 986 } 987 988 /* 989 * Install interface into kernel networking data structures 990 */ 991 void 992 ed_attach(isa_dev) 993 struct isa_device *isa_dev; 994 { 995 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 996 struct ifnet *ifp = &sc->arpcom.ac_if; 997 struct ifaddr *ifa; 998 struct sockaddr_dl *sdl; 999 1000 sc->alive++; 1001 /* 1002 * Set interface to stopped condition (reset) 1003 */ 1004 ed_stop(isa_dev->id_unit); 1005 1006 /* 1007 * Initialize ifnet structure 1008 */ 1009 ifp->if_unit = isa_dev->id_unit; 1010 ifp->if_name = "ed" ; 1011 ifp->if_mtu = ETHERMTU; 1012 ifp->if_init = ed_init; 1013 ifp->if_output = ether_output; 1014 ifp->if_start = ed_start; 1015 ifp->if_ioctl = ed_ioctl; 1016 ifp->if_reset = ed_reset; 1017 ifp->if_watchdog = ed_watchdog; 1018 1019 /* 1020 * Set default state for ALTPHYS flag (used to disable the tranceiver 1021 * for AUI operation), based on compile-time config option. 1022 */ 1023 if (isa_dev->id_flags & ED_FLAGS_DISABLE_TRANCEIVER) 1024 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS 1025 | IFF_ALTPHYS); 1026 else 1027 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS); 1028 1029 /* 1030 * Attach the interface 1031 */ 1032 if_attach(ifp); 1033 1034 /* 1035 * Search down the ifa address list looking for the AF_LINK type entry 1036 */ 1037 ifa = ifp->if_addrlist; 1038 while ((ifa != 0) && (ifa->ifa_addr != 0) && 1039 (ifa->ifa_addr->sa_family != AF_LINK)) 1040 ifa = ifa->ifa_next; 1041 /* 1042 * If we find an AF_LINK type entry we fill in the hardware address. 1043 * This is useful for netstat(1) to keep track of which interface 1044 * is which. 1045 */ 1046 if ((ifa != 0) && (ifa->ifa_addr != 0)) { 1047 /* 1048 * Fill in the link-level address for this interface 1049 */ 1050 sdl = (struct sockaddr_dl *)ifa->ifa_addr; 1051 sdl->sdl_type = IFT_ETHER; 1052 sdl->sdl_alen = ETHER_ADDR_LEN; 1053 sdl->sdl_slen = 0; 1054 memcpy(LLADDR(sdl), sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1055 } 1056 1057 /* 1058 * Print additional info when attached 1059 */ 1060 printf("ed%d: address %s, ", isa_dev->id_unit, 1061 ether_sprintf(sc->arpcom.ac_enaddr)); 1062 1063 if (sc->type_str && (*sc->type_str != 0)) 1064 printf("type %s ", sc->type_str); 1065 else 1066 printf("type unknown (0x%x) ", sc->type); 1067 1068 printf("%s ",sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1069 1070 printf("%s", ((sc->vendor == ED_VENDOR_3COM) && 1071 (ifp->if_flags & IFF_ALTPHYS)) ? "tranceiver disabled" : ""); 1072 1073 /* 1074 * If BPF is in the kernel, call the attach for it 1075 */ 1076 /* #if NBPFILTER > 0 */ 1077 bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 1078 /* #endif*/ 1079 } 1080 1081 /* 1082 * Reset interface. 1083 */ 1084 void 1085 ed_reset(unit, uban) 1086 int unit; 1087 int uban; /* XXX */ 1088 { 1089 int s; 1090 1091 s = splimp(); 1092 1093 /* 1094 * Stop interface and re-initialize. 1095 */ 1096 ed_stop(unit); 1097 ed_init(unit); 1098 1099 (void) splx(s); 1100 } 1101 1102 /* 1103 * Take interface offline. 1104 */ 1105 void 1106 ed_stop(unit) 1107 int unit; 1108 { 1109 struct ed_softc *sc = &ed_softc[unit]; 1110 int n = 5000; 1111 1112 /* 1113 * Stop everything on the interface, and select page 0 registers. 1114 */ 1115 if (sc->is790) { 1116 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP); 1117 } else { 1118 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP); 1119 } 1120 /* 1121 * Wait for interface to enter stopped state, but limit # of checks 1122 * to 'n' (about 5ms). It shouldn't even take 5us on modern 1123 * DS8390's, but just in case it's an old one. 1124 */ 1125 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1126 1127 /* 1128 * Sledge hammer for NE-2000; reset entire board, otherwise, it 1129 * will ignore reinitialization and jam bus on next packet send. 1130 */ 1131 if (sc->mem_shared == 0) { 1132 u_char tmp; 1133 1134 /* reset the board ala probe() below */ 1135 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 1136 1137 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 1138 DELAY(5000); 1139 1140 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP); 1141 1142 DELAY(5000); 1143 } 1144 } 1145 1146 /* 1147 * Device timeout/watchdog routine. Entered if the device neglects to 1148 * generate an interrupt after a transmit has been started on it. 1149 */ 1150 void 1151 ed_watchdog(unit) 1152 int unit; 1153 { 1154 struct ed_softc *sc = &ed_softc[unit]; 1155 1156 log(LOG_ERR, "ed%d: device timeout\n", unit); 1157 ++sc->arpcom.ac_if.if_oerrors; 1158 1159 ed_reset(unit, 0); 1160 } 1161 1162 /* 1163 * Initialize device. 1164 */ 1165 void 1166 ed_init(unit) 1167 int unit; 1168 { 1169 struct ed_softc *sc = &ed_softc[unit]; 1170 struct ifnet *ifp = &sc->arpcom.ac_if; 1171 int i, s; 1172 u_char command; 1173 1174 /* address not known */ 1175 if (ifp->if_addrlist == (struct ifaddr *)0) return; 1176 1177 /* 1178 * Initialize the NIC in the exact order outlined in the NS manual. 1179 * This init procedure is "mandatory"...don't change what or when 1180 * things happen. 1181 */ 1182 s = splimp(); 1183 1184 /* reset transmitter flags */ 1185 sc->xmit_busy = 0; 1186 sc->arpcom.ac_if.if_timer = 0; 1187 1188 sc->txb_inuse = 0; 1189 sc->txb_new = 0; 1190 sc->txb_next_tx = 0; 1191 1192 /* This variable is used below - don't move this assignment */ 1193 sc->next_packet = sc->rec_page_start + 1; 1194 1195 /* 1196 * Set interface for page 0, Remote DMA complete, Stopped 1197 */ 1198 if (sc->is790) { 1199 outb(sc->nic_addr + ED_P0_CR, ED_CR_STP); 1200 } else { 1201 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STP); 1202 } 1203 if (sc->isa16bit) { 1204 /* 1205 * Set FIFO threshold to 8, No auto-init Remote DMA, 1206 * byte order=80x86, word-wide DMA xfers, 1207 */ 1208 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_WTS|ED_DCR_LS); 1209 } else { 1210 /* 1211 * Same as above, but byte-wide DMA xfers 1212 */ 1213 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1|ED_DCR_LS); 1214 } 1215 1216 /* 1217 * Clear Remote Byte Count Registers 1218 */ 1219 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1220 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1221 1222 /* 1223 * Enable reception of broadcast packets 1224 */ 1225 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 1226 1227 /* 1228 * Place NIC in internal loopback mode 1229 */ 1230 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1231 1232 /* 1233 * Initialize transmit/receive (ring-buffer) Page Start 1234 */ 1235 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1236 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1237 /* Set lower bits of byte addressable framing to 0 */ 1238 if (sc->is790) 1239 outb(sc->nic_addr + 0x09, 0); 1240 1241 /* 1242 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1243 */ 1244 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1245 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1246 1247 /* 1248 * Clear all interrupts. A '1' in each bit position clears the 1249 * corresponding flag. 1250 */ 1251 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1252 1253 /* 1254 * Enable the following interrupts: receive/transmit complete, 1255 * receive/transmit error, and Receiver OverWrite. 1256 * 1257 * Counter overflow and Remote DMA complete are *not* enabled. 1258 */ 1259 outb(sc->nic_addr + ED_P0_IMR, 1260 ED_IMR_PRXE|ED_IMR_PTXE|ED_IMR_RXEE|ED_IMR_TXEE|ED_IMR_OVWE); 1261 1262 /* 1263 * Program Command Register for page 1 1264 */ 1265 if (sc->is790) { 1266 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STP); 1267 } else { 1268 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STP); 1269 } 1270 /* 1271 * Copy out our station address 1272 */ 1273 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1274 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1275 1276 /*#if NBPFILTER > 0*/ 1277 /* 1278 * Initialize multicast address hashing registers to accept 1279 * all multicasts (only used when in promiscuous mode) 1280 */ 1281 for (i = 0; i < 8; ++i) 1282 outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff); 1283 /* #endif */ 1284 1285 /* 1286 * Set Current Page pointer to next_packet (initialized above) 1287 */ 1288 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1289 1290 /* 1291 * Set Command Register for page 0, Remote DMA complete, 1292 * and interface Start. 1293 */ 1294 if (sc->is790) { 1295 outb(sc->nic_addr + ED_P1_CR, ED_CR_STA); 1296 } else { 1297 outb(sc->nic_addr + ED_P1_CR, ED_CR_RD2|ED_CR_STA); 1298 } 1299 /* 1300 * Take interface out of loopback 1301 */ 1302 outb(sc->nic_addr + ED_P0_TCR, 0); 1303 1304 /* 1305 * If this is a 3Com board, the tranceiver must be software enabled 1306 * (there is no settable hardware default). 1307 */ 1308 if (sc->vendor == ED_VENDOR_3COM) { 1309 if (ifp->if_flags & IFF_ALTPHYS) { 1310 outb(sc->asic_addr + ED_3COM_CR, 0); 1311 } else { 1312 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1313 } 1314 } 1315 1316 /* 1317 * Set 'running' flag, and clear output active flag. 1318 */ 1319 ifp->if_flags |= IFF_RUNNING; 1320 ifp->if_flags &= ~IFF_OACTIVE; 1321 1322 /* 1323 * ...and attempt to start output 1324 */ 1325 ed_start(ifp); 1326 1327 (void) splx(s); 1328 } 1329 1330 /* 1331 * This routine actually starts the transmission on the interface 1332 */ 1333 static inline void ed_xmit(ifp) 1334 struct ifnet *ifp; 1335 { 1336 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1337 unsigned short len; 1338 1339 len = sc->txb_len[sc->txb_next_tx]; 1340 1341 /* 1342 * Set NIC for page 0 register access 1343 */ 1344 if (sc->is790) { 1345 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA); 1346 } else { 1347 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 1348 } 1349 /* 1350 * Set TX buffer start page 1351 */ 1352 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 1353 sc->txb_next_tx * ED_TXBUF_SIZE); 1354 1355 /* 1356 * Set TX length 1357 */ 1358 outb(sc->nic_addr + ED_P0_TBCR0, len); 1359 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 1360 1361 /* 1362 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 1363 */ 1364 if (sc->is790) { 1365 outb(sc->nic_addr + ED_P0_CR, ED_CR_TXP | ED_CR_STA); 1366 } else { 1367 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_TXP|ED_CR_STA); 1368 } 1369 sc->xmit_busy = 1; 1370 1371 /* 1372 * Point to next transmit buffer slot and wrap if necessary. 1373 */ 1374 sc->txb_next_tx++; 1375 if (sc->txb_next_tx == sc->txb_cnt) 1376 sc->txb_next_tx = 0; 1377 1378 /* 1379 * Set a timer just in case we never hear from the board again 1380 */ 1381 ifp->if_timer = 2; 1382 } 1383 1384 /* 1385 * Start output on interface. 1386 * We make two assumptions here: 1387 * 1) that the current priority is set to splimp _before_ this code 1388 * is called *and* is returned to the appropriate priority after 1389 * return 1390 * 2) that the IFF_OACTIVE flag is checked before this code is called 1391 * (i.e. that the output part of the interface is idle) 1392 */ 1393 void 1394 ed_start(ifp) 1395 struct ifnet *ifp; 1396 { 1397 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1398 struct mbuf *m0, *m; 1399 caddr_t buffer; 1400 int len; 1401 1402 outloop: 1403 /* 1404 * First, see if there are buffered packets and an idle 1405 * transmitter - should never happen at this point. 1406 */ 1407 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 1408 printf("ed: packets buffers, but transmitter idle\n"); 1409 ed_xmit(ifp); 1410 } 1411 1412 /* 1413 * See if there is room to put another packet in the buffer. 1414 */ 1415 if (sc->txb_inuse == sc->txb_cnt) { 1416 /* 1417 * No room. Indicate this to the outside world 1418 * and exit. 1419 */ 1420 ifp->if_flags |= IFF_OACTIVE; 1421 return; 1422 } 1423 1424 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 1425 if (m == 0) { 1426 /* 1427 * We are using the !OACTIVE flag to indicate to the outside 1428 * world that we can accept an additional packet rather than 1429 * that the transmitter is _actually_ active. Indeed, the 1430 * transmitter may be active, but if we haven't filled all 1431 * the buffers with data then we still want to accept more. 1432 */ 1433 ifp->if_flags &= ~IFF_OACTIVE; 1434 return; 1435 } 1436 1437 /* 1438 * Copy the mbuf chain into the transmit buffer 1439 */ 1440 1441 m0 = m; 1442 1443 /* txb_new points to next open buffer slot */ 1444 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 1445 1446 if (sc->mem_shared) { 1447 /* 1448 * Special case setup for 16 bit boards... 1449 */ 1450 if (sc->isa16bit) { 1451 switch (sc->vendor) { 1452 /* 1453 * For 16bit 3Com boards (which have 16k of memory), 1454 * we have the xmit buffers in a different page 1455 * of memory ('page 0') - so change pages. 1456 */ 1457 case ED_VENDOR_3COM: 1458 outb(sc->asic_addr + ED_3COM_GACFR, 1459 ED_3COM_GACFR_RSEL); 1460 break; 1461 /* 1462 * Enable 16bit access to shared memory on WD/SMC boards 1463 * Don't update wd_laar_proto because we want to restore the 1464 * previous state (because an arp reply in the input code 1465 * may cause a call-back to ed_start) 1466 * XXX - the call-back to 'start' is a bug, IMHO. 1467 */ 1468 case ED_VENDOR_WD_SMC: 1469 outb(sc->asic_addr + ED_WD_LAAR, 1470 (sc->wd_laar_proto | ED_WD_LAAR_M16EN)); 1471 } 1472 } 1473 1474 for (len = 0; m != 0; m = m->m_next) { 1475 memcpy(buffer, mtod(m, caddr_t), m->m_len); 1476 buffer += m->m_len; 1477 len += m->m_len; 1478 } 1479 1480 /* 1481 * Restore previous shared memory access 1482 */ 1483 if (sc->isa16bit) { 1484 switch (sc->vendor) { 1485 case ED_VENDOR_3COM: 1486 outb(sc->asic_addr + ED_3COM_GACFR, 1487 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 1488 break; 1489 case ED_VENDOR_WD_SMC: 1490 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 1491 break; 1492 } 1493 } 1494 } else { 1495 len = ed_pio_write_mbufs(sc, m, buffer); 1496 } 1497 1498 sc->txb_len[sc->txb_new] = max(len, ETHER_MIN_LEN); 1499 1500 sc->txb_inuse++; 1501 1502 /* 1503 * Point to next buffer slot and wrap if necessary. 1504 */ 1505 sc->txb_new++; 1506 if (sc->txb_new == sc->txb_cnt) 1507 sc->txb_new = 0; 1508 1509 if (sc->xmit_busy == 0) 1510 ed_xmit(ifp); 1511 /* 1512 * If there is BPF support in the configuration, tap off here. 1513 * The following has support for converting trailer packets 1514 * back to normal. 1515 * XXX - support for trailer packets in BPF should be moved into 1516 * the bpf code proper to avoid code duplication in all of 1517 * the drivers. 1518 */ 1519 /*#if NBPFILTER > 0 */ 1520 if (sc->bpf) { 1521 u_short etype; 1522 int off, datasize, resid; 1523 struct ether_header *eh; 1524 struct trailer_header trailer_header; 1525 char ether_packet[ETHER_MAX_LEN]; 1526 char *ep; 1527 1528 ep = ether_packet; 1529 1530 /* 1531 * We handle trailers below: 1532 * Copy ether header first, then residual data, 1533 * then data. Put all this in a temporary buffer 1534 * 'ether_packet' and send off to bpf. Since the 1535 * system has generated this packet, we assume 1536 * that all of the offsets in the packet are 1537 * correct; if they're not, the system will almost 1538 * certainly crash in m_copydata. 1539 * We make no assumptions about how the data is 1540 * arranged in the mbuf chain (i.e. how much 1541 * data is in each mbuf, if mbuf clusters are 1542 * used, etc.), which is why we use m_copydata 1543 * to get the ether header rather than assume 1544 * that this is located in the first mbuf. 1545 */ 1546 /* copy ether header */ 1547 m_copydata(m0, 0, sizeof(struct ether_header), ep); 1548 eh = (struct ether_header *) ep; 1549 ep += sizeof(struct ether_header); 1550 etype = ntohs(eh->ether_type); 1551 if (etype >= ETHERTYPE_TRAIL && 1552 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) { 1553 datasize = ((etype - ETHERTYPE_TRAIL) << 9); 1554 off = datasize + sizeof(struct ether_header); 1555 1556 /* copy trailer_header into a data structure */ 1557 m_copydata(m0, off, sizeof(struct trailer_header), 1558 (caddr_t)&trailer_header.ether_type); 1559 1560 /* copy residual data */ 1561 m_copydata(m0, off+sizeof(struct trailer_header), 1562 resid = ntohs(trailer_header.ether_residual) - 1563 sizeof(struct trailer_header), ep); 1564 ep += resid; 1565 1566 /* copy data */ 1567 m_copydata(m0, sizeof(struct ether_header), 1568 datasize, ep); 1569 ep += datasize; 1570 1571 /* restore original ether packet type */ 1572 eh->ether_type = trailer_header.ether_type; 1573 1574 bpf_tap(sc->bpf, ether_packet, ep - ether_packet); 1575 } else 1576 bpf_mtap(sc->bpf, m0); 1577 } 1578 /* #endif */ 1579 1580 m_freem(m0); 1581 1582 /* 1583 * Loop back to the top to possibly buffer more packets 1584 */ 1585 goto outloop; 1586 } 1587 1588 /* 1589 * Ethernet interface receiver interrupt. 1590 */ 1591 static inline void 1592 ed_rint(unit) 1593 int unit; 1594 { 1595 register struct ed_softc *sc = &ed_softc[unit]; 1596 u_char boundry, current; 1597 u_short len; 1598 struct ed_ring packet_hdr; 1599 char *packet_ptr; 1600 1601 /* 1602 * Set NIC to page 1 registers to get 'current' pointer 1603 */ 1604 if (sc->is790) { 1605 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA); 1606 } else { 1607 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA); 1608 } 1609 /* 1610 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e. 1611 * it points to where new data has been buffered. The 'CURR' 1612 * (current) register points to the logical end of the ring-buffer 1613 * - i.e. it points to where additional new data will be added. 1614 * We loop here until the logical beginning equals the logical 1615 * end (or in other words, until the ring-buffer is empty). 1616 */ 1617 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 1618 1619 /* get pointer to this buffer's header structure */ 1620 packet_ptr = sc->mem_ring + 1621 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 1622 1623 /* 1624 * The byte count includes the FCS - Frame Check Sequence (a 1625 * 32 bit CRC). 1626 */ 1627 if (sc->mem_shared) 1628 packet_hdr = *(struct ed_ring *)packet_ptr; 1629 else 1630 ed_pio_readmem(sc, packet_ptr, (char *) &packet_hdr, 1631 sizeof(packet_hdr)); 1632 len = packet_hdr.count; 1633 if ((len >= ETHER_MIN_LEN) && (len <= ETHER_MAX_LEN)) { 1634 /* 1635 * Go get packet. len - 4 removes CRC from length. 1636 */ 1637 ed_get_packet(sc, packet_ptr + 4, len - 4); 1638 ++sc->arpcom.ac_if.if_ipackets; 1639 } else { 1640 /* 1641 * Really BAD...probably indicates that the ring pointers 1642 * are corrupted. Also seen on early rev chips under 1643 * high load - the byte order of the length gets switched. 1644 */ 1645 log(LOG_ERR, 1646 "ed%d: NIC memory corrupt - invalid packet length %d\n", 1647 unit, len); 1648 ++sc->arpcom.ac_if.if_ierrors; 1649 ed_reset(unit, 0); 1650 return; 1651 } 1652 1653 /* 1654 * Update next packet pointer 1655 */ 1656 sc->next_packet = packet_hdr.next_packet; 1657 1658 /* 1659 * Update NIC boundry pointer - being careful to keep it 1660 * one buffer behind. (as recommended by NS databook) 1661 */ 1662 boundry = sc->next_packet - 1; 1663 if (boundry < sc->rec_page_start) 1664 boundry = sc->rec_page_stop - 1; 1665 1666 /* 1667 * Set NIC to page 0 registers to update boundry register 1668 */ 1669 if (sc->is790) { 1670 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA); 1671 } else { 1672 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 1673 } 1674 outb(sc->nic_addr + ED_P0_BNRY, boundry); 1675 1676 /* 1677 * Set NIC to page 1 registers before looping to top (prepare to 1678 * get 'CURR' current pointer) 1679 */ 1680 if (sc->is790) { 1681 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_STA); 1682 } else { 1683 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_1|ED_CR_RD2|ED_CR_STA); 1684 } 1685 } 1686 } 1687 1688 /* 1689 * Ethernet interface interrupt processor 1690 */ 1691 void 1692 edintr(unit) 1693 int unit; 1694 { 1695 struct ed_softc *sc = &ed_softc[unit]; 1696 u_char isr; 1697 1698 /* 1699 * Set NIC to page 0 registers 1700 */ 1701 if (sc->is790) { 1702 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA); 1703 } else { 1704 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 1705 } 1706 /* 1707 * loop until there are no more new interrupts 1708 */ 1709 while (isr = inb(sc->nic_addr + ED_P0_ISR)) { 1710 1711 /* 1712 * reset all the bits that we are 'acknowledging' 1713 * by writing a '1' to each bit position that was set 1714 * (writing a '1' *clears* the bit) 1715 */ 1716 outb(sc->nic_addr + ED_P0_ISR, isr); 1717 1718 /* 1719 * Handle transmitter interrupts. Handle these first 1720 * because the receiver will reset the board under 1721 * some conditions. 1722 */ 1723 if (isr & (ED_ISR_PTX|ED_ISR_TXE)) { 1724 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 1725 1726 /* 1727 * Check for transmit error. If a TX completed with an 1728 * error, we end up throwing the packet away. Really 1729 * the only error that is possible is excessive 1730 * collisions, and in this case it is best to allow the 1731 * automatic mechanisms of TCP to backoff the flow. Of 1732 * course, with UDP we're screwed, but this is expected 1733 * when a network is heavily loaded. 1734 */ 1735 (void) inb(sc->nic_addr + ED_P0_TSR); 1736 if (isr & ED_ISR_TXE) { 1737 1738 /* 1739 * Excessive collisions (16) 1740 */ 1741 if ((inb(sc->nic_addr + ED_P0_TSR) & ED_TSR_ABT) 1742 && (collisions == 0)) { 1743 /* 1744 * When collisions total 16, the 1745 * P0_NCR will indicate 0, and the 1746 * TSR_ABT is set. 1747 */ 1748 collisions = 16; 1749 } 1750 1751 /* 1752 * update output errors counter 1753 */ 1754 ++sc->arpcom.ac_if.if_oerrors; 1755 } else { 1756 /* 1757 * Update total number of successfully 1758 * transmitted packets. 1759 */ 1760 ++sc->arpcom.ac_if.if_opackets; 1761 } 1762 1763 /* 1764 * reset tx busy and output active flags 1765 */ 1766 sc->xmit_busy = 0; 1767 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 1768 1769 /* 1770 * clear watchdog timer 1771 */ 1772 sc->arpcom.ac_if.if_timer = 0; 1773 1774 /* 1775 * Add in total number of collisions on last 1776 * transmission. 1777 */ 1778 sc->arpcom.ac_if.if_collisions += collisions; 1779 1780 /* 1781 * Decrement buffer in-use count if not zero (can only 1782 * be zero if a transmitter interrupt occured while 1783 * not actually transmitting). 1784 * If data is ready to transmit, start it transmitting, 1785 * otherwise defer until after handling receiver 1786 */ 1787 if (sc->txb_inuse && --sc->txb_inuse) 1788 ed_xmit(&sc->arpcom.ac_if); 1789 } 1790 1791 /* 1792 * Handle receiver interrupts 1793 */ 1794 if (isr & (ED_ISR_PRX|ED_ISR_RXE|ED_ISR_OVW)) { 1795 /* 1796 * Overwrite warning. In order to make sure that a lockup 1797 * of the local DMA hasn't occurred, we reset and 1798 * re-init the NIC. The NSC manual suggests only a 1799 * partial reset/re-init is necessary - but some 1800 * chips seem to want more. The DMA lockup has been 1801 * seen only with early rev chips - Methinks this 1802 * bug was fixed in later revs. -DG 1803 */ 1804 if (isr & ED_ISR_OVW) { 1805 ++sc->arpcom.ac_if.if_ierrors; 1806 #ifdef DIAGNOSTIC 1807 log(LOG_WARNING, 1808 "ed%d: warning - receiver ring buffer overrun\n", 1809 unit); 1810 #endif 1811 /* 1812 * Stop/reset/re-init NIC 1813 */ 1814 ed_reset(unit, 0); 1815 } else { 1816 1817 /* 1818 * Receiver Error. One or more of: CRC error, frame 1819 * alignment error FIFO overrun, or missed packet. 1820 */ 1821 if (isr & ED_ISR_RXE) { 1822 ++sc->arpcom.ac_if.if_ierrors; 1823 #ifdef ED_DEBUG 1824 printf("ed%d: receive error %x\n", unit, 1825 inb(sc->nic_addr + ED_P0_RSR)); 1826 #endif 1827 } 1828 1829 /* 1830 * Go get the packet(s) 1831 * XXX - Doing this on an error is dubious 1832 * because there shouldn't be any data to 1833 * get (we've configured the interface to 1834 * not accept packets with errors). 1835 */ 1836 1837 /* 1838 * Enable 16bit access to shared memory first 1839 * on WD/SMC boards. 1840 */ 1841 if (sc->isa16bit && 1842 (sc->vendor == ED_VENDOR_WD_SMC)) { 1843 1844 outb(sc->asic_addr + ED_WD_LAAR, 1845 (sc->wd_laar_proto |= 1846 ED_WD_LAAR_M16EN)); 1847 } 1848 1849 ed_rint (unit); 1850 1851 /* disable 16bit access */ 1852 if (sc->isa16bit && 1853 (sc->vendor == ED_VENDOR_WD_SMC)) { 1854 1855 outb(sc->asic_addr + ED_WD_LAAR, 1856 (sc->wd_laar_proto &= 1857 ~ED_WD_LAAR_M16EN)); 1858 } 1859 } 1860 } 1861 1862 /* 1863 * If it looks like the transmitter can take more data, 1864 * attempt to start output on the interface. 1865 * This is done after handling the receiver to 1866 * give the receiver priority. 1867 */ 1868 if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0) 1869 ed_start(&sc->arpcom.ac_if); 1870 1871 /* 1872 * return NIC CR to standard state: page 0, remote DMA complete, 1873 * start (toggling the TXP bit off, even if was just set 1874 * in the transmit routine, is *okay* - it is 'edge' 1875 * triggered from low to high) 1876 */ 1877 if (sc->is790) { 1878 outb(sc->nic_addr + ED_P0_CR, ED_CR_STA); 1879 } else { 1880 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 1881 } 1882 /* 1883 * If the Network Talley Counters overflow, read them to 1884 * reset them. It appears that old 8390's won't 1885 * clear the ISR flag otherwise - resulting in an 1886 * infinite loop. 1887 */ 1888 if (isr & ED_ISR_CNT) { 1889 (void) inb(sc->nic_addr + ED_P0_CNTR0); 1890 (void) inb(sc->nic_addr + ED_P0_CNTR1); 1891 (void) inb(sc->nic_addr + ED_P0_CNTR2); 1892 } 1893 } 1894 } 1895 1896 /* 1897 * Process an ioctl request. This code needs some work - it looks 1898 * pretty ugly. 1899 */ 1900 int 1901 ed_ioctl(ifp, command, data) 1902 register struct ifnet *ifp; 1903 int command; 1904 caddr_t data; 1905 { 1906 register struct ifaddr *ifa = (struct ifaddr *)data; 1907 struct ed_softc *sc = &ed_softc[ifp->if_unit]; 1908 struct ifreq *ifr = (struct ifreq *)data; 1909 int s, error = 0; 1910 1911 s = splimp(); 1912 1913 switch (command) { 1914 1915 case SIOCSIFADDR: 1916 ifp->if_flags |= IFF_UP; 1917 1918 switch (ifa->ifa_addr->sa_family) { 1919 #ifdef INET 1920 case AF_INET: 1921 ed_init(ifp->if_unit); /* before arpwhohas */ 1922 /* 1923 * See if another station has *our* IP address. 1924 * i.e.: There is an address conflict! If a 1925 * conflict exists, a message is sent to the 1926 * console. 1927 */ 1928 ((struct arpcom *)ifp)->ac_ipaddr = 1929 IA_SIN(ifa)->sin_addr; 1930 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr); 1931 break; 1932 #endif 1933 #ifdef NS 1934 /* 1935 * XXX - This code is probably wrong 1936 */ 1937 case AF_NS: 1938 { 1939 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr); 1940 1941 if (ns_nullhost(*ina)) 1942 ina->x_host = 1943 *(union ns_host *)(sc->arpcom.ac_enaddr); 1944 else { 1945 /* 1946 * 1947 */ 1948 memcpy((caddr_t)sc->arpcom.ac_enaddr, 1949 (caddr_t)ina->x_host.c_host, 1950 sizeof(sc->arpcom.ac_enaddr)); 1951 } 1952 /* 1953 * Set new address 1954 */ 1955 ed_init(ifp->if_unit); 1956 break; 1957 } 1958 #endif 1959 default: 1960 ed_init(ifp->if_unit); 1961 break; 1962 } 1963 break; 1964 1965 case SIOCSIFFLAGS: 1966 /* 1967 * If interface is marked down and it is running, then stop it 1968 */ 1969 if (((ifp->if_flags & IFF_UP) == 0) && 1970 (ifp->if_flags & IFF_RUNNING)) { 1971 ed_stop(ifp->if_unit); 1972 ifp->if_flags &= ~IFF_RUNNING; 1973 } else { 1974 /* 1975 * If interface is marked up and it is stopped, then start it 1976 */ 1977 if ((ifp->if_flags & IFF_UP) && 1978 ((ifp->if_flags & IFF_RUNNING) == 0)) 1979 ed_init(ifp->if_unit); 1980 } 1981 #if NBPFILTER > 0 1982 if (ifp->if_flags & IFF_PROMISC) { 1983 /* 1984 * Set promiscuous mode on interface. 1985 * XXX - for multicasts to work, we would need to 1986 * write 1's in all bits of multicast 1987 * hashing array. For now we assume that 1988 * this was done in ed_init(). 1989 */ 1990 outb(sc->nic_addr + ED_P0_RCR, 1991 ED_RCR_PRO|ED_RCR_AM|ED_RCR_AB); 1992 } else { 1993 /* 1994 * XXX - for multicasts to work, we would need to 1995 * rewrite the multicast hashing array with the 1996 * proper hash (would have been destroyed above). 1997 */ 1998 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 1999 } 2000 #endif 2001 /* 2002 * An unfortunate hack to provide the (required) software control 2003 * of the tranceiver for 3Com boards. The ALTPHYS flag disables 2004 * the tranceiver if set. 2005 */ 2006 if (sc->vendor == ED_VENDOR_3COM) { 2007 if (ifp->if_flags & IFF_ALTPHYS) { 2008 outb(sc->asic_addr + ED_3COM_CR, 0); 2009 } else { 2010 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2011 } 2012 } 2013 2014 break; 2015 2016 default: 2017 error = EINVAL; 2018 } 2019 (void) splx(s); 2020 return (error); 2021 } 2022 2023 /* 2024 * Macro to calculate a new address within shared memory when given an offset 2025 * from an address, taking into account ring-wrap. 2026 */ 2027 #define ringoffset(sc, start, off, type) \ 2028 ((type)( ((caddr_t)(start)+(off) >= (sc)->mem_end) ? \ 2029 (((caddr_t)(start)+(off))) - (sc)->mem_end \ 2030 + (sc)->mem_ring: \ 2031 ((caddr_t)(start)+(off)) )) 2032 2033 /* 2034 * Retreive packet from shared memory and send to the next level up via 2035 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2036 */ 2037 static void 2038 ed_get_packet(sc, buf, len) 2039 struct ed_softc *sc; 2040 char *buf; 2041 u_short len; 2042 { 2043 struct ether_header *eh; 2044 struct mbuf *m, *head = 0, *ed_ring_to_mbuf(); 2045 u_short off; 2046 int resid; 2047 u_short etype; 2048 struct trailer_header trailer_header; 2049 2050 /* Allocate a header mbuf */ 2051 MGETHDR(m, M_DONTWAIT, MT_DATA); 2052 if (m == 0) 2053 goto bad; 2054 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2055 m->m_pkthdr.len = len; 2056 m->m_len = 0; 2057 head = m; 2058 2059 /* The following sillines is to make NFS happy */ 2060 #define EROUND ((sizeof(struct ether_header) + 3) & ~3) 2061 #define EOFF (EROUND - sizeof(struct ether_header)) 2062 2063 /* 2064 * The following assumes there is room for 2065 * the ether header in the header mbuf 2066 */ 2067 head->m_data += EOFF; 2068 eh = mtod(head, struct ether_header *); 2069 2070 if (sc->mem_shared) 2071 memcpy(mtod(head, caddr_t), buf, sizeof(struct ether_header)); 2072 else 2073 ed_pio_readmem(sc, buf, mtod(head, caddr_t), 2074 sizeof(struct ether_header)); 2075 buf += sizeof(struct ether_header); 2076 head->m_len += sizeof(struct ether_header); 2077 len -= sizeof(struct ether_header); 2078 2079 etype = ntohs((u_short)eh->ether_type); 2080 2081 /* 2082 * Deal with trailer protocol: 2083 * If trailer protocol, calculate the datasize as 'off', 2084 * which is also the offset to the trailer header. 2085 * Set resid to the amount of packet data following the 2086 * trailer header. 2087 * Finally, copy residual data into mbuf chain. 2088 */ 2089 if (etype >= ETHERTYPE_TRAIL && 2090 etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) { 2091 2092 off = (etype - ETHERTYPE_TRAIL) << 9; 2093 if ((off + sizeof(struct trailer_header)) > len) 2094 goto bad; /* insanity */ 2095 2096 /* 2097 * If we have shared memory, we can get info directly from the 2098 * stored packet, otherwise we must get a local copy 2099 * of the trailer header using PIO. 2100 */ 2101 if (sc->mem_shared) { 2102 eh->ether_type = *ringoffset(sc, buf, off, u_short *); 2103 resid = ntohs(*ringoffset(sc, buf, off+2, u_short *)); 2104 } else { 2105 struct trailer_header trailer_header; 2106 ed_pio_readmem(sc, 2107 ringoffset(sc, buf, off, caddr_t), 2108 (char *) &trailer_header, 2109 sizeof(trailer_header)); 2110 eh->ether_type = trailer_header.ether_type; 2111 resid = trailer_header.ether_residual; 2112 } 2113 2114 if ((off + resid) > len) goto bad; /* insanity */ 2115 2116 resid -= sizeof(struct trailer_header); 2117 if (resid < 0) goto bad; /* insanity */ 2118 2119 m = ed_ring_to_mbuf(sc, ringoffset(sc, buf, off+4, char *), head, resid); 2120 if (m == 0) goto bad; 2121 2122 len = off; 2123 head->m_pkthdr.len -= 4; /* subtract trailer header */ 2124 } 2125 2126 /* 2127 * Pull packet off interface. Or if this was a trailer packet, 2128 * the data portion is appended. 2129 */ 2130 m = ed_ring_to_mbuf(sc, buf, m, len); 2131 if (m == 0) goto bad; 2132 2133 /*#if NBPFILTER > 0*/ 2134 /* 2135 * Check if there's a BPF listener on this interface. 2136 * If so, hand off the raw packet to bpf. 2137 */ 2138 if (sc->bpf) { 2139 bpf_mtap(sc->bpf, head); 2140 2141 /* 2142 * Note that the interface cannot be in promiscuous mode if 2143 * there are no BPF listeners. And if we are in promiscuous 2144 * mode, we have to check if this packet is really ours. 2145 * 2146 * XXX This test does not support multicasts. 2147 */ 2148 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2149 memcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2150 sizeof(eh->ether_dhost)) != 0 && 2151 memcmp(eh->ether_dhost, etherbroadcastaddr, 2152 sizeof(eh->ether_dhost)) != 0) { 2153 2154 m_freem(head); 2155 return; 2156 } 2157 } 2158 /* #endif */ 2159 2160 /* 2161 * Fix up data start offset in mbuf to point past ether header 2162 */ 2163 m_adj(head, sizeof(struct ether_header)); 2164 2165 /* 2166 * silly ether_input routine needs 'type' in host byte order 2167 */ 2168 eh->ether_type = ntohs(eh->ether_type); 2169 2170 ether_input(&sc->arpcom.ac_if, eh, head); 2171 return; 2172 2173 bad: if (head) 2174 m_freem(head); 2175 return; 2176 } 2177 2178 /* 2179 * Supporting routines 2180 */ 2181 2182 /* 2183 * Given a NIC memory source address and a host memory destination 2184 * address, copy 'amount' from NIC to host using Programmed I/O. 2185 * The 'amount' is rounded up to a word - okay as long as mbufs 2186 * are word sized. 2187 * This routine is currently Novell-specific. 2188 */ 2189 void 2190 ed_pio_readmem(sc,src,dst,amount) 2191 struct ed_softc *sc; 2192 unsigned short src; 2193 unsigned char *dst; 2194 unsigned short amount; 2195 { 2196 unsigned short tmp_amount; 2197 2198 /* select page 0 registers */ 2199 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 2200 2201 /* round up to a word */ 2202 tmp_amount = amount; 2203 if (amount & 1) ++amount; 2204 2205 /* set up DMA byte count */ 2206 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2207 outb(sc->nic_addr + ED_P0_RBCR1, amount>>8); 2208 2209 /* set up source address in NIC mem */ 2210 outb(sc->nic_addr + ED_P0_RSAR0, src); 2211 outb(sc->nic_addr + ED_P0_RSAR1, src>>8); 2212 2213 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2214 2215 if (sc->isa16bit) { 2216 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount/2); 2217 } else 2218 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2219 2220 } 2221 2222 /* 2223 * Stripped down routine for writing a linear buffer to NIC memory. 2224 * Only used in the probe routine to test the memory. 'len' must 2225 * be even. 2226 */ 2227 void 2228 ed_pio_writemem(sc,src,dst,len) 2229 struct ed_softc *sc; 2230 char *src; 2231 unsigned short dst; 2232 unsigned short len; 2233 { 2234 int maxwait=100; /* about 120us */ 2235 2236 /* select page 0 registers */ 2237 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 2238 2239 /* reset remote DMA complete flag */ 2240 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2241 2242 /* set up DMA byte count */ 2243 outb(sc->nic_addr + ED_P0_RBCR0, len); 2244 outb(sc->nic_addr + ED_P0_RBCR1, len>>8); 2245 2246 /* set up destination address in NIC mem */ 2247 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2248 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8); 2249 2250 /* set remote DMA write */ 2251 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2252 2253 if (sc->isa16bit) 2254 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len/2); 2255 else 2256 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2257 /* 2258 * Wait for remote DMA complete. This is necessary because on the 2259 * transmit side, data is handled internally by the NIC in bursts 2260 * and we can't start another remote DMA until this one completes. 2261 * Not waiting causes really bad things to happen - like the NIC 2262 * irrecoverably jamming the ISA bus. 2263 */ 2264 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2265 } 2266 2267 /* 2268 * Write an mbuf chain to the destination NIC memory address using 2269 * programmed I/O. 2270 */ 2271 u_short 2272 ed_pio_write_mbufs(sc,m,dst) 2273 struct ed_softc *sc; 2274 struct mbuf *m; 2275 unsigned short dst; 2276 { 2277 unsigned short len, mb_offset; 2278 struct mbuf *mp; 2279 unsigned char residual[2]; 2280 int maxwait=100; /* about 120us */ 2281 2282 /* First, count up the total number of bytes to copy */ 2283 for (len = 0, mp = m; mp; mp = mp->m_next) 2284 len += mp->m_len; 2285 2286 /* select page 0 registers */ 2287 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2|ED_CR_STA); 2288 2289 /* reset remote DMA complete flag */ 2290 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2291 2292 /* set up DMA byte count */ 2293 outb(sc->nic_addr + ED_P0_RBCR0, len); 2294 outb(sc->nic_addr + ED_P0_RBCR1, len>>8); 2295 2296 /* set up destination address in NIC mem */ 2297 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2298 outb(sc->nic_addr + ED_P0_RSAR1, dst>>8); 2299 2300 /* set remote DMA write */ 2301 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2302 2303 mb_offset = 0; 2304 /* 2305 * Transfer the mbuf chain to the NIC memory. 2306 * The following code isn't too pretty. The problem is that we can only 2307 * transfer words to the board, and if an mbuf has an odd number 2308 * of bytes in it, this is a problem. It's not a simple matter of 2309 * just removing a byte from the next mbuf (adjusting data++ and 2310 * len--) because this will hose-over the mbuf chain which might 2311 * be needed later for BPF. Instead, we maintain an offset 2312 * (mb_offset) which let's us skip over the first byte in the 2313 * following mbuf. 2314 */ 2315 while (m) { 2316 if (m->m_len - mb_offset) { 2317 if (sc->isa16bit) { 2318 if ((m->m_len - mb_offset) > 1) 2319 outsw(sc->asic_addr + ED_NOVELL_DATA, 2320 mtod(m, caddr_t) + mb_offset, 2321 (m->m_len - mb_offset) / 2); 2322 2323 /* 2324 * if odd number of bytes, get the odd byte from 2325 * the next mbuf with data 2326 */ 2327 if ((m->m_len - mb_offset) & 1) { 2328 /* first the last byte in current mbuf */ 2329 residual[0] = *(mtod(m, caddr_t) 2330 + m->m_len - 1); 2331 2332 /* advance past any empty mbufs */ 2333 while (m->m_next && (m->m_next->m_len == 0)) 2334 m = m->m_next; 2335 2336 if (m->m_next) { 2337 /* remove first byte in next mbuf */ 2338 residual[1] = *(mtod(m->m_next, caddr_t)); 2339 mb_offset = 1; 2340 } 2341 2342 outw(sc->asic_addr + ED_NOVELL_DATA, 2343 *((unsigned short *) residual)); 2344 } else 2345 mb_offset = 0; 2346 } else 2347 outsb(sc->asic_addr + ED_NOVELL_DATA, m->m_data, m->m_len); 2348 2349 } 2350 m = m->m_next; 2351 } 2352 2353 /* 2354 * Wait for remote DMA complete. This is necessary because on the 2355 * transmit side, data is handled internally by the NIC in bursts 2356 * and we can't start another remote DMA until this one completes. 2357 * Not waiting causes really bad things to happen - like the NIC 2358 * irrecoverably jamming the ISA bus. 2359 */ 2360 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2361 2362 if (!maxwait) { 2363 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 2364 sc->arpcom.ac_if.if_unit); 2365 ed_reset(sc->arpcom.ac_if.if_unit, 0); 2366 } 2367 2368 return(len); 2369 } 2370 2371 /* 2372 * Given a source and destination address, copy 'amount' of a packet from 2373 * the ring buffer into a linear destination buffer. Takes into account 2374 * ring-wrap. 2375 */ 2376 static inline char * 2377 ed_ring_copy(sc,src,dst,amount) 2378 struct ed_softc *sc; 2379 char *src; 2380 char *dst; 2381 u_short amount; 2382 { 2383 u_short tmp_amount; 2384 2385 /* does copy wrap to lower addr in ring buffer? */ 2386 if (src + amount > sc->mem_end) { 2387 tmp_amount = sc->mem_end - src; 2388 2389 /* copy amount up to end of NIC memory */ 2390 if (sc->mem_shared) 2391 memcpy(dst, src, tmp_amount); 2392 else 2393 ed_pio_readmem(sc,src,dst,tmp_amount); 2394 2395 amount -= tmp_amount; 2396 src = sc->mem_ring; 2397 dst += tmp_amount; 2398 } 2399 2400 if (sc->mem_shared) 2401 memcpy(dst, src, amount); 2402 else 2403 ed_pio_readmem(sc, src, dst, amount); 2404 2405 return(src + amount); 2406 } 2407 2408 /* 2409 * Copy data from receive buffer to end of mbuf chain 2410 * allocate additional mbufs as needed. return pointer 2411 * to last mbuf in chain. 2412 * sc = ed info (softc) 2413 * src = pointer in ed ring buffer 2414 * dst = pointer to last mbuf in mbuf chain to copy to 2415 * amount = amount of data to copy 2416 */ 2417 struct mbuf * 2418 ed_ring_to_mbuf(sc,src,dst,total_len) 2419 struct ed_softc *sc; 2420 char *src; 2421 struct mbuf *dst; 2422 u_short total_len; 2423 { 2424 register struct mbuf *m = dst; 2425 2426 while (total_len) { 2427 register u_short amount = min(total_len, M_TRAILINGSPACE(m)); 2428 2429 if (amount == 0) { /* no more data in this mbuf, alloc another */ 2430 /* 2431 * If there is enough data for an mbuf cluster, attempt 2432 * to allocate one of those, otherwise, a regular 2433 * mbuf will do. 2434 * Note that a regular mbuf is always required, even if 2435 * we get a cluster - getting a cluster does not 2436 * allocate any mbufs, and one is needed to assign 2437 * the cluster to. The mbuf that has a cluster 2438 * extension can not be used to contain data - only 2439 * the cluster can contain data. 2440 */ 2441 dst = m; 2442 MGET(m, M_DONTWAIT, MT_DATA); 2443 if (m == 0) 2444 return (0); 2445 2446 if (total_len >= MINCLSIZE) 2447 MCLGET(m, M_DONTWAIT); 2448 2449 m->m_len = 0; 2450 dst->m_next = m; 2451 amount = min(total_len, M_TRAILINGSPACE(m)); 2452 } 2453 2454 src = ed_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount); 2455 2456 m->m_len += amount; 2457 total_len -= amount; 2458 2459 } 2460 return (m); 2461 } 2462 2463 DRIVER_MODCONFIG() { 2464 char *cfg_string; 2465 2466 /* find configuration string. */ 2467 if (!config_scan(ed_config, &cfg_string)) 2468 return; 2469 2470 /* allocate controller resources */ 2471 ned = 1; 2472 (void)cfg_number(&cfg_string, &ned); 2473 ed_softc = (struct ed_softc *) 2474 malloc(sizeof(struct ed_softc) * ned, M_TEMP, M_NOWAIT); 2475 (void)memset((void *)ed_softc, 0, sizeof (struct ed_softc) * ned); 2476 2477 /* XXX: configure driver into kernel program (done by probe/attach) */ 2478 2479 /* probe for hardware */ 2480 new_isa_configure(&cfg_string, &eddriver); 2481 } 2482