1 /* Emulations of the CB operations of the Z80 instruction set. 2 * Copyright (C) 1994 Ian Collier. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #define var_t unsigned char t 20 #define rlc(x) (x=(x<<1)|(x>>7),rflags(x,x&1)) 21 #define rrc(x) do{var_t=x&1;x=(x>>1)|(t<<7);rflags(x,t);}while(0) 22 #define rl(x) do{var_t=x>>7;x=(x<<1)|(f&1);rflags(x,t);}while(0) 23 #define rr(x) do{var_t=x&1;x=(x>>1)|(f<<7);rflags(x,t);}while(0) 24 #define sla(x) do{var_t=x>>7;x<<=1;rflags(x,t);}while(0) 25 #define sra(x) do{var_t=x&1;x=((signed char)x)>>1;rflags(x,t);}while(0) 26 #define sll(x) do{var_t=x>>7;x=(x<<1)|1;rflags(x,t);}while(0) 27 #define srl(x) do{var_t=x&1;x>>=1;rflags(x,t);}while(0) 28 29 #define rflags(x,c) (f=(c)|(x&0xa8)|((!x)<<6)|parity(x)) 30 31 #define bit(n,x) (f=(f&1)|((x&(1<<n))?0x10:0x54)|(x&0x28)) 32 #define set(n,x) (x|=(1<<n)) 33 #define res(n,x) (x&=~(1<<n)) 34 35 { 36 /* reg/val are initialised to stop gcc's (incorrect) warning, 37 * and static to save initialising them every time. 38 */ 39 static unsigned char reg=0,val=0; 40 unsigned short addr; 41 unsigned char op; 42 if(ixoriy){ 43 addr=(ixoriy==1?ix:iy)+(signed char)fetch(pc); 44 pc++; 45 tstates+=8; 46 op=fetch(pc); 47 reg=op&7; 48 op=(op&0xf8)|6; 49 } 50 else{ 51 op=fetch(pc); 52 tstates+=4; 53 radjust++; 54 addr=hl; 55 } 56 pc++; 57 58 if(op<64)switch(op){ 59 case 0: rlc(b); break; 60 case 1: rlc(c); break; 61 case 2: rlc(d); break; 62 case 3: rlc(e); break; 63 case 4: rlc(h); break; 64 case 5: rlc(l); break; 65 case 6: tstates+=7;val=fetch(addr);rlc(val);store(addr,val);break; 66 case 7: rlc(a); break; 67 case 8: rrc(b); break; 68 case 9: rrc(c); break; 69 case 10: rrc(d); break; 70 case 11: rrc(e); break; 71 case 12: rrc(h); break; 72 case 13: rrc(l); break; 73 case 14: tstates+=7;val=fetch(addr);rrc(val);store(addr,val);break; 74 case 15: rrc(a); break; 75 case 0x10: rl(b); break; 76 case 0x11: rl(c); break; 77 case 0x12: rl(d); break; 78 case 0x13: rl(e); break; 79 case 0x14: rl(h); break; 80 case 0x15: rl(l); break; 81 case 0x16: tstates+=7;val=fetch(addr);rl(val);store(addr,val);break; 82 case 0x17: rl(a); break; 83 case 0x18: rr(b); break; 84 case 0x19: rr(c); break; 85 case 0x1a: rr(d); break; 86 case 0x1b: rr(e); break; 87 case 0x1c: rr(h); break; 88 case 0x1d: rr(l); break; 89 case 0x1e: tstates+=7;val=fetch(addr);rr(val);store(addr,val);break; 90 case 0x1f: rr(a); break; 91 case 0x20: sla(b); break; 92 case 0x21: sla(c); break; 93 case 0x22: sla(d); break; 94 case 0x23: sla(e); break; 95 case 0x24: sla(h); break; 96 case 0x25: sla(l); break; 97 case 0x26: tstates+=7;val=fetch(addr);sla(val);store(addr,val);break; 98 case 0x27: sla(a); break; 99 case 0x28: sra(b); break; 100 case 0x29: sra(c); break; 101 case 0x2a: sra(d); break; 102 case 0x2b: sra(e); break; 103 case 0x2c: sra(h); break; 104 case 0x2d: sra(l); break; 105 case 0x2e: tstates+=7;val=fetch(addr);sra(val);store(addr,val);break; 106 case 0x2f: sra(a); break; 107 case 0x30: sll(b); break; 108 case 0x31: sll(c); break; 109 case 0x32: sll(d); break; 110 case 0x33: sll(e); break; 111 case 0x34: sll(h); break; 112 case 0x35: sll(l); break; 113 case 0x36: tstates+=7;val=fetch(addr);sll(val);store(addr,val);break; 114 case 0x37: sll(a); break; 115 case 0x38: srl(b); break; 116 case 0x39: srl(c); break; 117 case 0x3a: srl(d); break; 118 case 0x3b: srl(e); break; 119 case 0x3c: srl(h); break; 120 case 0x3d: srl(l); break; 121 case 0x3e: tstates+=7;val=fetch(addr);srl(val);store(addr,val);break; 122 case 0x3f: srl(a); break; 123 } 124 else{ 125 unsigned char n=(op>>3)&7; 126 switch(op&0xc7){ 127 case 0x40: bit(n,b); break; 128 case 0x41: bit(n,c); break; 129 case 0x42: bit(n,d); break; 130 case 0x43: bit(n,e); break; 131 case 0x44: bit(n,h); break; 132 case 0x45: bit(n,l); break; 133 case 0x46: tstates+=4;val=fetch(addr);bit(n,val);store(addr,val);break; 134 case 0x47: bit(n,a); break; 135 case 0x80: res(n,b); break; 136 case 0x81: res(n,c); break; 137 case 0x82: res(n,d); break; 138 case 0x83: res(n,e); break; 139 case 0x84: res(n,h); break; 140 case 0x85: res(n,l); break; 141 case 0x86: tstates+=4;val=fetch(addr);res(n,val);store(addr,val);break; 142 case 0x87: res(n,a); break; 143 case 0xc0: set(n,b); break; 144 case 0xc1: set(n,c); break; 145 case 0xc2: set(n,d); break; 146 case 0xc3: set(n,e); break; 147 case 0xc4: set(n,h); break; 148 case 0xc5: set(n,l); break; 149 case 0xc6: tstates+=4;val=fetch(addr);set(n,val);store(addr,val);break; 150 case 0xc7: set(n,a); break; 151 } 152 } 153 if(ixoriy)switch(reg){ 154 case 0:b=val; break; 155 case 1:c=val; break; 156 case 2:d=val; break; 157 case 3:e=val; break; 158 case 4:h=val; break; 159 case 5:l=val; break; 160 case 7:a=val; break; 161 } 162 } 163 164 #undef var_t 165 #undef rlc 166 #undef rrc 167 #undef rl 168 #undef rr 169 #undef sla 170 #undef sra 171 #undef sll 172 #undef srl 173 #undef rflags 174 #undef bit 175 #undef set 176 #undef res 177