1--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
2----------------------------------------------------------------------------------
3--Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019
4--Date        : Mon May  4 20:06:12 2020
5--Host        : bata running 64-bit Ubuntu 18.04.3 LTS
6--Command     : generate_target main_wrapper.bd
7--Design      : main_wrapper
8--Purpose     : IP block netlist
9----------------------------------------------------------------------------------
10library IEEE;
11use IEEE.STD_LOGIC_1164.ALL;
12library UNISIM;
13use UNISIM.VCOMPONENTS.ALL;
14entity main_wrapper is
15  port (
16    ack_error : out STD_LOGIC;
17    bclk : out STD_LOGIC;
18    bclkpmod : out STD_LOGIC;
19    bypass_analog : in STD_LOGIC;
20    bypass_dsp : in STD_LOGIC;
21    bypass_faust : in STD_LOGIC;
22    in_mute : in STD_LOGIC;
23    mclk : out STD_LOGIC;
24    mclkpmod : out STD_LOGIC;
25    out_mute : out STD_LOGIC;
26    reset_btn : in STD_LOGIC;
27    sclk : inout STD_LOGIC;
28    sclpmod : out STD_LOGIC;
29    sd_rx : in STD_LOGIC;
30    sd_rxpmod : out STD_LOGIC;
31    sd_tx : out STD_LOGIC;
32    sd_txpmod : out STD_LOGIC;
33    sdapmod : out STD_LOGIC;
34    sdin : inout STD_LOGIC;
35    sys_clk : in STD_LOGIC;
36    vol_down : in STD_LOGIC;
37    vol_up : in STD_LOGIC;
38    ws_rx : out STD_LOGIC;
39    ws_tx : out STD_LOGIC;
40    wspmod : out STD_LOGIC
41  );
42end main_wrapper;
43
44architecture STRUCTURE of main_wrapper is
45  component main is
46  port (
47    ack_error : out STD_LOGIC;
48    bclk : out STD_LOGIC;
49    bclkpmod : out STD_LOGIC;
50    bypass_analog : in STD_LOGIC;
51    bypass_dsp : in STD_LOGIC;
52    bypass_faust : in STD_LOGIC;
53    mclk : out STD_LOGIC;
54    mclkpmod : out STD_LOGIC;
55    reset_btn : in STD_LOGIC;
56    sclk : inout STD_LOGIC;
57    sclpmod : out STD_LOGIC;
58    sd_rx : in STD_LOGIC;
59    sd_rxpmod : out STD_LOGIC;
60    sd_tx : out STD_LOGIC;
61    sd_txpmod : out STD_LOGIC;
62    sdapmod : out STD_LOGIC;
63    sdin : inout STD_LOGIC;
64    sys_clk : in STD_LOGIC;
65    vol_down : in STD_LOGIC;
66    vol_up : in STD_LOGIC;
67    ws_rx : out STD_LOGIC;
68    ws_tx : out STD_LOGIC;
69    wspmod : out STD_LOGIC;
70    in_mute : in STD_LOGIC;
71    out_mute : out STD_LOGIC
72  );
73  end component main;
74begin
75main_i: component main
76     port map (
77      ack_error => ack_error,
78      bclk => bclk,
79      bclkpmod => bclkpmod,
80      bypass_analog => bypass_analog,
81      bypass_dsp => bypass_dsp,
82      bypass_faust => bypass_faust,
83      in_mute => in_mute,
84      mclk => mclk,
85      mclkpmod => mclkpmod,
86      out_mute => out_mute,
87      reset_btn => reset_btn,
88      sclk => sclk,
89      sclpmod => sclpmod,
90      sd_rx => sd_rx,
91      sd_rxpmod => sd_rxpmod,
92      sd_tx => sd_tx,
93      sd_txpmod => sd_txpmod,
94      sdapmod => sdapmod,
95      sdin => sdin,
96      sys_clk => sys_clk,
97      vol_down => vol_down,
98      vol_up => vol_up,
99      ws_rx => ws_rx,
100      ws_tx => ws_tx,
101      wspmod => wspmod
102    );
103end STRUCTURE;
104