1/**
2  ******************************************************************************
3  * @file      startup_stm32f0xx.s
4  * @author    MCD Application Team
5  * @version   V1.5.0
6  * @date      05-December-2014
7  * @brief     STM32F031 Devices vector table for RIDE7 toolchain.
8  *            This module performs:
9  *                - Set the initial SP
10  *                - Set the initial PC == Reset_Handler,
11  *                - Set the vector table entries with the exceptions ISR address
12  *                - Configure the system clock
13  *                - Branches to main in the C library (which eventually
14  *                  calls main()).
15  *            After Reset the Cortex-M0 processor is in Thread mode,
16  *            priority is Privileged, and the Stack is set to Main.
17  ******************************************************************************
18  * @attention
19  *
20  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
21  *
22  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
23  * You may not use this file except in compliance with the License.
24  * You may obtain a copy of the License at:
25  *
26  *        http://www.st.com/software_license_agreement_liberty_v2
27  *
28  * Unless required by applicable law or agreed to in writing, software
29  * distributed under the License is distributed on an "AS IS" BASIS,
30  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
31  * See the License for the specific language governing permissions and
32  * limitations under the License.
33  *
34  ******************************************************************************
35  */
36
37  .syntax unified
38  .cpu cortex-m0
39  .fpu softvfp
40  .thumb
41
42.global g_pfnVectors
43.global Default_Handler
44
45/* start address for the initialization values of the .data section.
46defined in linker script */
47.word _sidata
48/* start address for the .data section. defined in linker script */
49.word _sdata
50/* end address for the .data section. defined in linker script */
51.word _edata
52/* start address for the .bss section. defined in linker script */
53.word _sbss
54/* end address for the .bss section. defined in linker script */
55.word _ebss
56
57.equ  BootRAM, 0xF108F85F
58/**
59 * @brief  This is the code that gets called when the processor first
60 *          starts execution following a reset event. Only the absolutely
61 *          necessary set is performed, after which the application
62 *          supplied main() routine is called.
63 * @param  None
64 * @retval : None
65*/
66
67  .section .text.Reset_Handler
68  .weak Reset_Handler
69  .type Reset_Handler, %function
70Reset_Handler:
71  ldr   r0, =_estack
72  mov   sp, r0          /* set stack pointer */
73
74/*Check if boot space corresponds to test memory*/
75
76    LDR R0,=0x00000004
77    LDR R1, [R0]
78    LSRS R1, R1, #24
79    LDR R2,=0x1F
80    CMP R1, R2
81    BNE ApplicationStart
82
83 /*SYSCFG clock enable*/
84
85    LDR R0,=0x40021018
86    LDR R1,=0x00000001
87    STR R1, [R0]
88
89/*Set CFGR1 register with flash memory remap at address 0*/
90    LDR R0,=0x40010000
91    LDR R1,=0x00000000
92    STR R1, [R0]
93
94ApplicationStart:
95/* Copy the data segment initializers from flash to SRAM */
96  movs r1, #0
97  b LoopCopyDataInit
98
99CopyDataInit:
100  ldr r3, =_sidata
101  ldr r3, [r3, r1]
102  str r3, [r0, r1]
103  adds r1, r1, #4
104
105LoopCopyDataInit:
106  ldr r0, =_sdata
107  ldr r3, =_edata
108  adds r2, r0, r1
109  cmp r2, r3
110  bcc CopyDataInit
111  ldr r2, =_sbss
112  b LoopFillZerobss
113/* Zero fill the bss segment. */
114FillZerobss:
115  movs r3, #0
116  str  r3, [r2]
117  adds r2, r2, #4
118
119
120LoopFillZerobss:
121  ldr r3, = _ebss
122  cmp r2, r3
123  bcc FillZerobss
124
125/* Call the clock system intitialization function.*/
126    bl  SystemInit
127
128/* Call the application's entry point.*/
129  bl main
130
131LoopForever:
132    b LoopForever
133
134
135.size Reset_Handler, .-Reset_Handler
136
137/**
138 * @brief  This is the code that gets called when the processor receives an
139 *         unexpected interrupt.  This simply enters an infinite loop, preserving
140 *         the system state for examination by a debugger.
141 *
142 * @param  None
143 * @retval : None
144*/
145    .section .text.Default_Handler,"ax",%progbits
146Default_Handler:
147Infinite_Loop:
148  b Infinite_Loop
149  .size Default_Handler, .-Default_Handler
150/******************************************************************************
151*
152* The minimal vector table for a Cortex M0.  Note that the proper constructs
153* must be placed on this to ensure that it ends up at physical address
154* 0x0000.0000.
155*
156******************************************************************************/
157   .section .isr_vector,"a",%progbits
158  .type g_pfnVectors, %object
159  .size g_pfnVectors, .-g_pfnVectors
160
161
162
163g_pfnVectors:
164  .word _estack
165  .word Reset_Handler
166
167  .word NMI_Handler
168  .word HardFault_Handler
169  .word 0
170  .word 0
171  .word 0
172  .word 0
173  .word 0
174  .word 0
175  .word 0
176  .word SVC_Handler
177  .word 0
178  .word 0
179  .word PendSV_Handler
180  .word SysTick_Handler
181
182
183  .word WWDG_IRQHandler
184  .word PVD_IRQHandler
185  .word RTC_IRQHandler
186  .word FLASH_IRQHandler
187  .word RCC_IRQHandler
188  .word EXTI0_1_IRQHandler
189  .word EXTI2_3_IRQHandler
190  .word EXTI4_15_IRQHandler
191  .word 0
192  .word DMA1_Channel1_IRQHandler
193  .word DMA1_Channel2_3_IRQHandler
194  .word DMA1_Channel4_5_IRQHandler
195  .word ADC1_IRQHandler
196  .word TIM1_BRK_UP_TRG_COM_IRQHandler
197  .word TIM1_CC_IRQHandler
198  .word TIM2_IRQHandler
199  .word TIM3_IRQHandler
200  .word 0
201  .word 0
202  .word TIM14_IRQHandler
203  .word 0
204  .word TIM16_IRQHandler
205  .word TIM17_IRQHandler
206  .word I2C1_IRQHandler
207  .word 0
208  .word SPI1_IRQHandler
209  .word 0
210  .word USART1_IRQHandler
211  .word 0
212  .word 0
213  .word 0
214  .word 0
215  .word BootRAM          /* @0x108. This is for boot in RAM mode for
216                            STM32F0xx devices. */
217
218/*******************************************************************************
219*
220* Provide weak aliases for each Exception handler to the Default_Handler.
221* As they are weak aliases, any function with the same name will override
222* this definition.
223*
224*******************************************************************************/
225
226  .weak NMI_Handler
227  .thumb_set NMI_Handler,Default_Handler
228
229  .weak HardFault_Handler
230  .thumb_set HardFault_Handler,Default_Handler
231
232  .weak SVC_Handler
233  .thumb_set SVC_Handler,Default_Handler
234
235  .weak PendSV_Handler
236  .thumb_set PendSV_Handler,Default_Handler
237
238  .weak SysTick_Handler
239  .thumb_set SysTick_Handler,Default_Handler
240
241  .weak WWDG_IRQHandler
242  .thumb_set WWDG_IRQHandler,Default_Handler
243
244  .weak PVD_IRQHandler
245  .thumb_set PVD_IRQHandler,Default_Handler
246
247  .weak RTC_IRQHandler
248  .thumb_set RTC_IRQHandler,Default_Handler
249
250  .weak FLASH_IRQHandler
251  .thumb_set FLASH_IRQHandler,Default_Handler
252
253  .weak RCC_IRQHandler
254  .thumb_set RCC_IRQHandler,Default_Handler
255
256  .weak EXTI0_1_IRQHandler
257  .thumb_set EXTI0_1_IRQHandler,Default_Handler
258
259  .weak EXTI2_3_IRQHandler
260  .thumb_set EXTI2_3_IRQHandler,Default_Handler
261
262  .weak EXTI4_15_IRQHandler
263  .thumb_set EXTI4_15_IRQHandler,Default_Handler
264
265  .weak DMA1_Channel1_IRQHandler
266  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
267
268  .weak DMA1_Channel2_3_IRQHandler
269  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
270
271  .weak DMA1_Channel4_5_IRQHandler
272  .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
273
274  .weak ADC1_IRQHandler
275  .thumb_set ADC1_IRQHandler,Default_Handler
276
277  .weak TIM1_BRK_UP_TRG_COM_IRQHandler
278  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
279
280  .weak TIM1_CC_IRQHandler
281  .thumb_set TIM1_CC_IRQHandler,Default_Handler
282
283  .weak TIM2_IRQHandler
284  .thumb_set TIM2_IRQHandler,Default_Handler
285
286  .weak TIM3_IRQHandler
287  .thumb_set TIM3_IRQHandler,Default_Handler
288
289  .weak TIM14_IRQHandler
290  .thumb_set TIM14_IRQHandler,Default_Handler
291
292  .weak TIM16_IRQHandler
293  .thumb_set TIM16_IRQHandler,Default_Handler
294
295  .weak TIM17_IRQHandler
296  .thumb_set TIM17_IRQHandler,Default_Handler
297
298  .weak I2C1_IRQHandler
299  .thumb_set I2C1_IRQHandler,Default_Handler
300
301  .weak SPI1_IRQHandler
302  .thumb_set SPI1_IRQHandler,Default_Handler
303
304  .weak USART1_IRQHandler
305  .thumb_set USART1_IRQHandler,Default_Handler
306
307
308/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
309