1 /** 2 ****************************************************************************** 3 * @file stm32g441xx.h 4 * @author MCD Application Team 5 * @brief CMSIS STM32G441xx Device Peripheral Access Layer Header File. 6 * 7 * This file contains: 8 * - Data structures and the address mapping for all peripherals 9 * - Peripheral's registers declarations and bits definition 10 * - Macros to access peripheral�s registers hardware 11 * 12 ****************************************************************************** 13 * @attention 14 * 15 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 16 * All rights reserved.</center></h2> 17 * 18 * This software component is licensed by ST under BSD 3-Clause license, 19 * the "License"; You may not use this file except in compliance with the 20 * License. You may obtain a copy of the License at: 21 * opensource.org/licenses/BSD-3-Clause 22 * 23 ****************************************************************************** 24 */ 25 26 /** @addtogroup CMSIS_Device 27 * @{ 28 */ 29 30 /** @addtogroup stm32g441xx 31 * @{ 32 */ 33 34 #ifndef __STM32G441xx_H 35 #define __STM32G441xx_H 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** @addtogroup Configuration_section_for_CMSIS 42 * @{ 43 */ 44 45 /** 46 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 47 */ 48 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ 49 #define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ 50 #define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ 51 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 52 #define __FPU_PRESENT 1 /*!< FPU present */ 53 54 /** 55 * @} 56 */ 57 58 /** @addtogroup Peripheral_interrupt_number_definition 59 * @{ 60 */ 61 62 /** 63 * @brief STM32G4XX Interrupt Number Definition, according to the selected device 64 * in @ref Library_configuration_section 65 */ 66 typedef enum 67 { 68 /****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/ 69 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ 70 HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ 71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 72 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 73 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 74 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 76 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 77 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 78 /****** STM32 specific Interrupt Numbers ***************************************************************************************/ 79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 80 PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ 81 RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ 82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ 83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 84 RCC_IRQn = 5, /*!< RCC global Interrupt */ 85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 90 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 91 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 92 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 93 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 94 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 95 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 96 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ 97 USB_HP_IRQn = 19, /*!< USB HP Interrupt */ 98 USB_LP_IRQn = 20, /*!< USB LP Interrupt */ 99 FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */ 100 FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */ 101 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 102 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */ 103 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ 104 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ 105 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 106 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 107 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 108 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 109 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 110 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 111 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 112 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 113 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 114 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 115 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 116 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 117 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 118 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 119 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ 120 USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */ 121 TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */ 122 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ 123 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */ 124 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ 125 LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ 126 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ 127 UART4_IRQn = 52, /*!< UART4 global Interrupt */ 128 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */ 129 TIM7_IRQn = 55, /*!< TIM7 global interrupts */ 130 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ 131 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ 132 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ 133 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ 134 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ 135 UCPD1_IRQn = 63, /*!< UCPD global Interrupt */ 136 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */ 137 COMP4_IRQn = 65, /*!< COMP4 */ 138 CRS_IRQn = 75, /*!< CRS global interrupt */ 139 SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ 140 FPU_IRQn = 81, /*!< FPU global interrupt */ 141 AES_IRQn = 85, /*!< AES global interrupt */ 142 RNG_IRQn = 90, /*!< RNG global interrupt */ 143 LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */ 144 I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ 145 I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ 146 DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ 147 DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ 148 CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */ 149 FMAC_IRQn = 101 /*!< FMAC global Interrupt */ 150 } IRQn_Type; 151 152 /** 153 * @} 154 */ 155 156 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 157 #include "system_stm32g4xx.h" 158 #include <stdint.h> 159 160 /** @addtogroup Peripheral_registers_structures 161 * @{ 162 */ 163 164 /** 165 * @brief Analog to Digital Converter 166 */ 167 168 typedef struct 169 { 170 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ 171 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ 172 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 173 __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ 174 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ 175 __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ 176 __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ 177 uint32_t RESERVED1; /*!< Reserved, 0x1C */ 178 __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ 179 __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ 180 __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ 181 uint32_t RESERVED2; /*!< Reserved, 0x2C */ 182 __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ 183 __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ 184 __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ 185 __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ 186 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ 187 uint32_t RESERVED3; /*!< Reserved, 0x44 */ 188 uint32_t RESERVED4; /*!< Reserved, 0x48 */ 189 __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ 190 uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ 191 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ 192 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ 193 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ 194 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ 195 uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ 196 __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ 197 __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ 198 __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ 199 __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ 200 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ 201 __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ 202 __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ 203 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ 204 uint32_t RESERVED9; /*!< Reserved, 0x0AC */ 205 __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ 206 __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ 207 uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */ 208 __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */ 209 } ADC_TypeDef; 210 211 typedef struct 212 { 213 __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ 214 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ 215 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ 216 __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ 217 } ADC_Common_TypeDef; 218 219 /** 220 * @brief FD Controller Area Network 221 */ 222 223 typedef struct 224 { 225 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ 226 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ 227 uint32_t RESERVED1; /*!< Reserved, 0x008 */ 228 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ 229 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ 230 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ 231 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ 232 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ 233 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ 234 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ 235 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ 236 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ 237 uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ 238 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ 239 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ 240 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ 241 uint32_t RESERVED3; /*!< Reserved, 0x04C */ 242 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ 243 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ 244 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ 245 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ 246 uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ 247 __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ 248 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ 249 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ 250 uint32_t RESERVED5; /*!< Reserved, 0x08C */ 251 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ 252 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ 253 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ 254 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ 255 uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ 256 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ 257 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ 258 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ 259 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ 260 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ 261 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ 262 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ 263 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ 264 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ 265 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ 266 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ 267 } FDCAN_GlobalTypeDef; 268 269 /** 270 * @brief FD Controller Area Network Configuration 271 */ 272 273 typedef struct 274 { 275 __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ 276 } FDCAN_Config_TypeDef; 277 278 /** 279 * @brief Comparator 280 */ 281 282 typedef struct 283 { 284 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ 285 } COMP_TypeDef; 286 287 /** 288 * @brief CRC calculation unit 289 */ 290 291 typedef struct 292 { 293 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 294 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 295 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 296 uint32_t RESERVED0; /*!< Reserved, 0x0C */ 297 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 298 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 299 } CRC_TypeDef; 300 301 /** 302 * @brief Clock Recovery System 303 */ 304 typedef struct 305 { 306 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ 307 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ 308 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ 309 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ 310 } CRS_TypeDef; 311 312 /** 313 * @brief Digital to Analog Converter 314 */ 315 316 typedef struct 317 { 318 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 319 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 320 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 321 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 322 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 323 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 324 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 325 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 326 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 327 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 328 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 329 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 330 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 331 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 332 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ 333 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ 334 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ 335 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ 336 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ 337 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ 338 __IO uint32_t RESERVED[2]; 339 __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */ 340 __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */ 341 __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */ 342 } DAC_TypeDef; 343 344 /** 345 * @brief Debug MCU 346 */ 347 348 typedef struct 349 { 350 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 351 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 352 __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ 353 __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ 354 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ 355 } DBGMCU_TypeDef; 356 357 /** 358 * @brief DMA Controller 359 */ 360 361 typedef struct 362 { 363 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 364 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 365 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 366 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 367 } DMA_Channel_TypeDef; 368 369 typedef struct 370 { 371 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 372 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 373 } DMA_TypeDef; 374 375 /** 376 * @brief DMA Multiplexer 377 */ 378 379 typedef struct 380 { 381 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ 382 }DMAMUX_Channel_TypeDef; 383 384 typedef struct 385 { 386 __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ 387 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ 388 }DMAMUX_ChannelStatus_TypeDef; 389 390 typedef struct 391 { 392 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ 393 }DMAMUX_RequestGen_TypeDef; 394 395 typedef struct 396 { 397 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ 398 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ 399 }DMAMUX_RequestGenStatus_TypeDef; 400 401 /** 402 * @brief External Interrupt/Event Controller 403 */ 404 405 typedef struct 406 { 407 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ 408 __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ 409 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ 410 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ 411 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ 412 __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ 413 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 414 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 415 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ 416 __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ 417 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ 418 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ 419 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ 420 __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ 421 } EXTI_TypeDef; 422 423 /** 424 * @brief FLASH Registers 425 */ 426 427 typedef struct 428 { 429 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ 430 __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ 431 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ 432 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ 433 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ 434 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ 435 __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ 436 uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ 437 __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ 438 __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ 439 __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ 440 __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ 441 __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ 442 uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */ 443 __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */ 444 } FLASH_TypeDef; 445 446 /** 447 * @brief FMAC 448 */ 449 typedef struct 450 { 451 __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ 452 __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ 453 __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ 454 __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ 455 __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ 456 __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ 457 __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ 458 __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ 459 } FMAC_TypeDef; 460 461 462 /** 463 * @brief General Purpose I/O 464 */ 465 466 typedef struct 467 { 468 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 469 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 470 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 471 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 472 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 473 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 474 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ 475 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 476 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ 477 __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ 478 } GPIO_TypeDef; 479 480 /** 481 * @brief Inter-integrated Circuit Interface 482 */ 483 484 typedef struct 485 { 486 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 487 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 488 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 489 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 490 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 491 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 492 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 493 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 494 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 495 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 496 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 497 } I2C_TypeDef; 498 499 /** 500 * @brief Independent WATCHDOG 501 */ 502 503 typedef struct 504 { 505 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 506 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 507 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 508 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 509 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 510 } IWDG_TypeDef; 511 512 /** 513 * @brief LPTIMER 514 */ 515 516 typedef struct 517 { 518 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ 519 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ 520 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ 521 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ 522 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ 523 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ 524 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ 525 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ 526 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ 527 } LPTIM_TypeDef; 528 529 /** 530 * @brief Operational Amplifier (OPAMP) 531 */ 532 533 typedef struct 534 { 535 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ 536 __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ 537 __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */ 538 } OPAMP_TypeDef; 539 540 /** 541 * @brief Power Control 542 */ 543 544 typedef struct 545 { 546 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ 547 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ 548 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ 549 __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ 550 __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ 551 __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ 552 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ 553 uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ 554 __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ 555 __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ 556 __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ 557 __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ 558 __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ 559 __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ 560 __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ 561 __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ 562 __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ 563 __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ 564 __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ 565 __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ 566 __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ 567 __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ 568 uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */ 569 __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ 570 } PWR_TypeDef; 571 572 573 /** 574 * @brief Reset and Clock Control 575 */ 576 577 typedef struct 578 { 579 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 580 __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ 581 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ 582 __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ 583 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ 584 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 585 __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ 586 __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ 587 __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ 588 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ 589 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ 590 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ 591 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ 592 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */ 593 __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ 594 __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ 595 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ 596 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */ 597 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ 598 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ 599 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ 600 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */ 601 __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ 602 __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ 603 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ 604 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */ 605 __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ 606 __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ 607 __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ 608 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */ 609 __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ 610 __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ 611 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ 612 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */ 613 __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ 614 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */ 615 __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ 616 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ 617 __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ 618 __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ 619 } RCC_TypeDef; 620 621 /** 622 * @brief Real-Time Clock 623 */ 624 /* 625 * @brief Specific device feature definitions 626 */ 627 #define RTC_TAMP_INT_6_SUPPORT 628 #define RTC_TAMP_INT_NB 4u 629 630 #define RTC_TAMP_NB 3u 631 #define RTC_BACKUP_NB 16u 632 633 634 typedef struct 635 { 636 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 637 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 638 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ 639 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ 640 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 641 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 642 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ 643 uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ 644 uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ 645 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 646 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ 647 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 648 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 649 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 650 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 651 uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */ 652 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ 653 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 654 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ 655 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ 656 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ 657 __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ 658 uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ 659 __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ 660 } RTC_TypeDef; 661 662 /** 663 * @brief Tamper and backup registers 664 */ 665 666 typedef struct 667 { 668 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ 669 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ 670 uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */ 671 __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ 672 uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */ 673 uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */ 674 __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ 675 __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ 676 __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */ 677 uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */ 678 __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ 679 uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */ 680 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ 681 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ 682 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ 683 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ 684 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ 685 __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ 686 __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ 687 __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ 688 __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ 689 __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ 690 __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ 691 __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ 692 __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ 693 __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ 694 __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ 695 __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ 696 } TAMP_TypeDef; 697 698 /** 699 * @brief Serial Audio Interface 700 */ 701 702 typedef struct 703 { 704 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ 705 uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ 706 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ 707 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ 708 } SAI_TypeDef; 709 710 typedef struct 711 { 712 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ 713 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ 714 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ 715 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ 716 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ 717 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ 718 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ 719 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ 720 } SAI_Block_TypeDef; 721 722 /** 723 * @brief Serial Peripheral Interface 724 */ 725 726 typedef struct 727 { 728 __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ 729 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 730 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 731 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 732 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ 733 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ 734 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ 735 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 736 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 737 } SPI_TypeDef; 738 739 /** 740 * @brief System configuration controller 741 */ 742 743 typedef struct 744 { 745 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ 746 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ 747 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ 748 __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */ 749 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ 750 __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */ 751 __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */ 752 } SYSCFG_TypeDef; 753 754 /** 755 * @brief TIM 756 */ 757 758 typedef struct 759 { 760 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 761 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 762 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 763 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 764 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 765 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 766 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 767 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 768 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 769 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 770 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ 771 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 772 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 773 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 774 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 775 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 776 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 777 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 778 __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ 779 __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ 780 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ 781 __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ 782 __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ 783 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ 784 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ 785 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ 786 __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */ 787 uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ 788 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ 789 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ 790 } TIM_TypeDef; 791 792 /** 793 * @brief Universal Synchronous Asynchronous Receiver Transmitter 794 */ 795 typedef struct 796 { 797 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 798 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 799 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 800 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 801 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 802 __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */ 803 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 804 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 805 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 806 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 807 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 808 __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ 809 } USART_TypeDef; 810 811 /** 812 * @brief Universal Serial Bus Full Speed Device 813 */ 814 815 typedef struct 816 { 817 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ 818 __IO uint16_t RESERVED0; /*!< Reserved */ 819 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ 820 __IO uint16_t RESERVED1; /*!< Reserved */ 821 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ 822 __IO uint16_t RESERVED2; /*!< Reserved */ 823 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ 824 __IO uint16_t RESERVED3; /*!< Reserved */ 825 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ 826 __IO uint16_t RESERVED4; /*!< Reserved */ 827 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ 828 __IO uint16_t RESERVED5; /*!< Reserved */ 829 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ 830 __IO uint16_t RESERVED6; /*!< Reserved */ 831 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ 832 __IO uint16_t RESERVED7[17]; /*!< Reserved */ 833 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ 834 __IO uint16_t RESERVED8; /*!< Reserved */ 835 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ 836 __IO uint16_t RESERVED9; /*!< Reserved */ 837 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ 838 __IO uint16_t RESERVEDA; /*!< Reserved */ 839 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ 840 __IO uint16_t RESERVEDB; /*!< Reserved */ 841 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ 842 __IO uint16_t RESERVEDC; /*!< Reserved */ 843 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ 844 __IO uint16_t RESERVEDD; /*!< Reserved */ 845 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ 846 __IO uint16_t RESERVEDE; /*!< Reserved */ 847 } USB_TypeDef; 848 849 /** 850 * @brief VREFBUF 851 */ 852 853 typedef struct 854 { 855 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ 856 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ 857 } VREFBUF_TypeDef; 858 859 /** 860 * @brief Window WATCHDOG 861 */ 862 863 typedef struct 864 { 865 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 866 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 867 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 868 } WWDG_TypeDef; 869 870 /** 871 * @brief AES hardware accelerator 872 */ 873 874 typedef struct 875 { 876 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ 877 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ 878 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ 879 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ 880 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ 881 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ 882 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ 883 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ 884 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ 885 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ 886 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ 887 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ 888 __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ 889 __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ 890 __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ 891 __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ 892 __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ 893 __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ 894 __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ 895 __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ 896 __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ 897 __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ 898 __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ 899 __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ 900 } AES_TypeDef; 901 902 /** 903 * @brief RNG 904 */ 905 typedef struct 906 { 907 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ 908 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ 909 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ 910 } RNG_TypeDef; 911 912 /** 913 * @brief CORDIC 914 */ 915 916 typedef struct 917 { 918 __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ 919 __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ 920 __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ 921 } CORDIC_TypeDef; 922 923 /** 924 * @brief UCPD 925 */ 926 927 typedef struct 928 { 929 __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ 930 __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ 931 __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ 932 __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ 933 __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ 934 __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ 935 __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ 936 __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ 937 __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ 938 __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ 939 __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ 940 __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ 941 __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ 942 __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ 943 __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ 944 } UCPD_TypeDef; 945 946 947 /** @addtogroup Peripheral_memory_map 948 * @{ 949 */ 950 951 #define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */ 952 #define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */ 953 #define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */ 954 #define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */ 955 #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ 956 957 #define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */ 958 #define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */ 959 #define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */ 960 #define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ 961 /* Legacy defines */ 962 #define SRAM_BASE SRAM1_BASE 963 #define SRAM_BB_BASE SRAM1_BB_BASE 964 965 #define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */ 966 #define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */ 967 #define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */ 968 969 /*!< Peripheral memory map */ 970 #define APB1PERIPH_BASE PERIPH_BASE 971 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 972 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) 973 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) 974 975 976 /*!< APB1 peripherals */ 977 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) 978 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) 979 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) 980 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) 981 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) 982 #define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) 983 #define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL) 984 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) 985 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) 986 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) 987 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) 988 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) 989 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) 990 #define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) 991 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) 992 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) 993 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) 994 #define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */ 995 #define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */ 996 #define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL) 997 #define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */ 998 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) 999 #define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL) 1000 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) 1001 #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) 1002 #define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL) 1003 #define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL) 1004 1005 /*!< APB2 peripherals */ 1006 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) 1007 #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) 1008 #define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) 1009 #define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) 1010 #define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL) 1011 #define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL) 1012 #define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL) 1013 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL) 1014 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL) 1015 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL) 1016 1017 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) 1018 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) 1019 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) 1020 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) 1021 #define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) 1022 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) 1023 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) 1024 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) 1025 #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) 1026 #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) 1027 #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) 1028 1029 /*!< AHB1 peripherals */ 1030 #define DMA1_BASE (AHB1PERIPH_BASE) 1031 #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) 1032 #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL) 1033 #define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL) 1034 #define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) 1035 #define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL) 1036 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) 1037 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) 1038 1039 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) 1040 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) 1041 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) 1042 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) 1043 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) 1044 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) 1045 1046 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) 1047 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) 1048 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) 1049 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) 1050 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) 1051 #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) 1052 1053 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) 1054 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) 1055 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) 1056 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) 1057 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) 1058 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) 1059 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL) 1060 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL) 1061 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL) 1062 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL) 1063 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL) 1064 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL) 1065 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) 1066 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) 1067 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) 1068 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) 1069 1070 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) 1071 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) 1072 1073 /*!< AHB2 peripherals */ 1074 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) 1075 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) 1076 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) 1077 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) 1078 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) 1079 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) 1080 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) 1081 1082 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL) 1083 #define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL) 1084 #define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL) 1085 1086 #define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL) 1087 #define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL) 1088 #define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL) 1089 #define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL) 1090 1091 #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) 1092 /* Debug MCU registers base address */ 1093 #define DBGMCU_BASE (0xE0042000UL) 1094 1095 #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ 1096 #define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ 1097 #define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ 1098 /** 1099 * @} 1100 */ 1101 1102 /** @addtogroup Peripheral_declaration 1103 * @{ 1104 */ 1105 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 1106 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 1107 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 1108 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 1109 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 1110 #define CRS ((CRS_TypeDef *) CRS_BASE) 1111 #define TAMP ((TAMP_TypeDef *) TAMP_BASE) 1112 #define RTC ((RTC_TypeDef *) RTC_BASE) 1113 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 1114 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 1115 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 1116 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 1117 #define USART2 ((USART_TypeDef *) USART2_BASE) 1118 #define USART3 ((USART_TypeDef *) USART3_BASE) 1119 #define UART4 ((USART_TypeDef *) UART4_BASE) 1120 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 1121 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 1122 #define USB ((USB_TypeDef *) USB_BASE) 1123 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) 1124 #define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) 1125 #define PWR ((PWR_TypeDef *) PWR_BASE) 1126 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 1127 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) 1128 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) 1129 #define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) 1130 1131 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 1132 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) 1133 #define COMP1 ((COMP_TypeDef *) COMP1_BASE) 1134 #define COMP2 ((COMP_TypeDef *) COMP2_BASE) 1135 #define COMP3 ((COMP_TypeDef *) COMP3_BASE) 1136 #define COMP4 ((COMP_TypeDef *) COMP4_BASE) 1137 1138 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) 1139 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) 1140 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) 1141 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) 1142 1143 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 1144 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 1145 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 1146 #define TIM8 ((TIM_TypeDef *) TIM8_BASE) 1147 #define USART1 ((USART_TypeDef *) USART1_BASE) 1148 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 1149 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 1150 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 1151 #define SAI1 ((SAI_TypeDef *) SAI1_BASE) 1152 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) 1153 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) 1154 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 1155 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 1156 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) 1157 #define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) 1158 #define RCC ((RCC_TypeDef *) RCC_BASE) 1159 #define FMAC ((FMAC_TypeDef *) FMAC_BASE) 1160 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 1161 #define CRC ((CRC_TypeDef *) CRC_BASE) 1162 1163 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 1164 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 1165 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 1166 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 1167 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 1168 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 1169 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 1170 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 1171 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 1172 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) 1173 #define DAC ((DAC_TypeDef *) DAC_BASE) 1174 #define DAC1 ((DAC_TypeDef *) DAC1_BASE) 1175 #define DAC3 ((DAC_TypeDef *) DAC3_BASE) 1176 #define AES ((AES_TypeDef *) AES_BASE) 1177 #define RNG ((RNG_TypeDef *) RNG_BASE) 1178 1179 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 1180 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 1181 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 1182 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 1183 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 1184 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 1185 1186 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 1187 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 1188 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 1189 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 1190 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 1191 #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) 1192 1193 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) 1194 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) 1195 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) 1196 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) 1197 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) 1198 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) 1199 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) 1200 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) 1201 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) 1202 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) 1203 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) 1204 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) 1205 1206 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) 1207 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) 1208 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) 1209 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) 1210 1211 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) 1212 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) 1213 1214 1215 1216 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 1217 1218 /** 1219 * @} 1220 */ 1221 1222 /** @addtogroup Exported_constants 1223 * @{ 1224 */ 1225 1226 /** @addtogroup Peripheral_Registers_Bits_Definition 1227 * @{ 1228 */ 1229 1230 /******************************************************************************/ 1231 /* Peripheral Registers_Bits_Definition */ 1232 /******************************************************************************/ 1233 1234 /******************************************************************************/ 1235 /* */ 1236 /* Analog to Digital Converter */ 1237 /* */ 1238 /******************************************************************************/ 1239 1240 /* 1241 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) 1242 */ 1243 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ 1244 1245 /******************** Bit definition for ADC_ISR register *******************/ 1246 #define ADC_ISR_ADRDY_Pos (0U) 1247 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 1248 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ 1249 #define ADC_ISR_EOSMP_Pos (1U) 1250 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 1251 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ 1252 #define ADC_ISR_EOC_Pos (2U) 1253 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 1254 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ 1255 #define ADC_ISR_EOS_Pos (3U) 1256 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ 1257 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 1258 #define ADC_ISR_OVR_Pos (4U) 1259 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 1260 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ 1261 #define ADC_ISR_JEOC_Pos (5U) 1262 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ 1263 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ 1264 #define ADC_ISR_JEOS_Pos (6U) 1265 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ 1266 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 1267 #define ADC_ISR_AWD1_Pos (7U) 1268 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ 1269 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ 1270 #define ADC_ISR_AWD2_Pos (8U) 1271 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ 1272 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ 1273 #define ADC_ISR_AWD3_Pos (9U) 1274 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ 1275 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ 1276 #define ADC_ISR_JQOVF_Pos (10U) 1277 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ 1278 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ 1279 1280 /******************** Bit definition for ADC_IER register *******************/ 1281 #define ADC_IER_ADRDYIE_Pos (0U) 1282 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 1283 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ 1284 #define ADC_IER_EOSMPIE_Pos (1U) 1285 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 1286 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ 1287 #define ADC_IER_EOCIE_Pos (2U) 1288 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 1289 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ 1290 #define ADC_IER_EOSIE_Pos (3U) 1291 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ 1292 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 1293 #define ADC_IER_OVRIE_Pos (4U) 1294 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 1295 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ 1296 #define ADC_IER_JEOCIE_Pos (5U) 1297 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ 1298 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ 1299 #define ADC_IER_JEOSIE_Pos (6U) 1300 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ 1301 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 1302 #define ADC_IER_AWD1IE_Pos (7U) 1303 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ 1304 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ 1305 #define ADC_IER_AWD2IE_Pos (8U) 1306 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ 1307 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ 1308 #define ADC_IER_AWD3IE_Pos (9U) 1309 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ 1310 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ 1311 #define ADC_IER_JQOVFIE_Pos (10U) 1312 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ 1313 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ 1314 1315 /******************** Bit definition for ADC_CR register ********************/ 1316 #define ADC_CR_ADEN_Pos (0U) 1317 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 1318 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ 1319 #define ADC_CR_ADDIS_Pos (1U) 1320 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 1321 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ 1322 #define ADC_CR_ADSTART_Pos (2U) 1323 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 1324 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ 1325 #define ADC_CR_JADSTART_Pos (3U) 1326 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ 1327 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ 1328 #define ADC_CR_ADSTP_Pos (4U) 1329 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 1330 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ 1331 #define ADC_CR_JADSTP_Pos (5U) 1332 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ 1333 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ 1334 #define ADC_CR_ADVREGEN_Pos (28U) 1335 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 1336 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ 1337 #define ADC_CR_DEEPPWD_Pos (29U) 1338 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ 1339 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ 1340 #define ADC_CR_ADCALDIF_Pos (30U) 1341 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ 1342 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ 1343 #define ADC_CR_ADCAL_Pos (31U) 1344 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 1345 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 1346 1347 /******************** Bit definition for ADC_CFGR register ******************/ 1348 #define ADC_CFGR_DMAEN_Pos (0U) 1349 #define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ 1350 #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ 1351 #define ADC_CFGR_DMACFG_Pos (1U) 1352 #define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ 1353 #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ 1354 1355 #define ADC_CFGR_RES_Pos (3U) 1356 #define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ 1357 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ 1358 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ 1359 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ 1360 1361 #define ADC_CFGR_EXTSEL_Pos (5U) 1362 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ 1363 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ 1364 #define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ 1365 #define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ 1366 #define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ 1367 #define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ 1368 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ 1369 1370 #define ADC_CFGR_EXTEN_Pos (10U) 1371 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ 1372 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ 1373 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ 1374 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ 1375 1376 #define ADC_CFGR_OVRMOD_Pos (12U) 1377 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ 1378 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ 1379 #define ADC_CFGR_CONT_Pos (13U) 1380 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ 1381 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ 1382 #define ADC_CFGR_AUTDLY_Pos (14U) 1383 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ 1384 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ 1385 #define ADC_CFGR_ALIGN_Pos (15U) 1386 #define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ 1387 #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ 1388 #define ADC_CFGR_DISCEN_Pos (16U) 1389 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ 1390 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 1391 1392 #define ADC_CFGR_DISCNUM_Pos (17U) 1393 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ 1394 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 1395 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ 1396 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ 1397 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ 1398 1399 #define ADC_CFGR_JDISCEN_Pos (20U) 1400 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ 1401 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 1402 #define ADC_CFGR_JQM_Pos (21U) 1403 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ 1404 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ 1405 #define ADC_CFGR_AWD1SGL_Pos (22U) 1406 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ 1407 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 1408 #define ADC_CFGR_AWD1EN_Pos (23U) 1409 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ 1410 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 1411 #define ADC_CFGR_JAWD1EN_Pos (24U) 1412 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ 1413 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 1414 #define ADC_CFGR_JAUTO_Pos (25U) 1415 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ 1416 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 1417 1418 #define ADC_CFGR_AWD1CH_Pos (26U) 1419 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ 1420 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 1421 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ 1422 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ 1423 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ 1424 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ 1425 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ 1426 1427 #define ADC_CFGR_JQDIS_Pos (31U) 1428 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ 1429 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ 1430 1431 /******************** Bit definition for ADC_CFGR2 register *****************/ 1432 #define ADC_CFGR2_ROVSE_Pos (0U) 1433 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ 1434 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ 1435 #define ADC_CFGR2_JOVSE_Pos (1U) 1436 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ 1437 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ 1438 1439 #define ADC_CFGR2_OVSR_Pos (2U) 1440 #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ 1441 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ 1442 #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ 1443 #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ 1444 #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ 1445 1446 #define ADC_CFGR2_OVSS_Pos (5U) 1447 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ 1448 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ 1449 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ 1450 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ 1451 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ 1452 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ 1453 1454 #define ADC_CFGR2_TROVS_Pos (9U) 1455 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ 1456 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ 1457 #define ADC_CFGR2_ROVSM_Pos (10U) 1458 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ 1459 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ 1460 1461 #define ADC_CFGR2_GCOMP_Pos (16U) 1462 #define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ 1463 #define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ 1464 1465 #define ADC_CFGR2_SWTRIG_Pos (25U) 1466 #define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ 1467 #define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ 1468 #define ADC_CFGR2_BULB_Pos (26U) 1469 #define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ 1470 #define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ 1471 #define ADC_CFGR2_SMPTRIG_Pos (27U) 1472 #define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ 1473 #define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ 1474 1475 #define ADC_CFGR2_LFTRIG_Pos (29U) 1476 #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ 1477 #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ 1478 1479 /******************** Bit definition for ADC_SMPR1 register *****************/ 1480 #define ADC_SMPR1_SMP0_Pos (0U) 1481 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ 1482 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 1483 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ 1484 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ 1485 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ 1486 1487 #define ADC_SMPR1_SMP1_Pos (3U) 1488 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ 1489 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 1490 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ 1491 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ 1492 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ 1493 1494 #define ADC_SMPR1_SMP2_Pos (6U) 1495 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ 1496 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 1497 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ 1498 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ 1499 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ 1500 1501 #define ADC_SMPR1_SMP3_Pos (9U) 1502 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ 1503 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 1504 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ 1505 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ 1506 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ 1507 1508 #define ADC_SMPR1_SMP4_Pos (12U) 1509 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ 1510 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 1511 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ 1512 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ 1513 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ 1514 1515 #define ADC_SMPR1_SMP5_Pos (15U) 1516 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ 1517 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 1518 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ 1519 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ 1520 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ 1521 1522 #define ADC_SMPR1_SMP6_Pos (18U) 1523 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ 1524 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 1525 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ 1526 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ 1527 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ 1528 1529 #define ADC_SMPR1_SMP7_Pos (21U) 1530 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ 1531 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 1532 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ 1533 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ 1534 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ 1535 1536 #define ADC_SMPR1_SMP8_Pos (24U) 1537 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ 1538 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 1539 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ 1540 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ 1541 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ 1542 1543 #define ADC_SMPR1_SMP9_Pos (27U) 1544 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ 1545 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 1546 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ 1547 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ 1548 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ 1549 1550 #define ADC_SMPR1_SMPPLUS_Pos (31U) 1551 #define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ 1552 #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ 1553 1554 /******************** Bit definition for ADC_SMPR2 register *****************/ 1555 #define ADC_SMPR2_SMP10_Pos (0U) 1556 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ 1557 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 1558 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ 1559 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ 1560 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ 1561 1562 #define ADC_SMPR2_SMP11_Pos (3U) 1563 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ 1564 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 1565 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ 1566 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ 1567 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ 1568 1569 #define ADC_SMPR2_SMP12_Pos (6U) 1570 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ 1571 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 1572 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ 1573 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ 1574 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ 1575 1576 #define ADC_SMPR2_SMP13_Pos (9U) 1577 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ 1578 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 1579 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ 1580 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ 1581 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ 1582 1583 #define ADC_SMPR2_SMP14_Pos (12U) 1584 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ 1585 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 1586 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ 1587 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ 1588 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ 1589 1590 #define ADC_SMPR2_SMP15_Pos (15U) 1591 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ 1592 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ 1593 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ 1594 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ 1595 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ 1596 1597 #define ADC_SMPR2_SMP16_Pos (18U) 1598 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ 1599 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 1600 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ 1601 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ 1602 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ 1603 1604 #define ADC_SMPR2_SMP17_Pos (21U) 1605 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ 1606 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 1607 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ 1608 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ 1609 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ 1610 1611 #define ADC_SMPR2_SMP18_Pos (24U) 1612 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ 1613 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ 1614 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ 1615 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ 1616 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ 1617 1618 /******************** Bit definition for ADC_TR1 register *******************/ 1619 #define ADC_TR1_LT1_Pos (0U) 1620 #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ 1621 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ 1622 1623 #define ADC_TR1_AWDFILT_Pos (12U) 1624 #define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ 1625 #define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ 1626 #define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ 1627 #define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ 1628 #define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ 1629 1630 #define ADC_TR1_HT1_Pos (16U) 1631 #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ 1632 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ 1633 1634 /******************** Bit definition for ADC_TR2 register *******************/ 1635 #define ADC_TR2_LT2_Pos (0U) 1636 #define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ 1637 #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ 1638 1639 #define ADC_TR2_HT2_Pos (16U) 1640 #define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ 1641 #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ 1642 1643 /******************** Bit definition for ADC_TR3 register *******************/ 1644 #define ADC_TR3_LT3_Pos (0U) 1645 #define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ 1646 #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ 1647 1648 #define ADC_TR3_HT3_Pos (16U) 1649 #define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ 1650 #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ 1651 1652 /******************** Bit definition for ADC_SQR1 register ******************/ 1653 #define ADC_SQR1_L_Pos (0U) 1654 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ 1655 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 1656 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ 1657 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ 1658 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ 1659 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ 1660 1661 #define ADC_SQR1_SQ1_Pos (6U) 1662 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ 1663 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 1664 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ 1665 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ 1666 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ 1667 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ 1668 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ 1669 1670 #define ADC_SQR1_SQ2_Pos (12U) 1671 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ 1672 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 1673 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ 1674 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ 1675 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ 1676 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ 1677 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ 1678 1679 #define ADC_SQR1_SQ3_Pos (18U) 1680 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ 1681 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 1682 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ 1683 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ 1684 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ 1685 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ 1686 #define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ 1687 1688 #define ADC_SQR1_SQ4_Pos (24U) 1689 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ 1690 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 1691 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ 1692 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ 1693 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ 1694 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ 1695 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ 1696 1697 /******************** Bit definition for ADC_SQR2 register ******************/ 1698 #define ADC_SQR2_SQ5_Pos (0U) 1699 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ 1700 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 1701 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ 1702 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ 1703 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ 1704 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ 1705 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ 1706 1707 #define ADC_SQR2_SQ6_Pos (6U) 1708 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ 1709 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 1710 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ 1711 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ 1712 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ 1713 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ 1714 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ 1715 1716 #define ADC_SQR2_SQ7_Pos (12U) 1717 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ 1718 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 1719 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ 1720 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ 1721 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ 1722 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ 1723 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ 1724 1725 #define ADC_SQR2_SQ8_Pos (18U) 1726 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ 1727 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 1728 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ 1729 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ 1730 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ 1731 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ 1732 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ 1733 1734 #define ADC_SQR2_SQ9_Pos (24U) 1735 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ 1736 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 1737 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ 1738 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ 1739 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ 1740 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ 1741 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ 1742 1743 /******************** Bit definition for ADC_SQR3 register ******************/ 1744 #define ADC_SQR3_SQ10_Pos (0U) 1745 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ 1746 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 1747 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ 1748 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ 1749 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ 1750 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ 1751 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ 1752 1753 #define ADC_SQR3_SQ11_Pos (6U) 1754 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ 1755 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ 1756 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ 1757 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ 1758 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ 1759 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ 1760 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ 1761 1762 #define ADC_SQR3_SQ12_Pos (12U) 1763 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ 1764 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 1765 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ 1766 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ 1767 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ 1768 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ 1769 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ 1770 1771 #define ADC_SQR3_SQ13_Pos (18U) 1772 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ 1773 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 1774 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ 1775 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ 1776 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ 1777 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ 1778 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ 1779 1780 #define ADC_SQR3_SQ14_Pos (24U) 1781 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ 1782 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 1783 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ 1784 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ 1785 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ 1786 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ 1787 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ 1788 1789 /******************** Bit definition for ADC_SQR4 register ******************/ 1790 #define ADC_SQR4_SQ15_Pos (0U) 1791 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ 1792 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 1793 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ 1794 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ 1795 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ 1796 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ 1797 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ 1798 1799 #define ADC_SQR4_SQ16_Pos (6U) 1800 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ 1801 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 1802 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ 1803 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ 1804 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ 1805 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ 1806 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ 1807 1808 /******************** Bit definition for ADC_DR register ********************/ 1809 #define ADC_DR_RDATA_Pos (0U) 1810 #define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ 1811 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ 1812 1813 /******************** Bit definition for ADC_JSQR register ******************/ 1814 #define ADC_JSQR_JL_Pos (0U) 1815 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ 1816 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 1817 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ 1818 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ 1819 1820 #define ADC_JSQR_JEXTSEL_Pos (2U) 1821 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ 1822 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 1823 #define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ 1824 #define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ 1825 #define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ 1826 #define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ 1827 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ 1828 1829 #define ADC_JSQR_JEXTEN_Pos (7U) 1830 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ 1831 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ 1832 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ 1833 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ 1834 1835 #define ADC_JSQR_JSQ1_Pos (9U) 1836 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ 1837 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 1838 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ 1839 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ 1840 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ 1841 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ 1842 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ 1843 1844 #define ADC_JSQR_JSQ2_Pos (15U) 1845 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ 1846 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 1847 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ 1848 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ 1849 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ 1850 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ 1851 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ 1852 1853 #define ADC_JSQR_JSQ3_Pos (21U) 1854 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ 1855 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 1856 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ 1857 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ 1858 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ 1859 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ 1860 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ 1861 1862 #define ADC_JSQR_JSQ4_Pos (27U) 1863 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ 1864 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 1865 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ 1866 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ 1867 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ 1868 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ 1869 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ 1870 1871 /******************** Bit definition for ADC_OFR1 register ******************/ 1872 #define ADC_OFR1_OFFSET1_Pos (0U) 1873 #define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ 1874 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ 1875 1876 #define ADC_OFR1_OFFSETPOS_Pos (24U) 1877 #define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ 1878 #define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ 1879 #define ADC_OFR1_SATEN_Pos (25U) 1880 #define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ 1881 #define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ 1882 1883 #define ADC_OFR1_OFFSET1_CH_Pos (26U) 1884 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ 1885 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ 1886 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ 1887 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ 1888 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ 1889 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ 1890 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ 1891 1892 #define ADC_OFR1_OFFSET1_EN_Pos (31U) 1893 #define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ 1894 #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ 1895 1896 /******************** Bit definition for ADC_OFR2 register ******************/ 1897 #define ADC_OFR2_OFFSET2_Pos (0U) 1898 #define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ 1899 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ 1900 1901 #define ADC_OFR2_OFFSETPOS_Pos (24U) 1902 #define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ 1903 #define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ 1904 #define ADC_OFR2_SATEN_Pos (25U) 1905 #define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ 1906 #define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ 1907 1908 #define ADC_OFR2_OFFSET2_CH_Pos (26U) 1909 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ 1910 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ 1911 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ 1912 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ 1913 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ 1914 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ 1915 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ 1916 1917 #define ADC_OFR2_OFFSET2_EN_Pos (31U) 1918 #define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ 1919 #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ 1920 1921 /******************** Bit definition for ADC_OFR3 register ******************/ 1922 #define ADC_OFR3_OFFSET3_Pos (0U) 1923 #define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ 1924 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ 1925 1926 #define ADC_OFR3_OFFSETPOS_Pos (24U) 1927 #define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ 1928 #define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ 1929 #define ADC_OFR3_SATEN_Pos (25U) 1930 #define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ 1931 #define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ 1932 1933 #define ADC_OFR3_OFFSET3_CH_Pos (26U) 1934 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ 1935 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ 1936 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ 1937 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ 1938 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ 1939 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ 1940 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ 1941 1942 #define ADC_OFR3_OFFSET3_EN_Pos (31U) 1943 #define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ 1944 #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ 1945 1946 /******************** Bit definition for ADC_OFR4 register ******************/ 1947 #define ADC_OFR4_OFFSET4_Pos (0U) 1948 #define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ 1949 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ 1950 1951 #define ADC_OFR4_OFFSETPOS_Pos (24U) 1952 #define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ 1953 #define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ 1954 #define ADC_OFR4_SATEN_Pos (25U) 1955 #define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ 1956 #define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ 1957 1958 #define ADC_OFR4_OFFSET4_CH_Pos (26U) 1959 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ 1960 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ 1961 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ 1962 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ 1963 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ 1964 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ 1965 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ 1966 1967 #define ADC_OFR4_OFFSET4_EN_Pos (31U) 1968 #define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ 1969 #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ 1970 1971 /******************** Bit definition for ADC_JDR1 register ******************/ 1972 #define ADC_JDR1_JDATA_Pos (0U) 1973 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 1974 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 1975 1976 /******************** Bit definition for ADC_JDR2 register ******************/ 1977 #define ADC_JDR2_JDATA_Pos (0U) 1978 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 1979 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 1980 1981 /******************** Bit definition for ADC_JDR3 register ******************/ 1982 #define ADC_JDR3_JDATA_Pos (0U) 1983 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 1984 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 1985 1986 /******************** Bit definition for ADC_JDR4 register ******************/ 1987 #define ADC_JDR4_JDATA_Pos (0U) 1988 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 1989 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 1990 1991 /******************** Bit definition for ADC_AWD2CR register ****************/ 1992 #define ADC_AWD2CR_AWD2CH_Pos (0U) 1993 #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ 1994 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ 1995 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ 1996 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ 1997 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ 1998 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ 1999 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ 2000 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ 2001 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ 2002 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ 2003 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ 2004 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ 2005 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ 2006 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ 2007 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ 2008 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ 2009 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ 2010 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ 2011 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ 2012 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ 2013 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ 2014 2015 /******************** Bit definition for ADC_AWD3CR register ****************/ 2016 #define ADC_AWD3CR_AWD3CH_Pos (0U) 2017 #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ 2018 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ 2019 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ 2020 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ 2021 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ 2022 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ 2023 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ 2024 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ 2025 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ 2026 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ 2027 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ 2028 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ 2029 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ 2030 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ 2031 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ 2032 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ 2033 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ 2034 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ 2035 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ 2036 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ 2037 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ 2038 2039 /******************** Bit definition for ADC_DIFSEL register ****************/ 2040 #define ADC_DIFSEL_DIFSEL_Pos (0U) 2041 #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ 2042 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ 2043 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ 2044 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ 2045 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ 2046 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ 2047 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ 2048 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ 2049 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ 2050 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ 2051 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ 2052 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ 2053 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ 2054 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ 2055 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ 2056 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ 2057 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ 2058 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ 2059 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ 2060 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ 2061 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ 2062 2063 /******************** Bit definition for ADC_CALFACT register ***************/ 2064 #define ADC_CALFACT_CALFACT_S_Pos (0U) 2065 #define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ 2066 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ 2067 #define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ 2068 #define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ 2069 #define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ 2070 #define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ 2071 #define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ 2072 #define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ 2073 #define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ 2074 2075 #define ADC_CALFACT_CALFACT_D_Pos (16U) 2076 #define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ 2077 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ 2078 #define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ 2079 #define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ 2080 #define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ 2081 #define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ 2082 #define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ 2083 #define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ 2084 #define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ 2085 2086 /******************** Bit definition for ADC_GCOMP register *****************/ 2087 #define ADC_GCOMP_GCOMPCOEFF_Pos (0U) 2088 #define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */ 2089 #define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */ 2090 2091 /************************* ADC Common registers *****************************/ 2092 /******************** Bit definition for ADC_CSR register *******************/ 2093 #define ADC_CSR_ADRDY_MST_Pos (0U) 2094 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ 2095 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ 2096 #define ADC_CSR_EOSMP_MST_Pos (1U) 2097 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ 2098 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ 2099 #define ADC_CSR_EOC_MST_Pos (2U) 2100 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ 2101 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ 2102 #define ADC_CSR_EOS_MST_Pos (3U) 2103 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ 2104 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ 2105 #define ADC_CSR_OVR_MST_Pos (4U) 2106 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ 2107 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ 2108 #define ADC_CSR_JEOC_MST_Pos (5U) 2109 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ 2110 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ 2111 #define ADC_CSR_JEOS_MST_Pos (6U) 2112 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ 2113 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ 2114 #define ADC_CSR_AWD1_MST_Pos (7U) 2115 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ 2116 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ 2117 #define ADC_CSR_AWD2_MST_Pos (8U) 2118 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ 2119 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ 2120 #define ADC_CSR_AWD3_MST_Pos (9U) 2121 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ 2122 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ 2123 #define ADC_CSR_JQOVF_MST_Pos (10U) 2124 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ 2125 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ 2126 2127 #define ADC_CSR_ADRDY_SLV_Pos (16U) 2128 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ 2129 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ 2130 #define ADC_CSR_EOSMP_SLV_Pos (17U) 2131 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ 2132 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ 2133 #define ADC_CSR_EOC_SLV_Pos (18U) 2134 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ 2135 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ 2136 #define ADC_CSR_EOS_SLV_Pos (19U) 2137 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ 2138 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ 2139 #define ADC_CSR_OVR_SLV_Pos (20U) 2140 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ 2141 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ 2142 #define ADC_CSR_JEOC_SLV_Pos (21U) 2143 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ 2144 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ 2145 #define ADC_CSR_JEOS_SLV_Pos (22U) 2146 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ 2147 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ 2148 #define ADC_CSR_AWD1_SLV_Pos (23U) 2149 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ 2150 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ 2151 #define ADC_CSR_AWD2_SLV_Pos (24U) 2152 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ 2153 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ 2154 #define ADC_CSR_AWD3_SLV_Pos (25U) 2155 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ 2156 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ 2157 #define ADC_CSR_JQOVF_SLV_Pos (26U) 2158 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ 2159 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ 2160 2161 /******************** Bit definition for ADC_CCR register *******************/ 2162 #define ADC_CCR_DUAL_Pos (0U) 2163 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ 2164 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ 2165 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ 2166 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ 2167 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ 2168 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ 2169 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ 2170 2171 #define ADC_CCR_DELAY_Pos (8U) 2172 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ 2173 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ 2174 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ 2175 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ 2176 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ 2177 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ 2178 2179 #define ADC_CCR_DMACFG_Pos (13U) 2180 #define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ 2181 #define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ 2182 2183 #define ADC_CCR_MDMA_Pos (14U) 2184 #define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ 2185 #define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ 2186 #define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ 2187 #define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ 2188 2189 #define ADC_CCR_CKMODE_Pos (16U) 2190 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ 2191 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ 2192 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ 2193 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ 2194 2195 #define ADC_CCR_PRESC_Pos (18U) 2196 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ 2197 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ 2198 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ 2199 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ 2200 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ 2201 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ 2202 2203 #define ADC_CCR_VREFEN_Pos (22U) 2204 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 2205 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ 2206 #define ADC_CCR_VSENSESEL_Pos (23U) 2207 #define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */ 2208 #define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */ 2209 #define ADC_CCR_VBATSEL_Pos (24U) 2210 #define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */ 2211 #define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */ 2212 2213 /******************** Bit definition for ADC_CDR register *******************/ 2214 #define ADC_CDR_RDATA_MST_Pos (0U) 2215 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ 2216 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ 2217 2218 #define ADC_CDR_RDATA_SLV_Pos (16U) 2219 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ 2220 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ 2221 2222 /******************************************************************************/ 2223 /* */ 2224 /* Advanced Encryption Standard (AES) */ 2225 /* */ 2226 /******************************************************************************/ 2227 /******************* Bit definition for AES_CR register *********************/ 2228 #define AES_CR_EN_Pos (0U) 2229 #define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ 2230 #define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ 2231 #define AES_CR_DATATYPE_Pos (1U) 2232 #define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ 2233 #define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ 2234 #define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ 2235 #define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ 2236 2237 #define AES_CR_MODE_Pos (3U) 2238 #define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ 2239 #define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ 2240 #define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ 2241 #define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ 2242 2243 #define AES_CR_CHMOD_Pos (5U) 2244 #define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ 2245 #define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ 2246 #define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ 2247 #define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ 2248 #define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ 2249 2250 #define AES_CR_CCFC_Pos (7U) 2251 #define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ 2252 #define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ 2253 #define AES_CR_ERRC_Pos (8U) 2254 #define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ 2255 #define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ 2256 #define AES_CR_CCFIE_Pos (9U) 2257 #define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ 2258 #define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ 2259 #define AES_CR_ERRIE_Pos (10U) 2260 #define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ 2261 #define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 2262 #define AES_CR_DMAINEN_Pos (11U) 2263 #define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ 2264 #define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ 2265 #define AES_CR_DMAOUTEN_Pos (12U) 2266 #define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ 2267 #define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ 2268 2269 #define AES_CR_GCMPH_Pos (13U) 2270 #define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ 2271 #define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ 2272 #define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ 2273 #define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ 2274 2275 #define AES_CR_KEYSIZE_Pos (18U) 2276 #define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ 2277 #define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ 2278 #define AES_CR_NPBLB_Pos (20U) 2279 #define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ 2280 #define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ 2281 #define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ 2282 #define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ 2283 #define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ 2284 #define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ 2285 2286 /******************* Bit definition for AES_SR register *********************/ 2287 #define AES_SR_CCF_Pos (0U) 2288 #define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ 2289 #define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ 2290 #define AES_SR_RDERR_Pos (1U) 2291 #define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ 2292 #define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ 2293 #define AES_SR_WRERR_Pos (2U) 2294 #define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ 2295 #define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ 2296 #define AES_SR_BUSY_Pos (3U) 2297 #define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ 2298 #define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ 2299 2300 /******************* Bit definition for AES_DINR register *******************/ 2301 #define AES_DINR_Pos (0U) 2302 #define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ 2303 #define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ 2304 2305 /******************* Bit definition for AES_DOUTR register ******************/ 2306 #define AES_DOUTR_Pos (0U) 2307 #define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ 2308 #define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ 2309 2310 /******************* Bit definition for AES_KEYR0 register ******************/ 2311 #define AES_KEYR0_Pos (0U) 2312 #define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ 2313 #define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ 2314 2315 /******************* Bit definition for AES_KEYR1 register ******************/ 2316 #define AES_KEYR1_Pos (0U) 2317 #define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ 2318 #define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ 2319 2320 /******************* Bit definition for AES_KEYR2 register ******************/ 2321 #define AES_KEYR2_Pos (0U) 2322 #define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ 2323 #define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ 2324 2325 /******************* Bit definition for AES_KEYR3 register ******************/ 2326 #define AES_KEYR3_Pos (0U) 2327 #define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ 2328 #define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ 2329 2330 /******************* Bit definition for AES_KEYR4 register ******************/ 2331 #define AES_KEYR4_Pos (0U) 2332 #define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ 2333 #define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ 2334 2335 /******************* Bit definition for AES_KEYR5 register ******************/ 2336 #define AES_KEYR5_Pos (0U) 2337 #define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ 2338 #define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ 2339 2340 /******************* Bit definition for AES_KEYR6 register ******************/ 2341 #define AES_KEYR6_Pos (0U) 2342 #define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ 2343 #define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ 2344 2345 /******************* Bit definition for AES_KEYR7 register ******************/ 2346 #define AES_KEYR7_Pos (0U) 2347 #define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ 2348 #define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ 2349 2350 /******************* Bit definition for AES_IVR0 register ******************/ 2351 #define AES_IVR0_Pos (0U) 2352 #define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ 2353 #define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ 2354 2355 /******************* Bit definition for AES_IVR1 register ******************/ 2356 #define AES_IVR1_Pos (0U) 2357 #define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ 2358 #define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ 2359 2360 /******************* Bit definition for AES_IVR2 register ******************/ 2361 #define AES_IVR2_Pos (0U) 2362 #define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ 2363 #define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ 2364 2365 /******************* Bit definition for AES_IVR3 register ******************/ 2366 #define AES_IVR3_Pos (0U) 2367 #define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ 2368 #define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ 2369 2370 /******************* Bit definition for AES_SUSP0R register ******************/ 2371 #define AES_SUSP0R_Pos (0U) 2372 #define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ 2373 #define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ 2374 2375 /******************* Bit definition for AES_SUSP1R register ******************/ 2376 #define AES_SUSP1R_Pos (0U) 2377 #define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ 2378 #define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ 2379 2380 /******************* Bit definition for AES_SUSP2R register ******************/ 2381 #define AES_SUSP2R_Pos (0U) 2382 #define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ 2383 #define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ 2384 2385 /******************* Bit definition for AES_SUSP3R register ******************/ 2386 #define AES_SUSP3R_Pos (0U) 2387 #define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ 2388 #define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ 2389 2390 /******************* Bit definition for AES_SUSP4R register ******************/ 2391 #define AES_SUSP4R_Pos (0U) 2392 #define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ 2393 #define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ 2394 2395 /******************* Bit definition for AES_SUSP5R register ******************/ 2396 #define AES_SUSP5R_Pos (0U) 2397 #define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ 2398 #define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ 2399 2400 /******************* Bit definition for AES_SUSP6R register ******************/ 2401 #define AES_SUSP6R_Pos (0U) 2402 #define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ 2403 #define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ 2404 2405 /******************* Bit definition for AES_SUSP7R register ******************/ 2406 #define AES_SUSP7R_Pos (0U) 2407 #define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ 2408 #define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ 2409 2410 2411 /******************************************************************************/ 2412 /* */ 2413 /* Analog Comparators (COMP) */ 2414 /* */ 2415 /******************************************************************************/ 2416 /********************** Bit definition for COMP_CSR register ****************/ 2417 #define COMP_CSR_EN_Pos (0U) 2418 #define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ 2419 #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ 2420 2421 #define COMP_CSR_INMSEL_Pos (4U) 2422 #define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ 2423 #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ 2424 #define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ 2425 #define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ 2426 #define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ 2427 #define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ 2428 2429 #define COMP_CSR_INPSEL_Pos (8U) 2430 #define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ 2431 #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ 2432 2433 #define COMP_CSR_POLARITY_Pos (15U) 2434 #define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ 2435 #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ 2436 2437 #define COMP_CSR_HYST_Pos (16U) 2438 #define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */ 2439 #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ 2440 #define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ 2441 #define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ 2442 #define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */ 2443 2444 #define COMP_CSR_BLANKING_Pos (19U) 2445 #define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */ 2446 #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ 2447 #define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ 2448 #define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ 2449 #define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */ 2450 2451 #define COMP_CSR_BRGEN_Pos (22U) 2452 #define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ 2453 #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ 2454 2455 #define COMP_CSR_SCALEN_Pos (23U) 2456 #define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ 2457 #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ 2458 2459 #define COMP_CSR_VALUE_Pos (30U) 2460 #define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ 2461 #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ 2462 2463 #define COMP_CSR_LOCK_Pos (31U) 2464 #define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ 2465 #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ 2466 2467 /******************************************************************************/ 2468 /* */ 2469 /* CORDIC calculation unit */ 2470 /* */ 2471 /******************************************************************************/ 2472 /******************* Bit definition for CORDIC_CSR register *****************/ 2473 #define CORDIC_CSR_FUNC_Pos (0U) 2474 #define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ 2475 #define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ 2476 #define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ 2477 #define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ 2478 #define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ 2479 #define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ 2480 #define CORDIC_CSR_PRECISION_Pos (4U) 2481 #define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ 2482 #define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ 2483 #define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ 2484 #define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ 2485 #define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ 2486 #define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ 2487 #define CORDIC_CSR_SCALE_Pos (8U) 2488 #define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ 2489 #define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ 2490 #define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ 2491 #define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ 2492 #define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ 2493 #define CORDIC_CSR_IEN_Pos (16U) 2494 #define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ 2495 #define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ 2496 #define CORDIC_CSR_DMAREN_Pos (17U) 2497 #define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ 2498 #define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ 2499 #define CORDIC_CSR_DMAWEN_Pos (18U) 2500 #define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ 2501 #define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ 2502 #define CORDIC_CSR_NRES_Pos (19U) 2503 #define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ 2504 #define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ 2505 #define CORDIC_CSR_NARGS_Pos (20U) 2506 #define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ 2507 #define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ 2508 #define CORDIC_CSR_RESSIZE_Pos (21U) 2509 #define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ 2510 #define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ 2511 #define CORDIC_CSR_ARGSIZE_Pos (22U) 2512 #define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ 2513 #define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ 2514 #define CORDIC_CSR_RRDY_Pos (31U) 2515 #define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ 2516 #define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ 2517 2518 /******************* Bit definition for CORDIC_WDATA register ***************/ 2519 #define CORDIC_WDATA_ARG_Pos (0U) 2520 #define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ 2521 #define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ 2522 2523 /******************* Bit definition for CORDIC_RDATA register ***************/ 2524 #define CORDIC_RDATA_RES_Pos (0U) 2525 #define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ 2526 #define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ 2527 2528 2529 /******************************************************************************/ 2530 /* */ 2531 /* CRC calculation unit */ 2532 /* */ 2533 /******************************************************************************/ 2534 /******************* Bit definition for CRC_DR register *********************/ 2535 #define CRC_DR_DR_Pos (0U) 2536 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 2537 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 2538 2539 /******************* Bit definition for CRC_IDR register ********************/ 2540 #define CRC_IDR_IDR_Pos (0U) 2541 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ 2542 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ 2543 2544 /******************** Bit definition for CRC_CR register ********************/ 2545 #define CRC_CR_RESET_Pos (0U) 2546 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 2547 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 2548 #define CRC_CR_POLYSIZE_Pos (3U) 2549 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 2550 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 2551 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 2552 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 2553 #define CRC_CR_REV_IN_Pos (5U) 2554 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 2555 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 2556 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 2557 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 2558 #define CRC_CR_REV_OUT_Pos (7U) 2559 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 2560 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 2561 2562 /******************* Bit definition for CRC_INIT register *******************/ 2563 #define CRC_INIT_INIT_Pos (0U) 2564 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 2565 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 2566 2567 /******************* Bit definition for CRC_POL register ********************/ 2568 #define CRC_POL_POL_Pos (0U) 2569 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 2570 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 2571 2572 /******************************************************************************/ 2573 /* */ 2574 /* CRS Clock Recovery System */ 2575 /******************************************************************************/ 2576 2577 /******************* Bit definition for CRS_CR register *********************/ 2578 #define CRS_CR_SYNCOKIE_Pos (0U) 2579 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ 2580 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ 2581 #define CRS_CR_SYNCWARNIE_Pos (1U) 2582 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ 2583 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ 2584 #define CRS_CR_ERRIE_Pos (2U) 2585 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ 2586 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ 2587 #define CRS_CR_ESYNCIE_Pos (3U) 2588 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ 2589 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ 2590 #define CRS_CR_CEN_Pos (5U) 2591 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ 2592 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ 2593 #define CRS_CR_AUTOTRIMEN_Pos (6U) 2594 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ 2595 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ 2596 #define CRS_CR_SWSYNC_Pos (7U) 2597 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ 2598 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ 2599 #define CRS_CR_TRIM_Pos (8U) 2600 #define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ 2601 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ 2602 2603 /******************* Bit definition for CRS_CFGR register *********************/ 2604 #define CRS_CFGR_RELOAD_Pos (0U) 2605 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ 2606 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ 2607 #define CRS_CFGR_FELIM_Pos (16U) 2608 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ 2609 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ 2610 2611 #define CRS_CFGR_SYNCDIV_Pos (24U) 2612 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ 2613 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ 2614 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ 2615 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ 2616 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ 2617 2618 #define CRS_CFGR_SYNCSRC_Pos (28U) 2619 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ 2620 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ 2621 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ 2622 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ 2623 2624 #define CRS_CFGR_SYNCPOL_Pos (31U) 2625 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ 2626 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ 2627 2628 /******************* Bit definition for CRS_ISR register *********************/ 2629 #define CRS_ISR_SYNCOKF_Pos (0U) 2630 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ 2631 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ 2632 #define CRS_ISR_SYNCWARNF_Pos (1U) 2633 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ 2634 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ 2635 #define CRS_ISR_ERRF_Pos (2U) 2636 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ 2637 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ 2638 #define CRS_ISR_ESYNCF_Pos (3U) 2639 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ 2640 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ 2641 #define CRS_ISR_SYNCERR_Pos (8U) 2642 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ 2643 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ 2644 #define CRS_ISR_SYNCMISS_Pos (9U) 2645 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ 2646 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ 2647 #define CRS_ISR_TRIMOVF_Pos (10U) 2648 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ 2649 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ 2650 #define CRS_ISR_FEDIR_Pos (15U) 2651 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ 2652 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ 2653 #define CRS_ISR_FECAP_Pos (16U) 2654 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ 2655 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ 2656 2657 /******************* Bit definition for CRS_ICR register *********************/ 2658 #define CRS_ICR_SYNCOKC_Pos (0U) 2659 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ 2660 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ 2661 #define CRS_ICR_SYNCWARNC_Pos (1U) 2662 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ 2663 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ 2664 #define CRS_ICR_ERRC_Pos (2U) 2665 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ 2666 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ 2667 #define CRS_ICR_ESYNCC_Pos (3U) 2668 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ 2669 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ 2670 2671 /******************************************************************************/ 2672 /* */ 2673 /* Digital to Analog Converter */ 2674 /* */ 2675 /******************************************************************************/ 2676 /* 2677 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) 2678 */ 2679 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ 2680 2681 /******************** Bit definition for DAC_CR register ********************/ 2682 #define DAC_CR_EN1_Pos (0U) 2683 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 2684 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ 2685 #define DAC_CR_TEN1_Pos (1U) 2686 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ 2687 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ 2688 2689 #define DAC_CR_TSEL1_Pos (2U) 2690 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */ 2691 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */ 2692 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ 2693 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 2694 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 2695 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 2696 2697 #define DAC_CR_WAVE1_Pos (6U) 2698 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 2699 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 2700 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 2701 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 2702 2703 #define DAC_CR_MAMP1_Pos (8U) 2704 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 2705 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 2706 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 2707 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 2708 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 2709 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 2710 2711 #define DAC_CR_DMAEN1_Pos (12U) 2712 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 2713 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ 2714 #define DAC_CR_DMAUDRIE1_Pos (13U) 2715 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 2716 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/ 2717 #define DAC_CR_CEN1_Pos (14U) 2718 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ 2719 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/ 2720 2721 #define DAC_CR_HFSEL_Pos (15U) 2722 #define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ 2723 #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/ 2724 2725 #define DAC_CR_EN2_Pos (16U) 2726 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 2727 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ 2728 #define DAC_CR_TEN2_Pos (17U) 2729 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */ 2730 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ 2731 2732 #define DAC_CR_TSEL2_Pos (18U) 2733 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */ 2734 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */ 2735 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */ 2736 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 2737 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 2738 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 2739 2740 #define DAC_CR_WAVE2_Pos (22U) 2741 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 2742 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 2743 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 2744 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 2745 2746 #define DAC_CR_MAMP2_Pos (24U) 2747 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 2748 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 2749 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 2750 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 2751 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 2752 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 2753 2754 #define DAC_CR_DMAEN2_Pos (28U) 2755 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 2756 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ 2757 #define DAC_CR_DMAUDRIE2_Pos (29U) 2758 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 2759 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/ 2760 #define DAC_CR_CEN2_Pos (30U) 2761 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ 2762 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/ 2763 2764 /***************** Bit definition for DAC_SWTRIGR register ******************/ 2765 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 2766 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 2767 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ 2768 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 2769 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 2770 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ 2771 #define DAC_SWTRIGR_SWTRIGB1_Pos (16U) 2772 #define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */ 2773 #define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */ 2774 #define DAC_SWTRIGR_SWTRIGB2_Pos (17U) 2775 #define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */ 2776 #define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */ 2777 2778 /***************** Bit definition for DAC_DHR12R1 register ******************/ 2779 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 2780 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 2781 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 2782 #define DAC_DHR12R1_DACC1DHRB_Pos (16U) 2783 #define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */ 2784 #define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */ 2785 2786 /***************** Bit definition for DAC_DHR12L1 register ******************/ 2787 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 2788 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 2789 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 2790 #define DAC_DHR12L1_DACC1DHRB_Pos (20U) 2791 #define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */ 2792 #define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */ 2793 2794 /****************** Bit definition for DAC_DHR8R1 register ******************/ 2795 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 2796 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 2797 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 2798 #define DAC_DHR8R1_DACC1DHRB_Pos (8U) 2799 #define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */ 2800 #define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */ 2801 2802 /***************** Bit definition for DAC_DHR12R2 register ******************/ 2803 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 2804 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 2805 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 2806 #define DAC_DHR12R2_DACC2DHRB_Pos (16U) 2807 #define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */ 2808 #define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */ 2809 2810 /***************** Bit definition for DAC_DHR12L2 register ******************/ 2811 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 2812 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 2813 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 2814 #define DAC_DHR12L2_DACC2DHRB_Pos (20U) 2815 #define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */ 2816 #define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */ 2817 2818 /****************** Bit definition for DAC_DHR8R2 register ******************/ 2819 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 2820 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 2821 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 2822 #define DAC_DHR8R2_DACC2DHRB_Pos (8U) 2823 #define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */ 2824 #define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */ 2825 2826 /***************** Bit definition for DAC_DHR12RD register ******************/ 2827 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 2828 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 2829 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ 2830 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 2831 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 2832 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ 2833 2834 /***************** Bit definition for DAC_DHR12LD register ******************/ 2835 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 2836 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 2837 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ 2838 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 2839 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 2840 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ 2841 2842 /****************** Bit definition for DAC_DHR8RD register ******************/ 2843 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 2844 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 2845 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ 2846 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 2847 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 2848 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ 2849 2850 /******************* Bit definition for DAC_DOR1 register *******************/ 2851 #define DAC_DOR1_DACC1DOR_Pos (0U) 2852 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 2853 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ 2854 #define DAC_DOR1_DACC1DORB_Pos (16U) 2855 #define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */ 2856 #define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */ 2857 2858 /******************* Bit definition for DAC_DOR2 register *******************/ 2859 #define DAC_DOR2_DACC2DOR_Pos (0U) 2860 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 2861 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ 2862 #define DAC_DOR2_DACC2DORB_Pos (16U) 2863 #define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */ 2864 #define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */ 2865 2866 /******************** Bit definition for DAC_SR register ********************/ 2867 #define DAC_SR_DAC1RDY_Pos (11U) 2868 #define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */ 2869 #define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */ 2870 #define DAC_SR_DORSTAT1_Pos (12U) 2871 #define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */ 2872 #define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */ 2873 #define DAC_SR_DMAUDR1_Pos (13U) 2874 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 2875 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ 2876 #define DAC_SR_CAL_FLAG1_Pos (14U) 2877 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ 2878 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */ 2879 #define DAC_SR_BWST1_Pos (15U) 2880 #define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ 2881 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */ 2882 2883 2884 #define DAC_SR_DAC2RDY_Pos (27U) 2885 #define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */ 2886 #define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */ 2887 #define DAC_SR_DORSTAT2_Pos (28U) 2888 #define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */ 2889 #define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */ 2890 #define DAC_SR_DMAUDR2_Pos (29U) 2891 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 2892 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ 2893 #define DAC_SR_CAL_FLAG2_Pos (30U) 2894 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */ 2895 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */ 2896 #define DAC_SR_BWST2_Pos (31U) 2897 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */ 2898 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */ 2899 2900 /******************* Bit definition for DAC_CCR register ********************/ 2901 #define DAC_CCR_OTRIM1_Pos (0U) 2902 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ 2903 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */ 2904 #define DAC_CCR_OTRIM2_Pos (16U) 2905 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */ 2906 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */ 2907 2908 /******************* Bit definition for DAC_MCR register *******************/ 2909 #define DAC_MCR_MODE1_Pos (0U) 2910 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ 2911 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */ 2912 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ 2913 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ 2914 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ 2915 2916 #define DAC_MCR_DMADOUBLE1_Pos (8U) 2917 #define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */ 2918 #define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */ 2919 2920 #define DAC_MCR_SINFORMAT1_Pos (9U) 2921 #define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */ 2922 #define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */ 2923 2924 #define DAC_MCR_HFSEL_Pos (14U) 2925 #define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */ 2926 #define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */ 2927 #define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */ 2928 #define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */ 2929 2930 #define DAC_MCR_MODE2_Pos (16U) 2931 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */ 2932 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */ 2933 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */ 2934 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */ 2935 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */ 2936 2937 #define DAC_MCR_DMADOUBLE2_Pos (24U) 2938 #define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */ 2939 #define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */ 2940 2941 #define DAC_MCR_SINFORMAT2_Pos (25U) 2942 #define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */ 2943 #define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */ 2944 2945 /****************** Bit definition for DAC_SHSR1 register ******************/ 2946 #define DAC_SHSR1_TSAMPLE1_Pos (0U) 2947 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ 2948 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */ 2949 2950 /****************** Bit definition for DAC_SHSR2 register ******************/ 2951 #define DAC_SHSR2_TSAMPLE2_Pos (0U) 2952 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */ 2953 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */ 2954 2955 /****************** Bit definition for DAC_SHHR register ******************/ 2956 #define DAC_SHHR_THOLD1_Pos (0U) 2957 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ 2958 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */ 2959 #define DAC_SHHR_THOLD2_Pos (16U) 2960 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */ 2961 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */ 2962 2963 /****************** Bit definition for DAC_SHRR register ******************/ 2964 #define DAC_SHRR_TREFRESH1_Pos (0U) 2965 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ 2966 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */ 2967 #define DAC_SHRR_TREFRESH2_Pos (16U) 2968 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */ 2969 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */ 2970 2971 /****************** Bit definition for DAC_STR1 register ******************/ 2972 #define DAC_STR1_STRSTDATA1_Pos (0U) 2973 #define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */ 2974 #define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */ 2975 #define DAC_STR1_STDIR1_Pos (12U) 2976 #define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */ 2977 #define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */ 2978 2979 #define DAC_STR1_STINCDATA1_Pos (16U) 2980 #define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */ 2981 #define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */ 2982 2983 /****************** Bit definition for DAC_STR2 register ******************/ 2984 #define DAC_STR2_STRSTDATA2_Pos (0U) 2985 #define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */ 2986 #define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */ 2987 #define DAC_STR2_STDIR2_Pos (12U) 2988 #define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */ 2989 #define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */ 2990 2991 #define DAC_STR2_STINCDATA2_Pos (16U) 2992 #define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */ 2993 #define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */ 2994 2995 /****************** Bit definition for DAC_STMODR register ****************/ 2996 #define DAC_STMODR_STRSTTRIGSEL1_Pos (0U) 2997 #define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */ 2998 #define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */ 2999 #define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */ 3000 #define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */ 3001 #define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */ 3002 #define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */ 3003 3004 #define DAC_STMODR_STINCTRIGSEL1_Pos (8U) 3005 #define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */ 3006 #define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */ 3007 #define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */ 3008 #define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */ 3009 #define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */ 3010 #define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */ 3011 3012 #define DAC_STMODR_STRSTTRIGSEL2_Pos (16U) 3013 #define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */ 3014 #define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */ 3015 #define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */ 3016 #define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */ 3017 #define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */ 3018 #define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */ 3019 3020 #define DAC_STMODR_STINCTRIGSEL2_Pos (24U) 3021 #define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */ 3022 #define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */ 3023 #define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */ 3024 #define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */ 3025 #define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */ 3026 #define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */ 3027 3028 /******************************************************************************/ 3029 /* */ 3030 /* Debug MCU */ 3031 /* */ 3032 /******************************************************************************/ 3033 /******************** Bit definition for DBGMCU_IDCODE register *************/ 3034 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 3035 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */ 3036 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk 3037 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 3038 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */ 3039 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk 3040 3041 /******************** Bit definition for DBGMCU_CR register *****************/ 3042 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 3043 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */ 3044 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk 3045 #define DBGMCU_CR_DBG_STOP_Pos (1U) 3046 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */ 3047 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk 3048 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 3049 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */ 3050 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk 3051 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 3052 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */ 3053 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk 3054 3055 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 3056 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */ 3057 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk 3058 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */ 3059 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */ 3060 3061 /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/ 3062 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) 3063 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */ 3064 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk 3065 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U) 3066 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */ 3067 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk 3068 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U) 3069 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */ 3070 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk 3071 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U) 3072 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */ 3073 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk 3074 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U) 3075 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */ 3076 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk 3077 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U) 3078 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */ 3079 #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk 3080 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U) 3081 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */ 3082 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk 3083 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U) 3084 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */ 3085 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk 3086 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U) 3087 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */ 3088 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk 3089 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U) 3090 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */ 3091 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk 3092 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U) 3093 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */ 3094 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk 3095 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U) 3096 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */ 3097 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk 3098 3099 /******************** Bit definition for DBGMCU_APB1FZR2 register **********/ 3100 3101 /******************** Bit definition for DBGMCU_APB2FZ register ************/ 3102 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U) 3103 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */ 3104 #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk 3105 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U) 3106 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */ 3107 #define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk 3108 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U) 3109 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */ 3110 #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk 3111 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U) 3112 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */ 3113 #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk 3114 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U) 3115 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ 3116 #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk 3117 3118 /******************************************************************************/ 3119 /* */ 3120 /* DMA Controller (DMA) */ 3121 /* */ 3122 /******************************************************************************/ 3123 3124 /******************* Bit definition for DMA_ISR register ********************/ 3125 #define DMA_ISR_GIF1_Pos (0U) 3126 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 3127 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 3128 #define DMA_ISR_TCIF1_Pos (1U) 3129 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 3130 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 3131 #define DMA_ISR_HTIF1_Pos (2U) 3132 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 3133 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 3134 #define DMA_ISR_TEIF1_Pos (3U) 3135 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 3136 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 3137 #define DMA_ISR_GIF2_Pos (4U) 3138 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 3139 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 3140 #define DMA_ISR_TCIF2_Pos (5U) 3141 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 3142 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 3143 #define DMA_ISR_HTIF2_Pos (6U) 3144 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 3145 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 3146 #define DMA_ISR_TEIF2_Pos (7U) 3147 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 3148 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 3149 #define DMA_ISR_GIF3_Pos (8U) 3150 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 3151 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 3152 #define DMA_ISR_TCIF3_Pos (9U) 3153 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 3154 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 3155 #define DMA_ISR_HTIF3_Pos (10U) 3156 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 3157 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 3158 #define DMA_ISR_TEIF3_Pos (11U) 3159 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 3160 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 3161 #define DMA_ISR_GIF4_Pos (12U) 3162 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 3163 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 3164 #define DMA_ISR_TCIF4_Pos (13U) 3165 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 3166 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 3167 #define DMA_ISR_HTIF4_Pos (14U) 3168 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 3169 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 3170 #define DMA_ISR_TEIF4_Pos (15U) 3171 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 3172 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 3173 #define DMA_ISR_GIF5_Pos (16U) 3174 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 3175 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 3176 #define DMA_ISR_TCIF5_Pos (17U) 3177 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 3178 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 3179 #define DMA_ISR_HTIF5_Pos (18U) 3180 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 3181 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 3182 #define DMA_ISR_TEIF5_Pos (19U) 3183 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 3184 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 3185 #define DMA_ISR_GIF6_Pos (20U) 3186 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 3187 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 3188 #define DMA_ISR_TCIF6_Pos (21U) 3189 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 3190 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 3191 #define DMA_ISR_HTIF6_Pos (22U) 3192 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 3193 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 3194 #define DMA_ISR_TEIF6_Pos (23U) 3195 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 3196 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 3197 3198 /******************* Bit definition for DMA_IFCR register *******************/ 3199 #define DMA_IFCR_CGIF1_Pos (0U) 3200 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 3201 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ 3202 #define DMA_IFCR_CTCIF1_Pos (1U) 3203 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 3204 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 3205 #define DMA_IFCR_CHTIF1_Pos (2U) 3206 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 3207 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 3208 #define DMA_IFCR_CTEIF1_Pos (3U) 3209 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 3210 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 3211 #define DMA_IFCR_CGIF2_Pos (4U) 3212 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 3213 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 3214 #define DMA_IFCR_CTCIF2_Pos (5U) 3215 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 3216 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 3217 #define DMA_IFCR_CHTIF2_Pos (6U) 3218 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 3219 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 3220 #define DMA_IFCR_CTEIF2_Pos (7U) 3221 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 3222 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 3223 #define DMA_IFCR_CGIF3_Pos (8U) 3224 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 3225 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 3226 #define DMA_IFCR_CTCIF3_Pos (9U) 3227 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 3228 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 3229 #define DMA_IFCR_CHTIF3_Pos (10U) 3230 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 3231 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 3232 #define DMA_IFCR_CTEIF3_Pos (11U) 3233 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 3234 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 3235 #define DMA_IFCR_CGIF4_Pos (12U) 3236 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 3237 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 3238 #define DMA_IFCR_CTCIF4_Pos (13U) 3239 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 3240 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 3241 #define DMA_IFCR_CHTIF4_Pos (14U) 3242 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 3243 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 3244 #define DMA_IFCR_CTEIF4_Pos (15U) 3245 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 3246 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 3247 #define DMA_IFCR_CGIF5_Pos (16U) 3248 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 3249 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 3250 #define DMA_IFCR_CTCIF5_Pos (17U) 3251 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 3252 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 3253 #define DMA_IFCR_CHTIF5_Pos (18U) 3254 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 3255 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 3256 #define DMA_IFCR_CTEIF5_Pos (19U) 3257 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 3258 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 3259 #define DMA_IFCR_CGIF6_Pos (20U) 3260 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 3261 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 3262 #define DMA_IFCR_CTCIF6_Pos (21U) 3263 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 3264 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 3265 #define DMA_IFCR_CHTIF6_Pos (22U) 3266 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 3267 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 3268 #define DMA_IFCR_CTEIF6_Pos (23U) 3269 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 3270 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 3271 3272 /******************* Bit definition for DMA_CCR register ********************/ 3273 #define DMA_CCR_EN_Pos (0U) 3274 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 3275 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 3276 #define DMA_CCR_TCIE_Pos (1U) 3277 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 3278 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 3279 #define DMA_CCR_HTIE_Pos (2U) 3280 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 3281 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 3282 #define DMA_CCR_TEIE_Pos (3U) 3283 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 3284 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 3285 #define DMA_CCR_DIR_Pos (4U) 3286 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 3287 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 3288 #define DMA_CCR_CIRC_Pos (5U) 3289 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 3290 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 3291 #define DMA_CCR_PINC_Pos (6U) 3292 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 3293 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 3294 #define DMA_CCR_MINC_Pos (7U) 3295 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 3296 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 3297 3298 #define DMA_CCR_PSIZE_Pos (8U) 3299 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 3300 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 3301 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 3302 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 3303 3304 #define DMA_CCR_MSIZE_Pos (10U) 3305 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 3306 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 3307 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 3308 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 3309 3310 #define DMA_CCR_PL_Pos (12U) 3311 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 3312 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 3313 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 3314 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 3315 3316 #define DMA_CCR_MEM2MEM_Pos (14U) 3317 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 3318 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 3319 3320 /****************** Bit definition for DMA_CNDTR register *******************/ 3321 #define DMA_CNDTR_NDT_Pos (0U) 3322 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 3323 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 3324 3325 /****************** Bit definition for DMA_CPAR register ********************/ 3326 #define DMA_CPAR_PA_Pos (0U) 3327 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 3328 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 3329 3330 /****************** Bit definition for DMA_CMAR register ********************/ 3331 #define DMA_CMAR_MA_Pos (0U) 3332 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 3333 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 3334 3335 /******************************************************************************/ 3336 /* */ 3337 /* DMAMUX Controller */ 3338 /* */ 3339 /******************************************************************************/ 3340 3341 /******************** Bits definition for DMAMUX_CxCR register **************/ 3342 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) 3343 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */ 3344 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk 3345 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */ 3346 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */ 3347 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */ 3348 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */ 3349 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */ 3350 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */ 3351 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */ 3352 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */ 3353 3354 #define DMAMUX_CxCR_SOIE_Pos (8U) 3355 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */ 3356 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk 3357 3358 #define DMAMUX_CxCR_EGE_Pos (9U) 3359 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */ 3360 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk 3361 3362 #define DMAMUX_CxCR_SE_Pos (16U) 3363 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */ 3364 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk 3365 3366 #define DMAMUX_CxCR_SPOL_Pos (17U) 3367 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */ 3368 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk 3369 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */ 3370 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */ 3371 3372 #define DMAMUX_CxCR_NBREQ_Pos (19U) 3373 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */ 3374 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk 3375 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */ 3376 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */ 3377 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */ 3378 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */ 3379 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */ 3380 3381 #define DMAMUX_CxCR_SYNC_ID_Pos (24U) 3382 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */ 3383 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk 3384 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */ 3385 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */ 3386 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */ 3387 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */ 3388 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */ 3389 3390 /******************** Bits definition for DMAMUX_CSR register ****************/ 3391 #define DMAMUX_CSR_SOF0_Pos (0U) 3392 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */ 3393 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk 3394 #define DMAMUX_CSR_SOF1_Pos (1U) 3395 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */ 3396 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk 3397 #define DMAMUX_CSR_SOF2_Pos (2U) 3398 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */ 3399 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk 3400 #define DMAMUX_CSR_SOF3_Pos (3U) 3401 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */ 3402 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk 3403 #define DMAMUX_CSR_SOF4_Pos (4U) 3404 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */ 3405 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk 3406 #define DMAMUX_CSR_SOF5_Pos (5U) 3407 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */ 3408 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk 3409 #define DMAMUX_CSR_SOF6_Pos (6U) 3410 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */ 3411 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk 3412 #define DMAMUX_CSR_SOF7_Pos (7U) 3413 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */ 3414 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk 3415 #define DMAMUX_CSR_SOF8_Pos (8U) 3416 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */ 3417 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk 3418 #define DMAMUX_CSR_SOF9_Pos (9U) 3419 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */ 3420 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk 3421 #define DMAMUX_CSR_SOF10_Pos (10U) 3422 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */ 3423 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk 3424 #define DMAMUX_CSR_SOF11_Pos (11U) 3425 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */ 3426 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk 3427 3428 /******************** Bits definition for DMAMUX_CFR register ****************/ 3429 #define DMAMUX_CFR_CSOF0_Pos (0U) 3430 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */ 3431 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk 3432 #define DMAMUX_CFR_CSOF1_Pos (1U) 3433 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */ 3434 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk 3435 #define DMAMUX_CFR_CSOF2_Pos (2U) 3436 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */ 3437 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk 3438 #define DMAMUX_CFR_CSOF3_Pos (3U) 3439 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */ 3440 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk 3441 #define DMAMUX_CFR_CSOF4_Pos (4U) 3442 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */ 3443 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk 3444 #define DMAMUX_CFR_CSOF5_Pos (5U) 3445 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */ 3446 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk 3447 #define DMAMUX_CFR_CSOF6_Pos (6U) 3448 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */ 3449 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk 3450 #define DMAMUX_CFR_CSOF7_Pos (7U) 3451 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */ 3452 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk 3453 #define DMAMUX_CFR_CSOF8_Pos (8U) 3454 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */ 3455 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk 3456 #define DMAMUX_CFR_CSOF9_Pos (9U) 3457 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */ 3458 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk 3459 #define DMAMUX_CFR_CSOF10_Pos (10U) 3460 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */ 3461 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk 3462 #define DMAMUX_CFR_CSOF11_Pos (11U) 3463 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */ 3464 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk 3465 3466 /******************** Bits definition for DMAMUX_RGxCR register ************/ 3467 #define DMAMUX_RGxCR_SIG_ID_Pos (0U) 3468 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */ 3469 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk 3470 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */ 3471 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */ 3472 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */ 3473 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */ 3474 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */ 3475 3476 #define DMAMUX_RGxCR_OIE_Pos (8U) 3477 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */ 3478 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk 3479 3480 #define DMAMUX_RGxCR_GE_Pos (16U) 3481 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */ 3482 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk 3483 3484 #define DMAMUX_RGxCR_GPOL_Pos (17U) 3485 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */ 3486 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk 3487 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */ 3488 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */ 3489 3490 #define DMAMUX_RGxCR_GNBREQ_Pos (19U) 3491 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */ 3492 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk 3493 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */ 3494 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */ 3495 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */ 3496 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */ 3497 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */ 3498 3499 /******************** Bits definition for DMAMUX_RGSR register **************/ 3500 #define DMAMUX_RGSR_OF0_Pos (0U) 3501 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */ 3502 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk 3503 #define DMAMUX_RGSR_OF1_Pos (1U) 3504 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */ 3505 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk 3506 #define DMAMUX_RGSR_OF2_Pos (2U) 3507 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */ 3508 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk 3509 #define DMAMUX_RGSR_OF3_Pos (3U) 3510 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */ 3511 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk 3512 3513 /******************** Bits definition for DMAMUX_RGCFR register ************/ 3514 #define DMAMUX_RGCFR_COF0_Pos (0U) 3515 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */ 3516 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk 3517 #define DMAMUX_RGCFR_COF1_Pos (1U) 3518 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */ 3519 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk 3520 #define DMAMUX_RGCFR_COF2_Pos (2U) 3521 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */ 3522 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk 3523 #define DMAMUX_RGCFR_COF3_Pos (3U) 3524 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */ 3525 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk 3526 3527 /******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/ 3528 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U) 3529 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */ 3530 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk 3531 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U) 3532 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */ 3533 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk 3534 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U) 3535 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */ 3536 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk 3537 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U) 3538 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */ 3539 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk 3540 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U) 3541 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */ 3542 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk 3543 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U) 3544 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */ 3545 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk 3546 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U) 3547 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */ 3548 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk 3549 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U) 3550 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */ 3551 #define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk 3552 3553 /******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/ 3554 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U) 3555 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */ 3556 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk 3557 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U) 3558 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */ 3559 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk 3560 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U) 3561 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */ 3562 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk 3563 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U) 3564 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */ 3565 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk 3566 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U) 3567 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */ 3568 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk 3569 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U) 3570 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */ 3571 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk 3572 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U) 3573 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */ 3574 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk 3575 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U) 3576 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */ 3577 #define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk 3578 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U) 3579 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */ 3580 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk 3581 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U) 3582 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */ 3583 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk 3584 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U) 3585 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */ 3586 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk 3587 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U) 3588 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */ 3589 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk 3590 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U) 3591 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */ 3592 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk 3593 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U) 3594 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */ 3595 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk 3596 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U) 3597 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */ 3598 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk 3599 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U) 3600 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */ 3601 #define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk 3602 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U) 3603 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */ 3604 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk 3605 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U) 3606 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */ 3607 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk 3608 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U) 3609 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */ 3610 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk 3611 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U) 3612 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */ 3613 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk 3614 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U) 3615 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */ 3616 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk 3617 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U) 3618 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */ 3619 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk 3620 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U) 3621 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */ 3622 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk 3623 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U) 3624 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */ 3625 #define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk 3626 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U) 3627 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */ 3628 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk 3629 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U) 3630 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */ 3631 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk 3632 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U) 3633 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */ 3634 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk 3635 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U) 3636 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */ 3637 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk 3638 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U) 3639 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */ 3640 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk 3641 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U) 3642 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */ 3643 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk 3644 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U) 3645 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */ 3646 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk 3647 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U) 3648 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */ 3649 #define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk 3650 3651 3652 /******************************************************************************/ 3653 /* */ 3654 /* External Interrupt/Event Controller */ 3655 /* */ 3656 /******************************************************************************/ 3657 /******************* Bit definition for EXTI_IMR1 register ******************/ 3658 #define EXTI_IMR1_IM0_Pos (0U) 3659 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ 3660 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ 3661 #define EXTI_IMR1_IM1_Pos (1U) 3662 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ 3663 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ 3664 #define EXTI_IMR1_IM2_Pos (2U) 3665 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ 3666 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ 3667 #define EXTI_IMR1_IM3_Pos (3U) 3668 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ 3669 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ 3670 #define EXTI_IMR1_IM4_Pos (4U) 3671 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ 3672 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ 3673 #define EXTI_IMR1_IM5_Pos (5U) 3674 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ 3675 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ 3676 #define EXTI_IMR1_IM6_Pos (6U) 3677 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ 3678 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ 3679 #define EXTI_IMR1_IM7_Pos (7U) 3680 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ 3681 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ 3682 #define EXTI_IMR1_IM8_Pos (8U) 3683 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ 3684 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ 3685 #define EXTI_IMR1_IM9_Pos (9U) 3686 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ 3687 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ 3688 #define EXTI_IMR1_IM10_Pos (10U) 3689 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ 3690 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ 3691 #define EXTI_IMR1_IM11_Pos (11U) 3692 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ 3693 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ 3694 #define EXTI_IMR1_IM12_Pos (12U) 3695 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ 3696 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ 3697 #define EXTI_IMR1_IM13_Pos (13U) 3698 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ 3699 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ 3700 #define EXTI_IMR1_IM14_Pos (14U) 3701 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ 3702 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ 3703 #define EXTI_IMR1_IM15_Pos (15U) 3704 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ 3705 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ 3706 #define EXTI_IMR1_IM16_Pos (16U) 3707 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ 3708 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ 3709 #define EXTI_IMR1_IM17_Pos (17U) 3710 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ 3711 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ 3712 #define EXTI_IMR1_IM18_Pos (18U) 3713 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ 3714 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ 3715 #define EXTI_IMR1_IM19_Pos (19U) 3716 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ 3717 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ 3718 #define EXTI_IMR1_IM20_Pos (20U) 3719 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ 3720 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ 3721 #define EXTI_IMR1_IM21_Pos (21U) 3722 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ 3723 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ 3724 #define EXTI_IMR1_IM22_Pos (22U) 3725 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ 3726 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */ 3727 #define EXTI_IMR1_IM23_Pos (23U) 3728 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ 3729 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ 3730 #define EXTI_IMR1_IM24_Pos (24U) 3731 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ 3732 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ 3733 #define EXTI_IMR1_IM25_Pos (25U) 3734 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ 3735 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ 3736 #define EXTI_IMR1_IM26_Pos (26U) 3737 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ 3738 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ 3739 #define EXTI_IMR1_IM27_Pos (27U) 3740 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ 3741 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */ 3742 #define EXTI_IMR1_IM28_Pos (28U) 3743 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ 3744 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */ 3745 #define EXTI_IMR1_IM29_Pos (29U) 3746 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ 3747 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */ 3748 #define EXTI_IMR1_IM30_Pos (30U) 3749 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ 3750 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */ 3751 #define EXTI_IMR1_IM_Pos (0U) 3752 #define EXTI_IMR1_IM_Msk (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x7FFFFFFF */ 3753 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ 3754 3755 /******************* Bit definition for EXTI_EMR1 register ******************/ 3756 #define EXTI_EMR1_EM0_Pos (0U) 3757 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ 3758 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ 3759 #define EXTI_EMR1_EM1_Pos (1U) 3760 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ 3761 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ 3762 #define EXTI_EMR1_EM2_Pos (2U) 3763 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ 3764 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ 3765 #define EXTI_EMR1_EM3_Pos (3U) 3766 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ 3767 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ 3768 #define EXTI_EMR1_EM4_Pos (4U) 3769 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ 3770 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ 3771 #define EXTI_EMR1_EM5_Pos (5U) 3772 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ 3773 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ 3774 #define EXTI_EMR1_EM6_Pos (6U) 3775 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ 3776 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ 3777 #define EXTI_EMR1_EM7_Pos (7U) 3778 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ 3779 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ 3780 #define EXTI_EMR1_EM8_Pos (8U) 3781 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ 3782 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ 3783 #define EXTI_EMR1_EM9_Pos (9U) 3784 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ 3785 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ 3786 #define EXTI_EMR1_EM10_Pos (10U) 3787 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ 3788 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ 3789 #define EXTI_EMR1_EM11_Pos (11U) 3790 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ 3791 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ 3792 #define EXTI_EMR1_EM12_Pos (12U) 3793 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ 3794 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ 3795 #define EXTI_EMR1_EM13_Pos (13U) 3796 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ 3797 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ 3798 #define EXTI_EMR1_EM14_Pos (14U) 3799 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ 3800 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ 3801 #define EXTI_EMR1_EM15_Pos (15U) 3802 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ 3803 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ 3804 #define EXTI_EMR1_EM16_Pos (16U) 3805 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ 3806 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ 3807 #define EXTI_EMR1_EM17_Pos (17U) 3808 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ 3809 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ 3810 #define EXTI_EMR1_EM18_Pos (18U) 3811 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ 3812 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ 3813 #define EXTI_EMR1_EM19_Pos (19U) 3814 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ 3815 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ 3816 #define EXTI_EMR1_EM20_Pos (20U) 3817 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ 3818 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */ 3819 #define EXTI_EMR1_EM21_Pos (21U) 3820 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ 3821 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ 3822 #define EXTI_EMR1_EM22_Pos (22U) 3823 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ 3824 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */ 3825 #define EXTI_EMR1_EM23_Pos (23U) 3826 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ 3827 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ 3828 #define EXTI_EMR1_EM24_Pos (24U) 3829 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ 3830 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */ 3831 #define EXTI_EMR1_EM25_Pos (25U) 3832 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ 3833 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ 3834 #define EXTI_EMR1_EM26_Pos (26U) 3835 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ 3836 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ 3837 #define EXTI_EMR1_EM27_Pos (27U) 3838 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ 3839 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */ 3840 #define EXTI_EMR1_EM28_Pos (28U) 3841 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ 3842 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */ 3843 #define EXTI_EMR1_EM29_Pos (29U) 3844 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ 3845 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */ 3846 #define EXTI_EMR1_EM30_Pos (30U) 3847 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ 3848 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */ 3849 3850 /****************** Bit definition for EXTI_RTSR1 register ******************/ 3851 #define EXTI_RTSR1_RT0_Pos (0U) 3852 #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ 3853 #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ 3854 #define EXTI_RTSR1_RT1_Pos (1U) 3855 #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ 3856 #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ 3857 #define EXTI_RTSR1_RT2_Pos (2U) 3858 #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ 3859 #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ 3860 #define EXTI_RTSR1_RT3_Pos (3U) 3861 #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ 3862 #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ 3863 #define EXTI_RTSR1_RT4_Pos (4U) 3864 #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ 3865 #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ 3866 #define EXTI_RTSR1_RT5_Pos (5U) 3867 #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ 3868 #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ 3869 #define EXTI_RTSR1_RT6_Pos (6U) 3870 #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ 3871 #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ 3872 #define EXTI_RTSR1_RT7_Pos (7U) 3873 #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ 3874 #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ 3875 #define EXTI_RTSR1_RT8_Pos (8U) 3876 #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ 3877 #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ 3878 #define EXTI_RTSR1_RT9_Pos (9U) 3879 #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ 3880 #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ 3881 #define EXTI_RTSR1_RT10_Pos (10U) 3882 #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ 3883 #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ 3884 #define EXTI_RTSR1_RT11_Pos (11U) 3885 #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ 3886 #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ 3887 #define EXTI_RTSR1_RT12_Pos (12U) 3888 #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ 3889 #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ 3890 #define EXTI_RTSR1_RT13_Pos (13U) 3891 #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ 3892 #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ 3893 #define EXTI_RTSR1_RT14_Pos (14U) 3894 #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ 3895 #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ 3896 #define EXTI_RTSR1_RT15_Pos (15U) 3897 #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ 3898 #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ 3899 #define EXTI_RTSR1_RT16_Pos (16U) 3900 #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ 3901 #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ 3902 #define EXTI_RTSR1_RT17_Pos (17U) 3903 #define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ 3904 #define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ 3905 #define EXTI_RTSR1_RT19_Pos (19U) 3906 #define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ 3907 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ 3908 #define EXTI_RTSR1_RT20_Pos (20U) 3909 #define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ 3910 #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ 3911 #define EXTI_RTSR1_RT21_Pos (21U) 3912 #define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ 3913 #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ 3914 #define EXTI_RTSR1_RT22_Pos (22U) 3915 #define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */ 3916 #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ 3917 #define EXTI_RTSR1_RT29_Pos (29U) 3918 #define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */ 3919 #define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */ 3920 #define EXTI_RTSR1_RT30_Pos (30U) 3921 #define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */ 3922 #define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */ 3923 3924 /****************** Bit definition for EXTI_FTSR1 register ******************/ 3925 #define EXTI_FTSR1_FT0_Pos (0U) 3926 #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ 3927 #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ 3928 #define EXTI_FTSR1_FT1_Pos (1U) 3929 #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ 3930 #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ 3931 #define EXTI_FTSR1_FT2_Pos (2U) 3932 #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ 3933 #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ 3934 #define EXTI_FTSR1_FT3_Pos (3U) 3935 #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ 3936 #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ 3937 #define EXTI_FTSR1_FT4_Pos (4U) 3938 #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ 3939 #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ 3940 #define EXTI_FTSR1_FT5_Pos (5U) 3941 #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ 3942 #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ 3943 #define EXTI_FTSR1_FT6_Pos (6U) 3944 #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ 3945 #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ 3946 #define EXTI_FTSR1_FT7_Pos (7U) 3947 #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ 3948 #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ 3949 #define EXTI_FTSR1_FT8_Pos (8U) 3950 #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ 3951 #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ 3952 #define EXTI_FTSR1_FT9_Pos (9U) 3953 #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ 3954 #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ 3955 #define EXTI_FTSR1_FT10_Pos (10U) 3956 #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ 3957 #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ 3958 #define EXTI_FTSR1_FT11_Pos (11U) 3959 #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ 3960 #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ 3961 #define EXTI_FTSR1_FT12_Pos (12U) 3962 #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ 3963 #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ 3964 #define EXTI_FTSR1_FT13_Pos (13U) 3965 #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ 3966 #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ 3967 #define EXTI_FTSR1_FT14_Pos (14U) 3968 #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ 3969 #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ 3970 #define EXTI_FTSR1_FT15_Pos (15U) 3971 #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ 3972 #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ 3973 #define EXTI_FTSR1_FT16_Pos (16U) 3974 #define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ 3975 #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ 3976 #define EXTI_FTSR1_FT17_Pos (17U) 3977 #define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ 3978 #define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ 3979 #define EXTI_FTSR1_FT19_Pos (19U) 3980 #define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ 3981 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ 3982 #define EXTI_FTSR1_FT20_Pos (20U) 3983 #define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ 3984 #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ 3985 #define EXTI_FTSR1_FT21_Pos (21U) 3986 #define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ 3987 #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ 3988 #define EXTI_FTSR1_FT22_Pos (22U) 3989 #define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */ 3990 #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ 3991 #define EXTI_FTSR1_FT29_Pos (29U) 3992 #define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */ 3993 #define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */ 3994 #define EXTI_FTSR1_FT30_Pos (30U) 3995 #define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */ 3996 #define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */ 3997 3998 /****************** Bit definition for EXTI_SWIER1 register *****************/ 3999 #define EXTI_SWIER1_SWI0_Pos (0U) 4000 #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ 4001 #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ 4002 #define EXTI_SWIER1_SWI1_Pos (1U) 4003 #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ 4004 #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ 4005 #define EXTI_SWIER1_SWI2_Pos (2U) 4006 #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ 4007 #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ 4008 #define EXTI_SWIER1_SWI3_Pos (3U) 4009 #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ 4010 #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ 4011 #define EXTI_SWIER1_SWI4_Pos (4U) 4012 #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ 4013 #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ 4014 #define EXTI_SWIER1_SWI5_Pos (5U) 4015 #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ 4016 #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ 4017 #define EXTI_SWIER1_SWI6_Pos (6U) 4018 #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ 4019 #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ 4020 #define EXTI_SWIER1_SWI7_Pos (7U) 4021 #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ 4022 #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ 4023 #define EXTI_SWIER1_SWI8_Pos (8U) 4024 #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ 4025 #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ 4026 #define EXTI_SWIER1_SWI9_Pos (9U) 4027 #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ 4028 #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ 4029 #define EXTI_SWIER1_SWI10_Pos (10U) 4030 #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ 4031 #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ 4032 #define EXTI_SWIER1_SWI11_Pos (11U) 4033 #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ 4034 #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ 4035 #define EXTI_SWIER1_SWI12_Pos (12U) 4036 #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ 4037 #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ 4038 #define EXTI_SWIER1_SWI13_Pos (13U) 4039 #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ 4040 #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ 4041 #define EXTI_SWIER1_SWI14_Pos (14U) 4042 #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ 4043 #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ 4044 #define EXTI_SWIER1_SWI15_Pos (15U) 4045 #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ 4046 #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ 4047 #define EXTI_SWIER1_SWI16_Pos (16U) 4048 #define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ 4049 #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ 4050 #define EXTI_SWIER1_SWI17_Pos (17U) 4051 #define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ 4052 #define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ 4053 #define EXTI_SWIER1_SWI19_Pos (19U) 4054 #define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ 4055 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ 4056 #define EXTI_SWIER1_SWI20_Pos (20U) 4057 #define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ 4058 #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ 4059 #define EXTI_SWIER1_SWI21_Pos (21U) 4060 #define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ 4061 #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ 4062 #define EXTI_SWIER1_SWI22_Pos (22U) 4063 #define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */ 4064 #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */ 4065 #define EXTI_SWIER1_SWI29_Pos (29U) 4066 #define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */ 4067 #define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */ 4068 #define EXTI_SWIER1_SWI30_Pos (30U) 4069 #define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */ 4070 #define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */ 4071 4072 /******************* Bit definition for EXTI_PR1 register *******************/ 4073 #define EXTI_PR1_PIF0_Pos (0U) 4074 #define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ 4075 #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ 4076 #define EXTI_PR1_PIF1_Pos (1U) 4077 #define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ 4078 #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ 4079 #define EXTI_PR1_PIF2_Pos (2U) 4080 #define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ 4081 #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ 4082 #define EXTI_PR1_PIF3_Pos (3U) 4083 #define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ 4084 #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ 4085 #define EXTI_PR1_PIF4_Pos (4U) 4086 #define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ 4087 #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ 4088 #define EXTI_PR1_PIF5_Pos (5U) 4089 #define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ 4090 #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ 4091 #define EXTI_PR1_PIF6_Pos (6U) 4092 #define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ 4093 #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ 4094 #define EXTI_PR1_PIF7_Pos (7U) 4095 #define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ 4096 #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ 4097 #define EXTI_PR1_PIF8_Pos (8U) 4098 #define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ 4099 #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ 4100 #define EXTI_PR1_PIF9_Pos (9U) 4101 #define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ 4102 #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ 4103 #define EXTI_PR1_PIF10_Pos (10U) 4104 #define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ 4105 #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ 4106 #define EXTI_PR1_PIF11_Pos (11U) 4107 #define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ 4108 #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ 4109 #define EXTI_PR1_PIF12_Pos (12U) 4110 #define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ 4111 #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ 4112 #define EXTI_PR1_PIF13_Pos (13U) 4113 #define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ 4114 #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ 4115 #define EXTI_PR1_PIF14_Pos (14U) 4116 #define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ 4117 #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ 4118 #define EXTI_PR1_PIF15_Pos (15U) 4119 #define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ 4120 #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ 4121 #define EXTI_PR1_PIF16_Pos (16U) 4122 #define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ 4123 #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ 4124 #define EXTI_PR1_PIF17_Pos (17U) 4125 #define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */ 4126 #define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */ 4127 #define EXTI_PR1_PIF19_Pos (19U) 4128 #define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ 4129 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ 4130 #define EXTI_PR1_PIF20_Pos (20U) 4131 #define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ 4132 #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ 4133 #define EXTI_PR1_PIF21_Pos (21U) 4134 #define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ 4135 #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ 4136 #define EXTI_PR1_PIF22_Pos (22U) 4137 #define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */ 4138 #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */ 4139 #define EXTI_PR1_PIF29_Pos (29U) 4140 #define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */ 4141 #define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */ 4142 #define EXTI_PR1_PIF30_Pos (30U) 4143 #define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */ 4144 #define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */ 4145 4146 /******************* Bit definition for EXTI_IMR2 register ******************/ 4147 #define EXTI_IMR2_IM34_Pos (2U) 4148 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */ 4149 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */ 4150 #define EXTI_IMR2_IM36_Pos (4U) 4151 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ 4152 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */ 4153 #define EXTI_IMR2_IM37_Pos (5U) 4154 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ 4155 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */ 4156 #define EXTI_IMR2_IM38_Pos (6U) 4157 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ 4158 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */ 4159 #define EXTI_IMR2_IM39_Pos (7U) 4160 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */ 4161 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */ 4162 #define EXTI_IMR2_IM40_Pos (8U) 4163 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */ 4164 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */ 4165 #define EXTI_IMR2_IM41_Pos (9U) 4166 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */ 4167 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */ 4168 #define EXTI_IMR2_IM_Pos (0U) 4169 #define EXTI_IMR2_IM_Msk (0x3F4UL << EXTI_IMR2_IM_Pos) /*!< 0x000003F4 */ 4170 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */ 4171 4172 /******************* Bit definition for EXTI_EMR2 register ******************/ 4173 #define EXTI_EMR2_EM34_Pos (2U) 4174 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */ 4175 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */ 4176 #define EXTI_EMR2_EM36_Pos (4U) 4177 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */ 4178 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */ 4179 #define EXTI_EMR2_EM37_Pos (5U) 4180 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */ 4181 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */ 4182 #define EXTI_EMR2_EM38_Pos (6U) 4183 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */ 4184 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */ 4185 #define EXTI_EMR2_EM39_Pos (7U) 4186 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */ 4187 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */ 4188 #define EXTI_EMR2_EM40_Pos (8U) 4189 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */ 4190 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */ 4191 #define EXTI_EMR2_EM41_Pos (9U) 4192 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */ 4193 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */ 4194 #define EXTI_EMR2_EM_Pos (0U) 4195 #define EXTI_EMR2_EM_Msk (0x3F4UL << EXTI_EMR2_EM_Pos) /*!< 0x000003F4 */ 4196 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */ 4197 4198 /****************** Bit definition for EXTI_RTSR2 register ******************/ 4199 #define EXTI_RTSR2_RT38_Pos (6U) 4200 #define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */ 4201 #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */ 4202 #define EXTI_RTSR2_RT39_Pos (7U) 4203 #define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */ 4204 #define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */ 4205 #define EXTI_RTSR2_RT40_Pos (8U) 4206 #define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */ 4207 #define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */ 4208 #define EXTI_RTSR2_RT41_Pos (9U) 4209 #define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */ 4210 #define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */ 4211 4212 /****************** Bit definition for EXTI_FTSR2 register ******************/ 4213 #define EXTI_FTSR2_FT38_Pos (6U) 4214 #define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */ 4215 #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */ 4216 #define EXTI_FTSR2_FT39_Pos (7U) 4217 #define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */ 4218 #define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */ 4219 #define EXTI_FTSR2_FT40_Pos (8U) 4220 #define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */ 4221 #define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */ 4222 #define EXTI_FTSR2_FT41_Pos (9U) 4223 #define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */ 4224 #define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */ 4225 4226 /****************** Bit definition for EXTI_SWIER2 register *****************/ 4227 #define EXTI_SWIER2_SWI38_Pos (6U) 4228 #define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */ 4229 #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */ 4230 #define EXTI_SWIER2_SWI39_Pos (7U) 4231 #define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */ 4232 #define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */ 4233 #define EXTI_SWIER2_SWI40_Pos (8U) 4234 #define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */ 4235 #define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */ 4236 #define EXTI_SWIER2_SWI41_Pos (9U) 4237 #define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */ 4238 #define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */ 4239 4240 /******************* Bit definition for EXTI_PR2 register *******************/ 4241 #define EXTI_PR2_PIF38_Pos (6U) 4242 #define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */ 4243 #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */ 4244 #define EXTI_PR2_PIF39_Pos (7U) 4245 #define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */ 4246 #define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */ 4247 #define EXTI_PR2_PIF40_Pos (8U) 4248 #define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */ 4249 #define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */ 4250 #define EXTI_PR2_PIF41_Pos (9U) 4251 #define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */ 4252 #define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */ 4253 4254 /******************************************************************************/ 4255 /* */ 4256 /* Flexible Datarate Controller Area Network */ 4257 /* */ 4258 /******************************************************************************/ 4259 /*!<FDCAN control and status registers */ 4260 /***************** Bit definition for FDCAN_CREL register *******************/ 4261 #define FDCAN_CREL_DAY_Pos (0U) 4262 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */ 4263 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */ 4264 #define FDCAN_CREL_MON_Pos (8U) 4265 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */ 4266 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */ 4267 #define FDCAN_CREL_YEAR_Pos (16U) 4268 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */ 4269 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */ 4270 #define FDCAN_CREL_SUBSTEP_Pos (20U) 4271 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */ 4272 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */ 4273 #define FDCAN_CREL_STEP_Pos (24U) 4274 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */ 4275 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */ 4276 #define FDCAN_CREL_REL_Pos (28U) 4277 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */ 4278 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */ 4279 4280 /***************** Bit definition for FDCAN_ENDN register *******************/ 4281 #define FDCAN_ENDN_ETV_Pos (0U) 4282 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ 4283 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */ 4284 4285 /***************** Bit definition for FDCAN_DBTP register *******************/ 4286 #define FDCAN_DBTP_DSJW_Pos (0U) 4287 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */ 4288 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */ 4289 #define FDCAN_DBTP_DTSEG2_Pos (4U) 4290 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */ 4291 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */ 4292 #define FDCAN_DBTP_DTSEG1_Pos (8U) 4293 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */ 4294 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */ 4295 #define FDCAN_DBTP_DBRP_Pos (16U) 4296 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */ 4297 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */ 4298 #define FDCAN_DBTP_TDC_Pos (23U) 4299 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */ 4300 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */ 4301 4302 /***************** Bit definition for FDCAN_TEST register *******************/ 4303 #define FDCAN_TEST_LBCK_Pos (4U) 4304 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */ 4305 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */ 4306 #define FDCAN_TEST_TX_Pos (5U) 4307 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */ 4308 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */ 4309 #define FDCAN_TEST_RX_Pos (7U) 4310 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */ 4311 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */ 4312 4313 /***************** Bit definition for FDCAN_RWD register ********************/ 4314 #define FDCAN_RWD_WDC_Pos (0U) 4315 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */ 4316 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */ 4317 #define FDCAN_RWD_WDV_Pos (8U) 4318 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */ 4319 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */ 4320 4321 /***************** Bit definition for FDCAN_CCCR register ********************/ 4322 #define FDCAN_CCCR_INIT_Pos (0U) 4323 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */ 4324 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */ 4325 #define FDCAN_CCCR_CCE_Pos (1U) 4326 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */ 4327 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */ 4328 #define FDCAN_CCCR_ASM_Pos (2U) 4329 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */ 4330 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */ 4331 #define FDCAN_CCCR_CSA_Pos (3U) 4332 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */ 4333 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */ 4334 #define FDCAN_CCCR_CSR_Pos (4U) 4335 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */ 4336 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */ 4337 #define FDCAN_CCCR_MON_Pos (5U) 4338 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */ 4339 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */ 4340 #define FDCAN_CCCR_DAR_Pos (6U) 4341 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */ 4342 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */ 4343 #define FDCAN_CCCR_TEST_Pos (7U) 4344 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */ 4345 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */ 4346 #define FDCAN_CCCR_FDOE_Pos (8U) 4347 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */ 4348 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */ 4349 #define FDCAN_CCCR_BRSE_Pos (9U) 4350 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */ 4351 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */ 4352 #define FDCAN_CCCR_PXHD_Pos (12U) 4353 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */ 4354 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */ 4355 #define FDCAN_CCCR_EFBI_Pos (13U) 4356 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */ 4357 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */ 4358 #define FDCAN_CCCR_TXP_Pos (14U) 4359 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */ 4360 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */ 4361 #define FDCAN_CCCR_NISO_Pos (15U) 4362 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */ 4363 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */ 4364 4365 /***************** Bit definition for FDCAN_NBTP register ********************/ 4366 #define FDCAN_NBTP_NTSEG2_Pos (0U) 4367 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */ 4368 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */ 4369 #define FDCAN_NBTP_NTSEG1_Pos (8U) 4370 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */ 4371 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */ 4372 #define FDCAN_NBTP_NBRP_Pos (16U) 4373 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */ 4374 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */ 4375 #define FDCAN_NBTP_NSJW_Pos (25U) 4376 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */ 4377 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */ 4378 4379 /***************** Bit definition for FDCAN_TSCC register ********************/ 4380 #define FDCAN_TSCC_TSS_Pos (0U) 4381 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */ 4382 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */ 4383 #define FDCAN_TSCC_TCP_Pos (16U) 4384 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */ 4385 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */ 4386 4387 /***************** Bit definition for FDCAN_TSCV register ********************/ 4388 #define FDCAN_TSCV_TSC_Pos (0U) 4389 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */ 4390 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */ 4391 4392 /***************** Bit definition for FDCAN_TOCC register ********************/ 4393 #define FDCAN_TOCC_ETOC_Pos (0U) 4394 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */ 4395 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */ 4396 #define FDCAN_TOCC_TOS_Pos (1U) 4397 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */ 4398 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */ 4399 #define FDCAN_TOCC_TOP_Pos (16U) 4400 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */ 4401 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */ 4402 4403 /***************** Bit definition for FDCAN_TOCV register ********************/ 4404 #define FDCAN_TOCV_TOC_Pos (0U) 4405 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */ 4406 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */ 4407 4408 /***************** Bit definition for FDCAN_ECR register *********************/ 4409 #define FDCAN_ECR_TEC_Pos (0U) 4410 #define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */ 4411 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */ 4412 #define FDCAN_ECR_REC_Pos (8U) 4413 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */ 4414 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */ 4415 #define FDCAN_ECR_RP_Pos (15U) 4416 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */ 4417 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */ 4418 #define FDCAN_ECR_CEL_Pos (16U) 4419 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */ 4420 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */ 4421 4422 /***************** Bit definition for FDCAN_PSR register *********************/ 4423 #define FDCAN_PSR_LEC_Pos (0U) 4424 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */ 4425 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */ 4426 #define FDCAN_PSR_ACT_Pos (3U) 4427 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */ 4428 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */ 4429 #define FDCAN_PSR_EP_Pos (5U) 4430 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */ 4431 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */ 4432 #define FDCAN_PSR_EW_Pos (6U) 4433 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */ 4434 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */ 4435 #define FDCAN_PSR_BO_Pos (7U) 4436 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */ 4437 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */ 4438 #define FDCAN_PSR_DLEC_Pos (8U) 4439 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */ 4440 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */ 4441 #define FDCAN_PSR_RESI_Pos (11U) 4442 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */ 4443 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */ 4444 #define FDCAN_PSR_RBRS_Pos (12U) 4445 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */ 4446 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */ 4447 #define FDCAN_PSR_REDL_Pos (13U) 4448 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */ 4449 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */ 4450 #define FDCAN_PSR_PXE_Pos (14U) 4451 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */ 4452 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */ 4453 #define FDCAN_PSR_TDCV_Pos (16U) 4454 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */ 4455 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */ 4456 4457 /***************** Bit definition for FDCAN_TDCR register ********************/ 4458 #define FDCAN_TDCR_TDCF_Pos (0U) 4459 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */ 4460 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */ 4461 #define FDCAN_TDCR_TDCO_Pos (8U) 4462 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */ 4463 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */ 4464 4465 /***************** Bit definition for FDCAN_IR register **********************/ 4466 #define FDCAN_IR_RF0N_Pos (0U) 4467 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */ 4468 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */ 4469 #define FDCAN_IR_RF0F_Pos (1U) 4470 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */ 4471 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */ 4472 #define FDCAN_IR_RF0L_Pos (2U) 4473 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */ 4474 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */ 4475 #define FDCAN_IR_RF1N_Pos (3U) 4476 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */ 4477 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */ 4478 #define FDCAN_IR_RF1F_Pos (4U) 4479 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */ 4480 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */ 4481 #define FDCAN_IR_RF1L_Pos (5U) 4482 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */ 4483 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */ 4484 #define FDCAN_IR_HPM_Pos (6U) 4485 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */ 4486 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */ 4487 #define FDCAN_IR_TC_Pos (7U) 4488 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */ 4489 #define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */ 4490 #define FDCAN_IR_TCF_Pos (8U) 4491 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */ 4492 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */ 4493 #define FDCAN_IR_TFE_Pos (9U) 4494 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */ 4495 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */ 4496 #define FDCAN_IR_TEFN_Pos (10U) 4497 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */ 4498 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */ 4499 #define FDCAN_IR_TEFF_Pos (11U) 4500 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */ 4501 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */ 4502 #define FDCAN_IR_TEFL_Pos (12U) 4503 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */ 4504 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */ 4505 #define FDCAN_IR_TSW_Pos (13U) 4506 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */ 4507 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */ 4508 #define FDCAN_IR_MRAF_Pos (14U) 4509 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */ 4510 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */ 4511 #define FDCAN_IR_TOO_Pos (15U) 4512 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */ 4513 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */ 4514 #define FDCAN_IR_ELO_Pos (16U) 4515 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */ 4516 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */ 4517 #define FDCAN_IR_EP_Pos (17U) 4518 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */ 4519 #define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */ 4520 #define FDCAN_IR_EW_Pos (18U) 4521 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */ 4522 #define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */ 4523 #define FDCAN_IR_BO_Pos (19U) 4524 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */ 4525 #define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */ 4526 #define FDCAN_IR_WDI_Pos (20U) 4527 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */ 4528 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */ 4529 #define FDCAN_IR_PEA_Pos (21U) 4530 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */ 4531 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */ 4532 #define FDCAN_IR_PED_Pos (22U) 4533 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */ 4534 #define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */ 4535 #define FDCAN_IR_ARA_Pos (23U) 4536 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */ 4537 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */ 4538 4539 /***************** Bit definition for FDCAN_IE register **********************/ 4540 #define FDCAN_IE_RF0NE_Pos (0U) 4541 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */ 4542 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */ 4543 #define FDCAN_IE_RF0FE_Pos (1U) 4544 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */ 4545 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */ 4546 #define FDCAN_IE_RF0LE_Pos (2U) 4547 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */ 4548 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */ 4549 #define FDCAN_IE_RF1NE_Pos (3U) 4550 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */ 4551 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */ 4552 #define FDCAN_IE_RF1FE_Pos (4U) 4553 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */ 4554 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */ 4555 #define FDCAN_IE_RF1LE_Pos (5U) 4556 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */ 4557 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */ 4558 #define FDCAN_IE_HPME_Pos (6U) 4559 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */ 4560 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */ 4561 #define FDCAN_IE_TCE_Pos (7U) 4562 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */ 4563 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */ 4564 #define FDCAN_IE_TCFE_Pos (8U) 4565 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */ 4566 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/ 4567 #define FDCAN_IE_TFEE_Pos (9U) 4568 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */ 4569 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */ 4570 #define FDCAN_IE_TEFNE_Pos (10U) 4571 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */ 4572 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */ 4573 #define FDCAN_IE_TEFFE_Pos (11U) 4574 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */ 4575 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */ 4576 #define FDCAN_IE_TEFLE_Pos (12U) 4577 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */ 4578 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */ 4579 #define FDCAN_IE_TSWE_Pos (13U) 4580 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */ 4581 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */ 4582 #define FDCAN_IE_MRAFE_Pos (14U) 4583 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */ 4584 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */ 4585 #define FDCAN_IE_TOOE_Pos (15U) 4586 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */ 4587 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */ 4588 #define FDCAN_IE_ELOE_Pos (16U) 4589 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */ 4590 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */ 4591 #define FDCAN_IE_EPE_Pos (17U) 4592 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */ 4593 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */ 4594 #define FDCAN_IE_EWE_Pos (18U) 4595 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */ 4596 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */ 4597 #define FDCAN_IE_BOE_Pos (19U) 4598 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */ 4599 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */ 4600 #define FDCAN_IE_WDIE_Pos (20U) 4601 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */ 4602 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */ 4603 #define FDCAN_IE_PEAE_Pos (21U) 4604 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */ 4605 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/ 4606 #define FDCAN_IE_PEDE_Pos (22U) 4607 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */ 4608 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */ 4609 #define FDCAN_IE_ARAE_Pos (23U) 4610 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */ 4611 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */ 4612 4613 /***************** Bit definition for FDCAN_ILS register **********************/ 4614 #define FDCAN_ILS_RXFIFO0_Pos (0U) 4615 #define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */ 4616 #define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost 4617 Rx FIFO 0 is Full 4618 Rx FIFO 0 Has New Message */ 4619 #define FDCAN_ILS_RXFIFO1_Pos (1U) 4620 #define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */ 4621 #define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost 4622 Rx FIFO 1 is Full 4623 Rx FIFO 1 Has New Message */ 4624 #define FDCAN_ILS_SMSG_Pos (2U) 4625 #define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */ 4626 #define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished 4627 Transmission Completed 4628 High Priority Message */ 4629 #define FDCAN_ILS_TFERR_Pos (3U) 4630 #define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */ 4631 #define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost 4632 Tx Event FIFO Full 4633 Tx Event FIFO New Entry 4634 Tx FIFO Empty Interrupt Line */ 4635 #define FDCAN_ILS_MISC_Pos (4U) 4636 #define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */ 4637 #define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred 4638 Message RAM Access Failure 4639 Timestamp Wraparound */ 4640 #define FDCAN_ILS_BERR_Pos (5U) 4641 #define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */ 4642 #define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive 4643 Error Logging Overflow */ 4644 #define FDCAN_ILS_PERR_Pos (6U) 4645 #define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */ 4646 #define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line 4647 Protocol Error in Data Phase Line 4648 Protocol Error in Arbitration Phase Line 4649 Watchdog Interrupt Line 4650 Bus_Off Status 4651 Warning Status */ 4652 4653 /***************** Bit definition for FDCAN_ILE register **********************/ 4654 #define FDCAN_ILE_EINT0_Pos (0U) 4655 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */ 4656 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */ 4657 #define FDCAN_ILE_EINT1_Pos (1U) 4658 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */ 4659 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */ 4660 4661 /***************** Bit definition for FDCAN_RXGFC register ********************/ 4662 #define FDCAN_RXGFC_RRFE_Pos (0U) 4663 #define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */ 4664 #define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */ 4665 #define FDCAN_RXGFC_RRFS_Pos (1U) 4666 #define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */ 4667 #define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */ 4668 #define FDCAN_RXGFC_ANFE_Pos (2U) 4669 #define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */ 4670 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */ 4671 #define FDCAN_RXGFC_ANFS_Pos (4U) 4672 #define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */ 4673 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */ 4674 #define FDCAN_RXGFC_F1OM_Pos (8U) 4675 #define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */ 4676 #define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */ 4677 #define FDCAN_RXGFC_F0OM_Pos (9U) 4678 #define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */ 4679 #define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */ 4680 #define FDCAN_RXGFC_LSS_Pos (16U) 4681 #define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */ 4682 #define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */ 4683 #define FDCAN_RXGFC_LSE_Pos (24U) 4684 #define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */ 4685 #define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */ 4686 4687 /***************** Bit definition for FDCAN_XIDAM register ********************/ 4688 #define FDCAN_XIDAM_EIDM_Pos (0U) 4689 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */ 4690 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */ 4691 4692 /***************** Bit definition for FDCAN_HPMS register *********************/ 4693 #define FDCAN_HPMS_BIDX_Pos (0U) 4694 #define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */ 4695 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */ 4696 #define FDCAN_HPMS_MSI_Pos (6U) 4697 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */ 4698 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */ 4699 #define FDCAN_HPMS_FIDX_Pos (8U) 4700 #define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */ 4701 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */ 4702 #define FDCAN_HPMS_FLST_Pos (15U) 4703 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */ 4704 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */ 4705 4706 /***************** Bit definition for FDCAN_RXF0S register ********************/ 4707 #define FDCAN_RXF0S_F0FL_Pos (0U) 4708 #define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */ 4709 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */ 4710 #define FDCAN_RXF0S_F0GI_Pos (8U) 4711 #define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */ 4712 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */ 4713 #define FDCAN_RXF0S_F0PI_Pos (16U) 4714 #define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */ 4715 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */ 4716 #define FDCAN_RXF0S_F0F_Pos (24U) 4717 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */ 4718 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */ 4719 #define FDCAN_RXF0S_RF0L_Pos (25U) 4720 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */ 4721 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */ 4722 4723 /***************** Bit definition for FDCAN_RXF0A register ********************/ 4724 #define FDCAN_RXF0A_F0AI_Pos (0U) 4725 #define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */ 4726 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */ 4727 4728 /***************** Bit definition for FDCAN_RXF1S register ********************/ 4729 #define FDCAN_RXF1S_F1FL_Pos (0U) 4730 #define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */ 4731 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */ 4732 #define FDCAN_RXF1S_F1GI_Pos (8U) 4733 #define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */ 4734 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */ 4735 #define FDCAN_RXF1S_F1PI_Pos (16U) 4736 #define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */ 4737 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */ 4738 #define FDCAN_RXF1S_F1F_Pos (24U) 4739 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */ 4740 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */ 4741 #define FDCAN_RXF1S_RF1L_Pos (25U) 4742 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */ 4743 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */ 4744 4745 /***************** Bit definition for FDCAN_RXF1A register ********************/ 4746 #define FDCAN_RXF1A_F1AI_Pos (0U) 4747 #define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */ 4748 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */ 4749 4750 /***************** Bit definition for FDCAN_TXBC register *********************/ 4751 #define FDCAN_TXBC_TFQM_Pos (24U) 4752 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */ 4753 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */ 4754 4755 /***************** Bit definition for FDCAN_TXFQS register *********************/ 4756 #define FDCAN_TXFQS_TFFL_Pos (0U) 4757 #define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */ 4758 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */ 4759 #define FDCAN_TXFQS_TFGI_Pos (8U) 4760 #define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */ 4761 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */ 4762 #define FDCAN_TXFQS_TFQPI_Pos (16U) 4763 #define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */ 4764 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */ 4765 #define FDCAN_TXFQS_TFQF_Pos (21U) 4766 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */ 4767 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */ 4768 4769 /***************** Bit definition for FDCAN_TXBRP register *********************/ 4770 #define FDCAN_TXBRP_TRP_Pos (0U) 4771 #define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */ 4772 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */ 4773 4774 /***************** Bit definition for FDCAN_TXBAR register *********************/ 4775 #define FDCAN_TXBAR_AR_Pos (0U) 4776 #define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */ 4777 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */ 4778 4779 /***************** Bit definition for FDCAN_TXBCR register *********************/ 4780 #define FDCAN_TXBCR_CR_Pos (0U) 4781 #define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */ 4782 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */ 4783 4784 /***************** Bit definition for FDCAN_TXBTO register *********************/ 4785 #define FDCAN_TXBTO_TO_Pos (0U) 4786 #define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */ 4787 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */ 4788 4789 /***************** Bit definition for FDCAN_TXBCF register *********************/ 4790 #define FDCAN_TXBCF_CF_Pos (0U) 4791 #define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */ 4792 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */ 4793 4794 /***************** Bit definition for FDCAN_TXBTIE register ********************/ 4795 #define FDCAN_TXBTIE_TIE_Pos (0U) 4796 #define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */ 4797 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */ 4798 4799 /***************** Bit definition for FDCAN_ TXBCIE register *******************/ 4800 #define FDCAN_TXBCIE_CFIE_Pos (0U) 4801 #define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */ 4802 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */ 4803 4804 /***************** Bit definition for FDCAN_TXEFS register *********************/ 4805 #define FDCAN_TXEFS_EFFL_Pos (0U) 4806 #define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */ 4807 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */ 4808 #define FDCAN_TXEFS_EFGI_Pos (8U) 4809 #define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */ 4810 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */ 4811 #define FDCAN_TXEFS_EFPI_Pos (16U) 4812 #define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */ 4813 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */ 4814 #define FDCAN_TXEFS_EFF_Pos (24U) 4815 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */ 4816 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */ 4817 #define FDCAN_TXEFS_TEFL_Pos (25U) 4818 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */ 4819 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */ 4820 4821 /***************** Bit definition for FDCAN_TXEFA register *********************/ 4822 #define FDCAN_TXEFA_EFAI_Pos (0U) 4823 #define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */ 4824 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */ 4825 4826 4827 /*!<FDCAN config registers */ 4828 /***************** Bit definition for FDCAN_CKDIV register *********************/ 4829 #define FDCAN_CKDIV_PDIV_Pos (0U) 4830 #define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */ 4831 #define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */ 4832 4833 /******************************************************************************/ 4834 /* */ 4835 /* FLASH */ 4836 /* */ 4837 /******************************************************************************/ 4838 /******************* Bits definition for FLASH_ACR register *****************/ 4839 #define FLASH_ACR_LATENCY_Pos (0U) 4840 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ 4841 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk 4842 #define FLASH_ACR_LATENCY_0WS (0x00000000U) 4843 #define FLASH_ACR_LATENCY_1WS (0x00000001U) 4844 #define FLASH_ACR_LATENCY_2WS (0x00000002U) 4845 #define FLASH_ACR_LATENCY_3WS (0x00000003U) 4846 #define FLASH_ACR_LATENCY_4WS (0x00000004U) 4847 #define FLASH_ACR_LATENCY_5WS (0x00000005U) 4848 #define FLASH_ACR_LATENCY_6WS (0x00000006U) 4849 #define FLASH_ACR_LATENCY_7WS (0x00000007U) 4850 #define FLASH_ACR_LATENCY_8WS (0x00000008U) 4851 #define FLASH_ACR_LATENCY_9WS (0x00000009U) 4852 #define FLASH_ACR_LATENCY_10WS (0x0000000AU) 4853 #define FLASH_ACR_LATENCY_11WS (0x0000000BU) 4854 #define FLASH_ACR_LATENCY_12WS (0x0000000CU) 4855 #define FLASH_ACR_LATENCY_13WS (0x0000000DU) 4856 #define FLASH_ACR_LATENCY_14WS (0x0000000EU) 4857 #define FLASH_ACR_LATENCY_15WS (0x0000000FU) 4858 #define FLASH_ACR_PRFTEN_Pos (8U) 4859 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ 4860 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk 4861 #define FLASH_ACR_ICEN_Pos (9U) 4862 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ 4863 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk 4864 #define FLASH_ACR_DCEN_Pos (10U) 4865 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ 4866 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk 4867 #define FLASH_ACR_ICRST_Pos (11U) 4868 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ 4869 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk 4870 #define FLASH_ACR_DCRST_Pos (12U) 4871 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ 4872 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk 4873 #define FLASH_ACR_RUN_PD_Pos (13U) 4874 #define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */ 4875 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */ 4876 #define FLASH_ACR_SLEEP_PD_Pos (14U) 4877 #define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ 4878 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */ 4879 #define FLASH_ACR_DBG_SWEN_Pos (18U) 4880 #define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */ 4881 #define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */ 4882 4883 /******************* Bits definition for FLASH_SR register ******************/ 4884 #define FLASH_SR_EOP_Pos (0U) 4885 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ 4886 #define FLASH_SR_EOP FLASH_SR_EOP_Msk 4887 #define FLASH_SR_OPERR_Pos (1U) 4888 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ 4889 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk 4890 #define FLASH_SR_PROGERR_Pos (3U) 4891 #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ 4892 #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk 4893 #define FLASH_SR_WRPERR_Pos (4U) 4894 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ 4895 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk 4896 #define FLASH_SR_PGAERR_Pos (5U) 4897 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ 4898 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk 4899 #define FLASH_SR_SIZERR_Pos (6U) 4900 #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ 4901 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk 4902 #define FLASH_SR_PGSERR_Pos (7U) 4903 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ 4904 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk 4905 #define FLASH_SR_MISERR_Pos (8U) 4906 #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ 4907 #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk 4908 #define FLASH_SR_FASTERR_Pos (9U) 4909 #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ 4910 #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk 4911 #define FLASH_SR_RDERR_Pos (14U) 4912 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ 4913 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk 4914 #define FLASH_SR_OPTVERR_Pos (15U) 4915 #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ 4916 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk 4917 #define FLASH_SR_BSY_Pos (16U) 4918 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ 4919 #define FLASH_SR_BSY FLASH_SR_BSY_Msk 4920 4921 /******************* Bits definition for FLASH_CR register ******************/ 4922 #define FLASH_CR_PG_Pos (0U) 4923 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 4924 #define FLASH_CR_PG FLASH_CR_PG_Msk 4925 #define FLASH_CR_PER_Pos (1U) 4926 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 4927 #define FLASH_CR_PER FLASH_CR_PER_Msk 4928 #define FLASH_CR_MER1_Pos (2U) 4929 #define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ 4930 #define FLASH_CR_MER1 FLASH_CR_MER1_Msk 4931 #define FLASH_CR_PNB_Pos (3U) 4932 #define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */ 4933 #define FLASH_CR_PNB FLASH_CR_PNB_Msk 4934 #define FLASH_CR_STRT_Pos (16U) 4935 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ 4936 #define FLASH_CR_STRT FLASH_CR_STRT_Msk 4937 #define FLASH_CR_OPTSTRT_Pos (17U) 4938 #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ 4939 #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk 4940 #define FLASH_CR_FSTPG_Pos (18U) 4941 #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ 4942 #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk 4943 #define FLASH_CR_EOPIE_Pos (24U) 4944 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ 4945 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk 4946 #define FLASH_CR_ERRIE_Pos (25U) 4947 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ 4948 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk 4949 #define FLASH_CR_RDERRIE_Pos (26U) 4950 #define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ 4951 #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk 4952 #define FLASH_CR_OBL_LAUNCH_Pos (27U) 4953 #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ 4954 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk 4955 #define FLASH_CR_SEC_PROT1_Pos (28U) 4956 #define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */ 4957 #define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk 4958 #define FLASH_CR_OPTLOCK_Pos (30U) 4959 #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ 4960 #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk 4961 #define FLASH_CR_LOCK_Pos (31U) 4962 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ 4963 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk 4964 4965 /******************* Bits definition for FLASH_ECCR register ***************/ 4966 #define FLASH_ECCR_ADDR_ECC_Pos (0U) 4967 #define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0003FFFF */ 4968 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk 4969 #define FLASH_ECCR_SYSF_ECC_Pos (22U) 4970 #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ 4971 #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk 4972 #define FLASH_ECCR_ECCIE_Pos (24U) 4973 #define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ 4974 #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk 4975 #define FLASH_ECCR_ECCC_Pos (30U) 4976 #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ 4977 #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk 4978 #define FLASH_ECCR_ECCD_Pos (31U) 4979 #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ 4980 #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk 4981 4982 /******************* Bits definition for FLASH_OPTR register ***************/ 4983 #define FLASH_OPTR_RDP_Pos (0U) 4984 #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ 4985 #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk 4986 #define FLASH_OPTR_BOR_LEV_Pos (8U) 4987 #define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ 4988 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk 4989 #define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */ 4990 #define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ 4991 #define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ 4992 #define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */ 4993 #define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ 4994 #define FLASH_OPTR_nRST_STOP_Pos (12U) 4995 #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ 4996 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk 4997 #define FLASH_OPTR_nRST_STDBY_Pos (13U) 4998 #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ 4999 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk 5000 #define FLASH_OPTR_nRST_SHDW_Pos (14U) 5001 #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ 5002 #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk 5003 #define FLASH_OPTR_IWDG_SW_Pos (16U) 5004 #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ 5005 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk 5006 #define FLASH_OPTR_IWDG_STOP_Pos (17U) 5007 #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ 5008 #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk 5009 #define FLASH_OPTR_IWDG_STDBY_Pos (18U) 5010 #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ 5011 #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk 5012 #define FLASH_OPTR_WWDG_SW_Pos (19U) 5013 #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ 5014 #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk 5015 #define FLASH_OPTR_nBOOT1_Pos (23U) 5016 #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ 5017 #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk 5018 #define FLASH_OPTR_SRAM_PE_Pos (24U) 5019 #define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */ 5020 #define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk 5021 #define FLASH_OPTR_CCMSRAM_RST_Pos (25U) 5022 #define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */ 5023 #define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk 5024 #define FLASH_OPTR_nSWBOOT0_Pos (26U) 5025 #define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ 5026 #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk 5027 #define FLASH_OPTR_nBOOT0_Pos (27U) 5028 #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ 5029 #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk 5030 #define FLASH_OPTR_NRST_MODE_Pos (28U) 5031 #define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */ 5032 #define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk 5033 #define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ 5034 #define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */ 5035 #define FLASH_OPTR_IRHEN_Pos (30U) 5036 #define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */ 5037 #define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk 5038 5039 /****************** Bits definition for FLASH_PCROP1SR register **********/ 5040 #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U) 5041 #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00003FFF */ 5042 #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk 5043 5044 /****************** Bits definition for FLASH_PCROP1ER register ***********/ 5045 #define FLASH_PCROP1ER_PCROP1_END_Pos (0U) 5046 #define FLASH_PCROP1ER_PCROP1_END_Msk (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00003FFF */ 5047 #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk 5048 #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U) 5049 #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */ 5050 #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk 5051 5052 /****************** Bits definition for FLASH_WRP1AR register ***************/ 5053 #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) 5054 #define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000003F */ 5055 #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk 5056 #define FLASH_WRP1AR_WRP1A_END_Pos (16U) 5057 #define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x003F0000 */ 5058 #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk 5059 5060 /****************** Bits definition for FLASH_WRPB1R register ***************/ 5061 #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) 5062 #define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000003F */ 5063 #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk 5064 #define FLASH_WRP1BR_WRP1B_END_Pos (16U) 5065 #define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x003F0000 */ 5066 #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk 5067 5068 5069 /****************** Bits definition for FLASH_SEC1R register **************/ 5070 #define FLASH_SEC1R_SEC_SIZE1_Pos (0U) 5071 #define FLASH_SEC1R_SEC_SIZE1_Msk (0x7FUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x0000007F */ 5072 #define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk 5073 #define FLASH_SEC1R_BOOT_LOCK_Pos (16U) 5074 #define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */ 5075 #define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk 5076 5077 5078 /******************************************************************************/ 5079 /* */ 5080 /* Filter Mathematical ACcelerator unit (FMAC) */ 5081 /* */ 5082 /******************************************************************************/ 5083 /***************** Bit definition for FMAC_X1BUFCFG register ****************/ 5084 #define FMAC_X1BUFCFG_X1_BASE_Pos (0U) 5085 #define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ 5086 #define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ 5087 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) 5088 #define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */ 5089 #define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ 5090 #define FMAC_X1BUFCFG_FULL_WM_Pos (24U) 5091 #define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ 5092 #define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ 5093 /***************** Bit definition for FMAC_X2BUFCFG register ****************/ 5094 #define FMAC_X2BUFCFG_X2_BASE_Pos (0U) 5095 #define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ 5096 #define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ 5097 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) 5098 #define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */ 5099 #define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ 5100 /***************** Bit definition for FMAC_YBUFCFG register *****************/ 5101 #define FMAC_YBUFCFG_Y_BASE_Pos (0U) 5102 #define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ 5103 #define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ 5104 #define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) 5105 #define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ 5106 #define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ 5107 #define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) 5108 #define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ 5109 #define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ 5110 /****************** Bit definition for FMAC_PARAM register ******************/ 5111 #define FMAC_PARAM_P_Pos (0U) 5112 #define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ 5113 #define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ 5114 #define FMAC_PARAM_Q_Pos (8U) 5115 #define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ 5116 #define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ 5117 #define FMAC_PARAM_R_Pos (16U) 5118 #define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ 5119 #define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ 5120 #define FMAC_PARAM_FUNC_Pos (24U) 5121 #define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ 5122 #define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ 5123 #define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ 5124 #define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ 5125 #define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ 5126 #define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ 5127 #define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ 5128 #define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ 5129 #define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ 5130 #define FMAC_PARAM_START_Pos (31U) 5131 #define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ 5132 #define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ 5133 /******************** Bit definition for FMAC_CR register *******************/ 5134 #define FMAC_CR_RIEN_Pos (0U) 5135 #define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ 5136 #define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ 5137 #define FMAC_CR_WIEN_Pos (1U) 5138 #define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ 5139 #define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ 5140 #define FMAC_CR_OVFLIEN_Pos (2U) 5141 #define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ 5142 #define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ 5143 #define FMAC_CR_UNFLIEN_Pos (3U) 5144 #define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ 5145 #define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ 5146 #define FMAC_CR_SATIEN_Pos (4U) 5147 #define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ 5148 #define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ 5149 #define FMAC_CR_DMAREN_Pos (8U) 5150 #define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ 5151 #define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ 5152 #define FMAC_CR_DMAWEN_Pos (9U) 5153 #define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ 5154 #define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ 5155 #define FMAC_CR_CLIPEN_Pos (15U) 5156 #define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ 5157 #define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ 5158 #define FMAC_CR_RESET_Pos (16U) 5159 #define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ 5160 #define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ 5161 /******************* Bit definition for FMAC_SR register ********************/ 5162 #define FMAC_SR_YEMPTY_Pos (0U) 5163 #define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ 5164 #define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ 5165 #define FMAC_SR_X1FULL_Pos (1U) 5166 #define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ 5167 #define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ 5168 #define FMAC_SR_OVFL_Pos (8U) 5169 #define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ 5170 #define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ 5171 #define FMAC_SR_UNFL_Pos (9U) 5172 #define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ 5173 #define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ 5174 #define FMAC_SR_SAT_Pos (10U) 5175 #define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ 5176 #define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ 5177 /****************** Bit definition for FMAC_WDATA register ******************/ 5178 #define FMAC_WDATA_WDATA_Pos (0U) 5179 #define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ 5180 #define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ 5181 /****************** Bit definition for FMACX_RDATA register *****************/ 5182 #define FMAC_RDATA_RDATA_Pos (0U) 5183 #define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ 5184 #define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ 5185 5186 5187 /******************************************************************************/ 5188 /* */ 5189 /* General Purpose IOs (GPIO) */ 5190 /* */ 5191 /******************************************************************************/ 5192 /****************** Bits definition for GPIO_MODER register *****************/ 5193 #define GPIO_MODER_MODE0_Pos (0U) 5194 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ 5195 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk 5196 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ 5197 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ 5198 #define GPIO_MODER_MODE1_Pos (2U) 5199 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ 5200 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk 5201 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ 5202 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ 5203 #define GPIO_MODER_MODE2_Pos (4U) 5204 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ 5205 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk 5206 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ 5207 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ 5208 #define GPIO_MODER_MODE3_Pos (6U) 5209 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ 5210 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk 5211 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ 5212 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ 5213 #define GPIO_MODER_MODE4_Pos (8U) 5214 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ 5215 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk 5216 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ 5217 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ 5218 #define GPIO_MODER_MODE5_Pos (10U) 5219 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ 5220 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk 5221 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ 5222 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ 5223 #define GPIO_MODER_MODE6_Pos (12U) 5224 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ 5225 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk 5226 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ 5227 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ 5228 #define GPIO_MODER_MODE7_Pos (14U) 5229 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ 5230 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk 5231 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ 5232 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ 5233 #define GPIO_MODER_MODE8_Pos (16U) 5234 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ 5235 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk 5236 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ 5237 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ 5238 #define GPIO_MODER_MODE9_Pos (18U) 5239 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ 5240 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk 5241 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ 5242 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ 5243 #define GPIO_MODER_MODE10_Pos (20U) 5244 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ 5245 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk 5246 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ 5247 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ 5248 #define GPIO_MODER_MODE11_Pos (22U) 5249 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ 5250 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk 5251 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ 5252 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ 5253 #define GPIO_MODER_MODE12_Pos (24U) 5254 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ 5255 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk 5256 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ 5257 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ 5258 #define GPIO_MODER_MODE13_Pos (26U) 5259 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ 5260 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk 5261 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ 5262 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ 5263 #define GPIO_MODER_MODE14_Pos (28U) 5264 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ 5265 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk 5266 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ 5267 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ 5268 #define GPIO_MODER_MODE15_Pos (30U) 5269 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ 5270 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk 5271 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ 5272 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ 5273 5274 /* Legacy defines */ 5275 #define GPIO_MODER_MODER0 GPIO_MODER_MODE0 5276 #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0 5277 #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1 5278 #define GPIO_MODER_MODER1 GPIO_MODER_MODE1 5279 #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0 5280 #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1 5281 #define GPIO_MODER_MODER2 GPIO_MODER_MODE2 5282 #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0 5283 #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1 5284 #define GPIO_MODER_MODER3 GPIO_MODER_MODE3 5285 #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0 5286 #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1 5287 #define GPIO_MODER_MODER4 GPIO_MODER_MODE4 5288 #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0 5289 #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1 5290 #define GPIO_MODER_MODER5 GPIO_MODER_MODE5 5291 #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0 5292 #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1 5293 #define GPIO_MODER_MODER6 GPIO_MODER_MODE6 5294 #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0 5295 #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1 5296 #define GPIO_MODER_MODER7 GPIO_MODER_MODE7 5297 #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0 5298 #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1 5299 #define GPIO_MODER_MODER8 GPIO_MODER_MODE8 5300 #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0 5301 #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1 5302 #define GPIO_MODER_MODER9 GPIO_MODER_MODE9 5303 #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0 5304 #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1 5305 #define GPIO_MODER_MODER10 GPIO_MODER_MODE10 5306 #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0 5307 #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1 5308 #define GPIO_MODER_MODER11 GPIO_MODER_MODE11 5309 #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0 5310 #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1 5311 #define GPIO_MODER_MODER12 GPIO_MODER_MODE12 5312 #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0 5313 #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1 5314 #define GPIO_MODER_MODER13 GPIO_MODER_MODE13 5315 #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0 5316 #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1 5317 #define GPIO_MODER_MODER14 GPIO_MODER_MODE14 5318 #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0 5319 #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1 5320 #define GPIO_MODER_MODER15 GPIO_MODER_MODE15 5321 #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0 5322 #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1 5323 5324 /****************** Bits definition for GPIO_OTYPER register ****************/ 5325 #define GPIO_OTYPER_OT0_Pos (0U) 5326 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ 5327 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk 5328 #define GPIO_OTYPER_OT1_Pos (1U) 5329 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ 5330 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk 5331 #define GPIO_OTYPER_OT2_Pos (2U) 5332 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ 5333 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk 5334 #define GPIO_OTYPER_OT3_Pos (3U) 5335 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ 5336 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk 5337 #define GPIO_OTYPER_OT4_Pos (4U) 5338 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ 5339 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk 5340 #define GPIO_OTYPER_OT5_Pos (5U) 5341 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ 5342 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk 5343 #define GPIO_OTYPER_OT6_Pos (6U) 5344 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ 5345 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk 5346 #define GPIO_OTYPER_OT7_Pos (7U) 5347 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ 5348 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk 5349 #define GPIO_OTYPER_OT8_Pos (8U) 5350 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ 5351 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk 5352 #define GPIO_OTYPER_OT9_Pos (9U) 5353 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ 5354 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk 5355 #define GPIO_OTYPER_OT10_Pos (10U) 5356 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ 5357 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk 5358 #define GPIO_OTYPER_OT11_Pos (11U) 5359 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ 5360 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk 5361 #define GPIO_OTYPER_OT12_Pos (12U) 5362 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ 5363 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk 5364 #define GPIO_OTYPER_OT13_Pos (13U) 5365 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ 5366 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk 5367 #define GPIO_OTYPER_OT14_Pos (14U) 5368 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ 5369 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk 5370 #define GPIO_OTYPER_OT15_Pos (15U) 5371 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ 5372 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk 5373 5374 /* Legacy defines */ 5375 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0 5376 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1 5377 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2 5378 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3 5379 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4 5380 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5 5381 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6 5382 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7 5383 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8 5384 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9 5385 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10 5386 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11 5387 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12 5388 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13 5389 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14 5390 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15 5391 5392 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 5393 #define GPIO_OSPEEDR_OSPEED0_Pos (0U) 5394 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ 5395 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk 5396 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ 5397 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ 5398 #define GPIO_OSPEEDR_OSPEED1_Pos (2U) 5399 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ 5400 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk 5401 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ 5402 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ 5403 #define GPIO_OSPEEDR_OSPEED2_Pos (4U) 5404 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ 5405 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk 5406 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ 5407 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ 5408 #define GPIO_OSPEEDR_OSPEED3_Pos (6U) 5409 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ 5410 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk 5411 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ 5412 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ 5413 #define GPIO_OSPEEDR_OSPEED4_Pos (8U) 5414 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ 5415 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk 5416 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ 5417 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ 5418 #define GPIO_OSPEEDR_OSPEED5_Pos (10U) 5419 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ 5420 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk 5421 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ 5422 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ 5423 #define GPIO_OSPEEDR_OSPEED6_Pos (12U) 5424 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ 5425 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk 5426 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ 5427 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ 5428 #define GPIO_OSPEEDR_OSPEED7_Pos (14U) 5429 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ 5430 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk 5431 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ 5432 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ 5433 #define GPIO_OSPEEDR_OSPEED8_Pos (16U) 5434 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ 5435 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk 5436 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ 5437 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ 5438 #define GPIO_OSPEEDR_OSPEED9_Pos (18U) 5439 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ 5440 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk 5441 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ 5442 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ 5443 #define GPIO_OSPEEDR_OSPEED10_Pos (20U) 5444 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ 5445 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk 5446 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ 5447 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ 5448 #define GPIO_OSPEEDR_OSPEED11_Pos (22U) 5449 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ 5450 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk 5451 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ 5452 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ 5453 #define GPIO_OSPEEDR_OSPEED12_Pos (24U) 5454 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ 5455 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk 5456 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ 5457 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ 5458 #define GPIO_OSPEEDR_OSPEED13_Pos (26U) 5459 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ 5460 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk 5461 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ 5462 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ 5463 #define GPIO_OSPEEDR_OSPEED14_Pos (28U) 5464 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ 5465 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk 5466 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ 5467 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ 5468 #define GPIO_OSPEEDR_OSPEED15_Pos (30U) 5469 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ 5470 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk 5471 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ 5472 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ 5473 5474 /* Legacy defines */ 5475 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0 5476 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0 5477 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1 5478 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1 5479 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0 5480 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1 5481 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2 5482 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0 5483 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1 5484 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3 5485 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0 5486 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1 5487 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4 5488 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0 5489 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1 5490 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5 5491 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0 5492 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1 5493 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6 5494 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0 5495 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1 5496 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7 5497 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0 5498 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1 5499 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8 5500 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0 5501 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1 5502 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9 5503 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0 5504 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1 5505 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10 5506 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0 5507 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1 5508 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11 5509 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0 5510 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1 5511 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12 5512 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0 5513 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1 5514 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13 5515 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0 5516 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1 5517 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14 5518 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0 5519 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1 5520 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15 5521 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0 5522 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1 5523 5524 /****************** Bits definition for GPIO_PUPDR register *****************/ 5525 #define GPIO_PUPDR_PUPD0_Pos (0U) 5526 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ 5527 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk 5528 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ 5529 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ 5530 #define GPIO_PUPDR_PUPD1_Pos (2U) 5531 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ 5532 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk 5533 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ 5534 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ 5535 #define GPIO_PUPDR_PUPD2_Pos (4U) 5536 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ 5537 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk 5538 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ 5539 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ 5540 #define GPIO_PUPDR_PUPD3_Pos (6U) 5541 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ 5542 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk 5543 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ 5544 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ 5545 #define GPIO_PUPDR_PUPD4_Pos (8U) 5546 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ 5547 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk 5548 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ 5549 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ 5550 #define GPIO_PUPDR_PUPD5_Pos (10U) 5551 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ 5552 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk 5553 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ 5554 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ 5555 #define GPIO_PUPDR_PUPD6_Pos (12U) 5556 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ 5557 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk 5558 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ 5559 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ 5560 #define GPIO_PUPDR_PUPD7_Pos (14U) 5561 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ 5562 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk 5563 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ 5564 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ 5565 #define GPIO_PUPDR_PUPD8_Pos (16U) 5566 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ 5567 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk 5568 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ 5569 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ 5570 #define GPIO_PUPDR_PUPD9_Pos (18U) 5571 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ 5572 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk 5573 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ 5574 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ 5575 #define GPIO_PUPDR_PUPD10_Pos (20U) 5576 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ 5577 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk 5578 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ 5579 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ 5580 #define GPIO_PUPDR_PUPD11_Pos (22U) 5581 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ 5582 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk 5583 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ 5584 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ 5585 #define GPIO_PUPDR_PUPD12_Pos (24U) 5586 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ 5587 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk 5588 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ 5589 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ 5590 #define GPIO_PUPDR_PUPD13_Pos (26U) 5591 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ 5592 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk 5593 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ 5594 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ 5595 #define GPIO_PUPDR_PUPD14_Pos (28U) 5596 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ 5597 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk 5598 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ 5599 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ 5600 #define GPIO_PUPDR_PUPD15_Pos (30U) 5601 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ 5602 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk 5603 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ 5604 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ 5605 5606 /* Legacy defines */ 5607 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0 5608 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0 5609 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1 5610 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1 5611 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0 5612 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1 5613 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2 5614 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0 5615 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1 5616 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3 5617 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0 5618 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1 5619 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4 5620 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0 5621 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1 5622 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5 5623 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0 5624 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1 5625 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6 5626 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0 5627 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1 5628 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7 5629 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0 5630 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1 5631 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8 5632 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0 5633 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1 5634 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9 5635 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0 5636 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1 5637 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10 5638 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0 5639 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1 5640 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11 5641 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0 5642 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1 5643 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12 5644 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0 5645 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1 5646 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13 5647 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0 5648 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1 5649 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14 5650 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0 5651 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1 5652 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15 5653 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0 5654 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1 5655 5656 /****************** Bits definition for GPIO_IDR register *******************/ 5657 #define GPIO_IDR_ID0_Pos (0U) 5658 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ 5659 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk 5660 #define GPIO_IDR_ID1_Pos (1U) 5661 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ 5662 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk 5663 #define GPIO_IDR_ID2_Pos (2U) 5664 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ 5665 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk 5666 #define GPIO_IDR_ID3_Pos (3U) 5667 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ 5668 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk 5669 #define GPIO_IDR_ID4_Pos (4U) 5670 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ 5671 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk 5672 #define GPIO_IDR_ID5_Pos (5U) 5673 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ 5674 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk 5675 #define GPIO_IDR_ID6_Pos (6U) 5676 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ 5677 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk 5678 #define GPIO_IDR_ID7_Pos (7U) 5679 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ 5680 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk 5681 #define GPIO_IDR_ID8_Pos (8U) 5682 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ 5683 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk 5684 #define GPIO_IDR_ID9_Pos (9U) 5685 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ 5686 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk 5687 #define GPIO_IDR_ID10_Pos (10U) 5688 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ 5689 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk 5690 #define GPIO_IDR_ID11_Pos (11U) 5691 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ 5692 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk 5693 #define GPIO_IDR_ID12_Pos (12U) 5694 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ 5695 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk 5696 #define GPIO_IDR_ID13_Pos (13U) 5697 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ 5698 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk 5699 #define GPIO_IDR_ID14_Pos (14U) 5700 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ 5701 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk 5702 #define GPIO_IDR_ID15_Pos (15U) 5703 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ 5704 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk 5705 5706 /* Legacy defines */ 5707 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0 5708 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1 5709 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2 5710 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3 5711 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4 5712 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5 5713 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6 5714 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7 5715 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8 5716 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9 5717 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10 5718 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11 5719 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12 5720 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13 5721 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14 5722 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15 5723 5724 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */ 5725 #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0 5726 #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1 5727 #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2 5728 #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3 5729 #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4 5730 #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5 5731 #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6 5732 #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7 5733 #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8 5734 #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9 5735 #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10 5736 #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11 5737 #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12 5738 #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13 5739 #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14 5740 #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15 5741 5742 /****************** Bits definition for GPIO_ODR register *******************/ 5743 #define GPIO_ODR_OD0_Pos (0U) 5744 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ 5745 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk 5746 #define GPIO_ODR_OD1_Pos (1U) 5747 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ 5748 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk 5749 #define GPIO_ODR_OD2_Pos (2U) 5750 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ 5751 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk 5752 #define GPIO_ODR_OD3_Pos (3U) 5753 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ 5754 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk 5755 #define GPIO_ODR_OD4_Pos (4U) 5756 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ 5757 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk 5758 #define GPIO_ODR_OD5_Pos (5U) 5759 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ 5760 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk 5761 #define GPIO_ODR_OD6_Pos (6U) 5762 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ 5763 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk 5764 #define GPIO_ODR_OD7_Pos (7U) 5765 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ 5766 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk 5767 #define GPIO_ODR_OD8_Pos (8U) 5768 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ 5769 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk 5770 #define GPIO_ODR_OD9_Pos (9U) 5771 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ 5772 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk 5773 #define GPIO_ODR_OD10_Pos (10U) 5774 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ 5775 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk 5776 #define GPIO_ODR_OD11_Pos (11U) 5777 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ 5778 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk 5779 #define GPIO_ODR_OD12_Pos (12U) 5780 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ 5781 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk 5782 #define GPIO_ODR_OD13_Pos (13U) 5783 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ 5784 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk 5785 #define GPIO_ODR_OD14_Pos (14U) 5786 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ 5787 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk 5788 #define GPIO_ODR_OD15_Pos (15U) 5789 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ 5790 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk 5791 5792 /* Legacy defines */ 5793 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0 5794 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1 5795 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2 5796 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3 5797 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4 5798 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5 5799 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6 5800 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7 5801 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8 5802 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9 5803 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10 5804 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11 5805 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12 5806 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13 5807 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14 5808 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15 5809 5810 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */ 5811 #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0 5812 #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1 5813 #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2 5814 #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3 5815 #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4 5816 #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5 5817 #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6 5818 #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7 5819 #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8 5820 #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9 5821 #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10 5822 #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11 5823 #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12 5824 #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13 5825 #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14 5826 #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15 5827 5828 /****************** Bits definition for GPIO_BSRR register ******************/ 5829 #define GPIO_BSRR_BS0_Pos (0U) 5830 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 5831 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk 5832 #define GPIO_BSRR_BS1_Pos (1U) 5833 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 5834 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk 5835 #define GPIO_BSRR_BS2_Pos (2U) 5836 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 5837 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk 5838 #define GPIO_BSRR_BS3_Pos (3U) 5839 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 5840 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk 5841 #define GPIO_BSRR_BS4_Pos (4U) 5842 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 5843 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk 5844 #define GPIO_BSRR_BS5_Pos (5U) 5845 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 5846 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk 5847 #define GPIO_BSRR_BS6_Pos (6U) 5848 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 5849 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk 5850 #define GPIO_BSRR_BS7_Pos (7U) 5851 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 5852 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk 5853 #define GPIO_BSRR_BS8_Pos (8U) 5854 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 5855 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk 5856 #define GPIO_BSRR_BS9_Pos (9U) 5857 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 5858 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk 5859 #define GPIO_BSRR_BS10_Pos (10U) 5860 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 5861 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk 5862 #define GPIO_BSRR_BS11_Pos (11U) 5863 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 5864 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk 5865 #define GPIO_BSRR_BS12_Pos (12U) 5866 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 5867 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk 5868 #define GPIO_BSRR_BS13_Pos (13U) 5869 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 5870 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk 5871 #define GPIO_BSRR_BS14_Pos (14U) 5872 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 5873 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk 5874 #define GPIO_BSRR_BS15_Pos (15U) 5875 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 5876 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk 5877 #define GPIO_BSRR_BR0_Pos (16U) 5878 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 5879 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk 5880 #define GPIO_BSRR_BR1_Pos (17U) 5881 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 5882 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk 5883 #define GPIO_BSRR_BR2_Pos (18U) 5884 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 5885 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk 5886 #define GPIO_BSRR_BR3_Pos (19U) 5887 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 5888 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk 5889 #define GPIO_BSRR_BR4_Pos (20U) 5890 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 5891 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk 5892 #define GPIO_BSRR_BR5_Pos (21U) 5893 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 5894 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk 5895 #define GPIO_BSRR_BR6_Pos (22U) 5896 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 5897 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk 5898 #define GPIO_BSRR_BR7_Pos (23U) 5899 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 5900 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk 5901 #define GPIO_BSRR_BR8_Pos (24U) 5902 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 5903 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk 5904 #define GPIO_BSRR_BR9_Pos (25U) 5905 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 5906 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk 5907 #define GPIO_BSRR_BR10_Pos (26U) 5908 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 5909 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk 5910 #define GPIO_BSRR_BR11_Pos (27U) 5911 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 5912 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk 5913 #define GPIO_BSRR_BR12_Pos (28U) 5914 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 5915 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk 5916 #define GPIO_BSRR_BR13_Pos (29U) 5917 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 5918 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk 5919 #define GPIO_BSRR_BR14_Pos (30U) 5920 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 5921 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk 5922 #define GPIO_BSRR_BR15_Pos (31U) 5923 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 5924 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk 5925 5926 /* Legacy defines */ 5927 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0 5928 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1 5929 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2 5930 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3 5931 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4 5932 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5 5933 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6 5934 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7 5935 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8 5936 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9 5937 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10 5938 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11 5939 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12 5940 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13 5941 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14 5942 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15 5943 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0 5944 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1 5945 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2 5946 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3 5947 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4 5948 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5 5949 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6 5950 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7 5951 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8 5952 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9 5953 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10 5954 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11 5955 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12 5956 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13 5957 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14 5958 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15 5959 5960 /****************** Bit definition for GPIO_LCKR register *********************/ 5961 #define GPIO_LCKR_LCK0_Pos (0U) 5962 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 5963 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 5964 #define GPIO_LCKR_LCK1_Pos (1U) 5965 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 5966 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 5967 #define GPIO_LCKR_LCK2_Pos (2U) 5968 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 5969 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 5970 #define GPIO_LCKR_LCK3_Pos (3U) 5971 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 5972 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 5973 #define GPIO_LCKR_LCK4_Pos (4U) 5974 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 5975 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 5976 #define GPIO_LCKR_LCK5_Pos (5U) 5977 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 5978 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 5979 #define GPIO_LCKR_LCK6_Pos (6U) 5980 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 5981 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 5982 #define GPIO_LCKR_LCK7_Pos (7U) 5983 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 5984 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 5985 #define GPIO_LCKR_LCK8_Pos (8U) 5986 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 5987 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 5988 #define GPIO_LCKR_LCK9_Pos (9U) 5989 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 5990 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 5991 #define GPIO_LCKR_LCK10_Pos (10U) 5992 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 5993 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 5994 #define GPIO_LCKR_LCK11_Pos (11U) 5995 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 5996 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 5997 #define GPIO_LCKR_LCK12_Pos (12U) 5998 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 5999 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 6000 #define GPIO_LCKR_LCK13_Pos (13U) 6001 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 6002 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 6003 #define GPIO_LCKR_LCK14_Pos (14U) 6004 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 6005 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 6006 #define GPIO_LCKR_LCK15_Pos (15U) 6007 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 6008 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 6009 #define GPIO_LCKR_LCKK_Pos (16U) 6010 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 6011 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 6012 6013 /****************** Bit definition for GPIO_AFRL register *********************/ 6014 #define GPIO_AFRL_AFSEL0_Pos (0U) 6015 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ 6016 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk 6017 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ 6018 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ 6019 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ 6020 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ 6021 #define GPIO_AFRL_AFSEL1_Pos (4U) 6022 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ 6023 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk 6024 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ 6025 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ 6026 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ 6027 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ 6028 #define GPIO_AFRL_AFSEL2_Pos (8U) 6029 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ 6030 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk 6031 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ 6032 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ 6033 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ 6034 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ 6035 #define GPIO_AFRL_AFSEL3_Pos (12U) 6036 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ 6037 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk 6038 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ 6039 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ 6040 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ 6041 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ 6042 #define GPIO_AFRL_AFSEL4_Pos (16U) 6043 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ 6044 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk 6045 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ 6046 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ 6047 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ 6048 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ 6049 #define GPIO_AFRL_AFSEL5_Pos (20U) 6050 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ 6051 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk 6052 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ 6053 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ 6054 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ 6055 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ 6056 #define GPIO_AFRL_AFSEL6_Pos (24U) 6057 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ 6058 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk 6059 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ 6060 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ 6061 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ 6062 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ 6063 #define GPIO_AFRL_AFSEL7_Pos (28U) 6064 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ 6065 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk 6066 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ 6067 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ 6068 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ 6069 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ 6070 6071 /* Legacy defines */ 6072 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 6073 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 6074 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 6075 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 6076 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 6077 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 6078 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 6079 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 6080 6081 /****************** Bit definition for GPIO_AFRH register *********************/ 6082 #define GPIO_AFRH_AFSEL8_Pos (0U) 6083 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ 6084 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk 6085 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ 6086 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ 6087 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ 6088 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ 6089 #define GPIO_AFRH_AFSEL9_Pos (4U) 6090 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ 6091 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk 6092 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ 6093 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ 6094 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ 6095 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ 6096 #define GPIO_AFRH_AFSEL10_Pos (8U) 6097 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ 6098 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk 6099 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ 6100 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ 6101 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ 6102 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ 6103 #define GPIO_AFRH_AFSEL11_Pos (12U) 6104 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ 6105 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk 6106 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ 6107 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ 6108 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ 6109 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ 6110 #define GPIO_AFRH_AFSEL12_Pos (16U) 6111 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ 6112 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk 6113 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ 6114 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ 6115 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ 6116 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ 6117 #define GPIO_AFRH_AFSEL13_Pos (20U) 6118 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ 6119 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk 6120 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ 6121 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ 6122 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ 6123 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ 6124 #define GPIO_AFRH_AFSEL14_Pos (24U) 6125 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ 6126 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk 6127 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ 6128 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ 6129 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ 6130 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ 6131 #define GPIO_AFRH_AFSEL15_Pos (28U) 6132 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ 6133 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk 6134 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ 6135 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ 6136 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ 6137 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ 6138 6139 /* Legacy defines */ 6140 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 6141 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 6142 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 6143 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 6144 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 6145 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 6146 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 6147 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 6148 6149 /****************** Bits definition for GPIO_BRR register ******************/ 6150 #define GPIO_BRR_BR0_Pos (0U) 6151 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 6152 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk 6153 #define GPIO_BRR_BR1_Pos (1U) 6154 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 6155 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk 6156 #define GPIO_BRR_BR2_Pos (2U) 6157 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 6158 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk 6159 #define GPIO_BRR_BR3_Pos (3U) 6160 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 6161 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk 6162 #define GPIO_BRR_BR4_Pos (4U) 6163 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 6164 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk 6165 #define GPIO_BRR_BR5_Pos (5U) 6166 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 6167 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk 6168 #define GPIO_BRR_BR6_Pos (6U) 6169 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 6170 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk 6171 #define GPIO_BRR_BR7_Pos (7U) 6172 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 6173 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk 6174 #define GPIO_BRR_BR8_Pos (8U) 6175 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 6176 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk 6177 #define GPIO_BRR_BR9_Pos (9U) 6178 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 6179 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk 6180 #define GPIO_BRR_BR10_Pos (10U) 6181 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 6182 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk 6183 #define GPIO_BRR_BR11_Pos (11U) 6184 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 6185 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk 6186 #define GPIO_BRR_BR12_Pos (12U) 6187 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 6188 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk 6189 #define GPIO_BRR_BR13_Pos (13U) 6190 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 6191 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk 6192 #define GPIO_BRR_BR14_Pos (14U) 6193 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 6194 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk 6195 #define GPIO_BRR_BR15_Pos (15U) 6196 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 6197 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk 6198 6199 /* Legacy defines */ 6200 #define GPIO_BRR_BR_0 GPIO_BRR_BR0 6201 #define GPIO_BRR_BR_1 GPIO_BRR_BR1 6202 #define GPIO_BRR_BR_2 GPIO_BRR_BR2 6203 #define GPIO_BRR_BR_3 GPIO_BRR_BR3 6204 #define GPIO_BRR_BR_4 GPIO_BRR_BR4 6205 #define GPIO_BRR_BR_5 GPIO_BRR_BR5 6206 #define GPIO_BRR_BR_6 GPIO_BRR_BR6 6207 #define GPIO_BRR_BR_7 GPIO_BRR_BR7 6208 #define GPIO_BRR_BR_8 GPIO_BRR_BR8 6209 #define GPIO_BRR_BR_9 GPIO_BRR_BR9 6210 #define GPIO_BRR_BR_10 GPIO_BRR_BR10 6211 #define GPIO_BRR_BR_11 GPIO_BRR_BR11 6212 #define GPIO_BRR_BR_12 GPIO_BRR_BR12 6213 #define GPIO_BRR_BR_13 GPIO_BRR_BR13 6214 #define GPIO_BRR_BR_14 GPIO_BRR_BR14 6215 #define GPIO_BRR_BR_15 GPIO_BRR_BR15 6216 6217 6218 /******************************************************************************/ 6219 /* */ 6220 /* Inter-integrated Circuit Interface (I2C) */ 6221 /* */ 6222 /******************************************************************************/ 6223 /******************* Bit definition for I2C_CR1 register *******************/ 6224 #define I2C_CR1_PE_Pos (0U) 6225 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 6226 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 6227 #define I2C_CR1_TXIE_Pos (1U) 6228 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 6229 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 6230 #define I2C_CR1_RXIE_Pos (2U) 6231 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 6232 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 6233 #define I2C_CR1_ADDRIE_Pos (3U) 6234 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 6235 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 6236 #define I2C_CR1_NACKIE_Pos (4U) 6237 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 6238 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 6239 #define I2C_CR1_STOPIE_Pos (5U) 6240 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 6241 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 6242 #define I2C_CR1_TCIE_Pos (6U) 6243 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 6244 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 6245 #define I2C_CR1_ERRIE_Pos (7U) 6246 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 6247 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 6248 #define I2C_CR1_DNF_Pos (8U) 6249 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 6250 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 6251 #define I2C_CR1_ANFOFF_Pos (12U) 6252 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 6253 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 6254 #define I2C_CR1_SWRST_Pos (13U) 6255 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ 6256 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ 6257 #define I2C_CR1_TXDMAEN_Pos (14U) 6258 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 6259 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 6260 #define I2C_CR1_RXDMAEN_Pos (15U) 6261 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 6262 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 6263 #define I2C_CR1_SBC_Pos (16U) 6264 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 6265 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 6266 #define I2C_CR1_NOSTRETCH_Pos (17U) 6267 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 6268 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 6269 #define I2C_CR1_WUPEN_Pos (18U) 6270 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 6271 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 6272 #define I2C_CR1_GCEN_Pos (19U) 6273 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 6274 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 6275 #define I2C_CR1_SMBHEN_Pos (20U) 6276 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 6277 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 6278 #define I2C_CR1_SMBDEN_Pos (21U) 6279 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 6280 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 6281 #define I2C_CR1_ALERTEN_Pos (22U) 6282 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 6283 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 6284 #define I2C_CR1_PECEN_Pos (23U) 6285 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 6286 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 6287 6288 /****************** Bit definition for I2C_CR2 register ********************/ 6289 #define I2C_CR2_SADD_Pos (0U) 6290 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 6291 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 6292 #define I2C_CR2_RD_WRN_Pos (10U) 6293 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 6294 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 6295 #define I2C_CR2_ADD10_Pos (11U) 6296 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 6297 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 6298 #define I2C_CR2_HEAD10R_Pos (12U) 6299 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 6300 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 6301 #define I2C_CR2_START_Pos (13U) 6302 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ 6303 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 6304 #define I2C_CR2_STOP_Pos (14U) 6305 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 6306 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 6307 #define I2C_CR2_NACK_Pos (15U) 6308 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 6309 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 6310 #define I2C_CR2_NBYTES_Pos (16U) 6311 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 6312 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 6313 #define I2C_CR2_RELOAD_Pos (24U) 6314 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 6315 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 6316 #define I2C_CR2_AUTOEND_Pos (25U) 6317 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 6318 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 6319 #define I2C_CR2_PECBYTE_Pos (26U) 6320 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 6321 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 6322 6323 /******************* Bit definition for I2C_OAR1 register ******************/ 6324 #define I2C_OAR1_OA1_Pos (0U) 6325 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 6326 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 6327 #define I2C_OAR1_OA1MODE_Pos (10U) 6328 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 6329 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 6330 #define I2C_OAR1_OA1EN_Pos (15U) 6331 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 6332 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 6333 6334 /******************* Bit definition for I2C_OAR2 register ******************/ 6335 #define I2C_OAR2_OA2_Pos (1U) 6336 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 6337 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 6338 #define I2C_OAR2_OA2MSK_Pos (8U) 6339 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 6340 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 6341 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 6342 #define I2C_OAR2_OA2MASK01_Pos (8U) 6343 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 6344 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 6345 #define I2C_OAR2_OA2MASK02_Pos (9U) 6346 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 6347 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 6348 #define I2C_OAR2_OA2MASK03_Pos (8U) 6349 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 6350 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 6351 #define I2C_OAR2_OA2MASK04_Pos (10U) 6352 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 6353 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 6354 #define I2C_OAR2_OA2MASK05_Pos (8U) 6355 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 6356 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 6357 #define I2C_OAR2_OA2MASK06_Pos (9U) 6358 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 6359 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 6360 #define I2C_OAR2_OA2MASK07_Pos (8U) 6361 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 6362 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 6363 #define I2C_OAR2_OA2EN_Pos (15U) 6364 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 6365 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 6366 6367 /******************* Bit definition for I2C_TIMINGR register *******************/ 6368 #define I2C_TIMINGR_SCLL_Pos (0U) 6369 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 6370 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 6371 #define I2C_TIMINGR_SCLH_Pos (8U) 6372 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 6373 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 6374 #define I2C_TIMINGR_SDADEL_Pos (16U) 6375 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 6376 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 6377 #define I2C_TIMINGR_SCLDEL_Pos (20U) 6378 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 6379 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 6380 #define I2C_TIMINGR_PRESC_Pos (28U) 6381 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 6382 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 6383 6384 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 6385 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 6386 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 6387 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 6388 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 6389 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 6390 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 6391 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 6392 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 6393 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 6394 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 6395 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 6396 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */ 6397 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 6398 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 6399 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 6400 6401 /****************** Bit definition for I2C_ISR register *********************/ 6402 #define I2C_ISR_TXE_Pos (0U) 6403 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 6404 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 6405 #define I2C_ISR_TXIS_Pos (1U) 6406 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 6407 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 6408 #define I2C_ISR_RXNE_Pos (2U) 6409 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 6410 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 6411 #define I2C_ISR_ADDR_Pos (3U) 6412 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 6413 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */ 6414 #define I2C_ISR_NACKF_Pos (4U) 6415 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 6416 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 6417 #define I2C_ISR_STOPF_Pos (5U) 6418 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 6419 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 6420 #define I2C_ISR_TC_Pos (6U) 6421 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 6422 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 6423 #define I2C_ISR_TCR_Pos (7U) 6424 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 6425 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 6426 #define I2C_ISR_BERR_Pos (8U) 6427 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 6428 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 6429 #define I2C_ISR_ARLO_Pos (9U) 6430 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 6431 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 6432 #define I2C_ISR_OVR_Pos (10U) 6433 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 6434 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 6435 #define I2C_ISR_PECERR_Pos (11U) 6436 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 6437 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 6438 #define I2C_ISR_TIMEOUT_Pos (12U) 6439 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 6440 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 6441 #define I2C_ISR_ALERT_Pos (13U) 6442 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 6443 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 6444 #define I2C_ISR_BUSY_Pos (15U) 6445 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 6446 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 6447 #define I2C_ISR_DIR_Pos (16U) 6448 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 6449 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 6450 #define I2C_ISR_ADDCODE_Pos (17U) 6451 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 6452 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 6453 6454 /****************** Bit definition for I2C_ICR register *********************/ 6455 #define I2C_ICR_ADDRCF_Pos (3U) 6456 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 6457 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 6458 #define I2C_ICR_NACKCF_Pos (4U) 6459 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 6460 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 6461 #define I2C_ICR_STOPCF_Pos (5U) 6462 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 6463 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 6464 #define I2C_ICR_BERRCF_Pos (8U) 6465 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 6466 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 6467 #define I2C_ICR_ARLOCF_Pos (9U) 6468 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 6469 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 6470 #define I2C_ICR_OVRCF_Pos (10U) 6471 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 6472 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 6473 #define I2C_ICR_PECCF_Pos (11U) 6474 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 6475 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 6476 #define I2C_ICR_TIMOUTCF_Pos (12U) 6477 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 6478 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 6479 #define I2C_ICR_ALERTCF_Pos (13U) 6480 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 6481 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 6482 6483 /****************** Bit definition for I2C_PECR register *********************/ 6484 #define I2C_PECR_PEC_Pos (0U) 6485 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 6486 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 6487 6488 /****************** Bit definition for I2C_RXDR register *********************/ 6489 #define I2C_RXDR_RXDATA_Pos (0U) 6490 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 6491 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 6492 6493 /****************** Bit definition for I2C_TXDR register *********************/ 6494 #define I2C_TXDR_TXDATA_Pos (0U) 6495 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 6496 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 6497 6498 /******************************************************************************/ 6499 /* */ 6500 /* Independent WATCHDOG */ 6501 /* */ 6502 /******************************************************************************/ 6503 /******************* Bit definition for IWDG_KR register ********************/ 6504 #define IWDG_KR_KEY_Pos (0U) 6505 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 6506 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ 6507 6508 /******************* Bit definition for IWDG_PR register ********************/ 6509 #define IWDG_PR_PR_Pos (0U) 6510 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 6511 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ 6512 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 6513 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 6514 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 6515 6516 /******************* Bit definition for IWDG_RLR register *******************/ 6517 #define IWDG_RLR_RL_Pos (0U) 6518 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 6519 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ 6520 6521 /******************* Bit definition for IWDG_SR register ********************/ 6522 #define IWDG_SR_PVU_Pos (0U) 6523 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 6524 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 6525 #define IWDG_SR_RVU_Pos (1U) 6526 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 6527 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 6528 #define IWDG_SR_WVU_Pos (2U) 6529 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 6530 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 6531 6532 /******************* Bit definition for IWDG_KR register ********************/ 6533 #define IWDG_WINR_WIN_Pos (0U) 6534 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 6535 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 6536 6537 /******************************************************************************/ 6538 /* */ 6539 /* Operational Amplifier (OPAMP) */ 6540 /* */ 6541 /******************************************************************************/ 6542 /********************* Bit definition for OPAMPx_CSR register ***************/ 6543 #define OPAMP_CSR_OPAMPxEN_Pos (0U) 6544 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */ 6545 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */ 6546 #define OPAMP_CSR_FORCEVP_Pos (1U) 6547 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */ 6548 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */ 6549 #define OPAMP_CSR_VPSEL_Pos (2U) 6550 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */ 6551 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */ 6552 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */ 6553 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */ 6554 #define OPAMP_CSR_USERTRIM_Pos (4U) 6555 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */ 6556 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ 6557 #define OPAMP_CSR_VMSEL_Pos (5U) 6558 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */ 6559 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */ 6560 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */ 6561 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */ 6562 #define OPAMP_CSR_HIGHSPEEDEN_Pos (7U) 6563 #define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */ 6564 #define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */ 6565 #define OPAMP_CSR_OPAMPINTEN_Pos (8U) 6566 #define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */ 6567 #define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */ 6568 #define OPAMP_CSR_CALON_Pos (11U) 6569 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */ 6570 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ 6571 #define OPAMP_CSR_CALSEL_Pos (12U) 6572 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */ 6573 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ 6574 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */ 6575 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ 6576 #define OPAMP_CSR_PGGAIN_Pos (14U) 6577 #define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */ 6578 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */ 6579 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */ 6580 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */ 6581 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */ 6582 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */ 6583 #define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */ 6584 #define OPAMP_CSR_TRIMOFFSETP_Pos (19U) 6585 #define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */ 6586 #define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */ 6587 #define OPAMP_CSR_TRIMOFFSETN_Pos (24U) 6588 #define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */ 6589 #define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */ 6590 #define OPAMP_CSR_OUTCAL_Pos (30U) 6591 #define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */ 6592 #define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */ 6593 #define OPAMP_CSR_LOCK_Pos (31U) 6594 #define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */ 6595 #define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */ 6596 6597 /********************* Bit definition for OPAMPx_TCMR register ***************/ 6598 6599 #define OPAMP_TCMR_VMSSEL_Pos (0U) 6600 #define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */ 6601 #define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */ 6602 #define OPAMP_TCMR_VPSSEL_Pos (1U) 6603 #define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */ 6604 #define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */ 6605 #define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */ 6606 #define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */ 6607 #define OPAMP_TCMR_T1CMEN_Pos (3U) 6608 #define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */ 6609 #define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */ 6610 #define OPAMP_TCMR_T8CMEN_Pos (4U) 6611 #define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */ 6612 #define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */ 6613 #define OPAMP_TCMR_T20CMEN_Pos (5U) 6614 #define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */ 6615 #define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */ 6616 #define OPAMP_TCMR_LOCK_Pos (31U) 6617 #define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */ 6618 #define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */ 6619 6620 6621 /******************************************************************************/ 6622 /* */ 6623 /* Power Control */ 6624 /* */ 6625 /******************************************************************************/ 6626 6627 /******************** Bit definition for PWR_CR1 register ********************/ 6628 6629 #define PWR_CR1_LPR_Pos (14U) 6630 #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ 6631 #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */ 6632 #define PWR_CR1_VOS_Pos (9U) 6633 #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */ 6634 #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ 6635 #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */ 6636 #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */ 6637 #define PWR_CR1_DBP_Pos (8U) 6638 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ 6639 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */ 6640 #define PWR_CR1_LPMS_Pos (0U) 6641 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ 6642 #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */ 6643 #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */ 6644 #define PWR_CR1_LPMS_STOP1_Pos (0U) 6645 #define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */ 6646 #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */ 6647 #define PWR_CR1_LPMS_STANDBY_Pos (0U) 6648 #define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */ 6649 #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */ 6650 #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U) 6651 #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */ 6652 #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */ 6653 6654 6655 /******************** Bit definition for PWR_CR2 register ********************/ 6656 6657 /*!< PVME Peripheral Voltage Monitor Enable */ 6658 #define PWR_CR2_PVME_Pos (4U) 6659 #define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */ 6660 #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */ 6661 #define PWR_CR2_PVME4_Pos (7U) 6662 #define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */ 6663 #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */ 6664 #define PWR_CR2_PVME3_Pos (6U) 6665 #define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */ 6666 #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */ 6667 #define PWR_CR2_PVME2_Pos (5U) 6668 #define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */ 6669 #define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */ 6670 #define PWR_CR2_PVME1_Pos (4U) 6671 #define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */ 6672 #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */ 6673 6674 /*!< PVD level configuration */ 6675 #define PWR_CR2_PLS_Pos (1U) 6676 #define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */ 6677 #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */ 6678 #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 6679 #define PWR_CR2_PLS_LEV1_Pos (1U) 6680 #define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */ 6681 #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */ 6682 #define PWR_CR2_PLS_LEV2_Pos (2U) 6683 #define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */ 6684 #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */ 6685 #define PWR_CR2_PLS_LEV3_Pos (1U) 6686 #define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */ 6687 #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */ 6688 #define PWR_CR2_PLS_LEV4_Pos (3U) 6689 #define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */ 6690 #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */ 6691 #define PWR_CR2_PLS_LEV5_Pos (1U) 6692 #define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */ 6693 #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */ 6694 #define PWR_CR2_PLS_LEV6_Pos (2U) 6695 #define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */ 6696 #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */ 6697 #define PWR_CR2_PLS_LEV7_Pos (1U) 6698 #define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */ 6699 #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */ 6700 #define PWR_CR2_PVDE_Pos (0U) 6701 #define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */ 6702 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */ 6703 6704 /******************** Bit definition for PWR_CR3 register ********************/ 6705 #define PWR_CR3_EIWF_Pos (15U) 6706 #define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */ 6707 #define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */ 6708 #define PWR_CR3_UCPD_DBDIS_Pos (14U) 6709 #define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */ 6710 #define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */ 6711 #define PWR_CR3_UCPD_STDBY_Pos (13U) 6712 #define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */ 6713 #define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */ 6714 #define PWR_CR3_APC_Pos (10U) 6715 #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */ 6716 #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */ 6717 #define PWR_CR3_RRS_Pos (8U) 6718 #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */ 6719 #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */ 6720 #define PWR_CR3_EWUP5_Pos (4U) 6721 #define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */ 6722 #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */ 6723 #define PWR_CR3_EWUP4_Pos (3U) 6724 #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */ 6725 #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */ 6726 #define PWR_CR3_EWUP3_Pos (2U) 6727 #define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */ 6728 #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */ 6729 #define PWR_CR3_EWUP2_Pos (1U) 6730 #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ 6731 #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */ 6732 #define PWR_CR3_EWUP1_Pos (0U) 6733 #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ 6734 #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */ 6735 #define PWR_CR3_EWUP_Pos (0U) 6736 #define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */ 6737 #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */ 6738 6739 /******************** Bit definition for PWR_CR4 register ********************/ 6740 #define PWR_CR4_VBRS_Pos (9U) 6741 #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ 6742 #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */ 6743 #define PWR_CR4_VBE_Pos (8U) 6744 #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ 6745 #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */ 6746 #define PWR_CR4_WP5_Pos (4U) 6747 #define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */ 6748 #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */ 6749 #define PWR_CR4_WP4_Pos (3U) 6750 #define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */ 6751 #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */ 6752 #define PWR_CR4_WP3_Pos (2U) 6753 #define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */ 6754 #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */ 6755 #define PWR_CR4_WP2_Pos (1U) 6756 #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ 6757 #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */ 6758 #define PWR_CR4_WP1_Pos (0U) 6759 #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ 6760 #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */ 6761 6762 /******************** Bit definition for PWR_SR1 register ********************/ 6763 #define PWR_SR1_WUFI_Pos (15U) 6764 #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ 6765 #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */ 6766 #define PWR_SR1_SBF_Pos (8U) 6767 #define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */ 6768 #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */ 6769 #define PWR_SR1_WUF_Pos (0U) 6770 #define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */ 6771 #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */ 6772 #define PWR_SR1_WUF5_Pos (4U) 6773 #define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */ 6774 #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */ 6775 #define PWR_SR1_WUF4_Pos (3U) 6776 #define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */ 6777 #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */ 6778 #define PWR_SR1_WUF3_Pos (2U) 6779 #define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */ 6780 #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */ 6781 #define PWR_SR1_WUF2_Pos (1U) 6782 #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ 6783 #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */ 6784 #define PWR_SR1_WUF1_Pos (0U) 6785 #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ 6786 #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */ 6787 6788 /******************** Bit definition for PWR_SR2 register ********************/ 6789 #define PWR_SR2_PVMO4_Pos (15U) 6790 #define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */ 6791 #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */ 6792 #define PWR_SR2_PVMO3_Pos (14U) 6793 #define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */ 6794 #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */ 6795 #define PWR_SR2_PVMO2_Pos (13U) 6796 #define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */ 6797 #define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */ 6798 #define PWR_SR2_PVMO1_Pos (12U) 6799 #define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */ 6800 #define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */ 6801 #define PWR_SR2_PVDO_Pos (11U) 6802 #define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */ 6803 #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */ 6804 #define PWR_SR2_VOSF_Pos (10U) 6805 #define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */ 6806 #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */ 6807 #define PWR_SR2_REGLPF_Pos (9U) 6808 #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ 6809 #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */ 6810 #define PWR_SR2_REGLPS_Pos (8U) 6811 #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ 6812 #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */ 6813 6814 /******************** Bit definition for PWR_SCR register ********************/ 6815 #define PWR_SCR_CSBF_Pos (8U) 6816 #define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */ 6817 #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */ 6818 #define PWR_SCR_CWUF_Pos (0U) 6819 #define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */ 6820 #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */ 6821 #define PWR_SCR_CWUF5_Pos (4U) 6822 #define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */ 6823 #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */ 6824 #define PWR_SCR_CWUF4_Pos (3U) 6825 #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */ 6826 #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */ 6827 #define PWR_SCR_CWUF3_Pos (2U) 6828 #define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */ 6829 #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */ 6830 #define PWR_SCR_CWUF2_Pos (1U) 6831 #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ 6832 #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */ 6833 #define PWR_SCR_CWUF1_Pos (0U) 6834 #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ 6835 #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */ 6836 6837 /******************** Bit definition for PWR_PUCRA register ********************/ 6838 #define PWR_PUCRA_PA15_Pos (15U) 6839 #define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */ 6840 #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */ 6841 #define PWR_PUCRA_PA13_Pos (13U) 6842 #define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */ 6843 #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */ 6844 #define PWR_PUCRA_PA12_Pos (12U) 6845 #define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */ 6846 #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */ 6847 #define PWR_PUCRA_PA11_Pos (11U) 6848 #define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */ 6849 #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */ 6850 #define PWR_PUCRA_PA10_Pos (10U) 6851 #define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */ 6852 #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */ 6853 #define PWR_PUCRA_PA9_Pos (9U) 6854 #define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */ 6855 #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */ 6856 #define PWR_PUCRA_PA8_Pos (8U) 6857 #define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */ 6858 #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */ 6859 #define PWR_PUCRA_PA7_Pos (7U) 6860 #define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */ 6861 #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */ 6862 #define PWR_PUCRA_PA6_Pos (6U) 6863 #define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */ 6864 #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */ 6865 #define PWR_PUCRA_PA5_Pos (5U) 6866 #define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */ 6867 #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */ 6868 #define PWR_PUCRA_PA4_Pos (4U) 6869 #define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */ 6870 #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */ 6871 #define PWR_PUCRA_PA3_Pos (3U) 6872 #define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */ 6873 #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */ 6874 #define PWR_PUCRA_PA2_Pos (2U) 6875 #define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */ 6876 #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */ 6877 #define PWR_PUCRA_PA1_Pos (1U) 6878 #define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */ 6879 #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */ 6880 #define PWR_PUCRA_PA0_Pos (0U) 6881 #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ 6882 #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */ 6883 6884 /******************** Bit definition for PWR_PDCRA register ********************/ 6885 #define PWR_PDCRA_PA14_Pos (14U) 6886 #define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */ 6887 #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */ 6888 #define PWR_PDCRA_PA12_Pos (12U) 6889 #define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */ 6890 #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */ 6891 #define PWR_PDCRA_PA11_Pos (11U) 6892 #define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */ 6893 #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */ 6894 #define PWR_PDCRA_PA10_Pos (10U) 6895 #define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */ 6896 #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */ 6897 #define PWR_PDCRA_PA9_Pos (9U) 6898 #define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */ 6899 #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */ 6900 #define PWR_PDCRA_PA8_Pos (8U) 6901 #define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */ 6902 #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */ 6903 #define PWR_PDCRA_PA7_Pos (7U) 6904 #define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */ 6905 #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */ 6906 #define PWR_PDCRA_PA6_Pos (6U) 6907 #define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */ 6908 #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */ 6909 #define PWR_PDCRA_PA5_Pos (5U) 6910 #define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */ 6911 #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */ 6912 #define PWR_PDCRA_PA4_Pos (4U) 6913 #define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */ 6914 #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */ 6915 #define PWR_PDCRA_PA3_Pos (3U) 6916 #define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */ 6917 #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */ 6918 #define PWR_PDCRA_PA2_Pos (2U) 6919 #define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */ 6920 #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */ 6921 #define PWR_PDCRA_PA1_Pos (1U) 6922 #define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */ 6923 #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */ 6924 #define PWR_PDCRA_PA0_Pos (0U) 6925 #define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */ 6926 #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */ 6927 6928 /******************** Bit definition for PWR_PUCRB register ********************/ 6929 6930 #define PWR_PUCRB_PB15_Pos (15U) 6931 #define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */ 6932 #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */ 6933 #define PWR_PUCRB_PB14_Pos (14U) 6934 #define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */ 6935 #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */ 6936 #define PWR_PUCRB_PB13_Pos (13U) 6937 #define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */ 6938 #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */ 6939 #define PWR_PUCRB_PB12_Pos (12U) 6940 #define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */ 6941 #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */ 6942 #define PWR_PUCRB_PB11_Pos (11U) 6943 #define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */ 6944 #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */ 6945 #define PWR_PUCRB_PB10_Pos (10U) 6946 #define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */ 6947 #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */ 6948 #define PWR_PUCRB_PB9_Pos (9U) 6949 #define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */ 6950 #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */ 6951 #define PWR_PUCRB_PB8_Pos (8U) 6952 #define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */ 6953 #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */ 6954 #define PWR_PUCRB_PB7_Pos (7U) 6955 #define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */ 6956 #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */ 6957 #define PWR_PUCRB_PB6_Pos (6U) 6958 #define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */ 6959 #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */ 6960 #define PWR_PUCRB_PB5_Pos (5U) 6961 #define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */ 6962 #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */ 6963 #define PWR_PUCRB_PB4_Pos (4U) 6964 #define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */ 6965 #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */ 6966 #define PWR_PUCRB_PB3_Pos (3U) 6967 #define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */ 6968 #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */ 6969 #define PWR_PUCRB_PB2_Pos (2U) 6970 #define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */ 6971 #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */ 6972 #define PWR_PUCRB_PB1_Pos (1U) 6973 #define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */ 6974 #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */ 6975 #define PWR_PUCRB_PB0_Pos (0U) 6976 #define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */ 6977 #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */ 6978 6979 /******************** Bit definition for PWR_PDCRB register ********************/ 6980 #define PWR_PDCRB_PB15_Pos (15U) 6981 #define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */ 6982 #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */ 6983 #define PWR_PDCRB_PB14_Pos (14U) 6984 #define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */ 6985 #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */ 6986 #define PWR_PDCRB_PB13_Pos (13U) 6987 #define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */ 6988 #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */ 6989 #define PWR_PDCRB_PB12_Pos (12U) 6990 #define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */ 6991 #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */ 6992 #define PWR_PDCRB_PB11_Pos (11U) 6993 #define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */ 6994 #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */ 6995 #define PWR_PDCRB_PB10_Pos (10U) 6996 #define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */ 6997 #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */ 6998 #define PWR_PDCRB_PB9_Pos (9U) 6999 #define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */ 7000 #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */ 7001 #define PWR_PDCRB_PB8_Pos (8U) 7002 #define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */ 7003 #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */ 7004 #define PWR_PDCRB_PB7_Pos (7U) 7005 #define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */ 7006 #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */ 7007 #define PWR_PDCRB_PB6_Pos (6U) 7008 #define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */ 7009 #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */ 7010 #define PWR_PDCRB_PB5_Pos (5U) 7011 #define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */ 7012 #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */ 7013 #define PWR_PDCRB_PB3_Pos (3U) 7014 #define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */ 7015 #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */ 7016 #define PWR_PDCRB_PB2_Pos (2U) 7017 #define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */ 7018 #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */ 7019 #define PWR_PDCRB_PB1_Pos (1U) 7020 #define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */ 7021 #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */ 7022 #define PWR_PDCRB_PB0_Pos (0U) 7023 #define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */ 7024 #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */ 7025 7026 /******************** Bit definition for PWR_PUCRC register ********************/ 7027 #define PWR_PUCRC_PC15_Pos (15U) 7028 #define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */ 7029 #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */ 7030 #define PWR_PUCRC_PC14_Pos (14U) 7031 #define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */ 7032 #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */ 7033 #define PWR_PUCRC_PC13_Pos (13U) 7034 #define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */ 7035 #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */ 7036 #define PWR_PUCRC_PC12_Pos (12U) 7037 #define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */ 7038 #define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */ 7039 #define PWR_PUCRC_PC11_Pos (11U) 7040 #define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */ 7041 #define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */ 7042 #define PWR_PUCRC_PC10_Pos (10U) 7043 #define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */ 7044 #define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */ 7045 #define PWR_PUCRC_PC9_Pos (9U) 7046 #define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */ 7047 #define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */ 7048 #define PWR_PUCRC_PC8_Pos (8U) 7049 #define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */ 7050 #define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */ 7051 #define PWR_PUCRC_PC7_Pos (7U) 7052 #define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */ 7053 #define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */ 7054 #define PWR_PUCRC_PC6_Pos (6U) 7055 #define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */ 7056 #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */ 7057 #define PWR_PUCRC_PC5_Pos (5U) 7058 #define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */ 7059 #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */ 7060 #define PWR_PUCRC_PC4_Pos (4U) 7061 #define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */ 7062 #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */ 7063 #define PWR_PUCRC_PC3_Pos (3U) 7064 #define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */ 7065 #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */ 7066 #define PWR_PUCRC_PC2_Pos (2U) 7067 #define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */ 7068 #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */ 7069 #define PWR_PUCRC_PC1_Pos (1U) 7070 #define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */ 7071 #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */ 7072 #define PWR_PUCRC_PC0_Pos (0U) 7073 #define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */ 7074 #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */ 7075 7076 /******************** Bit definition for PWR_PDCRC register ********************/ 7077 #define PWR_PDCRC_PC15_Pos (15U) 7078 #define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */ 7079 #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */ 7080 #define PWR_PDCRC_PC14_Pos (14U) 7081 #define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */ 7082 #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */ 7083 #define PWR_PDCRC_PC13_Pos (13U) 7084 #define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */ 7085 #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */ 7086 #define PWR_PDCRC_PC12_Pos (12U) 7087 #define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */ 7088 #define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */ 7089 #define PWR_PDCRC_PC11_Pos (11U) 7090 #define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */ 7091 #define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */ 7092 #define PWR_PDCRC_PC10_Pos (10U) 7093 #define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */ 7094 #define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */ 7095 #define PWR_PDCRC_PC9_Pos (9U) 7096 #define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */ 7097 #define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */ 7098 #define PWR_PDCRC_PC8_Pos (8U) 7099 #define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */ 7100 #define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */ 7101 #define PWR_PDCRC_PC7_Pos (7U) 7102 #define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */ 7103 #define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */ 7104 #define PWR_PDCRC_PC6_Pos (6U) 7105 #define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */ 7106 #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */ 7107 #define PWR_PDCRC_PC5_Pos (5U) 7108 #define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */ 7109 #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */ 7110 #define PWR_PDCRC_PC4_Pos (4U) 7111 #define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */ 7112 #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */ 7113 #define PWR_PDCRC_PC3_Pos (3U) 7114 #define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */ 7115 #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */ 7116 #define PWR_PDCRC_PC2_Pos (2U) 7117 #define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */ 7118 #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */ 7119 #define PWR_PDCRC_PC1_Pos (1U) 7120 #define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */ 7121 #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */ 7122 #define PWR_PDCRC_PC0_Pos (0U) 7123 #define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */ 7124 #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */ 7125 7126 /******************** Bit definition for PWR_PUCRD register ********************/ 7127 #define PWR_PUCRD_PD15_Pos (15U) 7128 #define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */ 7129 #define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */ 7130 #define PWR_PUCRD_PD14_Pos (14U) 7131 #define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */ 7132 #define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */ 7133 #define PWR_PUCRD_PD13_Pos (13U) 7134 #define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */ 7135 #define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */ 7136 #define PWR_PUCRD_PD12_Pos (12U) 7137 #define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */ 7138 #define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */ 7139 #define PWR_PUCRD_PD11_Pos (11U) 7140 #define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */ 7141 #define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */ 7142 #define PWR_PUCRD_PD10_Pos (10U) 7143 #define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */ 7144 #define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */ 7145 #define PWR_PUCRD_PD9_Pos (9U) 7146 #define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */ 7147 #define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */ 7148 #define PWR_PUCRD_PD8_Pos (8U) 7149 #define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */ 7150 #define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */ 7151 #define PWR_PUCRD_PD7_Pos (7U) 7152 #define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */ 7153 #define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */ 7154 #define PWR_PUCRD_PD6_Pos (6U) 7155 #define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */ 7156 #define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */ 7157 #define PWR_PUCRD_PD5_Pos (5U) 7158 #define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */ 7159 #define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */ 7160 #define PWR_PUCRD_PD4_Pos (4U) 7161 #define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */ 7162 #define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */ 7163 #define PWR_PUCRD_PD3_Pos (3U) 7164 #define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */ 7165 #define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */ 7166 #define PWR_PUCRD_PD2_Pos (2U) 7167 #define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */ 7168 #define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */ 7169 #define PWR_PUCRD_PD1_Pos (1U) 7170 #define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */ 7171 #define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */ 7172 #define PWR_PUCRD_PD0_Pos (0U) 7173 #define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */ 7174 #define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */ 7175 7176 /******************** Bit definition for PWR_PDCRD register ********************/ 7177 #define PWR_PDCRD_PD15_Pos (15U) 7178 #define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */ 7179 #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */ 7180 #define PWR_PDCRD_PD14_Pos (14U) 7181 #define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */ 7182 #define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */ 7183 #define PWR_PDCRD_PD13_Pos (13U) 7184 #define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */ 7185 #define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */ 7186 #define PWR_PDCRD_PD12_Pos (12U) 7187 #define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */ 7188 #define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */ 7189 #define PWR_PDCRD_PD11_Pos (11U) 7190 #define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */ 7191 #define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */ 7192 #define PWR_PDCRD_PD10_Pos (10U) 7193 #define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */ 7194 #define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */ 7195 #define PWR_PDCRD_PD9_Pos (9U) 7196 #define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */ 7197 #define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */ 7198 #define PWR_PDCRD_PD8_Pos (8U) 7199 #define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */ 7200 #define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */ 7201 #define PWR_PDCRD_PD7_Pos (7U) 7202 #define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */ 7203 #define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */ 7204 #define PWR_PDCRD_PD6_Pos (6U) 7205 #define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */ 7206 #define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */ 7207 #define PWR_PDCRD_PD5_Pos (5U) 7208 #define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */ 7209 #define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */ 7210 #define PWR_PDCRD_PD4_Pos (4U) 7211 #define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */ 7212 #define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */ 7213 #define PWR_PDCRD_PD3_Pos (3U) 7214 #define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */ 7215 #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */ 7216 #define PWR_PDCRD_PD2_Pos (2U) 7217 #define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */ 7218 #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */ 7219 #define PWR_PDCRD_PD1_Pos (1U) 7220 #define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */ 7221 #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */ 7222 #define PWR_PDCRD_PD0_Pos (0U) 7223 #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */ 7224 #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */ 7225 7226 /******************** Bit definition for PWR_PUCRE register ********************/ 7227 #define PWR_PUCRE_PE15_Pos (15U) 7228 #define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */ 7229 #define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */ 7230 #define PWR_PUCRE_PE14_Pos (14U) 7231 #define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */ 7232 #define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */ 7233 #define PWR_PUCRE_PE13_Pos (13U) 7234 #define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */ 7235 #define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */ 7236 #define PWR_PUCRE_PE12_Pos (12U) 7237 #define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */ 7238 #define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */ 7239 #define PWR_PUCRE_PE11_Pos (11U) 7240 #define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */ 7241 #define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */ 7242 #define PWR_PUCRE_PE10_Pos (10U) 7243 #define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */ 7244 #define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */ 7245 #define PWR_PUCRE_PE9_Pos (9U) 7246 #define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */ 7247 #define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */ 7248 #define PWR_PUCRE_PE8_Pos (8U) 7249 #define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */ 7250 #define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */ 7251 #define PWR_PUCRE_PE7_Pos (7U) 7252 #define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */ 7253 #define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */ 7254 #define PWR_PUCRE_PE6_Pos (6U) 7255 #define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */ 7256 #define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */ 7257 #define PWR_PUCRE_PE5_Pos (5U) 7258 #define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */ 7259 #define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */ 7260 #define PWR_PUCRE_PE4_Pos (4U) 7261 #define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */ 7262 #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */ 7263 #define PWR_PUCRE_PE3_Pos (3U) 7264 #define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */ 7265 #define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */ 7266 #define PWR_PUCRE_PE2_Pos (2U) 7267 #define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */ 7268 #define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */ 7269 #define PWR_PUCRE_PE1_Pos (1U) 7270 #define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */ 7271 #define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */ 7272 #define PWR_PUCRE_PE0_Pos (0U) 7273 #define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */ 7274 #define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */ 7275 7276 /******************** Bit definition for PWR_PDCRE register ********************/ 7277 #define PWR_PDCRE_PE15_Pos (15U) 7278 #define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */ 7279 #define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */ 7280 #define PWR_PDCRE_PE14_Pos (14U) 7281 #define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */ 7282 #define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */ 7283 #define PWR_PDCRE_PE13_Pos (13U) 7284 #define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */ 7285 #define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */ 7286 #define PWR_PDCRE_PE12_Pos (12U) 7287 #define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */ 7288 #define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */ 7289 #define PWR_PDCRE_PE11_Pos (11U) 7290 #define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */ 7291 #define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */ 7292 #define PWR_PDCRE_PE10_Pos (10U) 7293 #define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */ 7294 #define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */ 7295 #define PWR_PDCRE_PE9_Pos (9U) 7296 #define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */ 7297 #define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */ 7298 #define PWR_PDCRE_PE8_Pos (8U) 7299 #define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */ 7300 #define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */ 7301 #define PWR_PDCRE_PE7_Pos (7U) 7302 #define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */ 7303 #define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */ 7304 #define PWR_PDCRE_PE6_Pos (6U) 7305 #define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */ 7306 #define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */ 7307 #define PWR_PDCRE_PE5_Pos (5U) 7308 #define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */ 7309 #define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */ 7310 #define PWR_PDCRE_PE4_Pos (4U) 7311 #define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */ 7312 #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */ 7313 #define PWR_PDCRE_PE3_Pos (3U) 7314 #define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */ 7315 #define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */ 7316 #define PWR_PDCRE_PE2_Pos (2U) 7317 #define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */ 7318 #define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */ 7319 #define PWR_PDCRE_PE1_Pos (1U) 7320 #define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */ 7321 #define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */ 7322 #define PWR_PDCRE_PE0_Pos (0U) 7323 #define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */ 7324 #define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */ 7325 7326 /******************** Bit definition for PWR_PUCRF register ********************/ 7327 #define PWR_PUCRF_PF15_Pos (15U) 7328 #define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */ 7329 #define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */ 7330 #define PWR_PUCRF_PF14_Pos (14U) 7331 #define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */ 7332 #define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */ 7333 #define PWR_PUCRF_PF13_Pos (13U) 7334 #define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */ 7335 #define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */ 7336 #define PWR_PUCRF_PF12_Pos (12U) 7337 #define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */ 7338 #define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */ 7339 #define PWR_PUCRF_PF11_Pos (11U) 7340 #define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */ 7341 #define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */ 7342 #define PWR_PUCRF_PF10_Pos (10U) 7343 #define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */ 7344 #define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */ 7345 #define PWR_PUCRF_PF9_Pos (9U) 7346 #define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */ 7347 #define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */ 7348 #define PWR_PUCRF_PF8_Pos (8U) 7349 #define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */ 7350 #define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */ 7351 #define PWR_PUCRF_PF7_Pos (7U) 7352 #define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */ 7353 #define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */ 7354 #define PWR_PUCRF_PF6_Pos (6U) 7355 #define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */ 7356 #define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */ 7357 #define PWR_PUCRF_PF5_Pos (5U) 7358 #define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */ 7359 #define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */ 7360 #define PWR_PUCRF_PF4_Pos (4U) 7361 #define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */ 7362 #define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */ 7363 #define PWR_PUCRF_PF3_Pos (3U) 7364 #define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */ 7365 #define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */ 7366 #define PWR_PUCRF_PF2_Pos (2U) 7367 #define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */ 7368 #define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */ 7369 #define PWR_PUCRF_PF1_Pos (1U) 7370 #define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */ 7371 #define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */ 7372 #define PWR_PUCRF_PF0_Pos (0U) 7373 #define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */ 7374 #define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */ 7375 7376 /******************** Bit definition for PWR_PDCRF register ********************/ 7377 #define PWR_PDCRF_PF10_Pos (10U) 7378 #define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */ 7379 #define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */ 7380 #define PWR_PDCRF_PF9_Pos (9U) 7381 #define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */ 7382 #define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */ 7383 #define PWR_PDCRF_PF2_Pos (2U) 7384 #define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */ 7385 #define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */ 7386 #define PWR_PDCRF_PF1_Pos (1U) 7387 #define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */ 7388 #define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */ 7389 #define PWR_PDCRF_PF0_Pos (0U) 7390 #define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */ 7391 #define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */ 7392 7393 /******************** Bit definition for PWR_PUCRG register ********************/ 7394 #define PWR_PUCRG_PG10_Pos (10U) 7395 #define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */ 7396 #define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */ 7397 7398 /******************** Bit definition for PWR_PDCRG register ********************/ 7399 #define PWR_PDCRG_PG10_Pos (10U) 7400 #define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */ 7401 #define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */ 7402 #define PWR_PDCRG_PG9_Pos (9U) 7403 #define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */ 7404 #define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */ 7405 #define PWR_PDCRG_PG8_Pos (8U) 7406 #define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */ 7407 #define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */ 7408 #define PWR_PDCRG_PG7_Pos (7U) 7409 #define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */ 7410 #define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */ 7411 #define PWR_PDCRG_PG6_Pos (6U) 7412 #define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */ 7413 #define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */ 7414 #define PWR_PDCRG_PG5_Pos (5U) 7415 #define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */ 7416 #define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */ 7417 #define PWR_PDCRG_PG4_Pos (4U) 7418 #define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */ 7419 #define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */ 7420 #define PWR_PDCRG_PG3_Pos (3U) 7421 #define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */ 7422 #define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */ 7423 #define PWR_PDCRG_PG2_Pos (2U) 7424 #define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */ 7425 #define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */ 7426 #define PWR_PDCRG_PG1_Pos (1U) 7427 #define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */ 7428 #define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */ 7429 #define PWR_PDCRG_PG0_Pos (0U) 7430 #define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */ 7431 #define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */ 7432 7433 /******************** Bit definition for PWR_CR5 register ********************/ 7434 #define PWR_CR5_R1MODE_Pos (8U) 7435 #define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */ 7436 #define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */ 7437 7438 7439 /******************************************************************************/ 7440 /* */ 7441 /* Reset and Clock Control */ 7442 /* */ 7443 /******************************************************************************/ 7444 /* 7445 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) 7446 */ 7447 7448 #define RCC_HSI48_SUPPORT 7449 #define RCC_PLLP_DIV_2_31_SUPPORT 7450 7451 /******************** Bit definition for RCC_CR register ********************/ 7452 #define RCC_CR_HSION_Pos (8U) 7453 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ 7454 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ 7455 #define RCC_CR_HSIKERON_Pos (9U) 7456 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ 7457 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ 7458 #define RCC_CR_HSIRDY_Pos (10U) 7459 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ 7460 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ 7461 7462 #define RCC_CR_HSEON_Pos (16U) 7463 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 7464 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ 7465 #define RCC_CR_HSERDY_Pos (17U) 7466 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 7467 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ 7468 #define RCC_CR_HSEBYP_Pos (18U) 7469 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 7470 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */ 7471 #define RCC_CR_CSSON_Pos (19U) 7472 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 7473 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ 7474 7475 #define RCC_CR_PLLON_Pos (24U) 7476 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 7477 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ 7478 #define RCC_CR_PLLRDY_Pos (25U) 7479 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 7480 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ 7481 7482 /******************** Bit definition for RCC_ICSCR register ***************/ 7483 /*!< HSICAL configuration */ 7484 #define RCC_ICSCR_HSICAL_Pos (16U) 7485 #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */ 7486 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ 7487 #define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */ 7488 #define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */ 7489 #define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */ 7490 #define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */ 7491 #define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */ 7492 #define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */ 7493 #define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */ 7494 #define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */ 7495 7496 /*!< HSITRIM configuration */ 7497 #define RCC_ICSCR_HSITRIM_Pos (24U) 7498 #define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ 7499 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ 7500 #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */ 7501 #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */ 7502 #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */ 7503 #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */ 7504 #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */ 7505 #define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */ 7506 #define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */ 7507 7508 /******************** Bit definition for RCC_CFGR register ******************/ 7509 /*!< SW configuration */ 7510 #define RCC_CFGR_SW_Pos (0U) 7511 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 7512 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 7513 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 7514 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 7515 7516 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */ 7517 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */ 7518 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */ 7519 7520 /*!< SWS configuration */ 7521 #define RCC_CFGR_SWS_Pos (2U) 7522 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 7523 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 7524 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 7525 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 7526 7527 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */ 7528 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ 7529 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ 7530 7531 /*!< HPRE configuration */ 7532 #define RCC_CFGR_HPRE_Pos (4U) 7533 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 7534 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 7535 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 7536 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 7537 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 7538 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 7539 7540 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 7541 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 7542 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 7543 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 7544 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 7545 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 7546 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 7547 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 7548 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 7549 7550 /*!< PPRE1 configuration */ 7551 #define RCC_CFGR_PPRE1_Pos (8U) 7552 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 7553 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */ 7554 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 7555 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 7556 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 7557 7558 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 7559 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 7560 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 7561 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 7562 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 7563 7564 /*!< PPRE2 configuration */ 7565 #define RCC_CFGR_PPRE2_Pos (11U) 7566 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 7567 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 7568 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 7569 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 7570 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 7571 7572 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 7573 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 7574 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 7575 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 7576 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 7577 7578 /*!< MCOSEL configuration */ 7579 #define RCC_CFGR_MCOSEL_Pos (24U) 7580 #define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ 7581 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */ 7582 #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 7583 #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 7584 #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 7585 #define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ 7586 7587 #define RCC_CFGR_MCOPRE_Pos (28U) 7588 #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 7589 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ 7590 #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 7591 #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 7592 #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 7593 7594 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 7595 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 7596 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 7597 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 7598 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 7599 7600 /* Legacy aliases */ 7601 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE 7602 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 7603 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 7604 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 7605 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 7606 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 7607 7608 /******************** Bit definition for RCC_PLLCFGR register ***************/ 7609 #define RCC_PLLCFGR_PLLSRC_Pos (0U) 7610 #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */ 7611 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk 7612 #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */ 7613 #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */ 7614 7615 #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U) 7616 #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */ 7617 #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */ 7618 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U) 7619 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */ 7620 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */ 7621 7622 #define RCC_PLLCFGR_PLLM_Pos (4U) 7623 #define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */ 7624 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk 7625 #define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ 7626 #define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ 7627 #define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ 7628 #define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */ 7629 7630 #define RCC_PLLCFGR_PLLN_Pos (8U) 7631 #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */ 7632 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk 7633 #define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ 7634 #define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ 7635 #define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ 7636 #define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ 7637 #define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ 7638 #define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ 7639 #define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ 7640 7641 #define RCC_PLLCFGR_PLLPEN_Pos (16U) 7642 #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */ 7643 #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk 7644 #define RCC_PLLCFGR_PLLP_Pos (17U) 7645 #define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ 7646 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk 7647 #define RCC_PLLCFGR_PLLQEN_Pos (20U) 7648 #define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */ 7649 #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk 7650 7651 #define RCC_PLLCFGR_PLLQ_Pos (21U) 7652 #define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */ 7653 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk 7654 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */ 7655 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */ 7656 7657 #define RCC_PLLCFGR_PLLREN_Pos (24U) 7658 #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */ 7659 #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk 7660 #define RCC_PLLCFGR_PLLR_Pos (25U) 7661 #define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */ 7662 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk 7663 #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */ 7664 #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */ 7665 7666 #define RCC_PLLCFGR_PLLPDIV_Pos (27U) 7667 #define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */ 7668 #define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk 7669 #define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */ 7670 #define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */ 7671 #define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */ 7672 #define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */ 7673 #define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */ 7674 7675 /******************** Bit definition for RCC_CIER register ******************/ 7676 #define RCC_CIER_LSIRDYIE_Pos (0U) 7677 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ 7678 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk 7679 #define RCC_CIER_LSERDYIE_Pos (1U) 7680 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ 7681 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk 7682 #define RCC_CIER_HSIRDYIE_Pos (3U) 7683 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ 7684 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk 7685 #define RCC_CIER_HSERDYIE_Pos (4U) 7686 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ 7687 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk 7688 #define RCC_CIER_PLLRDYIE_Pos (5U) 7689 #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */ 7690 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk 7691 #define RCC_CIER_LSECSSIE_Pos (9U) 7692 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ 7693 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk 7694 #define RCC_CIER_HSI48RDYIE_Pos (10U) 7695 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */ 7696 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk 7697 7698 /******************** Bit definition for RCC_CIFR register ******************/ 7699 #define RCC_CIFR_LSIRDYF_Pos (0U) 7700 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ 7701 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk 7702 #define RCC_CIFR_LSERDYF_Pos (1U) 7703 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ 7704 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk 7705 #define RCC_CIFR_HSIRDYF_Pos (3U) 7706 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ 7707 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk 7708 #define RCC_CIFR_HSERDYF_Pos (4U) 7709 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ 7710 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk 7711 #define RCC_CIFR_PLLRDYF_Pos (5U) 7712 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */ 7713 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk 7714 #define RCC_CIFR_CSSF_Pos (8U) 7715 #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ 7716 #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk 7717 #define RCC_CIFR_LSECSSF_Pos (9U) 7718 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ 7719 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk 7720 #define RCC_CIFR_HSI48RDYF_Pos (10U) 7721 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */ 7722 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk 7723 7724 /******************** Bit definition for RCC_CICR register ******************/ 7725 #define RCC_CICR_LSIRDYC_Pos (0U) 7726 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ 7727 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk 7728 #define RCC_CICR_LSERDYC_Pos (1U) 7729 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ 7730 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk 7731 #define RCC_CICR_HSIRDYC_Pos (3U) 7732 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ 7733 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk 7734 #define RCC_CICR_HSERDYC_Pos (4U) 7735 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ 7736 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk 7737 #define RCC_CICR_PLLRDYC_Pos (5U) 7738 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */ 7739 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk 7740 #define RCC_CICR_CSSC_Pos (8U) 7741 #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ 7742 #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk 7743 #define RCC_CICR_LSECSSC_Pos (9U) 7744 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ 7745 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk 7746 #define RCC_CICR_HSI48RDYC_Pos (10U) 7747 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */ 7748 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk 7749 7750 /******************** Bit definition for RCC_AHB1RSTR register **************/ 7751 #define RCC_AHB1RSTR_DMA1RST_Pos (0U) 7752 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */ 7753 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk 7754 #define RCC_AHB1RSTR_DMA2RST_Pos (1U) 7755 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */ 7756 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk 7757 #define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U) 7758 #define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */ 7759 #define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk 7760 #define RCC_AHB1RSTR_CORDICRST_Pos (3U) 7761 #define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */ 7762 #define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk 7763 #define RCC_AHB1RSTR_FMACRST_Pos (4U) 7764 #define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */ 7765 #define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk 7766 #define RCC_AHB1RSTR_FLASHRST_Pos (8U) 7767 #define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */ 7768 #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk 7769 #define RCC_AHB1RSTR_CRCRST_Pos (12U) 7770 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */ 7771 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk 7772 7773 /******************** Bit definition for RCC_AHB2RSTR register **************/ 7774 #define RCC_AHB2RSTR_GPIOARST_Pos (0U) 7775 #define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */ 7776 #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk 7777 #define RCC_AHB2RSTR_GPIOBRST_Pos (1U) 7778 #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */ 7779 #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk 7780 #define RCC_AHB2RSTR_GPIOCRST_Pos (2U) 7781 #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */ 7782 #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk 7783 #define RCC_AHB2RSTR_GPIODRST_Pos (3U) 7784 #define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */ 7785 #define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk 7786 #define RCC_AHB2RSTR_GPIOERST_Pos (4U) 7787 #define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */ 7788 #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk 7789 #define RCC_AHB2RSTR_GPIOFRST_Pos (5U) 7790 #define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */ 7791 #define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk 7792 #define RCC_AHB2RSTR_GPIOGRST_Pos (6U) 7793 #define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */ 7794 #define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk 7795 #define RCC_AHB2RSTR_ADC12RST_Pos (13U) 7796 #define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */ 7797 #define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk 7798 #define RCC_AHB2RSTR_DAC1RST_Pos (16U) 7799 #define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */ 7800 #define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk 7801 #define RCC_AHB2RSTR_DAC3RST_Pos (18U) 7802 #define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */ 7803 #define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk 7804 #define RCC_AHB2RSTR_AESRST_Pos (24U) 7805 #define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos)/*!< 0x01000000 */ 7806 #define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk 7807 #define RCC_AHB2RSTR_RNGRST_Pos (26U) 7808 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */ 7809 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk 7810 7811 /******************** Bit definition for RCC_AHB3RSTR register **************/ 7812 7813 /******************** Bit definition for RCC_APB1RSTR1 register **************/ 7814 #define RCC_APB1RSTR1_TIM2RST_Pos (0U) 7815 #define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */ 7816 #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk 7817 #define RCC_APB1RSTR1_TIM3RST_Pos (1U) 7818 #define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */ 7819 #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk 7820 #define RCC_APB1RSTR1_TIM4RST_Pos (2U) 7821 #define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */ 7822 #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk 7823 #define RCC_APB1RSTR1_TIM6RST_Pos (4U) 7824 #define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */ 7825 #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk 7826 #define RCC_APB1RSTR1_TIM7RST_Pos (5U) 7827 #define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */ 7828 #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk 7829 #define RCC_APB1RSTR1_CRSRST_Pos (8U) 7830 #define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */ 7831 #define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk 7832 #define RCC_APB1RSTR1_SPI2RST_Pos (14U) 7833 #define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */ 7834 #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk 7835 #define RCC_APB1RSTR1_SPI3RST_Pos (15U) 7836 #define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */ 7837 #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk 7838 #define RCC_APB1RSTR1_USART2RST_Pos (17U) 7839 #define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */ 7840 #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk 7841 #define RCC_APB1RSTR1_USART3RST_Pos (18U) 7842 #define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */ 7843 #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk 7844 #define RCC_APB1RSTR1_UART4RST_Pos (19U) 7845 #define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */ 7846 #define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk 7847 #define RCC_APB1RSTR1_I2C1RST_Pos (21U) 7848 #define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */ 7849 #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk 7850 #define RCC_APB1RSTR1_I2C2RST_Pos (22U) 7851 #define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */ 7852 #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk 7853 #define RCC_APB1RSTR1_USBRST_Pos (23U) 7854 #define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */ 7855 #define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk 7856 #define RCC_APB1RSTR1_FDCANRST_Pos (25U) 7857 #define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */ 7858 #define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk 7859 #define RCC_APB1RSTR1_PWRRST_Pos (28U) 7860 #define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */ 7861 #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk 7862 #define RCC_APB1RSTR1_I2C3RST_Pos (30U) 7863 #define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */ 7864 #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk 7865 #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U) 7866 #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */ 7867 #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk 7868 7869 /******************** Bit definition for RCC_APB1RSTR2 register **************/ 7870 #define RCC_APB1RSTR2_LPUART1RST_Pos (0U) 7871 #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */ 7872 #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk 7873 #define RCC_APB1RSTR2_UCPD1RST_Pos (8U) 7874 #define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */ 7875 #define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk 7876 7877 /******************** Bit definition for RCC_APB2RSTR register **************/ 7878 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 7879 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */ 7880 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk 7881 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 7882 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */ 7883 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk 7884 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 7885 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */ 7886 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk 7887 #define RCC_APB2RSTR_TIM8RST_Pos (13U) 7888 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */ 7889 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk 7890 #define RCC_APB2RSTR_USART1RST_Pos (14U) 7891 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */ 7892 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk 7893 #define RCC_APB2RSTR_TIM15RST_Pos (16U) 7894 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */ 7895 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk 7896 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 7897 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */ 7898 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk 7899 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 7900 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */ 7901 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk 7902 #define RCC_APB2RSTR_SAI1RST_Pos (21U) 7903 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */ 7904 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk 7905 7906 /******************** Bit definition for RCC_AHB1ENR register ***************/ 7907 #define RCC_AHB1ENR_DMA1EN_Pos (0U) 7908 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */ 7909 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk 7910 #define RCC_AHB1ENR_DMA2EN_Pos (1U) 7911 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */ 7912 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk 7913 #define RCC_AHB1ENR_DMAMUX1EN_Pos (2U) 7914 #define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */ 7915 #define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk 7916 #define RCC_AHB1ENR_CORDICEN_Pos (3U) 7917 #define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */ 7918 #define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk 7919 #define RCC_AHB1ENR_FMACEN_Pos (4U) 7920 #define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */ 7921 #define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk 7922 #define RCC_AHB1ENR_FLASHEN_Pos (8U) 7923 #define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */ 7924 #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk 7925 #define RCC_AHB1ENR_CRCEN_Pos (12U) 7926 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ 7927 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk 7928 7929 /******************** Bit definition for RCC_AHB2ENR register ***************/ 7930 #define RCC_AHB2ENR_GPIOAEN_Pos (0U) 7931 #define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */ 7932 #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk 7933 #define RCC_AHB2ENR_GPIOBEN_Pos (1U) 7934 #define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */ 7935 #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk 7936 #define RCC_AHB2ENR_GPIOCEN_Pos (2U) 7937 #define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */ 7938 #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk 7939 #define RCC_AHB2ENR_GPIODEN_Pos (3U) 7940 #define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */ 7941 #define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk 7942 #define RCC_AHB2ENR_GPIOEEN_Pos (4U) 7943 #define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */ 7944 #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk 7945 #define RCC_AHB2ENR_GPIOFEN_Pos (5U) 7946 #define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */ 7947 #define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk 7948 #define RCC_AHB2ENR_GPIOGEN_Pos (6U) 7949 #define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */ 7950 #define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk 7951 #define RCC_AHB2ENR_ADC12EN_Pos (13U) 7952 #define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */ 7953 #define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk 7954 #define RCC_AHB2ENR_DAC1EN_Pos (16U) 7955 #define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */ 7956 #define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk 7957 #define RCC_AHB2ENR_DAC3EN_Pos (18U) 7958 #define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */ 7959 #define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk 7960 #define RCC_AHB2ENR_AESEN_Pos (24U) 7961 #define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x01000000 */ 7962 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk 7963 #define RCC_AHB2ENR_RNGEN_Pos (26U) 7964 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */ 7965 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk 7966 7967 /******************** Bit definition for RCC_AHB3ENR register ***************/ 7968 7969 /******************** Bit definition for RCC_APB1ENR1 register ***************/ 7970 #define RCC_APB1ENR1_TIM2EN_Pos (0U) 7971 #define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */ 7972 #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk 7973 #define RCC_APB1ENR1_TIM3EN_Pos (1U) 7974 #define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */ 7975 #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk 7976 #define RCC_APB1ENR1_TIM4EN_Pos (2U) 7977 #define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */ 7978 #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk 7979 #define RCC_APB1ENR1_TIM6EN_Pos (4U) 7980 #define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */ 7981 #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk 7982 #define RCC_APB1ENR1_TIM7EN_Pos (5U) 7983 #define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */ 7984 #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk 7985 #define RCC_APB1ENR1_CRSEN_Pos (8U) 7986 #define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */ 7987 #define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk 7988 #define RCC_APB1ENR1_RTCAPBEN_Pos (10U) 7989 #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */ 7990 #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk 7991 #define RCC_APB1ENR1_WWDGEN_Pos (11U) 7992 #define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */ 7993 #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk 7994 #define RCC_APB1ENR1_SPI2EN_Pos (14U) 7995 #define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */ 7996 #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk 7997 #define RCC_APB1ENR1_SPI3EN_Pos (15U) 7998 #define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */ 7999 #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk 8000 #define RCC_APB1ENR1_USART2EN_Pos (17U) 8001 #define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */ 8002 #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk 8003 #define RCC_APB1ENR1_USART3EN_Pos (18U) 8004 #define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */ 8005 #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk 8006 #define RCC_APB1ENR1_UART4EN_Pos (19U) 8007 #define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */ 8008 #define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk 8009 #define RCC_APB1ENR1_I2C1EN_Pos (21U) 8010 #define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */ 8011 #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk 8012 #define RCC_APB1ENR1_I2C2EN_Pos (22U) 8013 #define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */ 8014 #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk 8015 #define RCC_APB1ENR1_USBEN_Pos (23U) 8016 #define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */ 8017 #define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk 8018 #define RCC_APB1ENR1_FDCANEN_Pos (25U) 8019 #define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */ 8020 #define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk 8021 #define RCC_APB1ENR1_PWREN_Pos (28U) 8022 #define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */ 8023 #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk 8024 #define RCC_APB1ENR1_I2C3EN_Pos (30U) 8025 #define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */ 8026 #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk 8027 #define RCC_APB1ENR1_LPTIM1EN_Pos (31U) 8028 #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */ 8029 #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk 8030 8031 /******************** Bit definition for RCC_APB1RSTR2 register **************/ 8032 #define RCC_APB1ENR2_LPUART1EN_Pos (0U) 8033 #define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */ 8034 #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk 8035 #define RCC_APB1ENR2_UCPD1EN_Pos (8U) 8036 #define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */ 8037 #define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk 8038 8039 /******************** Bit definition for RCC_APB2ENR register ***************/ 8040 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 8041 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */ 8042 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk 8043 #define RCC_APB2ENR_TIM1EN_Pos (11U) 8044 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 8045 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk 8046 #define RCC_APB2ENR_SPI1EN_Pos (12U) 8047 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 8048 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk 8049 #define RCC_APB2ENR_TIM8EN_Pos (13U) 8050 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ 8051 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk 8052 #define RCC_APB2ENR_USART1EN_Pos (14U) 8053 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */ 8054 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk 8055 #define RCC_APB2ENR_TIM15EN_Pos (16U) 8056 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */ 8057 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk 8058 #define RCC_APB2ENR_TIM16EN_Pos (17U) 8059 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */ 8060 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk 8061 #define RCC_APB2ENR_TIM17EN_Pos (18U) 8062 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */ 8063 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk 8064 #define RCC_APB2ENR_SAI1EN_Pos (21U) 8065 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */ 8066 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk 8067 8068 /******************** Bit definition for RCC_AHB1SMENR register ***************/ 8069 #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) 8070 #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */ 8071 #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk 8072 #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U) 8073 #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */ 8074 #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk 8075 #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U) 8076 #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */ 8077 #define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk 8078 #define RCC_AHB1SMENR_CORDICSMEN_Pos (3U) 8079 #define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */ 8080 #define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk 8081 #define RCC_AHB1SMENR_FMACSMEN_Pos (4U) 8082 #define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */ 8083 #define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk 8084 #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U) 8085 #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */ 8086 #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk 8087 #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U) 8088 #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */ 8089 #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk 8090 #define RCC_AHB1SMENR_CRCSMEN_Pos (12U) 8091 #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */ 8092 #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk 8093 8094 /******************** Bit definition for RCC_AHB2SMENR register *************/ 8095 #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) 8096 #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */ 8097 #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk 8098 #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) 8099 #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */ 8100 #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk 8101 #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) 8102 #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */ 8103 #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk 8104 #define RCC_AHB2SMENR_GPIODSMEN_Pos (3U) 8105 #define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */ 8106 #define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk 8107 #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U) 8108 #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */ 8109 #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk 8110 #define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U) 8111 #define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */ 8112 #define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk 8113 #define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U) 8114 #define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */ 8115 #define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk 8116 #define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U) 8117 #define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */ 8118 #define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk 8119 #define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U) 8120 #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */ 8121 #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk 8122 #define RCC_AHB2SMENR_ADC12SMEN_Pos (13U) 8123 #define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */ 8124 #define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk 8125 #define RCC_AHB2SMENR_DAC1SMEN_Pos (16U) 8126 #define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */ 8127 #define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk 8128 #define RCC_AHB2SMENR_DAC3SMEN_Pos (18U) 8129 #define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */ 8130 #define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk 8131 #define RCC_AHB2SMENR_AESSMEN_Pos (24U) 8132 #define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos)/*!< 0x01000000 */ 8133 #define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk 8134 #define RCC_AHB2SMENR_RNGSMEN_Pos (26U) 8135 #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */ 8136 #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk 8137 8138 /******************** Bit definition for RCC_AHB3SMENR register *************/ 8139 8140 /******************** Bit definition for RCC_APB1SMENR1 register *************/ 8141 #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) 8142 #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */ 8143 #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk 8144 #define RCC_APB1SMENR1_TIM3SMEN_Pos (1U) 8145 #define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */ 8146 #define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk 8147 #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U) 8148 #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */ 8149 #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk 8150 #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U) 8151 #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */ 8152 #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk 8153 #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U) 8154 #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */ 8155 #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk 8156 #define RCC_APB1SMENR1_CRSSMEN_Pos (8U) 8157 #define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */ 8158 #define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk 8159 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U) 8160 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */ 8161 #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk 8162 #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) 8163 #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */ 8164 #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk 8165 #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U) 8166 #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */ 8167 #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk 8168 #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U) 8169 #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */ 8170 #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk 8171 #define RCC_APB1SMENR1_USART2SMEN_Pos (17U) 8172 #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */ 8173 #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk 8174 #define RCC_APB1SMENR1_USART3SMEN_Pos (18U) 8175 #define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */ 8176 #define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk 8177 #define RCC_APB1SMENR1_UART4SMEN_Pos (19U) 8178 #define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */ 8179 #define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk 8180 #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) 8181 #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */ 8182 #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk 8183 #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U) 8184 #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */ 8185 #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk 8186 #define RCC_APB1SMENR1_USBSMEN_Pos (23U) 8187 #define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */ 8188 #define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk 8189 #define RCC_APB1SMENR1_FDCANSMEN_Pos (25U) 8190 #define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */ 8191 #define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk 8192 #define RCC_APB1SMENR1_PWRSMEN_Pos (28U) 8193 #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */ 8194 #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk 8195 #define RCC_APB1SMENR1_I2C3SMEN_Pos (30U) 8196 #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */ 8197 #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk 8198 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U) 8199 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */ 8200 #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk 8201 8202 /******************** Bit definition for RCC_APB1SMENR2 register *************/ 8203 #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U) 8204 #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */ 8205 #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk 8206 #define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U) 8207 #define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */ 8208 #define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk 8209 8210 /******************** Bit definition for RCC_APB2SMENR register *************/ 8211 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) 8212 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */ 8213 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk 8214 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U) 8215 #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */ 8216 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk 8217 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) 8218 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */ 8219 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk 8220 #define RCC_APB2SMENR_TIM8SMEN_Pos (13U) 8221 #define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */ 8222 #define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk 8223 #define RCC_APB2SMENR_USART1SMEN_Pos (14U) 8224 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */ 8225 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk 8226 #define RCC_APB2SMENR_TIM15SMEN_Pos (16U) 8227 #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */ 8228 #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk 8229 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U) 8230 #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */ 8231 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk 8232 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U) 8233 #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ 8234 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk 8235 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U) 8236 #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */ 8237 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk 8238 8239 /******************** Bit definition for RCC_CCIPR register ******************/ 8240 #define RCC_CCIPR_USART1SEL_Pos (0U) 8241 #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */ 8242 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk 8243 #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */ 8244 #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */ 8245 8246 #define RCC_CCIPR_USART2SEL_Pos (2U) 8247 #define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */ 8248 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk 8249 #define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */ 8250 #define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */ 8251 8252 #define RCC_CCIPR_USART3SEL_Pos (4U) 8253 #define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */ 8254 #define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk 8255 #define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */ 8256 #define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */ 8257 8258 #define RCC_CCIPR_UART4SEL_Pos (6U) 8259 #define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */ 8260 #define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk 8261 #define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */ 8262 #define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */ 8263 8264 8265 #define RCC_CCIPR_LPUART1SEL_Pos (10U) 8266 #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */ 8267 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk 8268 #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */ 8269 #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */ 8270 8271 #define RCC_CCIPR_I2C1SEL_Pos (12U) 8272 #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ 8273 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk 8274 #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ 8275 #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ 8276 8277 #define RCC_CCIPR_I2C2SEL_Pos (14U) 8278 #define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */ 8279 #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk 8280 #define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */ 8281 #define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */ 8282 8283 #define RCC_CCIPR_I2C3SEL_Pos (16U) 8284 #define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ 8285 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk 8286 #define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ 8287 #define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ 8288 8289 #define RCC_CCIPR_LPTIM1SEL_Pos (18U) 8290 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */ 8291 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk 8292 #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */ 8293 #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */ 8294 8295 #define RCC_CCIPR_SAI1SEL_Pos (20U) 8296 #define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */ 8297 #define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk 8298 #define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */ 8299 #define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */ 8300 8301 #define RCC_CCIPR_I2S23SEL_Pos (22U) 8302 #define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */ 8303 #define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk 8304 #define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */ 8305 #define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */ 8306 8307 #define RCC_CCIPR_FDCANSEL_Pos (24U) 8308 #define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */ 8309 #define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk 8310 #define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */ 8311 #define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */ 8312 8313 #define RCC_CCIPR_CLK48SEL_Pos (26U) 8314 #define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ 8315 #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk 8316 #define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */ 8317 #define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */ 8318 8319 #define RCC_CCIPR_ADC12SEL_Pos (28U) 8320 #define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */ 8321 #define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk 8322 #define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */ 8323 #define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */ 8324 8325 8326 /******************** Bit definition for RCC_BDCR register ******************/ 8327 #define RCC_BDCR_LSEON_Pos (0U) 8328 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 8329 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk 8330 #define RCC_BDCR_LSERDY_Pos (1U) 8331 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 8332 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk 8333 #define RCC_BDCR_LSEBYP_Pos (2U) 8334 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 8335 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk 8336 8337 #define RCC_BDCR_LSEDRV_Pos (3U) 8338 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ 8339 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk 8340 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ 8341 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ 8342 8343 #define RCC_BDCR_LSECSSON_Pos (5U) 8344 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ 8345 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk 8346 #define RCC_BDCR_LSECSSD_Pos (6U) 8347 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ 8348 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk 8349 8350 #define RCC_BDCR_RTCSEL_Pos (8U) 8351 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 8352 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk 8353 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 8354 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 8355 8356 #define RCC_BDCR_RTCEN_Pos (15U) 8357 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 8358 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk 8359 #define RCC_BDCR_BDRST_Pos (16U) 8360 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 8361 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk 8362 #define RCC_BDCR_LSCOEN_Pos (24U) 8363 #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ 8364 #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk 8365 #define RCC_BDCR_LSCOSEL_Pos (25U) 8366 #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ 8367 #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk 8368 8369 /******************** Bit definition for RCC_CSR register *******************/ 8370 #define RCC_CSR_LSION_Pos (0U) 8371 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 8372 #define RCC_CSR_LSION RCC_CSR_LSION_Msk 8373 #define RCC_CSR_LSIRDY_Pos (1U) 8374 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 8375 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk 8376 8377 #define RCC_CSR_RMVF_Pos (23U) 8378 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ 8379 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk 8380 #define RCC_CSR_OBLRSTF_Pos (25U) 8381 #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 8382 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk 8383 #define RCC_CSR_PINRSTF_Pos (26U) 8384 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 8385 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk 8386 #define RCC_CSR_BORRSTF_Pos (27U) 8387 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ 8388 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk 8389 #define RCC_CSR_SFTRSTF_Pos (28U) 8390 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 8391 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk 8392 #define RCC_CSR_IWDGRSTF_Pos (29U) 8393 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 8394 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk 8395 #define RCC_CSR_WWDGRSTF_Pos (30U) 8396 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 8397 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk 8398 #define RCC_CSR_LPWRRSTF_Pos (31U) 8399 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 8400 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk 8401 8402 /******************** Bit definition for RCC_CRRCR register *****************/ 8403 #define RCC_CRRCR_HSI48ON_Pos (0U) 8404 #define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ 8405 #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk 8406 #define RCC_CRRCR_HSI48RDY_Pos (1U) 8407 #define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */ 8408 #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk 8409 8410 /*!< HSI48CAL configuration */ 8411 #define RCC_CRRCR_HSI48CAL_Pos (7U) 8412 #define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */ 8413 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */ 8414 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */ 8415 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */ 8416 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */ 8417 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */ 8418 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */ 8419 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */ 8420 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */ 8421 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */ 8422 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */ 8423 8424 /******************** Bit definition for RCC_CCIPR2 register ******************/ 8425 8426 8427 /******************************************************************************/ 8428 /* */ 8429 /* RNG */ 8430 /* */ 8431 /******************************************************************************/ 8432 /******************** Bits definition for RNG_CR register *******************/ 8433 #define RNG_CR_RNGEN_Pos (2U) 8434 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ 8435 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk 8436 #define RNG_CR_IE_Pos (3U) 8437 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ 8438 #define RNG_CR_IE RNG_CR_IE_Msk 8439 #define RNG_CR_CED_Pos (5U) 8440 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */ 8441 #define RNG_CR_CED RNG_CR_IE_Msk 8442 8443 /******************** Bits definition for RNG_SR register *******************/ 8444 #define RNG_SR_DRDY_Pos (0U) 8445 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ 8446 #define RNG_SR_DRDY RNG_SR_DRDY_Msk 8447 #define RNG_SR_CECS_Pos (1U) 8448 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ 8449 #define RNG_SR_CECS RNG_SR_CECS_Msk 8450 #define RNG_SR_SECS_Pos (2U) 8451 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ 8452 #define RNG_SR_SECS RNG_SR_SECS_Msk 8453 #define RNG_SR_CEIS_Pos (5U) 8454 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ 8455 #define RNG_SR_CEIS RNG_SR_CEIS_Msk 8456 #define RNG_SR_SEIS_Pos (6U) 8457 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ 8458 #define RNG_SR_SEIS RNG_SR_SEIS_Msk 8459 8460 /******************************************************************************/ 8461 /* */ 8462 /* Real-Time Clock (RTC) */ 8463 /* */ 8464 /******************************************************************************/ 8465 8466 /******************** Bits definition for RTC_TR register *******************/ 8467 #define RTC_TR_PM_Pos (22U) 8468 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ 8469 #define RTC_TR_PM RTC_TR_PM_Msk 8470 #define RTC_TR_HT_Pos (20U) 8471 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ 8472 #define RTC_TR_HT RTC_TR_HT_Msk 8473 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ 8474 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ 8475 #define RTC_TR_HU_Pos (16U) 8476 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 8477 #define RTC_TR_HU RTC_TR_HU_Msk 8478 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ 8479 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ 8480 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ 8481 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ 8482 #define RTC_TR_MNT_Pos (12U) 8483 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 8484 #define RTC_TR_MNT RTC_TR_MNT_Msk 8485 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 8486 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 8487 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 8488 #define RTC_TR_MNU_Pos (8U) 8489 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 8490 #define RTC_TR_MNU RTC_TR_MNU_Msk 8491 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 8492 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 8493 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 8494 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 8495 #define RTC_TR_ST_Pos (4U) 8496 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ 8497 #define RTC_TR_ST RTC_TR_ST_Msk 8498 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ 8499 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ 8500 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ 8501 #define RTC_TR_SU_Pos (0U) 8502 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ 8503 #define RTC_TR_SU RTC_TR_SU_Msk 8504 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ 8505 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ 8506 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ 8507 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ 8508 8509 /******************** Bits definition for RTC_DR register *******************/ 8510 #define RTC_DR_YT_Pos (20U) 8511 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 8512 #define RTC_DR_YT RTC_DR_YT_Msk 8513 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ 8514 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ 8515 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ 8516 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ 8517 #define RTC_DR_YU_Pos (16U) 8518 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 8519 #define RTC_DR_YU RTC_DR_YU_Msk 8520 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ 8521 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ 8522 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ 8523 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ 8524 #define RTC_DR_WDU_Pos (13U) 8525 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 8526 #define RTC_DR_WDU RTC_DR_WDU_Msk 8527 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 8528 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 8529 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 8530 #define RTC_DR_MT_Pos (12U) 8531 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ 8532 #define RTC_DR_MT RTC_DR_MT_Msk 8533 #define RTC_DR_MU_Pos (8U) 8534 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 8535 #define RTC_DR_MU RTC_DR_MU_Msk 8536 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ 8537 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ 8538 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ 8539 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ 8540 #define RTC_DR_DT_Pos (4U) 8541 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ 8542 #define RTC_DR_DT RTC_DR_DT_Msk 8543 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ 8544 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ 8545 #define RTC_DR_DU_Pos (0U) 8546 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ 8547 #define RTC_DR_DU RTC_DR_DU_Msk 8548 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ 8549 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ 8550 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ 8551 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ 8552 8553 /******************** Bits definition for RTC_SSR register ******************/ 8554 #define RTC_SSR_SS_Pos (0U) 8555 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 8556 #define RTC_SSR_SS RTC_SSR_SS_Msk 8557 8558 /******************** Bits definition for RTC_ICSR register ******************/ 8559 #define RTC_ICSR_RECALPF_Pos (16U) 8560 #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ 8561 #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk 8562 #define RTC_ICSR_INIT_Pos (7U) 8563 #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ 8564 #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk 8565 #define RTC_ICSR_INITF_Pos (6U) 8566 #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ 8567 #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk 8568 #define RTC_ICSR_RSF_Pos (5U) 8569 #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ 8570 #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk 8571 #define RTC_ICSR_INITS_Pos (4U) 8572 #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ 8573 #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk 8574 #define RTC_ICSR_SHPF_Pos (3U) 8575 #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ 8576 #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk 8577 #define RTC_ICSR_WUTWF_Pos (2U) 8578 #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ 8579 #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk 8580 #define RTC_ICSR_ALRBWF_Pos (1U) 8581 #define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ 8582 #define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk 8583 #define RTC_ICSR_ALRAWF_Pos (0U) 8584 #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ 8585 #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk 8586 8587 /******************** Bits definition for RTC_PRER register *****************/ 8588 #define RTC_PRER_PREDIV_A_Pos (16U) 8589 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 8590 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 8591 #define RTC_PRER_PREDIV_S_Pos (0U) 8592 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 8593 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 8594 8595 /******************** Bits definition for RTC_WUTR register *****************/ 8596 #define RTC_WUTR_WUT_Pos (0U) 8597 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 8598 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 8599 8600 /******************** Bits definition for RTC_CR register *******************/ 8601 #define RTC_CR_OUT2EN_Pos (31U) 8602 #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ 8603 #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */ 8604 #define RTC_CR_TAMPALRM_TYPE_Pos (30U) 8605 #define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ 8606 #define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */ 8607 #define RTC_CR_TAMPALRM_PU_Pos (29U) 8608 #define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ 8609 #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */ 8610 #define RTC_CR_TAMPOE_Pos (26U) 8611 #define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ 8612 #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */ 8613 #define RTC_CR_TAMPTS_Pos (25U) 8614 #define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ 8615 #define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */ 8616 #define RTC_CR_ITSE_Pos (24U) 8617 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ 8618 #define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */ 8619 #define RTC_CR_COE_Pos (23U) 8620 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ 8621 #define RTC_CR_COE RTC_CR_COE_Msk 8622 #define RTC_CR_OSEL_Pos (21U) 8623 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 8624 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 8625 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 8626 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 8627 #define RTC_CR_POL_Pos (20U) 8628 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ 8629 #define RTC_CR_POL RTC_CR_POL_Msk 8630 #define RTC_CR_COSEL_Pos (19U) 8631 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 8632 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 8633 #define RTC_CR_BKP_Pos (18U) 8634 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ 8635 #define RTC_CR_BKP RTC_CR_BKP_Msk 8636 #define RTC_CR_SUB1H_Pos (17U) 8637 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 8638 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 8639 #define RTC_CR_ADD1H_Pos (16U) 8640 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 8641 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 8642 #define RTC_CR_TSIE_Pos (15U) 8643 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 8644 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 8645 #define RTC_CR_WUTIE_Pos (14U) 8646 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 8647 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 8648 #define RTC_CR_ALRBIE_Pos (13U) 8649 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 8650 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 8651 #define RTC_CR_ALRAIE_Pos (12U) 8652 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 8653 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 8654 #define RTC_CR_TSE_Pos (11U) 8655 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 8656 #define RTC_CR_TSE RTC_CR_TSE_Msk 8657 #define RTC_CR_WUTE_Pos (10U) 8658 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 8659 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 8660 #define RTC_CR_ALRBE_Pos (9U) 8661 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 8662 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 8663 #define RTC_CR_ALRAE_Pos (8U) 8664 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 8665 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 8666 #define RTC_CR_FMT_Pos (6U) 8667 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 8668 #define RTC_CR_FMT RTC_CR_FMT_Msk 8669 #define RTC_CR_BYPSHAD_Pos (5U) 8670 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 8671 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 8672 #define RTC_CR_REFCKON_Pos (4U) 8673 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 8674 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 8675 #define RTC_CR_TSEDGE_Pos (3U) 8676 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 8677 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 8678 #define RTC_CR_WUCKSEL_Pos (0U) 8679 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 8680 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 8681 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 8682 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 8683 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 8684 8685 /******************** Bits definition for RTC_WPR register ******************/ 8686 #define RTC_WPR_KEY_Pos (0U) 8687 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 8688 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 8689 8690 /******************** Bits definition for RTC_CALR register *****************/ 8691 #define RTC_CALR_CALP_Pos (15U) 8692 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 8693 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 8694 #define RTC_CALR_CALW8_Pos (14U) 8695 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 8696 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 8697 #define RTC_CALR_CALW16_Pos (13U) 8698 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 8699 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 8700 #define RTC_CALR_CALM_Pos (0U) 8701 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 8702 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 8703 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 8704 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 8705 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 8706 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 8707 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 8708 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 8709 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 8710 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 8711 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 8712 8713 /******************** Bits definition for RTC_SHIFTR register ***************/ 8714 #define RTC_SHIFTR_SUBFS_Pos (0U) 8715 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 8716 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 8717 #define RTC_SHIFTR_ADD1S_Pos (31U) 8718 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 8719 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 8720 8721 /******************** Bits definition for RTC_TSTR register *****************/ 8722 #define RTC_TSTR_PM_Pos (22U) 8723 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 8724 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 8725 #define RTC_TSTR_HT_Pos (20U) 8726 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 8727 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 8728 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 8729 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 8730 #define RTC_TSTR_HU_Pos (16U) 8731 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 8732 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 8733 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 8734 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 8735 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 8736 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 8737 #define RTC_TSTR_MNT_Pos (12U) 8738 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 8739 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 8740 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 8741 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 8742 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 8743 #define RTC_TSTR_MNU_Pos (8U) 8744 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 8745 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 8746 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 8747 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 8748 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 8749 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 8750 #define RTC_TSTR_ST_Pos (4U) 8751 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 8752 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 8753 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 8754 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 8755 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 8756 #define RTC_TSTR_SU_Pos (0U) 8757 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 8758 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 8759 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 8760 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 8761 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 8762 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 8763 8764 /******************** Bits definition for RTC_TSDR register *****************/ 8765 #define RTC_TSDR_WDU_Pos (13U) 8766 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 8767 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 8768 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 8769 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 8770 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 8771 #define RTC_TSDR_MT_Pos (12U) 8772 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 8773 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 8774 #define RTC_TSDR_MU_Pos (8U) 8775 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 8776 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 8777 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 8778 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 8779 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 8780 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 8781 #define RTC_TSDR_DT_Pos (4U) 8782 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 8783 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 8784 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 8785 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 8786 #define RTC_TSDR_DU_Pos (0U) 8787 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 8788 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 8789 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 8790 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 8791 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 8792 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 8793 8794 /******************** Bits definition for RTC_TSSSR register ****************/ 8795 #define RTC_TSSSR_SS_Pos (0U) 8796 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 8797 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 8798 8799 /******************** Bits definition for RTC_ALRMAR register ***************/ 8800 #define RTC_ALRMAR_MSK4_Pos (31U) 8801 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 8802 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 8803 #define RTC_ALRMAR_WDSEL_Pos (30U) 8804 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 8805 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 8806 #define RTC_ALRMAR_DT_Pos (28U) 8807 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 8808 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 8809 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 8810 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 8811 #define RTC_ALRMAR_DU_Pos (24U) 8812 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 8813 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 8814 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 8815 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 8816 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 8817 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 8818 #define RTC_ALRMAR_MSK3_Pos (23U) 8819 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 8820 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 8821 #define RTC_ALRMAR_PM_Pos (22U) 8822 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 8823 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 8824 #define RTC_ALRMAR_HT_Pos (20U) 8825 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 8826 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 8827 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 8828 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 8829 #define RTC_ALRMAR_HU_Pos (16U) 8830 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 8831 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 8832 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 8833 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 8834 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 8835 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 8836 #define RTC_ALRMAR_MSK2_Pos (15U) 8837 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 8838 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 8839 #define RTC_ALRMAR_MNT_Pos (12U) 8840 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 8841 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 8842 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 8843 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 8844 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 8845 #define RTC_ALRMAR_MNU_Pos (8U) 8846 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 8847 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 8848 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 8849 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 8850 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 8851 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 8852 #define RTC_ALRMAR_MSK1_Pos (7U) 8853 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 8854 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 8855 #define RTC_ALRMAR_ST_Pos (4U) 8856 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 8857 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 8858 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 8859 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 8860 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 8861 #define RTC_ALRMAR_SU_Pos (0U) 8862 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 8863 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 8864 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 8865 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 8866 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 8867 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 8868 8869 /******************** Bits definition for RTC_ALRMASSR register *************/ 8870 #define RTC_ALRMASSR_MASKSS_Pos (24U) 8871 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 8872 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 8873 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 8874 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 8875 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 8876 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 8877 #define RTC_ALRMASSR_SS_Pos (0U) 8878 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 8879 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 8880 8881 /******************** Bits definition for RTC_ALRMBR register ***************/ 8882 #define RTC_ALRMBR_MSK4_Pos (31U) 8883 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 8884 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 8885 #define RTC_ALRMBR_WDSEL_Pos (30U) 8886 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 8887 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 8888 #define RTC_ALRMBR_DT_Pos (28U) 8889 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 8890 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 8891 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 8892 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 8893 #define RTC_ALRMBR_DU_Pos (24U) 8894 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 8895 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 8896 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 8897 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 8898 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 8899 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 8900 #define RTC_ALRMBR_MSK3_Pos (23U) 8901 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 8902 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 8903 #define RTC_ALRMBR_PM_Pos (22U) 8904 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 8905 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 8906 #define RTC_ALRMBR_HT_Pos (20U) 8907 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 8908 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 8909 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 8910 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 8911 #define RTC_ALRMBR_HU_Pos (16U) 8912 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 8913 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 8914 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 8915 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 8916 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 8917 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 8918 #define RTC_ALRMBR_MSK2_Pos (15U) 8919 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 8920 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 8921 #define RTC_ALRMBR_MNT_Pos (12U) 8922 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 8923 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 8924 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 8925 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 8926 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 8927 #define RTC_ALRMBR_MNU_Pos (8U) 8928 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 8929 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 8930 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 8931 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 8932 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 8933 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 8934 #define RTC_ALRMBR_MSK1_Pos (7U) 8935 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 8936 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 8937 #define RTC_ALRMBR_ST_Pos (4U) 8938 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 8939 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 8940 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 8941 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 8942 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 8943 #define RTC_ALRMBR_SU_Pos (0U) 8944 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 8945 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 8946 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 8947 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 8948 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 8949 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 8950 8951 /******************** Bits definition for RTC_ALRMASSR register *************/ 8952 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 8953 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 8954 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 8955 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 8956 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 8957 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 8958 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 8959 #define RTC_ALRMBSSR_SS_Pos (0U) 8960 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 8961 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 8962 8963 /******************** Bits definition for RTC_SR register *******************/ 8964 #define RTC_SR_ITSF_Pos (5U) 8965 #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ 8966 #define RTC_SR_ITSF RTC_SR_ITSF_Msk 8967 #define RTC_SR_TSOVF_Pos (4U) 8968 #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ 8969 #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk 8970 #define RTC_SR_TSF_Pos (3U) 8971 #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ 8972 #define RTC_SR_TSF RTC_SR_TSF_Msk 8973 #define RTC_SR_WUTF_Pos (2U) 8974 #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ 8975 #define RTC_SR_WUTF RTC_SR_WUTF_Msk 8976 #define RTC_SR_ALRBF_Pos (1U) 8977 #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ 8978 #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk 8979 #define RTC_SR_ALRAF_Pos (0U) 8980 #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ 8981 #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk 8982 8983 /******************** Bits definition for RTC_MISR register *****************/ 8984 #define RTC_MISR_ITSMF_Pos (5U) 8985 #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ 8986 #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk 8987 #define RTC_MISR_TSOVMF_Pos (4U) 8988 #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ 8989 #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk 8990 #define RTC_MISR_TSMF_Pos (3U) 8991 #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ 8992 #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk 8993 #define RTC_MISR_WUTMF_Pos (2U) 8994 #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ 8995 #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk 8996 #define RTC_MISR_ALRBMF_Pos (1U) 8997 #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ 8998 #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk 8999 #define RTC_MISR_ALRAMF_Pos (0U) 9000 #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ 9001 #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk 9002 9003 /******************** Bits definition for RTC_SCR register ******************/ 9004 #define RTC_SCR_CITSF_Pos (5U) 9005 #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ 9006 #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk 9007 #define RTC_SCR_CTSOVF_Pos (4U) 9008 #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ 9009 #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk 9010 #define RTC_SCR_CTSF_Pos (3U) 9011 #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ 9012 #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk 9013 #define RTC_SCR_CWUTF_Pos (2U) 9014 #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ 9015 #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk 9016 #define RTC_SCR_CALRBF_Pos (1U) 9017 #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ 9018 #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk 9019 #define RTC_SCR_CALRAF_Pos (0U) 9020 #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ 9021 #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk 9022 9023 /******************************************************************************/ 9024 /* */ 9025 /* Tamper and backup register (TAMP) */ 9026 /* */ 9027 /******************************************************************************/ 9028 /******************** Bits definition for TAMP_CR1 register *****************/ 9029 #define TAMP_CR1_TAMP1E_Pos (0U) 9030 #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ 9031 #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk 9032 #define TAMP_CR1_TAMP2E_Pos (1U) 9033 #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ 9034 #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk 9035 #define TAMP_CR1_TAMP3E_Pos (2U) 9036 #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ 9037 #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk 9038 #define TAMP_CR1_ITAMP3E_Pos (18U) 9039 #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ 9040 #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk 9041 #define TAMP_CR1_ITAMP4E_Pos (19U) 9042 #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ 9043 #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk 9044 #define TAMP_CR1_ITAMP5E_Pos (20U) 9045 #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ 9046 #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk 9047 #define TAMP_CR1_ITAMP6E_Pos (21U) 9048 #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ 9049 #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk 9050 9051 /******************** Bits definition for TAMP_CR2 register *****************/ 9052 #define TAMP_CR2_TAMP1NOERASE_Pos (0U) 9053 #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ 9054 #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk 9055 #define TAMP_CR2_TAMP2NOERASE_Pos (1U) 9056 #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ 9057 #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk 9058 #define TAMP_CR2_TAMP3NOERASE_Pos (2U) 9059 #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ 9060 #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk 9061 #define TAMP_CR2_TAMP1MF_Pos (16U) 9062 #define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */ 9063 #define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk 9064 #define TAMP_CR2_TAMP2MF_Pos (17U) 9065 #define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */ 9066 #define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk 9067 #define TAMP_CR2_TAMP3MF_Pos (18U) 9068 #define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */ 9069 #define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk 9070 #define TAMP_CR2_TAMP1TRG_Pos (24U) 9071 #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ 9072 #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk 9073 #define TAMP_CR2_TAMP2TRG_Pos (25U) 9074 #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ 9075 #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk 9076 #define TAMP_CR2_TAMP3TRG_Pos (26U) 9077 #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */ 9078 #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk 9079 9080 /******************** Bits definition for TAMP_FLTCR register ***************/ 9081 #define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL) 9082 #define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL) 9083 #define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL) 9084 #define TAMP_FLTCR_TAMPFREQ_Pos (0U) 9085 #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ 9086 #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk 9087 #define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL) 9088 #define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL) 9089 #define TAMP_FLTCR_TAMPFLT_Pos (3U) 9090 #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ 9091 #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk 9092 #define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL) 9093 #define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL) 9094 #define TAMP_FLTCR_TAMPPRCH_Pos (5U) 9095 #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ 9096 #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk 9097 #define TAMP_FLTCR_TAMPPUDIS_Pos (7U) 9098 #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ 9099 #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk 9100 9101 /******************** Bits definition for TAMP_IER register *****************/ 9102 #define TAMP_IER_TAMP1IE_Pos (0U) 9103 #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ 9104 #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk 9105 #define TAMP_IER_TAMP2IE_Pos (1U) 9106 #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ 9107 #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk 9108 #define TAMP_IER_TAMP3IE_Pos (2U) 9109 #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ 9110 #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk 9111 #define TAMP_IER_ITAMP3IE_Pos (18U) 9112 #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ 9113 #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk 9114 #define TAMP_IER_ITAMP4IE_Pos (19U) 9115 #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ 9116 #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk 9117 #define TAMP_IER_ITAMP5IE_Pos (20U) 9118 #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ 9119 #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk 9120 #define TAMP_IER_ITAMP6IE_Pos (21U) 9121 #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ 9122 #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk 9123 9124 /******************** Bits definition for TAMP_SR register ******************/ 9125 #define TAMP_SR_TAMP1F_Pos (0U) 9126 #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ 9127 #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk 9128 #define TAMP_SR_TAMP2F_Pos (1U) 9129 #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ 9130 #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk 9131 #define TAMP_SR_TAMP3F_Pos (2U) 9132 #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ 9133 #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk 9134 #define TAMP_SR_ITAMP3F_Pos (18U) 9135 #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ 9136 #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk 9137 #define TAMP_SR_ITAMP4F_Pos (19U) 9138 #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ 9139 #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk 9140 #define TAMP_SR_ITAMP5F_Pos (20U) 9141 #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ 9142 #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk 9143 #define TAMP_SR_ITAMP6F_Pos (21U) 9144 #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ 9145 #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk 9146 9147 /******************** Bits definition for TAMP_MISR register ****************/ 9148 #define TAMP_MISR_TAMP1MF_Pos (0U) 9149 #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ 9150 #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk 9151 #define TAMP_MISR_TAMP2MF_Pos (1U) 9152 #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ 9153 #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk 9154 #define TAMP_MISR_TAMP3MF_Pos (2U) 9155 #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ 9156 #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk 9157 #define TAMP_MISR_ITAMP3MF_Pos (18U) 9158 #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ 9159 #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk 9160 #define TAMP_MISR_ITAMP4MF_Pos (19U) 9161 #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ 9162 #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk 9163 #define TAMP_MISR_ITAMP5MF_Pos (20U) 9164 #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ 9165 #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk 9166 #define TAMP_MISR_ITAMP6MF_Pos (21U) 9167 #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ 9168 #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk 9169 9170 /******************** Bits definition for TAMP_SCR register *****************/ 9171 #define TAMP_SCR_CTAMP1F_Pos (0U) 9172 #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ 9173 #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk 9174 #define TAMP_SCR_CTAMP2F_Pos (1U) 9175 #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ 9176 #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk 9177 #define TAMP_SCR_CTAMP3F_Pos (2U) 9178 #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ 9179 #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk 9180 #define TAMP_SCR_CITAMP3F_Pos (18U) 9181 #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ 9182 #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk 9183 #define TAMP_SCR_CITAMP4F_Pos (19U) 9184 #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ 9185 #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk 9186 #define TAMP_SCR_CITAMP5F_Pos (20U) 9187 #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ 9188 #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk 9189 #define TAMP_SCR_CITAMP6F_Pos (21U) 9190 #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ 9191 #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk 9192 9193 /******************** Bits definition for TAMP_BKP0R register ***************/ 9194 #define TAMP_BKP0R_Pos (0U) 9195 #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ 9196 #define TAMP_BKP0R TAMP_BKP0R_Msk 9197 9198 /******************** Bits definition for TAMP_BKP1R register ***************/ 9199 #define TAMP_BKP1R_Pos (0U) 9200 #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ 9201 #define TAMP_BKP1R TAMP_BKP1R_Msk 9202 9203 /******************** Bits definition for TAMP_BKP2R register ***************/ 9204 #define TAMP_BKP2R_Pos (0U) 9205 #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ 9206 #define TAMP_BKP2R TAMP_BKP2R_Msk 9207 9208 /******************** Bits definition for TAMP_BKP3R register ***************/ 9209 #define TAMP_BKP3R_Pos (0U) 9210 #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ 9211 #define TAMP_BKP3R TAMP_BKP3R_Msk 9212 9213 /******************** Bits definition for TAMP_BKP4R register ***************/ 9214 #define TAMP_BKP4R_Pos (0U) 9215 #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ 9216 #define TAMP_BKP4R TAMP_BKP4R_Msk 9217 9218 /******************** Bits definition for TAMP_BKP5R register ***************/ 9219 #define TAMP_BKP5R_Pos (0U) 9220 #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ 9221 #define TAMP_BKP5R TAMP_BKP5R_Msk 9222 9223 /******************** Bits definition for TAMP_BKP6R register ***************/ 9224 #define TAMP_BKP6R_Pos (0U) 9225 #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ 9226 #define TAMP_BKP6R TAMP_BKP6R_Msk 9227 9228 /******************** Bits definition for TAMP_BKP7R register ***************/ 9229 #define TAMP_BKP7R_Pos (0U) 9230 #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ 9231 #define TAMP_BKP7R TAMP_BKP7R_Msk 9232 9233 /******************** Bits definition for TAMP_BKP8R register ***************/ 9234 #define TAMP_BKP8R_Pos (0U) 9235 #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ 9236 #define TAMP_BKP8R TAMP_BKP8R_Msk 9237 9238 /******************** Bits definition for TAMP_BKP9R register ***************/ 9239 #define TAMP_BKP9R_Pos (0U) 9240 #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ 9241 #define TAMP_BKP9R TAMP_BKP9R_Msk 9242 9243 /******************** Bits definition for TAMP_BKP10R register ***************/ 9244 #define TAMP_BKP10R_Pos (0U) 9245 #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ 9246 #define TAMP_BKP10R TAMP_BKP10R_Msk 9247 9248 /******************** Bits definition for TAMP_BKP11R register ***************/ 9249 #define TAMP_BKP11R_Pos (0U) 9250 #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ 9251 #define TAMP_BKP11R TAMP_BKP11R_Msk 9252 9253 /******************** Bits definition for TAMP_BKP12R register ***************/ 9254 #define TAMP_BKP12R_Pos (0U) 9255 #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ 9256 #define TAMP_BKP12R TAMP_BKP12R_Msk 9257 9258 /******************** Bits definition for TAMP_BKP13R register ***************/ 9259 #define TAMP_BKP13R_Pos (0U) 9260 #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ 9261 #define TAMP_BKP13R TAMP_BKP13R_Msk 9262 9263 /******************** Bits definition for TAMP_BKP14R register ***************/ 9264 #define TAMP_BKP14R_Pos (0U) 9265 #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ 9266 #define TAMP_BKP14R TAMP_BKP14R_Msk 9267 9268 /******************** Bits definition for TAMP_BKP15R register ***************/ 9269 #define TAMP_BKP15R_Pos (0U) 9270 #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ 9271 #define TAMP_BKP15R TAMP_BKP15R_Msk 9272 9273 9274 /******************************************************************************/ 9275 /* */ 9276 /* Serial Audio Interface */ 9277 /* */ 9278 /******************************************************************************/ 9279 /******************** Bit definition for SAI_GCR register *******************/ 9280 #define SAI_GCR_SYNCIN_Pos (0U) 9281 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ 9282 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ 9283 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ 9284 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ 9285 9286 #define SAI_GCR_SYNCOUT_Pos (4U) 9287 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ 9288 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ 9289 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ 9290 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ 9291 9292 /******************* Bit definition for SAI_xCR1 register *******************/ 9293 #define SAI_xCR1_MODE_Pos (0U) 9294 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ 9295 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */ 9296 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */ 9297 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */ 9298 9299 #define SAI_xCR1_PRTCFG_Pos (2U) 9300 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */ 9301 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */ 9302 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */ 9303 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */ 9304 9305 #define SAI_xCR1_DS_Pos (5U) 9306 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */ 9307 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */ 9308 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */ 9309 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */ 9310 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */ 9311 9312 #define SAI_xCR1_LSBFIRST_Pos (8U) 9313 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */ 9314 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */ 9315 #define SAI_xCR1_CKSTR_Pos (9U) 9316 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */ 9317 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */ 9318 9319 #define SAI_xCR1_SYNCEN_Pos (10U) 9320 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */ 9321 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */ 9322 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */ 9323 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */ 9324 9325 #define SAI_xCR1_MONO_Pos (12U) 9326 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */ 9327 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */ 9328 #define SAI_xCR1_OUTDRIV_Pos (13U) 9329 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */ 9330 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */ 9331 #define SAI_xCR1_SAIEN_Pos (16U) 9332 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */ 9333 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */ 9334 #define SAI_xCR1_DMAEN_Pos (17U) 9335 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */ 9336 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */ 9337 #define SAI_xCR1_NODIV_Pos (19U) 9338 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */ 9339 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */ 9340 9341 #define SAI_xCR1_MCKDIV_Pos (20U) 9342 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */ 9343 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */ 9344 #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */ 9345 #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */ 9346 #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */ 9347 #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */ 9348 #define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */ 9349 #define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */ 9350 9351 #define SAI_xCR1_OSR_Pos (26U) 9352 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */ 9353 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */ 9354 9355 #define SAI_xCR1_MCKEN_Pos (27U) 9356 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */ 9357 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */ 9358 9359 /******************* Bit definition for SAI_xCR2 register *******************/ 9360 #define SAI_xCR2_FTH_Pos (0U) 9361 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */ 9362 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */ 9363 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */ 9364 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */ 9365 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */ 9366 9367 #define SAI_xCR2_FFLUSH_Pos (3U) 9368 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */ 9369 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */ 9370 #define SAI_xCR2_TRIS_Pos (4U) 9371 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */ 9372 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */ 9373 #define SAI_xCR2_MUTE_Pos (5U) 9374 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */ 9375 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */ 9376 #define SAI_xCR2_MUTEVAL_Pos (6U) 9377 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */ 9378 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */ 9379 9380 9381 #define SAI_xCR2_MUTECNT_Pos (7U) 9382 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */ 9383 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */ 9384 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */ 9385 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */ 9386 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */ 9387 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */ 9388 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */ 9389 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */ 9390 9391 #define SAI_xCR2_CPL_Pos (13U) 9392 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */ 9393 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */ 9394 #define SAI_xCR2_COMP_Pos (14U) 9395 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */ 9396 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */ 9397 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */ 9398 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */ 9399 9400 9401 /****************** Bit definition for SAI_xFRCR register *******************/ 9402 #define SAI_xFRCR_FRL_Pos (0U) 9403 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */ 9404 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */ 9405 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */ 9406 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */ 9407 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */ 9408 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */ 9409 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */ 9410 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */ 9411 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */ 9412 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */ 9413 9414 #define SAI_xFRCR_FSALL_Pos (8U) 9415 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */ 9416 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */ 9417 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */ 9418 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */ 9419 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */ 9420 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */ 9421 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */ 9422 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */ 9423 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */ 9424 9425 #define SAI_xFRCR_FSDEF_Pos (16U) 9426 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */ 9427 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */ 9428 #define SAI_xFRCR_FSPOL_Pos (17U) 9429 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */ 9430 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */ 9431 #define SAI_xFRCR_FSOFF_Pos (18U) 9432 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */ 9433 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */ 9434 9435 /****************** Bit definition for SAI_xSLOTR register *******************/ 9436 #define SAI_xSLOTR_FBOFF_Pos (0U) 9437 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */ 9438 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */ 9439 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */ 9440 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */ 9441 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */ 9442 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */ 9443 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */ 9444 9445 #define SAI_xSLOTR_SLOTSZ_Pos (6U) 9446 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */ 9447 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */ 9448 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */ 9449 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */ 9450 9451 #define SAI_xSLOTR_NBSLOT_Pos (8U) 9452 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */ 9453 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */ 9454 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */ 9455 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */ 9456 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */ 9457 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */ 9458 9459 #define SAI_xSLOTR_SLOTEN_Pos (16U) 9460 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */ 9461 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */ 9462 9463 /******************* Bit definition for SAI_xIMR register *******************/ 9464 #define SAI_xIMR_OVRUDRIE_Pos (0U) 9465 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */ 9466 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */ 9467 #define SAI_xIMR_MUTEDETIE_Pos (1U) 9468 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */ 9469 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */ 9470 #define SAI_xIMR_WCKCFGIE_Pos (2U) 9471 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */ 9472 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */ 9473 #define SAI_xIMR_FREQIE_Pos (3U) 9474 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */ 9475 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */ 9476 #define SAI_xIMR_CNRDYIE_Pos (4U) 9477 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */ 9478 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */ 9479 #define SAI_xIMR_AFSDETIE_Pos (5U) 9480 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */ 9481 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */ 9482 #define SAI_xIMR_LFSDETIE_Pos (6U) 9483 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */ 9484 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */ 9485 9486 /******************** Bit definition for SAI_xSR register *******************/ 9487 #define SAI_xSR_OVRUDR_Pos (0U) 9488 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */ 9489 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */ 9490 #define SAI_xSR_MUTEDET_Pos (1U) 9491 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */ 9492 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */ 9493 #define SAI_xSR_WCKCFG_Pos (2U) 9494 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */ 9495 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */ 9496 #define SAI_xSR_FREQ_Pos (3U) 9497 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */ 9498 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */ 9499 #define SAI_xSR_CNRDY_Pos (4U) 9500 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */ 9501 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */ 9502 #define SAI_xSR_AFSDET_Pos (5U) 9503 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */ 9504 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */ 9505 #define SAI_xSR_LFSDET_Pos (6U) 9506 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */ 9507 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */ 9508 9509 #define SAI_xSR_FLVL_Pos (16U) 9510 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */ 9511 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */ 9512 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */ 9513 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */ 9514 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */ 9515 9516 /****************** Bit definition for SAI_xCLRFR register ******************/ 9517 #define SAI_xCLRFR_COVRUDR_Pos (0U) 9518 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */ 9519 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */ 9520 #define SAI_xCLRFR_CMUTEDET_Pos (1U) 9521 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */ 9522 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */ 9523 #define SAI_xCLRFR_CWCKCFG_Pos (2U) 9524 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */ 9525 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */ 9526 #define SAI_xCLRFR_CFREQ_Pos (3U) 9527 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */ 9528 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */ 9529 #define SAI_xCLRFR_CCNRDY_Pos (4U) 9530 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */ 9531 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */ 9532 #define SAI_xCLRFR_CAFSDET_Pos (5U) 9533 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */ 9534 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */ 9535 #define SAI_xCLRFR_CLFSDET_Pos (6U) 9536 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */ 9537 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */ 9538 9539 /****************** Bit definition for SAI_xDR register ******************/ 9540 #define SAI_xDR_DATA_Pos (0U) 9541 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */ 9542 #define SAI_xDR_DATA SAI_xDR_DATA_Msk 9543 9544 /****************** Bit definition for SAI_PDMCR register *******************/ 9545 #define SAI_PDMCR_PDMEN_Pos (0U) 9546 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */ 9547 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */ 9548 9549 #define SAI_PDMCR_MICNBR_Pos (4U) 9550 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */ 9551 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */ 9552 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */ 9553 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */ 9554 9555 #define SAI_PDMCR_CKEN1_Pos (8U) 9556 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */ 9557 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */ 9558 #define SAI_PDMCR_CKEN2_Pos (9U) 9559 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */ 9560 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */ 9561 #define SAI_PDMCR_CKEN3_Pos (10U) 9562 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */ 9563 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */ 9564 #define SAI_PDMCR_CKEN4_Pos (11U) 9565 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */ 9566 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */ 9567 9568 /****************** Bit definition for SAI_PDMDLY register ******************/ 9569 #define SAI_PDMDLY_DLYM1L_Pos (0U) 9570 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */ 9571 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */ 9572 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */ 9573 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */ 9574 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */ 9575 9576 #define SAI_PDMDLY_DLYM1R_Pos (4U) 9577 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */ 9578 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */ 9579 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */ 9580 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */ 9581 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */ 9582 9583 #define SAI_PDMDLY_DLYM2L_Pos (8U) 9584 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */ 9585 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */ 9586 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */ 9587 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */ 9588 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */ 9589 9590 #define SAI_PDMDLY_DLYM2R_Pos (12U) 9591 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */ 9592 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */ 9593 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */ 9594 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */ 9595 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */ 9596 9597 #define SAI_PDMDLY_DLYM3L_Pos (16U) 9598 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */ 9599 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */ 9600 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */ 9601 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */ 9602 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */ 9603 9604 #define SAI_PDMDLY_DLYM3R_Pos (20U) 9605 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */ 9606 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */ 9607 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */ 9608 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */ 9609 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */ 9610 9611 #define SAI_PDMDLY_DLYM4L_Pos (24U) 9612 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */ 9613 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */ 9614 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */ 9615 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */ 9616 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */ 9617 9618 #define SAI_PDMDLY_DLYM4R_Pos (28U) 9619 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */ 9620 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */ 9621 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */ 9622 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */ 9623 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */ 9624 9625 9626 /******************************************************************************/ 9627 /* */ 9628 /* Serial Peripheral Interface (SPI) */ 9629 /* */ 9630 /******************************************************************************/ 9631 /* 9632 * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie) 9633 */ 9634 #define SPI_I2S_SUPPORT /*!< I2S support */ 9635 9636 /******************* Bit definition for SPI_CR1 register ********************/ 9637 #define SPI_CR1_CPHA_Pos (0U) 9638 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 9639 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ 9640 #define SPI_CR1_CPOL_Pos (1U) 9641 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 9642 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ 9643 #define SPI_CR1_MSTR_Pos (2U) 9644 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 9645 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ 9646 9647 #define SPI_CR1_BR_Pos (3U) 9648 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 9649 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ 9650 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 9651 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 9652 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 9653 9654 #define SPI_CR1_SPE_Pos (6U) 9655 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 9656 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ 9657 #define SPI_CR1_LSBFIRST_Pos (7U) 9658 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 9659 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ 9660 #define SPI_CR1_SSI_Pos (8U) 9661 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 9662 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ 9663 #define SPI_CR1_SSM_Pos (9U) 9664 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 9665 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ 9666 #define SPI_CR1_RXONLY_Pos (10U) 9667 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 9668 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ 9669 #define SPI_CR1_CRCL_Pos (11U) 9670 #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ 9671 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ 9672 #define SPI_CR1_CRCNEXT_Pos (12U) 9673 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 9674 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ 9675 #define SPI_CR1_CRCEN_Pos (13U) 9676 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 9677 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ 9678 #define SPI_CR1_BIDIOE_Pos (14U) 9679 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 9680 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ 9681 #define SPI_CR1_BIDIMODE_Pos (15U) 9682 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 9683 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ 9684 9685 /******************* Bit definition for SPI_CR2 register ********************/ 9686 #define SPI_CR2_RXDMAEN_Pos (0U) 9687 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 9688 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 9689 #define SPI_CR2_TXDMAEN_Pos (1U) 9690 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 9691 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 9692 #define SPI_CR2_SSOE_Pos (2U) 9693 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 9694 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 9695 #define SPI_CR2_NSSP_Pos (3U) 9696 #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ 9697 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ 9698 #define SPI_CR2_FRF_Pos (4U) 9699 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 9700 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 9701 #define SPI_CR2_ERRIE_Pos (5U) 9702 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 9703 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 9704 #define SPI_CR2_RXNEIE_Pos (6U) 9705 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 9706 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 9707 #define SPI_CR2_TXEIE_Pos (7U) 9708 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 9709 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 9710 #define SPI_CR2_DS_Pos (8U) 9711 #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ 9712 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ 9713 #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */ 9714 #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */ 9715 #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */ 9716 #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */ 9717 #define SPI_CR2_FRXTH_Pos (12U) 9718 #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ 9719 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ 9720 #define SPI_CR2_LDMARX_Pos (13U) 9721 #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ 9722 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ 9723 #define SPI_CR2_LDMATX_Pos (14U) 9724 #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ 9725 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ 9726 9727 /******************** Bit definition for SPI_SR register ********************/ 9728 #define SPI_SR_RXNE_Pos (0U) 9729 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 9730 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 9731 #define SPI_SR_TXE_Pos (1U) 9732 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 9733 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 9734 #define SPI_SR_CHSIDE_Pos (2U) 9735 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 9736 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 9737 #define SPI_SR_UDR_Pos (3U) 9738 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 9739 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 9740 #define SPI_SR_CRCERR_Pos (4U) 9741 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 9742 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 9743 #define SPI_SR_MODF_Pos (5U) 9744 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 9745 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 9746 #define SPI_SR_OVR_Pos (6U) 9747 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 9748 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 9749 #define SPI_SR_BSY_Pos (7U) 9750 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 9751 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 9752 #define SPI_SR_FRE_Pos (8U) 9753 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 9754 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 9755 #define SPI_SR_FRLVL_Pos (9U) 9756 #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ 9757 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ 9758 #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ 9759 #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ 9760 #define SPI_SR_FTLVL_Pos (11U) 9761 #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ 9762 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ 9763 #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ 9764 #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ 9765 9766 /******************** Bit definition for SPI_DR register ********************/ 9767 #define SPI_DR_DR_Pos (0U) 9768 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 9769 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ 9770 9771 /******************* Bit definition for SPI_CRCPR register ******************/ 9772 #define SPI_CRCPR_CRCPOLY_Pos (0U) 9773 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 9774 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ 9775 9776 /****************** Bit definition for SPI_RXCRCR register ******************/ 9777 #define SPI_RXCRCR_RXCRC_Pos (0U) 9778 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 9779 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ 9780 9781 /****************** Bit definition for SPI_TXCRCR register ******************/ 9782 #define SPI_TXCRCR_TXCRC_Pos (0U) 9783 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 9784 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ 9785 9786 /****************** Bit definition for SPI_I2SCFGR register *****************/ 9787 #define SPI_I2SCFGR_CHLEN_Pos (0U) 9788 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 9789 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 9790 #define SPI_I2SCFGR_DATLEN_Pos (1U) 9791 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 9792 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 9793 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 9794 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 9795 #define SPI_I2SCFGR_CKPOL_Pos (3U) 9796 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 9797 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 9798 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 9799 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 9800 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 9801 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 9802 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 9803 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 9804 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 9805 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 9806 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 9807 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 9808 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 9809 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 9810 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 9811 #define SPI_I2SCFGR_I2SE_Pos (10U) 9812 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 9813 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 9814 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 9815 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 9816 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 9817 #define SPI_I2SCFGR_ASTRTEN_Pos (12U) 9818 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */ 9819 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */ 9820 9821 /****************** Bit definition for SPI_I2SPR register *******************/ 9822 #define SPI_I2SPR_I2SDIV_Pos (0U) 9823 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 9824 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 9825 #define SPI_I2SPR_ODD_Pos (8U) 9826 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 9827 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 9828 #define SPI_I2SPR_MCKOE_Pos (9U) 9829 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 9830 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 9831 9832 /******************************************************************************/ 9833 /* */ 9834 /* SYSCFG */ 9835 /* */ 9836 /******************************************************************************/ 9837 /****************** Bit definition for SYSCFG_MEMRMP register ***************/ 9838 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) 9839 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */ 9840 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 9841 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ 9842 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ 9843 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */ 9844 9845 #define SYSCFG_MEMRMP_FB_MODE_Pos (8U) 9846 #define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */ 9847 #define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */ 9848 9849 /****************** Bit definition for SYSCFG_CFGR1 register ******************/ 9850 #define SYSCFG_CFGR1_BOOSTEN_Pos (8U) 9851 #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */ 9852 #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */ 9853 #define SYSCFG_CFGR1_ANASWVDD_Pos (9U) 9854 #define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */ 9855 #define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */ 9856 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) 9857 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */ 9858 #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ 9859 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) 9860 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */ 9861 #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ 9862 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) 9863 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */ 9864 #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ 9865 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) 9866 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */ 9867 #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ 9868 #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) 9869 #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ 9870 #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ 9871 #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U) 9872 #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */ 9873 #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */ 9874 #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U) 9875 #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */ 9876 #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */ 9877 #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */ 9878 #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */ 9879 #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */ 9880 #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */ 9881 #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */ 9882 #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */ 9883 9884 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 9885 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 9886 #define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 9887 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */ 9888 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 9889 #define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 9890 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */ 9891 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 9892 #define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 9893 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */ 9894 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 9895 #define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 9896 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */ 9897 9898 /** 9899 * @brief EXTI0 configuration 9900 */ 9901 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */ 9902 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ 9903 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ 9904 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ 9905 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ 9906 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ 9907 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ 9908 9909 /** 9910 * @brief EXTI1 configuration 9911 */ 9912 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */ 9913 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ 9914 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ 9915 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ 9916 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ 9917 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ 9918 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ 9919 9920 /** 9921 * @brief EXTI2 configuration 9922 */ 9923 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */ 9924 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ 9925 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ 9926 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ 9927 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ 9928 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ 9929 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ 9930 9931 /** 9932 * @brief EXTI3 configuration 9933 */ 9934 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */ 9935 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ 9936 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ 9937 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ 9938 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ 9939 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ 9940 #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ 9941 9942 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ 9943 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 9944 #define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 9945 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */ 9946 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 9947 #define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 9948 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */ 9949 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 9950 #define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 9951 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */ 9952 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 9953 #define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 9954 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */ 9955 9956 /** 9957 * @brief EXTI4 configuration 9958 */ 9959 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */ 9960 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ 9961 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ 9962 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ 9963 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ 9964 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ 9965 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ 9966 9967 /** 9968 * @brief EXTI5 configuration 9969 */ 9970 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */ 9971 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ 9972 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ 9973 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ 9974 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ 9975 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ 9976 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ 9977 9978 /** 9979 * @brief EXTI6 configuration 9980 */ 9981 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */ 9982 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ 9983 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ 9984 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ 9985 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ 9986 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ 9987 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ 9988 9989 /** 9990 * @brief EXTI7 configuration 9991 */ 9992 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */ 9993 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ 9994 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ 9995 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ 9996 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ 9997 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ 9998 #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ 9999 10000 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ 10001 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 10002 #define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 10003 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */ 10004 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 10005 #define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 10006 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */ 10007 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 10008 #define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 10009 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */ 10010 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 10011 #define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 10012 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */ 10013 10014 /** 10015 * @brief EXTI8 configuration 10016 */ 10017 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */ 10018 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ 10019 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ 10020 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ 10021 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ 10022 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ 10023 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ 10024 10025 /** 10026 * @brief EXTI9 configuration 10027 */ 10028 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */ 10029 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ 10030 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ 10031 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ 10032 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ 10033 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ 10034 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ 10035 10036 /** 10037 * @brief EXTI10 configuration 10038 */ 10039 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */ 10040 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ 10041 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ 10042 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ 10043 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ 10044 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ 10045 10046 /** 10047 * @brief EXTI11 configuration 10048 */ 10049 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */ 10050 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ 10051 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ 10052 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ 10053 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ 10054 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ 10055 10056 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ 10057 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 10058 #define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ 10059 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */ 10060 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 10061 #define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */ 10062 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */ 10063 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 10064 #define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */ 10065 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */ 10066 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 10067 #define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */ 10068 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */ 10069 10070 /** 10071 * @brief EXTI12 configuration 10072 */ 10073 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */ 10074 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ 10075 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ 10076 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ 10077 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ 10078 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ 10079 10080 /** 10081 * @brief EXTI13 configuration 10082 */ 10083 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */ 10084 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ 10085 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ 10086 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ 10087 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ 10088 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ 10089 10090 /** 10091 * @brief EXTI14 configuration 10092 */ 10093 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */ 10094 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ 10095 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ 10096 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ 10097 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ 10098 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ 10099 10100 /** 10101 * @brief EXTI15 configuration 10102 */ 10103 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */ 10104 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ 10105 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ 10106 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ 10107 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ 10108 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ 10109 10110 /****************** Bit definition for SYSCFG_SCSR register ****************/ 10111 #define SYSCFG_SCSR_CCMER_Pos (0U) 10112 #define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */ 10113 #define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */ 10114 #define SYSCFG_SCSR_CCMBSY_Pos (1U) 10115 #define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */ 10116 #define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */ 10117 10118 /****************** Bit definition for SYSCFG_CFGR2 register ****************/ 10119 #define SYSCFG_CFGR2_CLL_Pos (0U) 10120 #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */ 10121 #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */ 10122 #define SYSCFG_CFGR2_SPL_Pos (1U) 10123 #define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */ 10124 #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/ 10125 #define SYSCFG_CFGR2_PVDL_Pos (2U) 10126 #define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */ 10127 #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */ 10128 #define SYSCFG_CFGR2_ECCL_Pos (3U) 10129 #define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */ 10130 #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/ 10131 #define SYSCFG_CFGR2_SPF_Pos (8U) 10132 #define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */ 10133 #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */ 10134 10135 /****************** Bit definition for SYSCFG_SWPR register ****************/ 10136 #define SYSCFG_SWPR_PAGE0_Pos (0U) 10137 #define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */ 10138 #define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */ 10139 #define SYSCFG_SWPR_PAGE1_Pos (1U) 10140 #define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */ 10141 #define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */ 10142 #define SYSCFG_SWPR_PAGE2_Pos (2U) 10143 #define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */ 10144 #define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */ 10145 #define SYSCFG_SWPR_PAGE3_Pos (3U) 10146 #define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */ 10147 #define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */ 10148 #define SYSCFG_SWPR_PAGE4_Pos (4U) 10149 #define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */ 10150 #define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */ 10151 #define SYSCFG_SWPR_PAGE5_Pos (5U) 10152 #define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */ 10153 #define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */ 10154 #define SYSCFG_SWPR_PAGE6_Pos (6U) 10155 #define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */ 10156 #define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */ 10157 #define SYSCFG_SWPR_PAGE7_Pos (7U) 10158 #define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */ 10159 #define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */ 10160 #define SYSCFG_SWPR_PAGE8_Pos (8U) 10161 #define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */ 10162 #define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */ 10163 #define SYSCFG_SWPR_PAGE9_Pos (9U) 10164 #define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */ 10165 #define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */ 10166 /****************** Bit definition for SYSCFG_SKR register ****************/ 10167 #define SYSCFG_SKR_KEY_Pos (0U) 10168 #define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */ 10169 #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */ 10170 10171 /******************************************************************************/ 10172 /* */ 10173 /* TIM */ 10174 /* */ 10175 /******************************************************************************/ 10176 /******************* Bit definition for TIM_CR1 register ********************/ 10177 #define TIM_CR1_CEN_Pos (0U) 10178 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 10179 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 10180 #define TIM_CR1_UDIS_Pos (1U) 10181 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 10182 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 10183 #define TIM_CR1_URS_Pos (2U) 10184 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 10185 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 10186 #define TIM_CR1_OPM_Pos (3U) 10187 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 10188 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 10189 #define TIM_CR1_DIR_Pos (4U) 10190 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 10191 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 10192 10193 #define TIM_CR1_CMS_Pos (5U) 10194 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 10195 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 10196 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 10197 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 10198 10199 #define TIM_CR1_ARPE_Pos (7U) 10200 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 10201 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 10202 10203 #define TIM_CR1_CKD_Pos (8U) 10204 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 10205 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 10206 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 10207 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 10208 10209 #define TIM_CR1_UIFREMAP_Pos (11U) 10210 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ 10211 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ 10212 10213 #define TIM_CR1_DITHEN_Pos (12U) 10214 #define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */ 10215 #define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */ 10216 10217 /******************* Bit definition for TIM_CR2 register ********************/ 10218 #define TIM_CR2_CCPC_Pos (0U) 10219 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 10220 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 10221 #define TIM_CR2_CCUS_Pos (2U) 10222 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 10223 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 10224 #define TIM_CR2_CCDS_Pos (3U) 10225 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 10226 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 10227 10228 #define TIM_CR2_MMS_Pos (4U) 10229 #define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */ 10230 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */ 10231 #define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 10232 #define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 10233 #define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 10234 #define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */ 10235 10236 #define TIM_CR2_TI1S_Pos (7U) 10237 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 10238 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 10239 #define TIM_CR2_OIS1_Pos (8U) 10240 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 10241 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 10242 #define TIM_CR2_OIS1N_Pos (9U) 10243 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 10244 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 10245 #define TIM_CR2_OIS2_Pos (10U) 10246 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 10247 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 10248 #define TIM_CR2_OIS2N_Pos (11U) 10249 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 10250 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 10251 #define TIM_CR2_OIS3_Pos (12U) 10252 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 10253 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 10254 #define TIM_CR2_OIS3N_Pos (13U) 10255 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 10256 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 10257 #define TIM_CR2_OIS4_Pos (14U) 10258 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 10259 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 10260 #define TIM_CR2_OIS4N_Pos (15U) 10261 #define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */ 10262 #define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */ 10263 #define TIM_CR2_OIS5_Pos (16U) 10264 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ 10265 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */ 10266 #define TIM_CR2_OIS6_Pos (18U) 10267 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ 10268 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */ 10269 10270 #define TIM_CR2_MMS2_Pos (20U) 10271 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ 10272 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 10273 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ 10274 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ 10275 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ 10276 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ 10277 10278 /******************* Bit definition for TIM_SMCR register *******************/ 10279 #define TIM_SMCR_SMS_Pos (0U) 10280 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ 10281 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 10282 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 10283 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 10284 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 10285 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */ 10286 10287 #define TIM_SMCR_OCCS_Pos (3U) 10288 #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 10289 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 10290 10291 #define TIM_SMCR_TS_Pos (4U) 10292 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */ 10293 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 10294 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 10295 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 10296 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 10297 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */ 10298 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */ 10299 10300 #define TIM_SMCR_MSM_Pos (7U) 10301 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 10302 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 10303 10304 #define TIM_SMCR_ETF_Pos (8U) 10305 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 10306 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 10307 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 10308 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 10309 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 10310 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 10311 10312 #define TIM_SMCR_ETPS_Pos (12U) 10313 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 10314 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 10315 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 10316 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 10317 10318 #define TIM_SMCR_ECE_Pos (14U) 10319 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 10320 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 10321 #define TIM_SMCR_ETP_Pos (15U) 10322 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 10323 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 10324 10325 #define TIM_SMCR_SMSPE_Pos (24U) 10326 #define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */ 10327 #define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */ 10328 10329 #define TIM_SMCR_SMSPS_Pos (25U) 10330 #define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */ 10331 #define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */ 10332 10333 /******************* Bit definition for TIM_DIER register *******************/ 10334 #define TIM_DIER_UIE_Pos (0U) 10335 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 10336 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 10337 #define TIM_DIER_CC1IE_Pos (1U) 10338 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 10339 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 10340 #define TIM_DIER_CC2IE_Pos (2U) 10341 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 10342 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 10343 #define TIM_DIER_CC3IE_Pos (3U) 10344 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 10345 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 10346 #define TIM_DIER_CC4IE_Pos (4U) 10347 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 10348 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 10349 #define TIM_DIER_COMIE_Pos (5U) 10350 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 10351 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 10352 #define TIM_DIER_TIE_Pos (6U) 10353 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 10354 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 10355 #define TIM_DIER_BIE_Pos (7U) 10356 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 10357 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 10358 #define TIM_DIER_UDE_Pos (8U) 10359 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 10360 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 10361 #define TIM_DIER_CC1DE_Pos (9U) 10362 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 10363 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 10364 #define TIM_DIER_CC2DE_Pos (10U) 10365 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 10366 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 10367 #define TIM_DIER_CC3DE_Pos (11U) 10368 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 10369 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 10370 #define TIM_DIER_CC4DE_Pos (12U) 10371 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 10372 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 10373 #define TIM_DIER_COMDE_Pos (13U) 10374 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 10375 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 10376 #define TIM_DIER_TDE_Pos (14U) 10377 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 10378 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 10379 #define TIM_DIER_IDXIE_Pos (20U) 10380 #define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */ 10381 #define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */ 10382 #define TIM_DIER_DIRIE_Pos (21U) 10383 #define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */ 10384 #define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */ 10385 #define TIM_DIER_IERRIE_Pos (22U) 10386 #define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */ 10387 #define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */ 10388 #define TIM_DIER_TERRIE_Pos (23U) 10389 #define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */ 10390 #define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */ 10391 10392 /******************** Bit definition for TIM_SR register ********************/ 10393 #define TIM_SR_UIF_Pos (0U) 10394 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 10395 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 10396 #define TIM_SR_CC1IF_Pos (1U) 10397 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 10398 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 10399 #define TIM_SR_CC2IF_Pos (2U) 10400 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 10401 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 10402 #define TIM_SR_CC3IF_Pos (3U) 10403 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 10404 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 10405 #define TIM_SR_CC4IF_Pos (4U) 10406 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 10407 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 10408 #define TIM_SR_COMIF_Pos (5U) 10409 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 10410 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 10411 #define TIM_SR_TIF_Pos (6U) 10412 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 10413 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 10414 #define TIM_SR_BIF_Pos (7U) 10415 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 10416 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 10417 #define TIM_SR_B2IF_Pos (8U) 10418 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ 10419 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */ 10420 #define TIM_SR_CC1OF_Pos (9U) 10421 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 10422 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 10423 #define TIM_SR_CC2OF_Pos (10U) 10424 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 10425 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 10426 #define TIM_SR_CC3OF_Pos (11U) 10427 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 10428 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 10429 #define TIM_SR_CC4OF_Pos (12U) 10430 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 10431 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 10432 #define TIM_SR_SBIF_Pos (13U) 10433 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */ 10434 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */ 10435 #define TIM_SR_CC5IF_Pos (16U) 10436 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ 10437 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ 10438 #define TIM_SR_CC6IF_Pos (17U) 10439 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ 10440 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ 10441 #define TIM_SR_IDXF_Pos (20U) 10442 #define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */ 10443 #define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */ 10444 #define TIM_SR_DIRF_Pos (21U) 10445 #define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */ 10446 #define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */ 10447 #define TIM_SR_IERRF_Pos (22U) 10448 #define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */ 10449 #define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */ 10450 #define TIM_SR_TERRF_Pos (23U) 10451 #define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */ 10452 #define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */ 10453 10454 /******************* Bit definition for TIM_EGR register ********************/ 10455 #define TIM_EGR_UG_Pos (0U) 10456 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 10457 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 10458 #define TIM_EGR_CC1G_Pos (1U) 10459 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 10460 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 10461 #define TIM_EGR_CC2G_Pos (2U) 10462 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 10463 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 10464 #define TIM_EGR_CC3G_Pos (3U) 10465 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 10466 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 10467 #define TIM_EGR_CC4G_Pos (4U) 10468 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 10469 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 10470 #define TIM_EGR_COMG_Pos (5U) 10471 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 10472 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 10473 #define TIM_EGR_TG_Pos (6U) 10474 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 10475 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 10476 #define TIM_EGR_BG_Pos (7U) 10477 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 10478 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 10479 #define TIM_EGR_B2G_Pos (8U) 10480 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ 10481 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */ 10482 10483 10484 /****************** Bit definition for TIM_CCMR1 register *******************/ 10485 #define TIM_CCMR1_CC1S_Pos (0U) 10486 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 10487 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 10488 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 10489 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 10490 10491 #define TIM_CCMR1_OC1FE_Pos (2U) 10492 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 10493 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 10494 #define TIM_CCMR1_OC1PE_Pos (3U) 10495 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 10496 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 10497 10498 #define TIM_CCMR1_OC1M_Pos (4U) 10499 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ 10500 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 10501 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 10502 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 10503 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 10504 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */ 10505 10506 #define TIM_CCMR1_OC1CE_Pos (7U) 10507 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 10508 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */ 10509 10510 #define TIM_CCMR1_CC2S_Pos (8U) 10511 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 10512 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 10513 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 10514 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 10515 10516 #define TIM_CCMR1_OC2FE_Pos (10U) 10517 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 10518 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 10519 #define TIM_CCMR1_OC2PE_Pos (11U) 10520 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 10521 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 10522 10523 #define TIM_CCMR1_OC2M_Pos (12U) 10524 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ 10525 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 10526 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 10527 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 10528 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 10529 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */ 10530 10531 #define TIM_CCMR1_OC2CE_Pos (15U) 10532 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 10533 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 10534 10535 /*----------------------------------------------------------------------------*/ 10536 #define TIM_CCMR1_IC1PSC_Pos (2U) 10537 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 10538 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 10539 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 10540 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 10541 10542 #define TIM_CCMR1_IC1F_Pos (4U) 10543 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 10544 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 10545 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 10546 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 10547 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 10548 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 10549 10550 #define TIM_CCMR1_IC2PSC_Pos (10U) 10551 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 10552 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 10553 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 10554 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 10555 10556 #define TIM_CCMR1_IC2F_Pos (12U) 10557 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 10558 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 10559 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 10560 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 10561 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 10562 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 10563 10564 /****************** Bit definition for TIM_CCMR2 register *******************/ 10565 #define TIM_CCMR2_CC3S_Pos (0U) 10566 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 10567 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 10568 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 10569 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 10570 10571 #define TIM_CCMR2_OC3FE_Pos (2U) 10572 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 10573 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 10574 #define TIM_CCMR2_OC3PE_Pos (3U) 10575 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 10576 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 10577 10578 #define TIM_CCMR2_OC3M_Pos (4U) 10579 #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ 10580 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 10581 #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 10582 #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 10583 #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 10584 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */ 10585 10586 #define TIM_CCMR2_OC3CE_Pos (7U) 10587 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 10588 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 10589 10590 #define TIM_CCMR2_CC4S_Pos (8U) 10591 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 10592 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 10593 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 10594 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 10595 10596 #define TIM_CCMR2_OC4FE_Pos (10U) 10597 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 10598 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 10599 #define TIM_CCMR2_OC4PE_Pos (11U) 10600 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 10601 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 10602 10603 #define TIM_CCMR2_OC4M_Pos (12U) 10604 #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ 10605 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 10606 #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 10607 #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 10608 #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 10609 #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */ 10610 10611 #define TIM_CCMR2_OC4CE_Pos (15U) 10612 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 10613 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 10614 10615 /*----------------------------------------------------------------------------*/ 10616 #define TIM_CCMR2_IC3PSC_Pos (2U) 10617 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 10618 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 10619 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 10620 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 10621 10622 #define TIM_CCMR2_IC3F_Pos (4U) 10623 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 10624 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 10625 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 10626 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 10627 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 10628 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 10629 10630 #define TIM_CCMR2_IC4PSC_Pos (10U) 10631 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 10632 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 10633 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 10634 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 10635 10636 #define TIM_CCMR2_IC4F_Pos (12U) 10637 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 10638 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 10639 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 10640 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 10641 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 10642 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 10643 10644 /****************** Bit definition for TIM_CCMR3 register *******************/ 10645 #define TIM_CCMR3_OC5FE_Pos (2U) 10646 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ 10647 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ 10648 #define TIM_CCMR3_OC5PE_Pos (3U) 10649 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ 10650 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ 10651 10652 #define TIM_CCMR3_OC5M_Pos (4U) 10653 #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ 10654 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */ 10655 #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ 10656 #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ 10657 #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ 10658 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ 10659 10660 #define TIM_CCMR3_OC5CE_Pos (7U) 10661 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ 10662 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ 10663 10664 #define TIM_CCMR3_OC6FE_Pos (10U) 10665 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ 10666 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ 10667 #define TIM_CCMR3_OC6PE_Pos (11U) 10668 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ 10669 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ 10670 10671 #define TIM_CCMR3_OC6M_Pos (12U) 10672 #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ 10673 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */ 10674 #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ 10675 #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ 10676 #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ 10677 #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ 10678 10679 #define TIM_CCMR3_OC6CE_Pos (15U) 10680 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ 10681 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ 10682 10683 /******************* Bit definition for TIM_CCER register *******************/ 10684 #define TIM_CCER_CC1E_Pos (0U) 10685 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 10686 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 10687 #define TIM_CCER_CC1P_Pos (1U) 10688 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 10689 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 10690 #define TIM_CCER_CC1NE_Pos (2U) 10691 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 10692 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 10693 #define TIM_CCER_CC1NP_Pos (3U) 10694 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 10695 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 10696 #define TIM_CCER_CC2E_Pos (4U) 10697 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 10698 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 10699 #define TIM_CCER_CC2P_Pos (5U) 10700 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 10701 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 10702 #define TIM_CCER_CC2NE_Pos (6U) 10703 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 10704 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 10705 #define TIM_CCER_CC2NP_Pos (7U) 10706 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 10707 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 10708 #define TIM_CCER_CC3E_Pos (8U) 10709 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 10710 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 10711 #define TIM_CCER_CC3P_Pos (9U) 10712 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 10713 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 10714 #define TIM_CCER_CC3NE_Pos (10U) 10715 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 10716 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 10717 #define TIM_CCER_CC3NP_Pos (11U) 10718 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 10719 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 10720 #define TIM_CCER_CC4E_Pos (12U) 10721 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 10722 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 10723 #define TIM_CCER_CC4P_Pos (13U) 10724 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 10725 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 10726 #define TIM_CCER_CC4NE_Pos (14U) 10727 #define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */ 10728 #define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */ 10729 #define TIM_CCER_CC4NP_Pos (15U) 10730 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 10731 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 10732 #define TIM_CCER_CC5E_Pos (16U) 10733 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ 10734 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ 10735 #define TIM_CCER_CC5P_Pos (17U) 10736 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ 10737 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ 10738 #define TIM_CCER_CC6E_Pos (20U) 10739 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ 10740 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ 10741 #define TIM_CCER_CC6P_Pos (21U) 10742 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ 10743 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ 10744 10745 /******************* Bit definition for TIM_CNT register ********************/ 10746 #define TIM_CNT_CNT_Pos (0U) 10747 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 10748 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 10749 #define TIM_CNT_UIFCPY_Pos (31U) 10750 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ 10751 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */ 10752 10753 /******************* Bit definition for TIM_PSC register ********************/ 10754 #define TIM_PSC_PSC_Pos (0U) 10755 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 10756 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 10757 10758 /******************* Bit definition for TIM_ARR register ********************/ 10759 #define TIM_ARR_ARR_Pos (0U) 10760 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 10761 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */ 10762 10763 /******************* Bit definition for TIM_RCR register ********************/ 10764 #define TIM_RCR_REP_Pos (0U) 10765 #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ 10766 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 10767 10768 /******************* Bit definition for TIM_CCR1 register *******************/ 10769 #define TIM_CCR1_CCR1_Pos (0U) 10770 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 10771 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 10772 10773 /******************* Bit definition for TIM_CCR2 register *******************/ 10774 #define TIM_CCR2_CCR2_Pos (0U) 10775 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 10776 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 10777 10778 /******************* Bit definition for TIM_CCR3 register *******************/ 10779 #define TIM_CCR3_CCR3_Pos (0U) 10780 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 10781 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 10782 10783 /******************* Bit definition for TIM_CCR4 register *******************/ 10784 #define TIM_CCR4_CCR4_Pos (0U) 10785 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 10786 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 10787 10788 /******************* Bit definition for TIM_CCR5 register *******************/ 10789 #define TIM_CCR5_CCR5_Pos (0U) 10790 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ 10791 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ 10792 #define TIM_CCR5_GC5C1_Pos (29U) 10793 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ 10794 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ 10795 #define TIM_CCR5_GC5C2_Pos (30U) 10796 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ 10797 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ 10798 #define TIM_CCR5_GC5C3_Pos (31U) 10799 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ 10800 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ 10801 10802 /******************* Bit definition for TIM_CCR6 register *******************/ 10803 #define TIM_CCR6_CCR6_Pos (0U) 10804 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ 10805 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ 10806 10807 /******************* Bit definition for TIM_BDTR register *******************/ 10808 #define TIM_BDTR_DTG_Pos (0U) 10809 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 10810 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 10811 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 10812 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 10813 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 10814 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 10815 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 10816 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 10817 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 10818 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 10819 10820 #define TIM_BDTR_LOCK_Pos (8U) 10821 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 10822 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 10823 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 10824 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 10825 10826 #define TIM_BDTR_OSSI_Pos (10U) 10827 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 10828 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 10829 #define TIM_BDTR_OSSR_Pos (11U) 10830 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 10831 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 10832 #define TIM_BDTR_BKE_Pos (12U) 10833 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 10834 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */ 10835 #define TIM_BDTR_BKP_Pos (13U) 10836 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 10837 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */ 10838 #define TIM_BDTR_AOE_Pos (14U) 10839 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 10840 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 10841 #define TIM_BDTR_MOE_Pos (15U) 10842 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 10843 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 10844 10845 #define TIM_BDTR_BKF_Pos (16U) 10846 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ 10847 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */ 10848 #define TIM_BDTR_BK2F_Pos (20U) 10849 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ 10850 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */ 10851 10852 #define TIM_BDTR_BK2E_Pos (24U) 10853 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ 10854 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */ 10855 #define TIM_BDTR_BK2P_Pos (25U) 10856 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ 10857 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */ 10858 10859 #define TIM_BDTR_BKDSRM_Pos (26U) 10860 #define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */ 10861 #define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */ 10862 #define TIM_BDTR_BK2DSRM_Pos (27U) 10863 #define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */ 10864 #define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */ 10865 10866 #define TIM_BDTR_BKBID_Pos (28U) 10867 #define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */ 10868 #define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */ 10869 #define TIM_BDTR_BK2BID_Pos (29U) 10870 #define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */ 10871 #define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */ 10872 10873 /******************* Bit definition for TIM_DCR register ********************/ 10874 #define TIM_DCR_DBA_Pos (0U) 10875 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 10876 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 10877 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 10878 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 10879 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 10880 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 10881 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 10882 10883 #define TIM_DCR_DBL_Pos (8U) 10884 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 10885 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 10886 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 10887 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 10888 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 10889 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 10890 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 10891 10892 /******************* Bit definition for TIM1_AF1 register *******************/ 10893 #define TIM1_AF1_BKINE_Pos (0U) 10894 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */ 10895 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */ 10896 #define TIM1_AF1_BKCMP1E_Pos (1U) 10897 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */ 10898 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */ 10899 #define TIM1_AF1_BKCMP2E_Pos (2U) 10900 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */ 10901 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */ 10902 #define TIM1_AF1_BKCMP3E_Pos (3U) 10903 #define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */ 10904 #define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */ 10905 #define TIM1_AF1_BKCMP4E_Pos (4U) 10906 #define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */ 10907 #define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */ 10908 #define TIM1_AF1_BKINP_Pos (9U) 10909 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */ 10910 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */ 10911 #define TIM1_AF1_BKCMP1P_Pos (10U) 10912 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */ 10913 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ 10914 #define TIM1_AF1_BKCMP2P_Pos (11U) 10915 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */ 10916 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ 10917 #define TIM1_AF1_BKCMP3P_Pos (12U) 10918 #define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */ 10919 #define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */ 10920 #define TIM1_AF1_BKCMP4P_Pos (13U) 10921 #define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */ 10922 #define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */ 10923 #define TIM1_AF1_ETRSEL_Pos (14U) 10924 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */ 10925 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */ 10926 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */ 10927 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */ 10928 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */ 10929 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */ 10930 10931 /******************* Bit definition for TIM1_AF2 register *********************/ 10932 #define TIM1_AF2_BK2INE_Pos (0U) 10933 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */ 10934 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */ 10935 #define TIM1_AF2_BK2CMP1E_Pos (1U) 10936 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */ 10937 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */ 10938 #define TIM1_AF2_BK2CMP2E_Pos (2U) 10939 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */ 10940 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */ 10941 #define TIM1_AF2_BK2CMP3E_Pos (3U) 10942 #define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */ 10943 #define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */ 10944 #define TIM1_AF2_BK2CMP4E_Pos (4U) 10945 #define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */ 10946 #define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */ 10947 #define TIM1_AF2_BK2INP_Pos (9U) 10948 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */ 10949 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */ 10950 #define TIM1_AF2_BK2CMP1P_Pos (10U) 10951 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */ 10952 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */ 10953 #define TIM1_AF2_BK2CMP2P_Pos (11U) 10954 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */ 10955 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */ 10956 #define TIM1_AF2_BK2CMP3P_Pos (12U) 10957 #define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */ 10958 #define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */ 10959 #define TIM1_AF2_BK2CMP4P_Pos (13U) 10960 #define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */ 10961 #define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */ 10962 #define TIM1_AF2_OCRSEL_Pos (16U) 10963 #define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */ 10964 #define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */ 10965 #define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */ 10966 #define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */ 10967 #define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */ 10968 10969 /******************* Bit definition for TIM_OR register *********************/ 10970 #define TIM_OR_HSE32EN_Pos (0U) 10971 #define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */ 10972 #define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */ 10973 10974 /******************* Bit definition for TIM_TISEL register *********************/ 10975 #define TIM_TISEL_TI1SEL_Pos (0U) 10976 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */ 10977 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/ 10978 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */ 10979 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */ 10980 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */ 10981 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */ 10982 10983 #define TIM_TISEL_TI2SEL_Pos (8U) 10984 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */ 10985 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/ 10986 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */ 10987 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */ 10988 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */ 10989 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */ 10990 10991 #define TIM_TISEL_TI3SEL_Pos (16U) 10992 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */ 10993 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/ 10994 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */ 10995 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */ 10996 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */ 10997 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */ 10998 10999 #define TIM_TISEL_TI4SEL_Pos (24U) 11000 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */ 11001 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/ 11002 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */ 11003 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */ 11004 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */ 11005 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */ 11006 11007 /******************* Bit definition for TIM_DTR2 register *********************/ 11008 #define TIM_DTR2_DTGF_Pos (0U) 11009 #define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */ 11010 #define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/ 11011 #define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */ 11012 #define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */ 11013 #define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */ 11014 #define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */ 11015 #define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */ 11016 #define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */ 11017 #define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */ 11018 #define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */ 11019 11020 #define TIM_DTR2_DTAE_Pos (16U) 11021 #define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */ 11022 #define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */ 11023 #define TIM_DTR2_DTPE_Pos (17U) 11024 #define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */ 11025 #define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */ 11026 11027 /******************* Bit definition for TIM_ECR register *********************/ 11028 #define TIM_ECR_IE_Pos (0U) 11029 #define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */ 11030 #define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */ 11031 11032 #define TIM_ECR_IDIR_Pos (1U) 11033 #define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */ 11034 #define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/ 11035 #define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */ 11036 #define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */ 11037 11038 #define TIM_ECR_FIDX_Pos (5U) 11039 #define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */ 11040 #define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */ 11041 11042 #define TIM_ECR_IPOS_Pos (6U) 11043 #define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */ 11044 #define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/ 11045 #define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */ 11046 #define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */ 11047 11048 #define TIM_ECR_PW_Pos (16U) 11049 #define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */ 11050 #define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/ 11051 #define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */ 11052 #define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */ 11053 #define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */ 11054 #define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */ 11055 #define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */ 11056 #define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */ 11057 #define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */ 11058 #define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */ 11059 11060 #define TIM_ECR_PWPRSC_Pos (24U) 11061 #define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */ 11062 #define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/ 11063 #define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */ 11064 #define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */ 11065 #define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */ 11066 11067 /******************* Bit definition for TIM_DMAR register *******************/ 11068 #define TIM_DMAR_DMAB_Pos (0U) 11069 #define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */ 11070 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 11071 11072 /******************************************************************************/ 11073 /* */ 11074 /* Low Power Timer (LPTIM) */ 11075 /* */ 11076 /******************************************************************************/ 11077 /****************** Bit definition for LPTIM_ISR register *******************/ 11078 #define LPTIM_ISR_CMPM_Pos (0U) 11079 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ 11080 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ 11081 #define LPTIM_ISR_ARRM_Pos (1U) 11082 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ 11083 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ 11084 #define LPTIM_ISR_EXTTRIG_Pos (2U) 11085 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ 11086 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ 11087 #define LPTIM_ISR_CMPOK_Pos (3U) 11088 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ 11089 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ 11090 #define LPTIM_ISR_ARROK_Pos (4U) 11091 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ 11092 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ 11093 #define LPTIM_ISR_UP_Pos (5U) 11094 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ 11095 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ 11096 #define LPTIM_ISR_DOWN_Pos (6U) 11097 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ 11098 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ 11099 11100 /****************** Bit definition for LPTIM_ICR register *******************/ 11101 #define LPTIM_ICR_CMPMCF_Pos (0U) 11102 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ 11103 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ 11104 #define LPTIM_ICR_ARRMCF_Pos (1U) 11105 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ 11106 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ 11107 #define LPTIM_ICR_EXTTRIGCF_Pos (2U) 11108 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ 11109 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ 11110 #define LPTIM_ICR_CMPOKCF_Pos (3U) 11111 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ 11112 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ 11113 #define LPTIM_ICR_ARROKCF_Pos (4U) 11114 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ 11115 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ 11116 #define LPTIM_ICR_UPCF_Pos (5U) 11117 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ 11118 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ 11119 #define LPTIM_ICR_DOWNCF_Pos (6U) 11120 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ 11121 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ 11122 11123 /****************** Bit definition for LPTIM_IER register ********************/ 11124 #define LPTIM_IER_CMPMIE_Pos (0U) 11125 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ 11126 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ 11127 #define LPTIM_IER_ARRMIE_Pos (1U) 11128 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ 11129 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ 11130 #define LPTIM_IER_EXTTRIGIE_Pos (2U) 11131 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ 11132 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ 11133 #define LPTIM_IER_CMPOKIE_Pos (3U) 11134 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ 11135 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ 11136 #define LPTIM_IER_ARROKIE_Pos (4U) 11137 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ 11138 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ 11139 #define LPTIM_IER_UPIE_Pos (5U) 11140 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ 11141 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ 11142 #define LPTIM_IER_DOWNIE_Pos (6U) 11143 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ 11144 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ 11145 11146 /****************** Bit definition for LPTIM_CFGR register *******************/ 11147 #define LPTIM_CFGR_CKSEL_Pos (0U) 11148 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ 11149 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ 11150 11151 #define LPTIM_CFGR_CKPOL_Pos (1U) 11152 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ 11153 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ 11154 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ 11155 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ 11156 11157 #define LPTIM_CFGR_CKFLT_Pos (3U) 11158 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ 11159 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ 11160 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ 11161 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ 11162 11163 #define LPTIM_CFGR_TRGFLT_Pos (6U) 11164 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ 11165 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ 11166 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ 11167 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ 11168 11169 #define LPTIM_CFGR_PRESC_Pos (9U) 11170 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ 11171 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ 11172 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ 11173 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ 11174 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ 11175 11176 #define LPTIM_CFGR_TRIGSEL_Pos (13U) 11177 #define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */ 11178 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ 11179 #define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ 11180 #define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ 11181 #define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ 11182 #define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */ 11183 11184 #define LPTIM_CFGR_TRIGEN_Pos (17U) 11185 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ 11186 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ 11187 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ 11188 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ 11189 11190 #define LPTIM_CFGR_TIMOUT_Pos (19U) 11191 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ 11192 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ 11193 #define LPTIM_CFGR_WAVE_Pos (20U) 11194 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ 11195 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ 11196 #define LPTIM_CFGR_WAVPOL_Pos (21U) 11197 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ 11198 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ 11199 #define LPTIM_CFGR_PRELOAD_Pos (22U) 11200 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ 11201 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ 11202 #define LPTIM_CFGR_COUNTMODE_Pos (23U) 11203 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ 11204 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ 11205 #define LPTIM_CFGR_ENC_Pos (24U) 11206 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ 11207 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ 11208 11209 /****************** Bit definition for LPTIM_CR register ********************/ 11210 #define LPTIM_CR_ENABLE_Pos (0U) 11211 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ 11212 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ 11213 #define LPTIM_CR_SNGSTRT_Pos (1U) 11214 #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ 11215 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ 11216 #define LPTIM_CR_CNTSTRT_Pos (2U) 11217 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ 11218 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ 11219 #define LPTIM_CR_COUNTRST_Pos (3U) 11220 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */ 11221 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */ 11222 #define LPTIM_CR_RSTARE_Pos (4U) 11223 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */ 11224 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */ 11225 11226 /****************** Bit definition for LPTIM_CMP register *******************/ 11227 #define LPTIM_CMP_CMP_Pos (0U) 11228 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ 11229 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ 11230 11231 /****************** Bit definition for LPTIM_ARR register *******************/ 11232 #define LPTIM_ARR_ARR_Pos (0U) 11233 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 11234 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ 11235 11236 /****************** Bit definition for LPTIM_CNT register *******************/ 11237 #define LPTIM_CNT_CNT_Pos (0U) 11238 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 11239 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ 11240 11241 /****************** Bit definition for LPTIM_OR register *******************/ 11242 #define LPTIM_OR_IN1_Pos (0U) 11243 #define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */ 11244 #define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */ 11245 #define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */ 11246 #define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */ 11247 #define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */ 11248 11249 #define LPTIM_OR_IN2_Pos (1U) 11250 #define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */ 11251 #define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */ 11252 #define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */ 11253 #define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */ 11254 #define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */ 11255 /******************************************************************************/ 11256 /* */ 11257 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 11258 /* */ 11259 /******************************************************************************/ 11260 /****************** Bit definition for USART_CR1 register *******************/ 11261 #define USART_CR1_UE_Pos (0U) 11262 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ 11263 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 11264 #define USART_CR1_UESM_Pos (1U) 11265 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 11266 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 11267 #define USART_CR1_RE_Pos (2U) 11268 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 11269 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 11270 #define USART_CR1_TE_Pos (3U) 11271 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 11272 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 11273 #define USART_CR1_IDLEIE_Pos (4U) 11274 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 11275 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 11276 #define USART_CR1_RXNEIE_Pos (5U) 11277 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 11278 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 11279 #define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos 11280 #define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */ 11281 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */ 11282 #define USART_CR1_TCIE_Pos (6U) 11283 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 11284 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 11285 #define USART_CR1_TXEIE_Pos (7U) 11286 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 11287 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 11288 #define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos 11289 #define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */ 11290 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */ 11291 #define USART_CR1_PEIE_Pos (8U) 11292 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 11293 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 11294 #define USART_CR1_PS_Pos (9U) 11295 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 11296 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 11297 #define USART_CR1_PCE_Pos (10U) 11298 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 11299 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 11300 #define USART_CR1_WAKE_Pos (11U) 11301 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 11302 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 11303 #define USART_CR1_M_Pos (12U) 11304 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ 11305 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 11306 #define USART_CR1_M0_Pos (12U) 11307 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ 11308 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ 11309 #define USART_CR1_MME_Pos (13U) 11310 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ 11311 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 11312 #define USART_CR1_CMIE_Pos (14U) 11313 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 11314 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 11315 #define USART_CR1_OVER8_Pos (15U) 11316 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 11317 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 11318 #define USART_CR1_DEDT_Pos (16U) 11319 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 11320 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 11321 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 11322 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 11323 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 11324 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 11325 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 11326 #define USART_CR1_DEAT_Pos (21U) 11327 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 11328 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 11329 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 11330 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 11331 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 11332 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 11333 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 11334 #define USART_CR1_RTOIE_Pos (26U) 11335 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 11336 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 11337 #define USART_CR1_EOBIE_Pos (27U) 11338 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 11339 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 11340 #define USART_CR1_M1_Pos (28U) 11341 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ 11342 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ 11343 #define USART_CR1_FIFOEN_Pos (29U) 11344 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */ 11345 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */ 11346 #define USART_CR1_TXFEIE_Pos (30U) 11347 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */ 11348 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */ 11349 #define USART_CR1_RXFFIE_Pos (31U) 11350 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */ 11351 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */ 11352 11353 /****************** Bit definition for USART_CR2 register *******************/ 11354 #define USART_CR2_SLVEN_Pos (0U) 11355 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */ 11356 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */ 11357 #define USART_CR2_DIS_NSS_Pos (3U) 11358 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */ 11359 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */ 11360 #define USART_CR2_ADDM7_Pos (4U) 11361 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 11362 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 11363 #define USART_CR2_LBDL_Pos (5U) 11364 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 11365 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 11366 #define USART_CR2_LBDIE_Pos (6U) 11367 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 11368 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 11369 #define USART_CR2_LBCL_Pos (8U) 11370 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 11371 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 11372 #define USART_CR2_CPHA_Pos (9U) 11373 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 11374 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 11375 #define USART_CR2_CPOL_Pos (10U) 11376 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 11377 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 11378 #define USART_CR2_CLKEN_Pos (11U) 11379 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 11380 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 11381 #define USART_CR2_STOP_Pos (12U) 11382 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 11383 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 11384 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 11385 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 11386 #define USART_CR2_LINEN_Pos (14U) 11387 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 11388 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 11389 #define USART_CR2_SWAP_Pos (15U) 11390 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 11391 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 11392 #define USART_CR2_RXINV_Pos (16U) 11393 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 11394 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 11395 #define USART_CR2_TXINV_Pos (17U) 11396 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 11397 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 11398 #define USART_CR2_DATAINV_Pos (18U) 11399 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 11400 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 11401 #define USART_CR2_MSBFIRST_Pos (19U) 11402 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 11403 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 11404 #define USART_CR2_ABREN_Pos (20U) 11405 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 11406 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 11407 #define USART_CR2_ABRMODE_Pos (21U) 11408 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 11409 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 11410 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 11411 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 11412 #define USART_CR2_RTOEN_Pos (23U) 11413 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 11414 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 11415 #define USART_CR2_ADD_Pos (24U) 11416 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 11417 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 11418 11419 /****************** Bit definition for USART_CR3 register *******************/ 11420 #define USART_CR3_EIE_Pos (0U) 11421 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 11422 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 11423 #define USART_CR3_IREN_Pos (1U) 11424 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 11425 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 11426 #define USART_CR3_IRLP_Pos (2U) 11427 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 11428 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 11429 #define USART_CR3_HDSEL_Pos (3U) 11430 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 11431 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 11432 #define USART_CR3_NACK_Pos (4U) 11433 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 11434 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 11435 #define USART_CR3_SCEN_Pos (5U) 11436 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 11437 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 11438 #define USART_CR3_DMAR_Pos (6U) 11439 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 11440 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 11441 #define USART_CR3_DMAT_Pos (7U) 11442 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 11443 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 11444 #define USART_CR3_RTSE_Pos (8U) 11445 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 11446 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 11447 #define USART_CR3_CTSE_Pos (9U) 11448 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 11449 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 11450 #define USART_CR3_CTSIE_Pos (10U) 11451 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 11452 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 11453 #define USART_CR3_ONEBIT_Pos (11U) 11454 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 11455 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 11456 #define USART_CR3_OVRDIS_Pos (12U) 11457 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 11458 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 11459 #define USART_CR3_DDRE_Pos (13U) 11460 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 11461 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 11462 #define USART_CR3_DEM_Pos (14U) 11463 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 11464 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 11465 #define USART_CR3_DEP_Pos (15U) 11466 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 11467 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 11468 #define USART_CR3_SCARCNT_Pos (17U) 11469 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 11470 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 11471 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 11472 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 11473 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 11474 #define USART_CR3_WUS_Pos (20U) 11475 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 11476 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 11477 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 11478 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 11479 #define USART_CR3_WUFIE_Pos (22U) 11480 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 11481 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 11482 #define USART_CR3_TXFTIE_Pos (23U) 11483 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */ 11484 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */ 11485 #define USART_CR3_TCBGTIE_Pos (24U) 11486 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ 11487 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ 11488 #define USART_CR3_RXFTCFG_Pos (25U) 11489 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */ 11490 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */ 11491 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */ 11492 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */ 11493 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */ 11494 #define USART_CR3_RXFTIE_Pos (28U) 11495 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */ 11496 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */ 11497 #define USART_CR3_TXFTCFG_Pos (29U) 11498 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */ 11499 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */ 11500 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */ 11501 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */ 11502 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */ 11503 11504 /****************** Bit definition for USART_BRR register *******************/ 11505 #define USART_BRR_LPUART_Pos (0U) 11506 #define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */ 11507 #define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */ 11508 #define USART_BRR_BRR_Pos (0U) 11509 #define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */ 11510 #define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */ 11511 11512 /****************** Bit definition for USART_GTPR register ******************/ 11513 #define USART_GTPR_PSC_Pos (0U) 11514 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 11515 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 11516 #define USART_GTPR_GT_Pos (8U) 11517 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 11518 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 11519 11520 /******************* Bit definition for USART_RTOR register *****************/ 11521 #define USART_RTOR_RTO_Pos (0U) 11522 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 11523 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 11524 #define USART_RTOR_BLEN_Pos (24U) 11525 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 11526 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 11527 11528 /******************* Bit definition for USART_RQR register ******************/ 11529 #define USART_RQR_ABRRQ_Pos (0U) 11530 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 11531 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 11532 #define USART_RQR_SBKRQ_Pos (1U) 11533 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 11534 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 11535 #define USART_RQR_MMRQ_Pos (2U) 11536 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 11537 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 11538 #define USART_RQR_RXFRQ_Pos (3U) 11539 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 11540 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 11541 #define USART_RQR_TXFRQ_Pos (4U) 11542 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 11543 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ 11544 11545 /******************* Bit definition for USART_ISR register ******************/ 11546 #define USART_ISR_PE_Pos (0U) 11547 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ 11548 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 11549 #define USART_ISR_FE_Pos (1U) 11550 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ 11551 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 11552 #define USART_ISR_NE_Pos (2U) 11553 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ 11554 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 11555 #define USART_ISR_ORE_Pos (3U) 11556 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 11557 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 11558 #define USART_ISR_IDLE_Pos (4U) 11559 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 11560 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 11561 #define USART_ISR_RXNE_Pos (5U) 11562 #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 11563 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 11564 #define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos 11565 #define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */ 11566 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */ 11567 #define USART_ISR_TC_Pos (6U) 11568 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ 11569 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 11570 #define USART_ISR_TXE_Pos (7U) 11571 #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 11572 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 11573 #define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos 11574 #define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */ 11575 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */ 11576 #define USART_ISR_LBDF_Pos (8U) 11577 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 11578 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 11579 #define USART_ISR_CTSIF_Pos (9U) 11580 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 11581 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 11582 #define USART_ISR_CTS_Pos (10U) 11583 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 11584 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 11585 #define USART_ISR_RTOF_Pos (11U) 11586 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 11587 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 11588 #define USART_ISR_EOBF_Pos (12U) 11589 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 11590 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 11591 #define USART_ISR_UDR_Pos (13U) 11592 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */ 11593 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */ 11594 #define USART_ISR_ABRE_Pos (14U) 11595 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 11596 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 11597 #define USART_ISR_ABRF_Pos (15U) 11598 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 11599 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 11600 #define USART_ISR_BUSY_Pos (16U) 11601 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 11602 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 11603 #define USART_ISR_CMF_Pos (17U) 11604 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 11605 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 11606 #define USART_ISR_SBKF_Pos (18U) 11607 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 11608 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 11609 #define USART_ISR_RWU_Pos (19U) 11610 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 11611 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 11612 #define USART_ISR_WUF_Pos (20U) 11613 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 11614 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 11615 #define USART_ISR_TEACK_Pos (21U) 11616 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 11617 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 11618 #define USART_ISR_REACK_Pos (22U) 11619 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 11620 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 11621 #define USART_ISR_TXFE_Pos (23U) 11622 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */ 11623 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */ 11624 #define USART_ISR_RXFF_Pos (24U) 11625 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */ 11626 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */ 11627 #define USART_ISR_TCBGT_Pos (25U) 11628 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ 11629 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */ 11630 #define USART_ISR_RXFT_Pos (26U) 11631 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */ 11632 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */ 11633 #define USART_ISR_TXFT_Pos (27U) 11634 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */ 11635 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */ 11636 11637 /******************* Bit definition for USART_ICR register ******************/ 11638 #define USART_ICR_PECF_Pos (0U) 11639 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 11640 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 11641 #define USART_ICR_FECF_Pos (1U) 11642 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 11643 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 11644 #define USART_ICR_NECF_Pos (2U) 11645 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */ 11646 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */ 11647 #define USART_ICR_ORECF_Pos (3U) 11648 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 11649 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 11650 #define USART_ICR_IDLECF_Pos (4U) 11651 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 11652 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 11653 #define USART_ICR_TXFECF_Pos (5U) 11654 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */ 11655 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */ 11656 #define USART_ICR_TCCF_Pos (6U) 11657 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 11658 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 11659 #define USART_ICR_TCBGTCF_Pos (7U) 11660 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ 11661 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ 11662 #define USART_ICR_LBDCF_Pos (8U) 11663 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 11664 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 11665 #define USART_ICR_CTSCF_Pos (9U) 11666 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 11667 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 11668 #define USART_ICR_RTOCF_Pos (11U) 11669 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 11670 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 11671 #define USART_ICR_EOBCF_Pos (12U) 11672 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 11673 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 11674 #define USART_ICR_UDRCF_Pos (13U) 11675 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */ 11676 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */ 11677 #define USART_ICR_CMCF_Pos (17U) 11678 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 11679 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 11680 #define USART_ICR_WUCF_Pos (20U) 11681 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 11682 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 11683 11684 /******************* Bit definition for USART_RDR register ******************/ 11685 #define USART_RDR_RDR_Pos (0U) 11686 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 11687 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 11688 11689 /******************* Bit definition for USART_TDR register ******************/ 11690 #define USART_TDR_TDR_Pos (0U) 11691 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 11692 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 11693 11694 /******************* Bit definition for USART_PRESC register ****************/ 11695 #define USART_PRESC_PRESCALER_Pos (0U) 11696 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */ 11697 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */ 11698 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */ 11699 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */ 11700 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ 11701 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ 11702 11703 /******************************************************************************/ 11704 /* */ 11705 /* VREFBUF */ 11706 /* */ 11707 /******************************************************************************/ 11708 /******************* Bit definition for VREFBUF_CSR register ****************/ 11709 #define VREFBUF_CSR_ENVR_Pos (0U) 11710 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ 11711 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */ 11712 #define VREFBUF_CSR_HIZ_Pos (1U) 11713 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */ 11714 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */ 11715 #define VREFBUF_CSR_VRR_Pos (3U) 11716 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */ 11717 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */ 11718 #define VREFBUF_CSR_VRS_Pos (4U) 11719 #define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */ 11720 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<VRS[5:0] bits (Voltage reference scale) */ 11721 #define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000010 */ 11722 #define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */ 11723 11724 /******************* Bit definition for VREFBUF_CCR register ******************/ 11725 #define VREFBUF_CCR_TRIM_Pos (0U) 11726 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */ 11727 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */ 11728 11729 /******************************************************************************/ 11730 /* */ 11731 /* USB Device FS Endpoint registers */ 11732 /* */ 11733 /******************************************************************************/ 11734 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */ 11735 #define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */ 11736 #define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */ 11737 #define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */ 11738 #define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */ 11739 #define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */ 11740 #define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */ 11741 #define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */ 11742 11743 /* bit positions */ 11744 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */ 11745 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */ 11746 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */ 11747 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */ 11748 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */ 11749 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */ 11750 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */ 11751 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */ 11752 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */ 11753 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */ 11754 11755 /* EndPoint REGister MASK (no toggle fields) */ 11756 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) 11757 /*!< EP_TYPE[1:0] EndPoint TYPE */ 11758 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */ 11759 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */ 11760 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */ 11761 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */ 11762 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */ 11763 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK) 11764 11765 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ 11766 /*!< STAT_TX[1:0] STATus for TX transfer */ 11767 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */ 11768 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */ 11769 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */ 11770 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */ 11771 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */ 11772 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */ 11773 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) 11774 /*!< STAT_RX[1:0] STATus for RX transfer */ 11775 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */ 11776 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */ 11777 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */ 11778 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */ 11779 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */ 11780 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ 11781 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) 11782 11783 /******************************************************************************/ 11784 /* */ 11785 /* USB Device FS General registers */ 11786 /* */ 11787 /******************************************************************************/ 11788 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */ 11789 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */ 11790 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */ 11791 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */ 11792 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */ 11793 #define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */ 11794 #define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/ 11795 11796 /****************** Bits definition for USB_CNTR register *******************/ 11797 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */ 11798 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */ 11799 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */ 11800 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */ 11801 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */ 11802 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */ 11803 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */ 11804 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */ 11805 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */ 11806 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */ 11807 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */ 11808 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */ 11809 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */ 11810 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */ 11811 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */ 11812 11813 /****************** Bits definition for USB_ISTR register *******************/ 11814 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */ 11815 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */ 11816 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */ 11817 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */ 11818 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */ 11819 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */ 11820 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */ 11821 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */ 11822 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */ 11823 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ 11824 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ 11825 11826 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */ 11827 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ 11828 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ 11829 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ 11830 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ 11831 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ 11832 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ 11833 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ 11834 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ 11835 11836 /****************** Bits definition for USB_FNR register ********************/ 11837 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */ 11838 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */ 11839 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */ 11840 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */ 11841 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */ 11842 11843 /****************** Bits definition for USB_DADDR register ****************/ 11844 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */ 11845 #define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */ 11846 #define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */ 11847 #define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */ 11848 #define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */ 11849 #define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */ 11850 #define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */ 11851 #define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */ 11852 11853 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */ 11854 11855 /****************** Bit definition for USB_BTABLE register ******************/ 11856 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */ 11857 11858 /****************** Bits definition for USB_BCDR register *******************/ 11859 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */ 11860 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */ 11861 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */ 11862 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */ 11863 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */ 11864 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */ 11865 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */ 11866 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */ 11867 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */ 11868 11869 /******************* Bit definition for LPMCSR register *********************/ 11870 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */ 11871 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/ 11872 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */ 11873 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */ 11874 11875 /*!< Buffer descriptor table */ 11876 /***************** Bit definition for USB_ADDR0_TX register *****************/ 11877 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) 11878 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */ 11879 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ 11880 11881 /***************** Bit definition for USB_ADDR1_TX register *****************/ 11882 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) 11883 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */ 11884 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ 11885 11886 /***************** Bit definition for USB_ADDR2_TX register *****************/ 11887 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) 11888 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */ 11889 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ 11890 11891 /***************** Bit definition for USB_ADDR3_TX register *****************/ 11892 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) 11893 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */ 11894 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ 11895 11896 /***************** Bit definition for USB_ADDR4_TX register *****************/ 11897 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) 11898 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */ 11899 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ 11900 11901 /***************** Bit definition for USB_ADDR5_TX register *****************/ 11902 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) 11903 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */ 11904 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ 11905 11906 /***************** Bit definition for USB_ADDR6_TX register *****************/ 11907 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) 11908 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */ 11909 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ 11910 11911 /***************** Bit definition for USB_ADDR7_TX register *****************/ 11912 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) 11913 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */ 11914 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ 11915 11916 /*----------------------------------------------------------------------------*/ 11917 11918 /***************** Bit definition for USB_COUNT0_TX register ****************/ 11919 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) 11920 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */ 11921 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ 11922 11923 /***************** Bit definition for USB_COUNT1_TX register ****************/ 11924 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) 11925 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */ 11926 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ 11927 11928 /***************** Bit definition for USB_COUNT2_TX register ****************/ 11929 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) 11930 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */ 11931 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ 11932 11933 /***************** Bit definition for USB_COUNT3_TX register ****************/ 11934 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) 11935 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */ 11936 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ 11937 11938 /***************** Bit definition for USB_COUNT4_TX register ****************/ 11939 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) 11940 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */ 11941 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ 11942 11943 /***************** Bit definition for USB_COUNT5_TX register ****************/ 11944 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) 11945 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */ 11946 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ 11947 11948 /***************** Bit definition for USB_COUNT6_TX register ****************/ 11949 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) 11950 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */ 11951 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ 11952 11953 /***************** Bit definition for USB_COUNT7_TX register ****************/ 11954 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) 11955 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */ 11956 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ 11957 11958 /*----------------------------------------------------------------------------*/ 11959 11960 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 11961 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */ 11962 11963 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 11964 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */ 11965 11966 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 11967 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */ 11968 11969 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 11970 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */ 11971 11972 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 11973 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */ 11974 11975 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 11976 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */ 11977 11978 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 11979 #define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */ 11980 11981 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 11982 #define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */ 11983 11984 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 11985 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */ 11986 11987 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 11988 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */ 11989 11990 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 11991 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */ 11992 11993 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 11994 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */ 11995 11996 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 11997 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */ 11998 11999 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 12000 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */ 12001 12002 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 12003 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */ 12004 12005 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 12006 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */ 12007 12008 /*----------------------------------------------------------------------------*/ 12009 12010 /***************** Bit definition for USB_ADDR0_RX register *****************/ 12011 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) 12012 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */ 12013 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ 12014 12015 /***************** Bit definition for USB_ADDR1_RX register *****************/ 12016 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) 12017 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */ 12018 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ 12019 12020 /***************** Bit definition for USB_ADDR2_RX register *****************/ 12021 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) 12022 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */ 12023 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ 12024 12025 /***************** Bit definition for USB_ADDR3_RX register *****************/ 12026 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) 12027 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */ 12028 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ 12029 12030 /***************** Bit definition for USB_ADDR4_RX register *****************/ 12031 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) 12032 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */ 12033 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ 12034 12035 /***************** Bit definition for USB_ADDR5_RX register *****************/ 12036 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) 12037 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */ 12038 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ 12039 12040 /***************** Bit definition for USB_ADDR6_RX register *****************/ 12041 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) 12042 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */ 12043 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ 12044 12045 /***************** Bit definition for USB_ADDR7_RX register *****************/ 12046 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) 12047 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */ 12048 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ 12049 12050 /*----------------------------------------------------------------------------*/ 12051 12052 /***************** Bit definition for USB_COUNT0_RX register ****************/ 12053 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) 12054 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */ 12055 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ 12056 12057 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) 12058 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */ 12059 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 12060 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */ 12061 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */ 12062 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */ 12063 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */ 12064 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */ 12065 12066 #define USB_COUNT0_RX_BLSIZE_Pos (15U) 12067 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */ 12068 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ 12069 12070 /***************** Bit definition for USB_COUNT1_RX register ****************/ 12071 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) 12072 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */ 12073 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ 12074 12075 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) 12076 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */ 12077 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 12078 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */ 12079 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */ 12080 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */ 12081 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */ 12082 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */ 12083 12084 #define USB_COUNT1_RX_BLSIZE_Pos (15U) 12085 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */ 12086 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ 12087 12088 /***************** Bit definition for USB_COUNT2_RX register ****************/ 12089 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) 12090 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */ 12091 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ 12092 12093 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) 12094 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */ 12095 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 12096 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */ 12097 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */ 12098 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */ 12099 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */ 12100 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */ 12101 12102 #define USB_COUNT2_RX_BLSIZE_Pos (15U) 12103 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */ 12104 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ 12105 12106 /***************** Bit definition for USB_COUNT3_RX register ****************/ 12107 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) 12108 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */ 12109 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ 12110 12111 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) 12112 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */ 12113 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 12114 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */ 12115 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */ 12116 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */ 12117 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */ 12118 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */ 12119 12120 #define USB_COUNT3_RX_BLSIZE_Pos (15U) 12121 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */ 12122 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ 12123 12124 /***************** Bit definition for USB_COUNT4_RX register ****************/ 12125 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) 12126 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */ 12127 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ 12128 12129 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) 12130 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */ 12131 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 12132 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */ 12133 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */ 12134 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */ 12135 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */ 12136 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */ 12137 12138 #define USB_COUNT4_RX_BLSIZE_Pos (15U) 12139 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */ 12140 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ 12141 12142 /***************** Bit definition for USB_COUNT5_RX register ****************/ 12143 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) 12144 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */ 12145 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ 12146 12147 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) 12148 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */ 12149 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 12150 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */ 12151 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */ 12152 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */ 12153 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */ 12154 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */ 12155 12156 #define USB_COUNT5_RX_BLSIZE_Pos (15U) 12157 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */ 12158 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ 12159 12160 /***************** Bit definition for USB_COUNT6_RX register ****************/ 12161 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) 12162 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */ 12163 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ 12164 12165 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) 12166 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */ 12167 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 12168 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */ 12169 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */ 12170 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */ 12171 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */ 12172 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */ 12173 12174 #define USB_COUNT6_RX_BLSIZE_Pos (15U) 12175 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */ 12176 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ 12177 12178 /***************** Bit definition for USB_COUNT7_RX register ****************/ 12179 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) 12180 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */ 12181 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ 12182 12183 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) 12184 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */ 12185 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 12186 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */ 12187 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */ 12188 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */ 12189 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */ 12190 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */ 12191 12192 #define USB_COUNT7_RX_BLSIZE_Pos (15U) 12193 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */ 12194 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ 12195 12196 /*----------------------------------------------------------------------------*/ 12197 12198 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 12199 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 12200 12201 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 12202 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 12203 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 12204 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 12205 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 12206 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 12207 12208 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 12209 12210 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 12211 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 12212 12213 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 12214 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */ 12215 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 12216 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 12217 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 12218 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 12219 12220 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 12221 12222 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 12223 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 12224 12225 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 12226 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 12227 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 12228 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 12229 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 12230 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 12231 12232 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 12233 12234 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 12235 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 12236 12237 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 12238 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 12239 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 12240 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 12241 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 12242 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 12243 12244 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 12245 12246 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 12247 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 12248 12249 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 12250 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 12251 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 12252 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 12253 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 12254 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 12255 12256 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 12257 12258 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 12259 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 12260 12261 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 12262 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 12263 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 12264 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 12265 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 12266 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 12267 12268 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 12269 12270 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 12271 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 12272 12273 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 12274 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 12275 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 12276 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 12277 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 12278 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 12279 12280 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 12281 12282 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 12283 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 12284 12285 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 12286 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 12287 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 12288 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 12289 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 12290 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 12291 12292 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 12293 12294 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 12295 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 12296 12297 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 12298 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 12299 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 12300 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 12301 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 12302 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 12303 12304 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 12305 12306 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 12307 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 12308 12309 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 12310 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 12311 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 12312 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 12313 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 12314 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 12315 12316 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 12317 12318 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 12319 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 12320 12321 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 12322 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 12323 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 12324 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 12325 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 12326 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 12327 12328 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 12329 12330 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 12331 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 12332 12333 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 12334 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 12335 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 12336 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 12337 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 12338 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 12339 12340 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 12341 12342 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 12343 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 12344 12345 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 12346 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 12347 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 12348 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 12349 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 12350 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 12351 12352 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 12353 12354 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 12355 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 12356 12357 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 12358 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 12359 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 12360 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 12361 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 12362 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 12363 12364 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 12365 12366 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 12367 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */ 12368 12369 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 12370 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */ 12371 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */ 12372 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */ 12373 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */ 12374 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */ 12375 12376 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */ 12377 12378 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 12379 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */ 12380 12381 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 12382 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */ 12383 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */ 12384 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */ 12385 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */ 12386 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */ 12387 12388 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */ 12389 12390 /******************************************************************************/ 12391 /* */ 12392 /* UCPD */ 12393 /* */ 12394 /******************************************************************************/ 12395 /******************** Bits definition for UCPD_CFG1 register *******************/ 12396 #define UCPD_CFG1_HBITCLKDIV_Pos (0U) 12397 #define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */ 12398 #define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */ 12399 #define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */ 12400 #define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */ 12401 #define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */ 12402 #define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */ 12403 #define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */ 12404 #define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */ 12405 #define UCPD_CFG1_IFRGAP_Pos (6U) 12406 #define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */ 12407 #define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */ 12408 #define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */ 12409 #define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */ 12410 #define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */ 12411 #define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */ 12412 #define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */ 12413 #define UCPD_CFG1_TRANSWIN_Pos (11U) 12414 #define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */ 12415 #define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */ 12416 #define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */ 12417 #define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */ 12418 #define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */ 12419 #define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */ 12420 #define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */ 12421 #define UCPD_CFG1_PSC_UCPDCLK_Pos (17U) 12422 #define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */ 12423 #define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */ 12424 #define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */ 12425 #define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */ 12426 #define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */ 12427 #define UCPD_CFG1_RXORDSETEN_Pos (20U) 12428 #define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */ 12429 #define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */ 12430 #define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */ 12431 #define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */ 12432 #define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */ 12433 #define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */ 12434 #define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */ 12435 #define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */ 12436 #define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */ 12437 #define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */ 12438 #define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */ 12439 #define UCPD_CFG1_TXDMAEN_Pos (29U) 12440 #define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */ 12441 #define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 12442 #define UCPD_CFG1_RXDMAEN_Pos (30U) 12443 #define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */ 12444 #define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */ 12445 #define UCPD_CFG1_UCPDEN_Pos (31U) 12446 #define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */ 12447 #define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */ 12448 12449 /******************** Bits definition for UCPD_CFG2 register *******************/ 12450 #define UCPD_CFG2_RXFILTDIS_Pos (0U) 12451 #define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */ 12452 #define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */ 12453 #define UCPD_CFG2_RXFILT2N3_Pos (1U) 12454 #define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */ 12455 #define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */ 12456 #define UCPD_CFG2_FORCECLK_Pos (2U) 12457 #define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */ 12458 #define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */ 12459 #define UCPD_CFG2_WUPEN_Pos (3U) 12460 #define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */ 12461 #define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */ 12462 12463 /******************** Bits definition for UCPD_CR register ********************/ 12464 #define UCPD_CR_TXMODE_Pos (0U) 12465 #define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ 12466 #define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */ 12467 #define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */ 12468 #define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */ 12469 #define UCPD_CR_TXSEND_Pos (2U) 12470 #define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */ 12471 #define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */ 12472 #define UCPD_CR_TXHRST_Pos (3U) 12473 #define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */ 12474 #define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */ 12475 #define UCPD_CR_RXMODE_Pos (4U) 12476 #define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */ 12477 #define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */ 12478 #define UCPD_CR_PHYRXEN_Pos (5U) 12479 #define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */ 12480 #define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */ 12481 #define UCPD_CR_PHYCCSEL_Pos (6U) 12482 #define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */ 12483 #define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */ 12484 #define UCPD_CR_ANASUBMODE_Pos (7U) 12485 #define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */ 12486 #define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */ 12487 #define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */ 12488 #define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */ 12489 #define UCPD_CR_ANAMODE_Pos (9U) 12490 #define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */ 12491 #define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */ 12492 #define UCPD_CR_CCENABLE_Pos (10U) 12493 #define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */ 12494 #define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */ 12495 #define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */ 12496 #define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */ 12497 #define UCPD_CR_FRSRXEN_Pos (16U) 12498 #define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */ 12499 #define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */ 12500 #define UCPD_CR_FRSTX_Pos (17U) 12501 #define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */ 12502 #define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */ 12503 #define UCPD_CR_RDCH_Pos (18U) 12504 #define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */ 12505 #define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */ 12506 #define UCPD_CR_CC1TCDIS_Pos (20U) 12507 #define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */ 12508 #define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */ 12509 #define UCPD_CR_CC2TCDIS_Pos (21U) 12510 #define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */ 12511 #define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */ 12512 12513 /******************** Bits definition for UCPD_IMR register *******************/ 12514 #define UCPD_IMR_TXISIE_Pos (0U) 12515 #define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */ 12516 #define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */ 12517 #define UCPD_IMR_TXMSGDISCIE_Pos (1U) 12518 #define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */ 12519 #define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */ 12520 #define UCPD_IMR_TXMSGSENTIE_Pos (2U) 12521 #define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */ 12522 #define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */ 12523 #define UCPD_IMR_TXMSGABTIE_Pos (3U) 12524 #define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */ 12525 #define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */ 12526 #define UCPD_IMR_HRSTDISCIE_Pos (4U) 12527 #define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */ 12528 #define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */ 12529 #define UCPD_IMR_HRSTSENTIE_Pos (5U) 12530 #define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */ 12531 #define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */ 12532 #define UCPD_IMR_TXUNDIE_Pos (6U) 12533 #define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */ 12534 #define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */ 12535 #define UCPD_IMR_RXNEIE_Pos (8U) 12536 #define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */ 12537 #define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */ 12538 #define UCPD_IMR_RXORDDETIE_Pos (9U) 12539 #define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */ 12540 #define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */ 12541 #define UCPD_IMR_RXHRSTDETIE_Pos (10U) 12542 #define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */ 12543 #define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */ 12544 #define UCPD_IMR_RXOVRIE_Pos (11U) 12545 #define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */ 12546 #define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */ 12547 #define UCPD_IMR_RXMSGENDIE_Pos (12U) 12548 #define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */ 12549 #define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */ 12550 #define UCPD_IMR_TYPECEVT1IE_Pos (14U) 12551 #define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */ 12552 #define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */ 12553 #define UCPD_IMR_TYPECEVT2IE_Pos (15U) 12554 #define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */ 12555 #define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */ 12556 #define UCPD_IMR_FRSEVTIE_Pos (20U) 12557 #define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */ 12558 #define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */ 12559 12560 /******************** Bits definition for UCPD_SR register ********************/ 12561 #define UCPD_SR_TXIS_Pos (0U) 12562 #define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */ 12563 #define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */ 12564 #define UCPD_SR_TXMSGDISC_Pos (1U) 12565 #define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */ 12566 #define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */ 12567 #define UCPD_SR_TXMSGSENT_Pos (2U) 12568 #define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */ 12569 #define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */ 12570 #define UCPD_SR_TXMSGABT_Pos (3U) 12571 #define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */ 12572 #define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */ 12573 #define UCPD_SR_HRSTDISC_Pos (4U) 12574 #define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */ 12575 #define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */ 12576 #define UCPD_SR_HRSTSENT_Pos (5U) 12577 #define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */ 12578 #define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */ 12579 #define UCPD_SR_TXUND_Pos (6U) 12580 #define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */ 12581 #define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */ 12582 #define UCPD_SR_RXNE_Pos (8U) 12583 #define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */ 12584 #define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */ 12585 #define UCPD_SR_RXORDDET_Pos (9U) 12586 #define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */ 12587 #define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */ 12588 #define UCPD_SR_RXHRSTDET_Pos (10U) 12589 #define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */ 12590 #define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */ 12591 #define UCPD_SR_RXOVR_Pos (11U) 12592 #define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */ 12593 #define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */ 12594 #define UCPD_SR_RXMSGEND_Pos (12U) 12595 #define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */ 12596 #define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */ 12597 #define UCPD_SR_RXERR_Pos (13U) 12598 #define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */ 12599 #define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */ 12600 #define UCPD_SR_TYPECEVT1_Pos (14U) 12601 #define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */ 12602 #define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */ 12603 #define UCPD_SR_TYPECEVT2_Pos (15U) 12604 #define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */ 12605 #define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */ 12606 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) 12607 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */ 12608 #define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */ 12609 #define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */ 12610 #define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */ 12611 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) 12612 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */ 12613 #define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */ 12614 #define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */ 12615 #define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */ 12616 #define UCPD_SR_FRSEVT_Pos (20U) 12617 #define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */ 12618 #define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */ 12619 12620 /******************** Bits definition for UCPD_ICR register *******************/ 12621 #define UCPD_ICR_TXMSGDISCCF_Pos (1U) 12622 #define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */ 12623 #define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */ 12624 #define UCPD_ICR_TXMSGSENTCF_Pos (2U) 12625 #define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */ 12626 #define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */ 12627 #define UCPD_ICR_TXMSGABTCF_Pos (3U) 12628 #define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */ 12629 #define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */ 12630 #define UCPD_ICR_HRSTDISCCF_Pos (4U) 12631 #define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */ 12632 #define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */ 12633 #define UCPD_ICR_HRSTSENTCF_Pos (5U) 12634 #define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */ 12635 #define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */ 12636 #define UCPD_ICR_TXUNDCF_Pos (6U) 12637 #define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */ 12638 #define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */ 12639 #define UCPD_ICR_RXORDDETCF_Pos (9U) 12640 #define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */ 12641 #define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */ 12642 #define UCPD_ICR_RXHRSTDETCF_Pos (10U) 12643 #define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */ 12644 #define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */ 12645 #define UCPD_ICR_RXOVRCF_Pos (11U) 12646 #define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */ 12647 #define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */ 12648 #define UCPD_ICR_RXMSGENDCF_Pos (12U) 12649 #define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */ 12650 #define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */ 12651 #define UCPD_ICR_TYPECEVT1CF_Pos (14U) 12652 #define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */ 12653 #define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */ 12654 #define UCPD_ICR_TYPECEVT2CF_Pos (15U) 12655 #define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */ 12656 #define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */ 12657 #define UCPD_ICR_FRSEVTCF_Pos (20U) 12658 #define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */ 12659 #define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */ 12660 12661 /******************** Bits definition for UCPD_TXORDSET register **************/ 12662 #define UCPD_TX_ORDSET_TXORDSET_Pos (0U) 12663 #define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */ 12664 #define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */ 12665 12666 /******************** Bits definition for UCPD_TXPAYSZ register ****************/ 12667 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U) 12668 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */ 12669 #define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */ 12670 12671 /******************** Bits definition for UCPD_TXDR register *******************/ 12672 #define UCPD_TXDR_TXDATA_Pos (0U) 12673 #define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 12674 #define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */ 12675 12676 /******************** Bits definition for UCPD_RXORDSET register **************/ 12677 #define UCPD_RX_ORDSET_RXORDSET_Pos (0U) 12678 #define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */ 12679 #define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */ 12680 #define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */ 12681 #define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */ 12682 #define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */ 12683 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U) 12684 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */ 12685 #define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */ 12686 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U) 12687 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */ 12688 #define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */ 12689 12690 /******************** Bits definition for UCPD_RXPAYSZ register ****************/ 12691 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U) 12692 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */ 12693 #define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */ 12694 12695 /******************** Bits definition for UCPD_RXDR register *******************/ 12696 #define UCPD_RXDR_RXDATA_Pos (0U) 12697 #define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 12698 #define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 12699 12700 /******************** Bits definition for UCPD_RXORDEXT1 register **************/ 12701 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U) 12702 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */ 12703 #define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */ 12704 12705 /******************** Bits definition for UCPD_RXORDEXT2 register **************/ 12706 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U) 12707 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */ 12708 #define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */ 12709 12710 /******************************************************************************/ 12711 /* */ 12712 /* Window WATCHDOG */ 12713 /* */ 12714 /******************************************************************************/ 12715 /******************* Bit definition for WWDG_CR register ********************/ 12716 #define WWDG_CR_T_Pos (0U) 12717 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 12718 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ 12719 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 12720 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 12721 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 12722 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 12723 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 12724 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 12725 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 12726 12727 #define WWDG_CR_WDGA_Pos (7U) 12728 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 12729 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ 12730 12731 /******************* Bit definition for WWDG_CFR register *******************/ 12732 #define WWDG_CFR_W_Pos (0U) 12733 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 12734 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ 12735 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 12736 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 12737 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 12738 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 12739 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 12740 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 12741 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 12742 12743 #define WWDG_CFR_WDGTB_Pos (11U) 12744 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */ 12745 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */ 12746 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */ 12747 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */ 12748 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */ 12749 12750 #define WWDG_CFR_EWI_Pos (9U) 12751 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 12752 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ 12753 12754 /******************* Bit definition for WWDG_SR register ********************/ 12755 #define WWDG_SR_EWIF_Pos (0U) 12756 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 12757 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ 12758 12759 /** 12760 * @} 12761 */ 12762 12763 /** 12764 * @} 12765 */ 12766 12767 /** @addtogroup Exported_macros 12768 * @{ 12769 */ 12770 12771 /******************************* ADC Instances ********************************/ 12772 12773 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ 12774 ((INSTANCE) == ADC2)) 12775 12776 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 12777 12778 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) 12779 12780 /******************************* AES Instances ********************************/ 12781 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES) 12782 12783 /******************************** FDCAN Instances ******************************/ 12784 #define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1) 12785 12786 #define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG) 12787 /******************************** COMP Instances ******************************/ 12788 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 12789 ((INSTANCE) == COMP2) || \ 12790 ((INSTANCE) == COMP3) || \ 12791 ((INSTANCE) == COMP4)) 12792 12793 /******************************* CORDIC Instances *****************************/ 12794 #define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC) 12795 12796 /******************************* CRC Instances ********************************/ 12797 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 12798 12799 /******************************* DAC Instances ********************************/ 12800 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \ 12801 ((INSTANCE) == DAC3)) 12802 12803 12804 /******************************** DMA Instances *******************************/ 12805 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 12806 ((INSTANCE) == DMA1_Channel2) || \ 12807 ((INSTANCE) == DMA1_Channel3) || \ 12808 ((INSTANCE) == DMA1_Channel4) || \ 12809 ((INSTANCE) == DMA1_Channel5) || \ 12810 ((INSTANCE) == DMA1_Channel6) || \ 12811 ((INSTANCE) == DMA2_Channel1) || \ 12812 ((INSTANCE) == DMA2_Channel2) || \ 12813 ((INSTANCE) == DMA2_Channel3) || \ 12814 ((INSTANCE) == DMA2_Channel4) || \ 12815 ((INSTANCE) == DMA2_Channel5) || \ 12816 ((INSTANCE) == DMA2_Channel6)) 12817 12818 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \ 12819 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \ 12820 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \ 12821 ((INSTANCE) == DMAMUX1_RequestGenerator3)) 12822 12823 /******************************* FMAC Instances *******************************/ 12824 #define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC) 12825 12826 /******************************* GPIO Instances *******************************/ 12827 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 12828 ((INSTANCE) == GPIOB) || \ 12829 ((INSTANCE) == GPIOC) || \ 12830 ((INSTANCE) == GPIOD) || \ 12831 ((INSTANCE) == GPIOE) || \ 12832 ((INSTANCE) == GPIOF) || \ 12833 ((INSTANCE) == GPIOG)) 12834 12835 /******************************* GPIO AF Instances ****************************/ 12836 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 12837 12838 /**************************** GPIO Lock Instances *****************************/ 12839 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 12840 12841 /******************************** I2C Instances *******************************/ 12842 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 12843 ((INSTANCE) == I2C2) || \ 12844 ((INSTANCE) == I2C3)) 12845 12846 /****************** I2C Instances : wakeup capability from stop modes *********/ 12847 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) 12848 12849 /****************************** OPAMP Instances *******************************/ 12850 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \ 12851 ((INSTANCE) == OPAMP2) || \ 12852 ((INSTANCE) == OPAMP3)) 12853 12854 12855 /******************************** PCD Instances *******************************/ 12856 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) 12857 12858 12859 /******************************* RNG Instances ********************************/ 12860 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) 12861 12862 /****************************** RTC Instances *********************************/ 12863 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 12864 12865 #define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP) 12866 12867 /****************************** SMBUS Instances *******************************/ 12868 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 12869 ((INSTANCE) == I2C2) || \ 12870 ((INSTANCE) == I2C3)) 12871 12872 /******************************** SAI Instances *******************************/ 12873 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B)) 12874 12875 /******************************** SPI Instances *******************************/ 12876 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 12877 ((INSTANCE) == SPI2) || \ 12878 ((INSTANCE) == SPI3)) 12879 12880 /******************************** I2S Instances *******************************/ 12881 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \ 12882 ((__INSTANCE__) == SPI3)) 12883 12884 /****************** LPTIM Instances : All supported instances *****************/ 12885 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 12886 12887 /****************** LPTIM Instances : supporting encoder interface **************/ 12888 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 12889 12890 /****************** LPTIM Instances : All supported instances *****************/ 12891 #define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 12892 12893 /****************** TIM Instances : All supported instances *******************/ 12894 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12895 ((INSTANCE) == TIM2) || \ 12896 ((INSTANCE) == TIM3) || \ 12897 ((INSTANCE) == TIM4) || \ 12898 ((INSTANCE) == TIM6) || \ 12899 ((INSTANCE) == TIM7) || \ 12900 ((INSTANCE) == TIM8) || \ 12901 ((INSTANCE) == TIM15) || \ 12902 ((INSTANCE) == TIM16) || \ 12903 ((INSTANCE) == TIM17)) 12904 12905 /****************** TIM Instances : supporting 32 bits counter ****************/ 12906 12907 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) 12908 12909 /****************** TIM Instances : supporting the break function *************/ 12910 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12911 ((INSTANCE) == TIM8) || \ 12912 ((INSTANCE) == TIM15) || \ 12913 ((INSTANCE) == TIM16) || \ 12914 ((INSTANCE) == TIM17)) 12915 12916 /************** TIM Instances : supporting Break source selection *************/ 12917 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12918 ((INSTANCE) == TIM8) || \ 12919 ((INSTANCE) == TIM15) || \ 12920 ((INSTANCE) == TIM16) || \ 12921 ((INSTANCE) == TIM17)) 12922 12923 /****************** TIM Instances : supporting 2 break inputs *****************/ 12924 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12925 ((INSTANCE) == TIM8)) 12926 12927 /************* TIM Instances : at least 1 capture/compare channel *************/ 12928 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12929 ((INSTANCE) == TIM2) || \ 12930 ((INSTANCE) == TIM3) || \ 12931 ((INSTANCE) == TIM4) || \ 12932 ((INSTANCE) == TIM8) || \ 12933 ((INSTANCE) == TIM15) || \ 12934 ((INSTANCE) == TIM16) || \ 12935 ((INSTANCE) == TIM17)) 12936 12937 /************ TIM Instances : at least 2 capture/compare channels *************/ 12938 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12939 ((INSTANCE) == TIM2) || \ 12940 ((INSTANCE) == TIM3) || \ 12941 ((INSTANCE) == TIM4) || \ 12942 ((INSTANCE) == TIM8) || \ 12943 ((INSTANCE) == TIM15)) 12944 12945 /************ TIM Instances : at least 3 capture/compare channels *************/ 12946 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12947 ((INSTANCE) == TIM2) || \ 12948 ((INSTANCE) == TIM3) || \ 12949 ((INSTANCE) == TIM4) || \ 12950 ((INSTANCE) == TIM8)) 12951 12952 /************ TIM Instances : at least 4 capture/compare channels *************/ 12953 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12954 ((INSTANCE) == TIM2) || \ 12955 ((INSTANCE) == TIM3) || \ 12956 ((INSTANCE) == TIM4) || \ 12957 ((INSTANCE) == TIM8)) 12958 12959 /****************** TIM Instances : at least 5 capture/compare channels *******/ 12960 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12961 ((INSTANCE) == TIM8)) 12962 12963 /****************** TIM Instances : at least 6 capture/compare channels *******/ 12964 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12965 ((INSTANCE) == TIM8)) 12966 12967 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ 12968 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12969 ((INSTANCE) == TIM8) || \ 12970 ((INSTANCE) == TIM15) || \ 12971 ((INSTANCE) == TIM16) || \ 12972 ((INSTANCE) == TIM17)) 12973 12974 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ 12975 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12976 ((INSTANCE) == TIM2) || \ 12977 ((INSTANCE) == TIM3) || \ 12978 ((INSTANCE) == TIM4) || \ 12979 ((INSTANCE) == TIM6) || \ 12980 ((INSTANCE) == TIM7) || \ 12981 ((INSTANCE) == TIM8) || \ 12982 ((INSTANCE) == TIM15) || \ 12983 ((INSTANCE) == TIM16) || \ 12984 ((INSTANCE) == TIM17)) 12985 12986 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ 12987 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12988 ((INSTANCE) == TIM2) || \ 12989 ((INSTANCE) == TIM3) || \ 12990 ((INSTANCE) == TIM4) || \ 12991 ((INSTANCE) == TIM8) || \ 12992 ((INSTANCE) == TIM15) || \ 12993 ((INSTANCE) == TIM16) || \ 12994 ((INSTANCE) == TIM17)) 12995 12996 /******************** TIM Instances : DMA burst feature ***********************/ 12997 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 12998 ((INSTANCE) == TIM2) || \ 12999 ((INSTANCE) == TIM3) || \ 13000 ((INSTANCE) == TIM4) || \ 13001 ((INSTANCE) == TIM8) || \ 13002 ((INSTANCE) == TIM15) || \ 13003 ((INSTANCE) == TIM16) || \ 13004 ((INSTANCE) == TIM17)) 13005 13006 /******************* TIM Instances : output(s) available **********************/ 13007 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 13008 ((((INSTANCE) == TIM1) && \ 13009 (((CHANNEL) == TIM_CHANNEL_1) || \ 13010 ((CHANNEL) == TIM_CHANNEL_2) || \ 13011 ((CHANNEL) == TIM_CHANNEL_3) || \ 13012 ((CHANNEL) == TIM_CHANNEL_4) || \ 13013 ((CHANNEL) == TIM_CHANNEL_5) || \ 13014 ((CHANNEL) == TIM_CHANNEL_6))) \ 13015 || \ 13016 (((INSTANCE) == TIM2) && \ 13017 (((CHANNEL) == TIM_CHANNEL_1) || \ 13018 ((CHANNEL) == TIM_CHANNEL_2) || \ 13019 ((CHANNEL) == TIM_CHANNEL_3) || \ 13020 ((CHANNEL) == TIM_CHANNEL_4))) \ 13021 || \ 13022 (((INSTANCE) == TIM3) && \ 13023 (((CHANNEL) == TIM_CHANNEL_1) || \ 13024 ((CHANNEL) == TIM_CHANNEL_2) || \ 13025 ((CHANNEL) == TIM_CHANNEL_3) || \ 13026 ((CHANNEL) == TIM_CHANNEL_4))) \ 13027 || \ 13028 (((INSTANCE) == TIM4) && \ 13029 (((CHANNEL) == TIM_CHANNEL_1) || \ 13030 ((CHANNEL) == TIM_CHANNEL_2) || \ 13031 ((CHANNEL) == TIM_CHANNEL_3) || \ 13032 ((CHANNEL) == TIM_CHANNEL_4))) \ 13033 || \ 13034 (((INSTANCE) == TIM8) && \ 13035 (((CHANNEL) == TIM_CHANNEL_1) || \ 13036 ((CHANNEL) == TIM_CHANNEL_2) || \ 13037 ((CHANNEL) == TIM_CHANNEL_3) || \ 13038 ((CHANNEL) == TIM_CHANNEL_4) || \ 13039 ((CHANNEL) == TIM_CHANNEL_5) || \ 13040 ((CHANNEL) == TIM_CHANNEL_6))) \ 13041 || \ 13042 (((INSTANCE) == TIM15) && \ 13043 (((CHANNEL) == TIM_CHANNEL_1) || \ 13044 ((CHANNEL) == TIM_CHANNEL_2))) \ 13045 || \ 13046 (((INSTANCE) == TIM16) && \ 13047 (((CHANNEL) == TIM_CHANNEL_1))) \ 13048 || \ 13049 (((INSTANCE) == TIM17) && \ 13050 (((CHANNEL) == TIM_CHANNEL_1)))) 13051 13052 /****************** TIM Instances : supporting complementary output(s) ********/ 13053 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 13054 ((((INSTANCE) == TIM1) && \ 13055 (((CHANNEL) == TIM_CHANNEL_1) || \ 13056 ((CHANNEL) == TIM_CHANNEL_2) || \ 13057 ((CHANNEL) == TIM_CHANNEL_3) || \ 13058 ((CHANNEL) == TIM_CHANNEL_4))) \ 13059 || \ 13060 (((INSTANCE) == TIM8) && \ 13061 (((CHANNEL) == TIM_CHANNEL_1) || \ 13062 ((CHANNEL) == TIM_CHANNEL_2) || \ 13063 ((CHANNEL) == TIM_CHANNEL_3) || \ 13064 ((CHANNEL) == TIM_CHANNEL_4))) \ 13065 || \ 13066 (((INSTANCE) == TIM15) && \ 13067 ((CHANNEL) == TIM_CHANNEL_1)) \ 13068 || \ 13069 (((INSTANCE) == TIM16) && \ 13070 ((CHANNEL) == TIM_CHANNEL_1)) \ 13071 || \ 13072 (((INSTANCE) == TIM17) && \ 13073 ((CHANNEL) == TIM_CHANNEL_1))) 13074 13075 /****************** TIM Instances : supporting clock division *****************/ 13076 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13077 ((INSTANCE) == TIM2) || \ 13078 ((INSTANCE) == TIM3) || \ 13079 ((INSTANCE) == TIM4) || \ 13080 ((INSTANCE) == TIM8) || \ 13081 ((INSTANCE) == TIM15) || \ 13082 ((INSTANCE) == TIM16) || \ 13083 ((INSTANCE) == TIM17)) 13084 13085 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 13086 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13087 ((INSTANCE) == TIM2) || \ 13088 ((INSTANCE) == TIM3) || \ 13089 ((INSTANCE) == TIM4) || \ 13090 ((INSTANCE) == TIM8)) 13091 13092 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 13093 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13094 ((INSTANCE) == TIM2) || \ 13095 ((INSTANCE) == TIM3) || \ 13096 ((INSTANCE) == TIM4) || \ 13097 ((INSTANCE) == TIM8)) 13098 13099 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 13100 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13101 ((INSTANCE) == TIM2) || \ 13102 ((INSTANCE) == TIM3) || \ 13103 ((INSTANCE) == TIM4) || \ 13104 ((INSTANCE) == TIM8) || \ 13105 ((INSTANCE) == TIM15)) 13106 13107 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 13108 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13109 ((INSTANCE) == TIM2) || \ 13110 ((INSTANCE) == TIM3) || \ 13111 ((INSTANCE) == TIM4) || \ 13112 ((INSTANCE) == TIM8) || \ 13113 ((INSTANCE) == TIM15)) 13114 13115 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ 13116 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13117 ((INSTANCE) == TIM8)) 13118 13119 /****************** TIM Instances : supporting commutation event generation ***/ 13120 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13121 ((INSTANCE) == TIM8) || \ 13122 ((INSTANCE) == TIM15) || \ 13123 ((INSTANCE) == TIM16) || \ 13124 ((INSTANCE) == TIM17)) 13125 13126 /****************** TIM Instances : supporting counting mode selection ********/ 13127 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13128 ((INSTANCE) == TIM2) || \ 13129 ((INSTANCE) == TIM3) || \ 13130 ((INSTANCE) == TIM4) || \ 13131 ((INSTANCE) == TIM8)) 13132 13133 /****************** TIM Instances : supporting encoder interface **************/ 13134 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13135 ((INSTANCE) == TIM2) || \ 13136 ((INSTANCE) == TIM3) || \ 13137 ((INSTANCE) == TIM4) || \ 13138 ((INSTANCE) == TIM8)) 13139 13140 /****************** TIM Instances : supporting Hall sensor interface **********/ 13141 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13142 ((INSTANCE) == TIM2) || \ 13143 ((INSTANCE) == TIM3) || \ 13144 ((INSTANCE) == TIM4) || \ 13145 ((INSTANCE) == TIM8) || \ 13146 ((INSTANCE) == TIM15)) 13147 13148 /**************** TIM Instances : external trigger input available ************/ 13149 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13150 ((INSTANCE) == TIM2) || \ 13151 ((INSTANCE) == TIM3) || \ 13152 ((INSTANCE) == TIM4) || \ 13153 ((INSTANCE) == TIM8)) 13154 13155 /************* TIM Instances : supporting ETR source selection ***************/ 13156 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13157 ((INSTANCE) == TIM2) || \ 13158 ((INSTANCE) == TIM3) || \ 13159 ((INSTANCE) == TIM4) || \ 13160 ((INSTANCE) == TIM8)) 13161 13162 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ 13163 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13164 ((INSTANCE) == TIM2) || \ 13165 ((INSTANCE) == TIM3) || \ 13166 ((INSTANCE) == TIM4) || \ 13167 ((INSTANCE) == TIM6) || \ 13168 ((INSTANCE) == TIM7) || \ 13169 ((INSTANCE) == TIM8) || \ 13170 ((INSTANCE) == TIM15)) 13171 13172 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 13173 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13174 ((INSTANCE) == TIM2) || \ 13175 ((INSTANCE) == TIM3) || \ 13176 ((INSTANCE) == TIM4) || \ 13177 ((INSTANCE) == TIM8) || \ 13178 ((INSTANCE) == TIM15)) 13179 13180 /****************** TIM Instances : supporting OCxREF clear *******************/ 13181 13182 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13183 ((INSTANCE) == TIM2) || \ 13184 ((INSTANCE) == TIM3) || \ 13185 ((INSTANCE) == TIM4) || \ 13186 ((INSTANCE) == TIM8) || \ 13187 ((INSTANCE) == TIM15) || \ 13188 ((INSTANCE) == TIM16) || \ 13189 ((INSTANCE) == TIM17)) 13190 13191 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ 13192 #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13193 ((INSTANCE) == TIM2) || \ 13194 ((INSTANCE) == TIM3) || \ 13195 ((INSTANCE) == TIM8) || \ 13196 ((INSTANCE) == TIM15) || \ 13197 ((INSTANCE) == TIM16) || \ 13198 ((INSTANCE) == TIM17)) 13199 13200 /****************** TIM Instances : remapping capability **********************/ 13201 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13202 ((INSTANCE) == TIM2) || \ 13203 ((INSTANCE) == TIM3) || \ 13204 ((INSTANCE) == TIM4) || \ 13205 ((INSTANCE) == TIM8)) 13206 13207 /****************** TIM Instances : supporting repetition counter *************/ 13208 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13209 ((INSTANCE) == TIM8) || \ 13210 ((INSTANCE) == TIM15) || \ 13211 ((INSTANCE) == TIM16) || \ 13212 ((INSTANCE) == TIM17)) 13213 13214 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ 13215 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13216 ((INSTANCE) == TIM8)) 13217 13218 /******************* TIM Instances : Timer input XOR function *****************/ 13219 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13220 ((INSTANCE) == TIM2) || \ 13221 ((INSTANCE) == TIM3) || \ 13222 ((INSTANCE) == TIM4) || \ 13223 ((INSTANCE) == TIM8) || \ 13224 ((INSTANCE) == TIM15)) 13225 13226 /******************* TIM Instances : Timer input selection ********************/ 13227 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13228 ((INSTANCE) == TIM2) || \ 13229 ((INSTANCE) == TIM3) || \ 13230 ((INSTANCE) == TIM4) || \ 13231 ((INSTANCE) == TIM8) || \ 13232 ((INSTANCE) == TIM15) || \ 13233 ((INSTANCE) == TIM16) || \ 13234 ((INSTANCE) == TIM17)) 13235 13236 13237 /****************** TIM Instances : Advanced timer instances *******************/ 13238 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 13239 ((INSTANCE) == TIM8)) 13240 13241 13242 /****************** TIM Instances : supporting HSE/32 request instances *******************/ 13243 #define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \ 13244 ((INSTANCE) == TIM17)) 13245 13246 13247 /******************** USART Instances : Synchronous mode **********************/ 13248 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13249 ((INSTANCE) == USART2) || \ 13250 ((INSTANCE) == USART3)) 13251 13252 /******************** UART Instances : Asynchronous mode **********************/ 13253 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13254 ((INSTANCE) == USART2) || \ 13255 ((INSTANCE) == USART3) || \ 13256 ((INSTANCE) == UART4)) 13257 13258 /*********************** UART Instances : FIFO mode ***************************/ 13259 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13260 ((INSTANCE) == USART2) || \ 13261 ((INSTANCE) == USART3) || \ 13262 ((INSTANCE) == UART4) || \ 13263 ((INSTANCE) == LPUART1)) 13264 13265 /*********************** UART Instances : SPI Slave mode **********************/ 13266 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13267 ((INSTANCE) == USART2) || \ 13268 ((INSTANCE) == USART3)) 13269 13270 /****************** UART Instances : Auto Baud Rate detection ****************/ 13271 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13272 ((INSTANCE) == USART2) || \ 13273 ((INSTANCE) == USART3) || \ 13274 ((INSTANCE) == UART4)) 13275 13276 /****************** UART Instances : Driver Enable *****************/ 13277 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13278 ((INSTANCE) == USART2) || \ 13279 ((INSTANCE) == USART3) || \ 13280 ((INSTANCE) == UART4) || \ 13281 ((INSTANCE) == LPUART1)) 13282 13283 /******************** UART Instances : Half-Duplex mode **********************/ 13284 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13285 ((INSTANCE) == USART2) || \ 13286 ((INSTANCE) == USART3) || \ 13287 ((INSTANCE) == UART4) || \ 13288 ((INSTANCE) == LPUART1)) 13289 13290 /****************** UART Instances : Hardware Flow control ********************/ 13291 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13292 ((INSTANCE) == USART2) || \ 13293 ((INSTANCE) == USART3) || \ 13294 ((INSTANCE) == UART4) || \ 13295 ((INSTANCE) == LPUART1)) 13296 13297 /******************** UART Instances : LIN mode **********************/ 13298 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13299 ((INSTANCE) == USART2) || \ 13300 ((INSTANCE) == USART3) || \ 13301 ((INSTANCE) == UART4)) 13302 13303 /******************** UART Instances : Wake-up from Stop mode **********************/ 13304 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13305 ((INSTANCE) == USART2) || \ 13306 ((INSTANCE) == USART3) || \ 13307 ((INSTANCE) == UART4) || \ 13308 ((INSTANCE) == LPUART1)) 13309 13310 /*********************** UART Instances : IRDA mode ***************************/ 13311 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13312 ((INSTANCE) == USART2) || \ 13313 ((INSTANCE) == USART3) || \ 13314 ((INSTANCE) == UART4)) 13315 13316 /********************* USART Instances : Smard card mode ***********************/ 13317 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 13318 ((INSTANCE) == USART2) || \ 13319 ((INSTANCE) == USART3)) 13320 13321 /******************** LPUART Instance *****************************************/ 13322 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) 13323 13324 /****************************** IWDG Instances ********************************/ 13325 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 13326 13327 /****************************** WWDG Instances ********************************/ 13328 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 13329 13330 /****************************** UCPD Instances ********************************/ 13331 #define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1) 13332 13333 /******************************* USB Instances *******************************/ 13334 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) 13335 13336 /** 13337 * @} 13338 */ 13339 13340 13341 /******************************************************************************/ 13342 /* For a painless codes migration between the STM32G4xx device product */ 13343 /* lines, the aliases defined below are put in place to overcome the */ 13344 /* differences in the interrupt handlers and IRQn definitions. */ 13345 /* No need to update developed interrupt code when moving across */ 13346 /* product lines within the same STM32G4 Family */ 13347 /******************************************************************************/ 13348 13349 /* Aliases for __IRQn */ 13350 #define TIM7_DAC_IRQn TIM7_IRQn 13351 #define COMP4_5_6_IRQn COMP4_IRQn 13352 13353 /* Aliases for __IRQHandler */ 13354 #define TIM7_DAC_IRQHandler TIM7_IRQHandler 13355 #define COMP4_5_6_IRQHandler COMP4_IRQHandler 13356 13357 #ifdef __cplusplus 13358 } 13359 #endif /* __cplusplus */ 13360 13361 #endif /* __STM32G441xx_H */ 13362 13363 /** 13364 * @} 13365 */ 13366 13367 /** 13368 * @} 13369 */ 13370 13371 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 13372