1 /**
2 ******************************************************************************
3 * @file stm32f37x_wwdg.c
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 20-September-2012
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Window watchdog (WWDG) peripheral:
9 * + Prescaler, Refresh window and Counter configuration
10 * + WWDG activation
11 * + Interrupts and flags management
12 *
13 * @verbatim
14 *
15 ==============================================================================
16 ##### WWDG features #####
17 ==============================================================================
18 [..] Once enabled the WWDG generates a system reset on expiry of a programmed
19 time period, unless the program refreshes the counter (downcounter)
20 before to reach 0x3F value (i.e. a reset is generated when the counter
21 value rolls over from 0x40 to 0x3F).
22 [..] An MCU reset is also generated if the counter value is refreshed
23 before the counter has reached the refresh window value. This
24 implies that the counter must be refreshed in a limited window.
25
26 [..] Once enabled the WWDG cannot be disabled except by a system reset.
27
28 [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
29 reset occurs.
30
31 [..] The WWDG counter input clock is derived from the APB clock divided
32 by a programmable prescaler.
33
34 [..] WWDG counter clock = PCLK1 / Prescaler.
35 [..] WWDG timeout = (WWDG counter clock) * (counter value).
36
37 [..] Min-max timeout value @36MHz (PCLK1): ~114us / ~58.3ms.
38
39 ##### How to use this driver #####
40 ==============================================================================
41 [..]
42 (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
43 function.
44
45 (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
46
47 (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
48
49 (#) Set the WWDG counter value and start it using WWDG_Enable() function.
50 When the WWDG is enabled the counter value should be configured to
51 a value greater than 0x40 to prevent generating an immediate reset.
52
53 (#) Optionally you can enable the Early wakeup interrupt which is
54 generated when the counter reach 0x40.
55 Once enabled this interrupt cannot be disabled except by a system reset.
56
57 (#) Then the application program must refresh the WWDG counter at regular
58 intervals during normal operation to prevent an MCU reset, using
59 WWDG_SetCounter() function. This operation must occur only when
60 the counter value is lower than the refresh window value,
61 programmed using WWDG_SetWindowValue().
62
63 * @endverbatim
64 *
65 ******************************************************************************
66 * @attention
67 *
68 * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
69 *
70 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
71 * You may not use this file except in compliance with the License.
72 * You may obtain a copy of the License at:
73 *
74 * http://www.st.com/software_license_agreement_liberty_v2
75 *
76 * Unless required by applicable law or agreed to in writing, software
77 * distributed under the License is distributed on an "AS IS" BASIS,
78 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
79 * See the License for the specific language governing permissions and
80 * limitations under the License.
81 *
82 ******************************************************************************
83 */
84
85 /* Includes ------------------------------------------------------------------*/
86 #include "stm32f37x_wwdg.h"
87 #include "stm32f37x_rcc.h"
88
89 /** @addtogroup STM32F37x_StdPeriph_Driver
90 * @{
91 */
92
93 /** @defgroup WWDG
94 * @brief WWDG driver modules
95 * @{
96 */
97
98 /* Private typedef -----------------------------------------------------------*/
99 /* Private define ------------------------------------------------------------*/
100
101 /* ----------- WWDG registers bit address in the alias region ----------- */
102 #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
103
104 /* Alias word address of EWI bit */
105 #define CFR_OFFSET (WWDG_OFFSET + 0x04)
106 #define EWI_BitNumber 0x09
107 #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
108
109 /* --------------------- WWDG registers bit mask ------------------------ */
110
111 /* CFR register bit mask */
112 #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
113 #define CFR_W_MASK ((uint32_t)0xFFFFFF80)
114 #define BIT_MASK ((uint8_t)0x7F)
115
116 /* Private macro -------------------------------------------------------------*/
117 /* Private variables ---------------------------------------------------------*/
118 /* Private function prototypes -----------------------------------------------*/
119 /* Private functions ---------------------------------------------------------*/
120
121 /** @defgroup WWDG_Private_Functions
122 * @{
123 */
124
125 /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
126 * @brief Prescaler, Refresh window and Counter configuration functions
127 *
128 @verbatim
129 ==============================================================================
130 ##### Prescaler, Refresh window and Counter configuration functions #####
131 ==============================================================================
132
133 @endverbatim
134 * @{
135 */
136
137 /**
138 * @brief Deinitializes the WWDG peripheral registers to their default reset values.
139 * @param None
140 * @retval None
141 */
WWDG_DeInit(void)142 void WWDG_DeInit(void)
143 {
144 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
145 RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
146 }
147
148 /**
149 * @brief Sets the WWDG Prescaler.
150 * @param WWDG_Prescaler: specifies the WWDG Prescaler.
151 * This parameter can be one of the following values:
152 * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
153 * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
154 * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
155 * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
156 * @retval None
157 */
WWDG_SetPrescaler(uint32_t WWDG_Prescaler)158 void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
159 {
160 uint32_t tmpreg = 0;
161 /* Check the parameters */
162 assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
163 /* Clear WDGTB[1:0] bits */
164 tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
165 /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
166 tmpreg |= WWDG_Prescaler;
167 /* Store the new value */
168 WWDG->CFR = tmpreg;
169 }
170
171 /**
172 * @brief Sets the WWDG window value.
173 * @param WindowValue: specifies the window value to be compared to the downcounter.
174 * This parameter value must be lower than 0x80.
175 * @retval None
176 */
WWDG_SetWindowValue(uint8_t WindowValue)177 void WWDG_SetWindowValue(uint8_t WindowValue)
178 {
179 __IO uint32_t tmpreg = 0;
180
181 /* Check the parameters */
182 assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
183 /* Clear W[6:0] bits */
184
185 tmpreg = WWDG->CFR & CFR_W_MASK;
186
187 /* Set W[6:0] bits according to WindowValue value */
188 tmpreg |= WindowValue & (uint32_t) BIT_MASK;
189
190 /* Store the new value */
191 WWDG->CFR = tmpreg;
192 }
193
194 /**
195 * @brief Enables the WWDG Early Wakeup interrupt(EWI).
196 * @note Once enabled this interrupt cannot be disabled except by a system reset.
197 * @param None
198 * @retval None
199 */
WWDG_EnableIT(void)200 void WWDG_EnableIT(void)
201 {
202 *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
203 }
204
205 /**
206 * @brief Sets the WWDG counter value.
207 * @param Counter: specifies the watchdog counter value.
208 * This parameter must be a number between 0x40 and 0x7F (to prevent
209 * generating an immediate reset).
210 * @retval None
211 */
WWDG_SetCounter(uint8_t Counter)212 void WWDG_SetCounter(uint8_t Counter)
213 {
214 /* Check the parameters */
215 assert_param(IS_WWDG_COUNTER(Counter));
216 /* Write to T[6:0] bits to configure the counter value, no need to do
217 a read-modify-write; writing a 0 to WDGA bit does nothing */
218 WWDG->CR = Counter & BIT_MASK;
219 }
220
221 /**
222 * @}
223 */
224
225 /** @defgroup WWDG_Group2 WWDG activation functions
226 * @brief WWDG activation functions
227 *
228 @verbatim
229 ==============================================================================
230 ##### WWDG activation function #####
231 ==============================================================================
232
233 @endverbatim
234 * @{
235 */
236
237 /**
238 * @brief Enables WWDG and load the counter value.
239 * @param Counter: specifies the watchdog counter value.
240 * This parameter must be a number between 0x40 and 0x7F (to prevent
241 * generating an immediate reset).
242 * @retval None
243 */
WWDG_Enable(uint8_t Counter)244 void WWDG_Enable(uint8_t Counter)
245 {
246 /* Check the parameters */
247 assert_param(IS_WWDG_COUNTER(Counter));
248 WWDG->CR = WWDG_CR_WDGA | Counter;
249 }
250
251 /**
252 * @}
253 */
254
255 /** @defgroup WWDG_Group3 Interrupts and flags management functions
256 * @brief Interrupts and flags management functions
257 *
258 @verbatim
259 ==============================================================================
260 ##### Interrupts and flags management functions #####
261 ==============================================================================
262
263 @endverbatim
264 * @{
265 */
266
267 /**
268 * @brief Checks whether the Early Wakeup interrupt flag is set or not.
269 * @param None
270 * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
271 */
WWDG_GetFlagStatus(void)272 FlagStatus WWDG_GetFlagStatus(void)
273 {
274 FlagStatus bitstatus = RESET;
275
276 if ((WWDG->SR) != (uint32_t)RESET)
277 {
278 bitstatus = SET;
279 }
280 else
281 {
282 bitstatus = RESET;
283 }
284 return bitstatus;
285 }
286
287 /**
288 * @brief Clears Early Wakeup interrupt flag.
289 * @param None
290 * @retval None
291 */
WWDG_ClearFlag(void)292 void WWDG_ClearFlag(void)
293 {
294 WWDG->SR = (uint32_t)RESET;
295 }
296
297 /**
298 * @}
299 */
300
301 /**
302 * @}
303 */
304
305 /**
306 * @}
307 */
308
309 /**
310 * @}
311 */
312
313 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
314