1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32G4xx_HAL_TIM_H 22 #define STM32G4xx_HAL_TIM_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32g4xx_hal_def.h" 30 31 /** @addtogroup STM32G4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup TIM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup TIM_Exported_Types TIM Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief TIM Time base Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 51 Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */ 52 53 uint32_t CounterMode; /*!< Specifies the counter mode. 54 This parameter can be a value of @ref TIM_Counter_Mode */ 55 56 uint32_t Period; /*!< Specifies the period value to be loaded into the active 57 Auto-Reload Register at the next update event. 58 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) 59 Macros __HAL_TIM_CALC_PERIOD(), __HAL_TIM_CALC_PERIOD_DITHER(), __HAL_TIM_CALC_PERIOD_BY_DELAY(), __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY() 60 can be used to calculate Period value */ 61 62 uint32_t ClockDivision; /*!< Specifies the clock division. 63 This parameter can be a value of @ref TIM_ClockDivision */ 64 65 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 66 reaches zero, an update event is generated and counting restarts 67 from the RCR value (N). 68 This means in PWM mode that (N+1) corresponds to: 69 - the number of PWM periods in edge-aligned mode 70 - the number of half PWM period in center-aligned mode 71 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 72 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ 73 74 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 75 This parameter can be a value of @ref TIM_AutoReloadPreload */ 76 } TIM_Base_InitTypeDef; 77 78 /** 79 * @brief TIM Output Compare Configuration Structure definition 80 */ 81 typedef struct 82 { 83 uint32_t OCMode; /*!< Specifies the TIM mode. 84 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 85 86 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 87 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) 88 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() 89 can be used to calculate Pulse value */ 90 91 uint32_t OCPolarity; /*!< Specifies the output polarity. 92 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 93 94 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 95 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 96 @note This parameter is valid only for timer instances supporting break feature. */ 97 98 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 99 This parameter can be a value of @ref TIM_Output_Fast_State 100 @note This parameter is valid only in PWM1 and PWM2 mode. */ 101 102 103 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 104 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 105 @note This parameter is valid only for timer instances supporting break feature. */ 106 107 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 108 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 109 @note This parameter is valid only for timer instances supporting break feature. */ 110 } TIM_OC_InitTypeDef; 111 112 /** 113 * @brief TIM One Pulse Mode Configuration Structure definition 114 */ 115 typedef struct 116 { 117 uint32_t OCMode; /*!< Specifies the TIM mode. 118 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 119 120 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 121 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated) 122 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() 123 can be used to calculate Pulse value */ 124 125 uint32_t OCPolarity; /*!< Specifies the output polarity. 126 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 127 128 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 129 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 130 @note This parameter is valid only for timer instances supporting break feature. */ 131 132 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 133 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 134 @note This parameter is valid only for timer instances supporting break feature. */ 135 136 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 137 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 138 @note This parameter is valid only for timer instances supporting break feature. */ 139 140 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 141 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 142 143 uint32_t ICSelection; /*!< Specifies the input. 144 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 145 146 uint32_t ICFilter; /*!< Specifies the input capture filter. 147 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 148 } TIM_OnePulse_InitTypeDef; 149 150 /** 151 * @brief TIM Input Capture Configuration Structure definition 152 */ 153 typedef struct 154 { 155 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 156 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 157 158 uint32_t ICSelection; /*!< Specifies the input. 159 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 160 161 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 162 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 163 164 uint32_t ICFilter; /*!< Specifies the input capture filter. 165 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 166 } TIM_IC_InitTypeDef; 167 168 /** 169 * @brief TIM Encoder Configuration Structure definition 170 */ 171 typedef struct 172 { 173 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 174 This parameter can be a value of @ref TIM_Encoder_Mode */ 175 176 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 177 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 178 179 uint32_t IC1Selection; /*!< Specifies the input. 180 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 181 182 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 183 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 184 185 uint32_t IC1Filter; /*!< Specifies the input capture filter. 186 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 187 188 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 189 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 190 191 uint32_t IC2Selection; /*!< Specifies the input. 192 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 193 194 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 195 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 196 197 uint32_t IC2Filter; /*!< Specifies the input capture filter. 198 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 199 } TIM_Encoder_InitTypeDef; 200 201 /** 202 * @brief Clock Configuration Handle Structure definition 203 */ 204 typedef struct 205 { 206 uint32_t ClockSource; /*!< TIM clock sources 207 This parameter can be a value of @ref TIM_Clock_Source */ 208 uint32_t ClockPolarity; /*!< TIM clock polarity 209 This parameter can be a value of @ref TIM_Clock_Polarity */ 210 uint32_t ClockPrescaler; /*!< TIM clock prescaler 211 This parameter can be a value of @ref TIM_Clock_Prescaler */ 212 uint32_t ClockFilter; /*!< TIM clock filter 213 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 214 } TIM_ClockConfigTypeDef; 215 216 /** 217 * @brief TIM Clear Input Configuration Handle Structure definition 218 */ 219 typedef struct 220 { 221 uint32_t ClearInputState; /*!< TIM clear Input state 222 This parameter can be ENABLE or DISABLE */ 223 uint32_t ClearInputSource; /*!< TIM clear Input sources 224 This parameter can be a value of @ref TIM_ClearInput_Source */ 225 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 226 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 227 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 228 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ 229 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 230 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 231 } TIM_ClearInputConfigTypeDef; 232 233 /** 234 * @brief TIM Master configuration Structure definition 235 * @note Advanced timers provide TRGO2 internal line which is redirected 236 * to the ADC 237 */ 238 typedef struct 239 { 240 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 241 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 242 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 243 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 244 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 245 This parameter can be a value of @ref TIM_Master_Slave_Mode 246 @note When the Master/slave mode is enabled, the effect of 247 an event on the trigger input (TRGI) is delayed to allow a 248 perfect synchronization between the current timer and its 249 slaves (through TRGO). It is not mandatory in case of timer 250 synchronization mode. */ 251 } TIM_MasterConfigTypeDef; 252 253 /** 254 * @brief TIM Slave configuration Structure definition 255 */ 256 typedef struct 257 { 258 uint32_t SlaveMode; /*!< Slave mode selection 259 This parameter can be a value of @ref TIM_Slave_Mode */ 260 uint32_t InputTrigger; /*!< Input Trigger source 261 This parameter can be a value of @ref TIM_Trigger_Selection */ 262 uint32_t TriggerPolarity; /*!< Input Trigger polarity 263 This parameter can be a value of @ref TIM_Trigger_Polarity */ 264 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 265 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 266 uint32_t TriggerFilter; /*!< Input trigger filter 267 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 268 269 } TIM_SlaveConfigTypeDef; 270 271 /** 272 * @brief TIM Break input(s) and Dead time configuration Structure definition 273 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 274 * filter and polarity. 275 */ 276 typedef struct 277 { 278 uint32_t OffStateRunMode; /*!< TIM off state in run mode 279 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 280 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode 281 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 282 uint32_t LockLevel; /*!< TIM Lock level 283 This parameter can be a value of @ref TIM_Lock_level */ 284 uint32_t DeadTime; /*!< TIM dead Time 285 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 286 uint32_t BreakState; /*!< TIM Break State 287 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 288 uint32_t BreakPolarity; /*!< TIM Break input polarity 289 This parameter can be a value of @ref TIM_Break_Polarity */ 290 uint32_t BreakFilter; /*!< Specifies the break input filter. 291 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 292 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. 293 This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ 294 uint32_t Break2State; /*!< TIM Break2 State 295 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 296 uint32_t Break2Polarity; /*!< TIM Break2 input polarity 297 This parameter can be a value of @ref TIM_Break2_Polarity */ 298 uint32_t Break2Filter; /*!< TIM break2 input filter. 299 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 300 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. 301 This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ 302 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state 303 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 304 } TIM_BreakDeadTimeConfigTypeDef; 305 306 /** 307 * @brief HAL State structures definition 308 */ 309 typedef enum 310 { 311 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 312 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 313 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 314 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 315 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 316 } HAL_TIM_StateTypeDef; 317 318 /** 319 * @brief TIM Channel States definition 320 */ 321 typedef enum 322 { 323 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 324 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 325 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 326 } HAL_TIM_ChannelStateTypeDef; 327 328 /** 329 * @brief DMA Burst States definition 330 */ 331 typedef enum 332 { 333 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 334 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 335 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 336 } HAL_TIM_DMABurstStateTypeDef; 337 338 /** 339 * @brief HAL Active channel structures definition 340 */ 341 typedef enum 342 { 343 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 344 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 345 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 346 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 347 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 348 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 349 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 350 } HAL_TIM_ActiveChannel; 351 352 /** 353 * @brief TIM Time Base Handle Structure definition 354 */ 355 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 356 typedef struct __TIM_HandleTypeDef 357 #else 358 typedef struct 359 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 360 { 361 TIM_TypeDef *Instance; /*!< Register base address */ 362 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 363 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 364 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 365 This array is accessed by a @ref DMA_Handle_index */ 366 HAL_LockTypeDef Lock; /*!< Locking object */ 367 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 368 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 369 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 370 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 371 372 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 373 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 374 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 375 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 376 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 377 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 378 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 379 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 380 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 381 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 382 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 383 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 384 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 385 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 386 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 387 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 388 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 389 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 390 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 391 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 392 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 393 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 394 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 395 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 396 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 397 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 398 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 399 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 400 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 401 void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ 402 void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ 403 void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ 404 void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */ 405 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 406 } TIM_HandleTypeDef; 407 408 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 409 /** 410 * @brief HAL TIM Callback ID enumeration definition 411 */ 412 typedef enum 413 { 414 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 415 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 416 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 417 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 418 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 419 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 420 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 421 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 422 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 423 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 424 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 425 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 426 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 427 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 428 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 429 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 430 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 431 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 432 433 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 434 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 435 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 436 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 437 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 438 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 439 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 440 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 441 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 442 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 443 ,HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ 444 ,HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ 445 ,HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ 446 ,HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ 447 } HAL_TIM_CallbackIDTypeDef; 448 449 /** 450 * @brief HAL TIM Callback pointer definition 451 */ 452 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 453 454 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 455 456 /** 457 * @} 458 */ 459 /* End of exported types -----------------------------------------------------*/ 460 461 /* Exported constants --------------------------------------------------------*/ 462 /** @defgroup TIM_Exported_Constants TIM Exported Constants 463 * @{ 464 */ 465 466 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 467 * @{ 468 */ 469 #define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ 470 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 471 #define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ 472 #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ 473 #define TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF_CLR_INT is connected to COMP3 output */ 474 #define TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP4 output */ 475 #if defined (COMP5) 476 #define TIM_CLEARINPUTSOURCE_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF_CLR_INT is connected to COMP5 output */ 477 #endif /* COMP5 */ 478 #if defined (COMP6) 479 #define TIM_CLEARINPUTSOURCE_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP6 output */ 480 #endif /* COMP6 */ 481 #if defined (COMP7) 482 #define TIM_CLEARINPUTSOURCE_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF_CLR_INT is connected to COMP7 output */ 483 #endif /* COMP7 */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 489 * @{ 490 */ 491 #define TIM_DMABASE_CR1 0x00000000U 492 #define TIM_DMABASE_CR2 0x00000001U 493 #define TIM_DMABASE_SMCR 0x00000002U 494 #define TIM_DMABASE_DIER 0x00000003U 495 #define TIM_DMABASE_SR 0x00000004U 496 #define TIM_DMABASE_EGR 0x00000005U 497 #define TIM_DMABASE_CCMR1 0x00000006U 498 #define TIM_DMABASE_CCMR2 0x00000007U 499 #define TIM_DMABASE_CCER 0x00000008U 500 #define TIM_DMABASE_CNT 0x00000009U 501 #define TIM_DMABASE_PSC 0x0000000AU 502 #define TIM_DMABASE_ARR 0x0000000BU 503 #define TIM_DMABASE_RCR 0x0000000CU 504 #define TIM_DMABASE_CCR1 0x0000000DU 505 #define TIM_DMABASE_CCR2 0x0000000EU 506 #define TIM_DMABASE_CCR3 0x0000000FU 507 #define TIM_DMABASE_CCR4 0x00000010U 508 #define TIM_DMABASE_BDTR 0x00000011U 509 #define TIM_DMABASE_CCR5 0x00000012U 510 #define TIM_DMABASE_CCR6 0x00000013U 511 #define TIM_DMABASE_CCMR3 0x00000014U 512 #define TIM_DMABASE_DTR2 0x00000015U 513 #define TIM_DMABASE_ECR 0x00000016U 514 #define TIM_DMABASE_TISEL 0x00000017U 515 #define TIM_DMABASE_AF1 0x00000018U 516 #define TIM_DMABASE_AF2 0x00000019U 517 #define TIM_DMABASE_OR 0x0000001AU 518 /** 519 * @} 520 */ 521 522 /** @defgroup TIM_Event_Source TIM Event Source 523 * @{ 524 */ 525 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 526 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 527 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 528 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 529 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 530 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 531 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 532 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 533 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 534 /** 535 * @} 536 */ 537 538 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 539 * @{ 540 */ 541 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 542 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 543 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 544 /** 545 * @} 546 */ 547 548 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 549 * @{ 550 */ 551 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 552 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 553 /** 554 * @} 555 */ 556 557 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 558 * @{ 559 */ 560 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 561 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 562 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 563 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 564 /** 565 * @} 566 */ 567 568 /** @defgroup TIM_Counter_Mode TIM Counter Mode 569 * @{ 570 */ 571 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 572 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 573 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 574 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 575 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 576 /** 577 * @} 578 */ 579 580 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 581 * @{ 582 */ 583 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 584 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup TIM_ClockDivision TIM Clock Division 590 * @{ 591 */ 592 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 593 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 594 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 595 /** 596 * @} 597 */ 598 599 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 600 * @{ 601 */ 602 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 603 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 604 /** 605 * @} 606 */ 607 608 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 609 * @{ 610 */ 611 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 612 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 613 614 /** 615 * @} 616 */ 617 618 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 619 * @{ 620 */ 621 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 622 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 623 /** 624 * @} 625 */ 626 627 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 628 * @{ 629 */ 630 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 631 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 632 /** 633 * @} 634 */ 635 636 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 637 * @{ 638 */ 639 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 640 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 641 /** 642 * @} 643 */ 644 645 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 646 * @{ 647 */ 648 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 649 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 650 /** 651 * @} 652 */ 653 654 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 655 * @{ 656 */ 657 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 658 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 659 /** 660 * @} 661 */ 662 663 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 664 * @{ 665 */ 666 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 667 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 668 /** 669 * @} 670 */ 671 672 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 673 * @{ 674 */ 675 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 676 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 677 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 678 /** 679 * @} 680 */ 681 682 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 683 * @{ 684 */ 685 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 686 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 687 /** 688 * @} 689 */ 690 691 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 692 * @{ 693 */ 694 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be 695 connected to IC1, IC2, IC3 or IC4, respectively */ 696 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be 697 connected to IC2, IC1, IC4 or IC3, respectively */ 698 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 699 /** 700 * @} 701 */ 702 703 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 704 * @{ 705 */ 706 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 707 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 708 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 709 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 710 /** 711 * @} 712 */ 713 714 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 715 * @{ 716 */ 717 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 718 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 719 /** 720 * @} 721 */ 722 723 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 724 * @{ 725 */ 726 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 727 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 728 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 729 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */ 730 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */ 731 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */ 732 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ 733 #define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */ 734 #define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */ 735 /** 736 * @} 737 */ 738 739 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 740 * @{ 741 */ 742 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 743 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 744 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 745 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 746 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 747 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 748 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 749 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 750 #define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */ 751 #define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */ 752 #define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */ 753 #define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */ 754 /** 755 * @} 756 */ 757 758 /** @defgroup TIM_Commutation_Source TIM Commutation Source 759 * @{ 760 */ 761 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 762 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 763 /** 764 * @} 765 */ 766 767 /** @defgroup TIM_DMA_sources TIM DMA Sources 768 * @{ 769 */ 770 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 771 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 772 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 773 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 774 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 775 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 776 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 777 /** 778 * @} 779 */ 780 781 /** @defgroup TIM_Flag_definition TIM Flag Definition 782 * @{ 783 */ 784 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 785 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 786 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 787 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 788 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 789 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 790 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 791 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 792 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 793 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 794 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 795 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 796 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 797 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 798 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 799 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 800 #define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */ 801 #define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */ 802 #define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */ 803 #define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */ 804 /** 805 * @} 806 */ 807 808 /** @defgroup TIM_Channel TIM Channel 809 * @{ 810 */ 811 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 812 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 813 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 814 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 815 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 816 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 817 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 818 /** 819 * @} 820 */ 821 822 /** @defgroup TIM_Clock_Source TIM Clock Source 823 * @{ 824 */ 825 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 826 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 827 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 828 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 829 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 830 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 831 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 832 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 833 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 834 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 835 #if defined (TIM5) 836 #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ 837 #endif /* TIM5 */ 838 #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ 839 #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ 840 #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ 841 #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ 842 #if defined (TIM20) 843 #define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */ 844 #endif /* TIM20 */ 845 #define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */ 846 #define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ 847 /** 848 * @} 849 */ 850 851 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 852 * @{ 853 */ 854 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 855 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 856 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 857 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 858 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 859 /** 860 * @} 861 */ 862 863 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 864 * @{ 865 */ 866 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 867 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 868 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 869 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 870 /** 871 * @} 872 */ 873 874 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 875 * @{ 876 */ 877 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 878 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 879 /** 880 * @} 881 */ 882 883 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 884 * @{ 885 */ 886 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 887 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 888 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 889 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 890 /** 891 * @} 892 */ 893 894 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 895 * @{ 896 */ 897 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 898 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 899 /** 900 * @} 901 */ 902 903 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 904 * @{ 905 */ 906 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 907 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 908 /** 909 * @} 910 */ 911 /** @defgroup TIM_Lock_level TIM Lock level 912 * @{ 913 */ 914 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 915 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 916 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 917 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 918 /** 919 * @} 920 */ 921 922 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 923 * @{ 924 */ 925 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 926 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 927 /** 928 * @} 929 */ 930 931 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 932 * @{ 933 */ 934 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 935 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 936 /** 937 * @} 938 */ 939 940 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode 941 * @{ 942 */ 943 #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ 944 #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ 945 /** 946 * @} 947 */ 948 949 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 950 * @{ 951 */ 952 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 953 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 954 /** 955 * @} 956 */ 957 958 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 959 * @{ 960 */ 961 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 962 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 963 /** 964 * @} 965 */ 966 967 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode 968 * @{ 969 */ 970 #define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ 971 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ 972 /** 973 * @} 974 */ 975 976 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 977 * @{ 978 */ 979 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 980 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event 981 (if none of the break inputs BRK and BRK2 is active) */ 982 /** 983 * @} 984 */ 985 986 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 987 * @{ 988 */ 989 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 990 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ 991 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ 992 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ 993 /** 994 * @} 995 */ 996 997 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 998 * @{ 999 */ 1000 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 1001 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 1002 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 1003 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 1004 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 1005 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 1006 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 1007 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 1008 #define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */ 1009 /** 1010 * @} 1011 */ 1012 1013 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 1014 * @{ 1015 */ 1016 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 1017 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 1018 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 1019 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 1020 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 1021 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 1022 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 1023 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 1024 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 1025 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 1026 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 1027 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 1028 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 1029 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 1030 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 1031 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 1032 /** 1033 * @} 1034 */ 1035 1036 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 1037 * @{ 1038 */ 1039 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 1040 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 1041 /** 1042 * @} 1043 */ 1044 1045 /** @defgroup TIM_Slave_Mode TIM Slave mode 1046 * @{ 1047 */ 1048 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 1049 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 1050 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 1051 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 1052 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 1053 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 1054 #define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */ 1055 /** 1056 * @} 1057 */ 1058 1059 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 1060 * @{ 1061 */ 1062 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 1063 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 1064 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 1065 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 1066 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 1067 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 1068 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 1069 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 1070 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 1071 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 1072 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 1073 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 1074 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 1075 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 1076 #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ 1077 #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ 1078 /** 1079 * @} 1080 */ 1081 1082 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 1083 * @{ 1084 */ 1085 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 1086 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 1087 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 1088 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 1089 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 1090 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 1091 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 1092 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 1093 #if defined (TIM5) 1094 #define TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR9) */ 1095 #endif /* TIM5 */ 1096 #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ 1097 #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ 1098 #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ 1099 #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ 1100 #if defined (TIM20) 1101 #define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ 1102 #endif /* TIM20 */ 1103 #define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ 1104 #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ 1105 #define TIM_TS_NONE 0xFFFFFFFFU /*!< No trigger selected */ 1106 /** 1107 * @} 1108 */ 1109 1110 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 1111 * @{ 1112 */ 1113 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1114 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1115 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1116 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1117 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1118 /** 1119 * @} 1120 */ 1121 1122 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1123 * @{ 1124 */ 1125 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1126 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1127 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1128 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1129 /** 1130 * @} 1131 */ 1132 1133 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1134 * @{ 1135 */ 1136 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1137 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1138 /** 1139 * @} 1140 */ 1141 1142 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1143 * @{ 1144 */ 1145 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1146 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1147 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1148 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1149 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1150 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1151 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1152 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1153 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1154 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1155 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1156 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1157 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1158 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1159 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1160 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1161 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1162 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1163 #define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1164 #define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1165 #define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1166 #define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1167 #define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1168 #define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1169 #define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1170 #define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ 1171 /** 1172 * @} 1173 */ 1174 1175 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1176 * @{ 1177 */ 1178 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1179 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1180 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1181 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1182 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1183 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1184 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1185 /** 1186 * @} 1187 */ 1188 1189 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1190 * @{ 1191 */ 1192 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1193 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1194 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1195 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1196 /** 1197 * @} 1198 */ 1199 1200 /** @defgroup TIM_Break_System TIM Break System 1201 * @{ 1202 */ 1203 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */ 1204 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1205 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */ 1206 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */ 1207 /** 1208 * @} 1209 */ 1210 1211 /** 1212 * @} 1213 */ 1214 /* End of exported constants -------------------------------------------------*/ 1215 1216 /* Exported macros -----------------------------------------------------------*/ 1217 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1218 * @{ 1219 */ 1220 1221 /** @brief Reset TIM handle state. 1222 * @param __HANDLE__ TIM handle. 1223 * @retval None 1224 */ 1225 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1226 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1227 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1228 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1229 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1230 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1231 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1232 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1233 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1234 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1235 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1236 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1237 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1238 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1239 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1240 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1241 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1242 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1243 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1244 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1245 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1246 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1247 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1248 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1249 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1250 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1251 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1252 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1253 } while(0) 1254 #else 1255 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1256 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1257 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1258 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1259 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1260 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1261 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1262 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1263 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1264 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1265 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1266 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1267 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1268 } while(0) 1269 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1270 1271 /** 1272 * @brief Enable the TIM peripheral. 1273 * @param __HANDLE__ TIM handle 1274 * @retval None 1275 */ 1276 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1277 1278 /** 1279 * @brief Enable the TIM main Output. 1280 * @param __HANDLE__ TIM handle 1281 * @retval None 1282 */ 1283 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1284 1285 /** 1286 * @brief Disable the TIM peripheral. 1287 * @param __HANDLE__ TIM handle 1288 * @retval None 1289 */ 1290 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1291 do { \ 1292 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1293 { \ 1294 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1295 { \ 1296 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1297 } \ 1298 } \ 1299 } while(0) 1300 1301 /** 1302 * @brief Disable the TIM main Output. 1303 * @param __HANDLE__ TIM handle 1304 * @retval None 1305 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled 1306 */ 1307 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1308 do { \ 1309 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1310 { \ 1311 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1312 { \ 1313 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1314 } \ 1315 } \ 1316 } while(0) 1317 1318 /** 1319 * @brief Disable the TIM main Output. 1320 * @param __HANDLE__ TIM handle 1321 * @retval None 1322 * @note The Main Output Enable of a timer instance is disabled unconditionally 1323 */ 1324 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1325 1326 /** @brief Enable the specified TIM interrupt. 1327 * @param __HANDLE__ specifies the TIM Handle. 1328 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1329 * This parameter can be one of the following values: 1330 * @arg TIM_IT_UPDATE: Update interrupt 1331 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1332 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1333 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1334 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1335 * @arg TIM_IT_COM: Commutation interrupt 1336 * @arg TIM_IT_TRIGGER: Trigger interrupt 1337 * @arg TIM_IT_BREAK: Break interrupt 1338 * @arg TIM_IT_IDX: Index interrupt 1339 * @arg TIM_IT_DIR: Direction change interrupt 1340 * @arg TIM_IT_IERR: Index error interrupt 1341 * @arg TIM_IT_TERR: Transition error interrupt 1342 * @retval None 1343 */ 1344 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1345 1346 /** @brief Disable the specified TIM interrupt. 1347 * @param __HANDLE__ specifies the TIM Handle. 1348 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1349 * This parameter can be one of the following values: 1350 * @arg TIM_IT_UPDATE: Update interrupt 1351 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1352 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1353 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1354 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1355 * @arg TIM_IT_COM: Commutation interrupt 1356 * @arg TIM_IT_TRIGGER: Trigger interrupt 1357 * @arg TIM_IT_BREAK: Break interrupt 1358 * @arg TIM_IT_IDX: Index interrupt 1359 * @arg TIM_IT_DIR: Direction change interrupt 1360 * @arg TIM_IT_IERR: Index error interrupt 1361 * @arg TIM_IT_TERR: Transition error interrupt 1362 * @retval None 1363 */ 1364 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1365 1366 /** @brief Enable the specified DMA request. 1367 * @param __HANDLE__ specifies the TIM Handle. 1368 * @param __DMA__ specifies the TIM DMA request to enable. 1369 * This parameter can be one of the following values: 1370 * @arg TIM_DMA_UPDATE: Update DMA request 1371 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1372 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1373 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1374 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1375 * @arg TIM_DMA_COM: Commutation DMA request 1376 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1377 * @retval None 1378 */ 1379 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1380 1381 /** @brief Disable the specified DMA request. 1382 * @param __HANDLE__ specifies the TIM Handle. 1383 * @param __DMA__ specifies the TIM DMA request to disable. 1384 * This parameter can be one of the following values: 1385 * @arg TIM_DMA_UPDATE: Update DMA request 1386 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1387 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1388 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1389 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1390 * @arg TIM_DMA_COM: Commutation DMA request 1391 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1392 * @retval None 1393 */ 1394 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1395 1396 /** @brief Check whether the specified TIM interrupt flag is set or not. 1397 * @param __HANDLE__ specifies the TIM Handle. 1398 * @param __FLAG__ specifies the TIM interrupt flag to check. 1399 * This parameter can be one of the following values: 1400 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1401 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1402 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1403 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1404 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1405 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1406 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1407 * @arg TIM_FLAG_COM: Commutation interrupt flag 1408 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1409 * @arg TIM_FLAG_BREAK: Break interrupt flag 1410 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1411 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1412 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1413 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1414 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1415 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1416 * @arg TIM_FLAG_IDX: Index interrupt flag 1417 * @arg TIM_FLAG_DIR: Direction change interrupt flag 1418 * @arg TIM_FLAG_IERR: Index error interrupt flag 1419 * @arg TIM_FLAG_TERR: Transition error interrupt flag 1420 * @retval The new state of __FLAG__ (TRUE or FALSE). 1421 */ 1422 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1423 1424 /** @brief Clear the specified TIM interrupt flag. 1425 * @param __HANDLE__ specifies the TIM Handle. 1426 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1427 * This parameter can be one of the following values: 1428 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1429 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1430 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1431 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1432 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1433 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1434 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1435 * @arg TIM_FLAG_COM: Commutation interrupt flag 1436 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1437 * @arg TIM_FLAG_BREAK: Break interrupt flag 1438 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1439 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1440 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1441 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1442 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1443 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1444 * @arg TIM_FLAG_IDX: Index interrupt flag 1445 * @arg TIM_FLAG_DIR: Direction change interrupt flag 1446 * @arg TIM_FLAG_IERR: Index error interrupt flag 1447 * @arg TIM_FLAG_TERR: Transition error interrupt flag 1448 * @retval The new state of __FLAG__ (TRUE or FALSE). 1449 */ 1450 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1451 1452 /** 1453 * @brief Check whether the specified TIM interrupt source is enabled or not. 1454 * @param __HANDLE__ TIM handle 1455 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1456 * This parameter can be one of the following values: 1457 * @arg TIM_IT_UPDATE: Update interrupt 1458 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1459 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1460 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1461 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1462 * @arg TIM_IT_COM: Commutation interrupt 1463 * @arg TIM_IT_TRIGGER: Trigger interrupt 1464 * @arg TIM_IT_BREAK: Break interrupt 1465 * @arg TIM_IT_IDX: Index interrupt 1466 * @arg TIM_IT_DIR: Direction change interrupt 1467 * @arg TIM_IT_IERR: Index error interrupt 1468 * @arg TIM_IT_TERR: Transition error interrupt 1469 * @retval The state of TIM_IT (SET or RESET). 1470 */ 1471 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1472 == (__INTERRUPT__)) ? SET : RESET) 1473 1474 /** @brief Clear the TIM interrupt pending bits. 1475 * @param __HANDLE__ TIM handle 1476 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1477 * This parameter can be one of the following values: 1478 * @arg TIM_IT_UPDATE: Update interrupt 1479 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1480 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1481 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1482 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1483 * @arg TIM_IT_COM: Commutation interrupt 1484 * @arg TIM_IT_TRIGGER: Trigger interrupt 1485 * @arg TIM_IT_BREAK: Break interrupt 1486 * @arg TIM_IT_IDX: Index interrupt 1487 * @arg TIM_IT_DIR: Direction change interrupt 1488 * @arg TIM_IT_IERR: Index error interrupt 1489 * @arg TIM_IT_TERR: Transition error interrupt 1490 * @retval None 1491 */ 1492 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1493 1494 /** 1495 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1496 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. 1497 * @param __HANDLE__ TIM handle. 1498 * @retval None 1499 mode. 1500 */ 1501 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 1502 1503 /** 1504 * @brief Disable update interrupt flag (UIF) remapping. 1505 * @param __HANDLE__ TIM handle. 1506 * @retval None 1507 mode. 1508 */ 1509 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 1510 1511 /** 1512 * @brief Get update interrupt flag (UIF) copy status. 1513 * @param __COUNTER__ Counter value. 1514 * @retval The state of UIFCPY (TRUE or FALSE). 1515 mode. 1516 */ 1517 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 1518 1519 /** 1520 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1521 * @param __HANDLE__ TIM handle. 1522 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1523 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder 1524 mode. 1525 */ 1526 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1527 1528 /** 1529 * @brief Set the TIM Prescaler on runtime. 1530 * @param __HANDLE__ TIM handle. 1531 * @param __PRESC__ specifies the Prescaler new value. 1532 * @retval None 1533 */ 1534 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1535 1536 /** 1537 * @brief Set the TIM Counter Register value on runtime. 1538 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. 1539 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 1540 * @param __HANDLE__ TIM handle. 1541 * @param __COUNTER__ specifies the Counter register new value. 1542 * @retval None 1543 */ 1544 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1545 1546 /** 1547 * @brief Get the TIM Counter Register value on runtime. 1548 * @param __HANDLE__ TIM handle. 1549 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1550 */ 1551 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1552 1553 /** 1554 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1555 * @param __HANDLE__ TIM handle. 1556 * @param __AUTORELOAD__ specifies the Counter register new value. 1557 * @retval None 1558 */ 1559 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1560 do{ \ 1561 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1562 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1563 } while(0) 1564 1565 /** 1566 * @brief Get the TIM Autoreload Register value on runtime. 1567 * @param __HANDLE__ TIM handle. 1568 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1569 */ 1570 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1571 1572 /** 1573 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1574 * @param __HANDLE__ TIM handle. 1575 * @param __CKD__ specifies the clock division value. 1576 * This parameter can be one of the following value: 1577 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1578 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1579 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1580 * @retval None 1581 */ 1582 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1583 do{ \ 1584 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1585 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1586 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1587 } while(0) 1588 1589 /** 1590 * @brief Get the TIM Clock Division value on runtime. 1591 * @param __HANDLE__ TIM handle. 1592 * @retval The clock division can be one of the following values: 1593 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1594 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1595 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1596 */ 1597 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1598 1599 /** 1600 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. 1601 * @param __HANDLE__ TIM handle. 1602 * @param __CHANNEL__ TIM Channels to be configured. 1603 * This parameter can be one of the following values: 1604 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1605 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1606 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1607 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1608 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1609 * This parameter can be one of the following values: 1610 * @arg TIM_ICPSC_DIV1: no prescaler 1611 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1612 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1613 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1614 * @retval None 1615 */ 1616 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1617 do{ \ 1618 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1619 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1620 } while(0) 1621 1622 /** 1623 * @brief Get the TIM Input Capture prescaler on runtime. 1624 * @param __HANDLE__ TIM handle. 1625 * @param __CHANNEL__ TIM Channels to be configured. 1626 * This parameter can be one of the following values: 1627 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1628 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1629 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1630 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1631 * @retval The input capture prescaler can be one of the following values: 1632 * @arg TIM_ICPSC_DIV1: no prescaler 1633 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1634 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1635 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1636 */ 1637 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1638 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1639 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1640 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1641 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1642 1643 /** 1644 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1645 * @param __HANDLE__ TIM handle. 1646 * @param __CHANNEL__ TIM Channels to be configured. 1647 * This parameter can be one of the following values: 1648 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1649 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1650 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1651 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1652 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1653 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1654 * @param __COMPARE__ specifies the Capture Compare register new value. 1655 * @retval None 1656 */ 1657 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1658 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1659 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1660 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1661 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1662 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1663 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1664 1665 /** 1666 * @brief Get the TIM Capture Compare Register value on runtime. 1667 * @param __HANDLE__ TIM handle. 1668 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1669 * This parameter can be one of the following values: 1670 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1671 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1672 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1673 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1674 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1675 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1676 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1677 */ 1678 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1679 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1680 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1681 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1682 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1683 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1684 ((__HANDLE__)->Instance->CCR6)) 1685 1686 /** 1687 * @brief Set the TIM Output compare preload. 1688 * @param __HANDLE__ TIM handle. 1689 * @param __CHANNEL__ TIM Channels to be configured. 1690 * This parameter can be one of the following values: 1691 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1692 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1693 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1694 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1695 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1696 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1697 * @retval None 1698 */ 1699 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1700 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1701 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1702 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1703 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1704 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1705 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1706 1707 /** 1708 * @brief Reset the TIM Output compare preload. 1709 * @param __HANDLE__ TIM handle. 1710 * @param __CHANNEL__ TIM Channels to be configured. 1711 * This parameter can be one of the following values: 1712 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1713 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1714 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1715 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1716 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1717 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1718 * @retval None 1719 */ 1720 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1721 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1722 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1723 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1724 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1725 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1726 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1727 1728 /** 1729 * @brief Enable fast mode for a given channel. 1730 * @param __HANDLE__ TIM handle. 1731 * @param __CHANNEL__ TIM Channels to be configured. 1732 * This parameter can be one of the following values: 1733 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1734 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1735 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1736 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1737 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1738 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1739 * @note When fast mode is enabled an active edge on the trigger input acts 1740 * like a compare match on CCx output. Delay to sample the trigger 1741 * input and to activate CCx output is reduced to 3 clock cycles. 1742 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1743 * @retval None 1744 */ 1745 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1746 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1747 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1748 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1749 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1750 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1751 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1752 1753 /** 1754 * @brief Disable fast mode for a given channel. 1755 * @param __HANDLE__ TIM handle. 1756 * @param __CHANNEL__ TIM Channels to be configured. 1757 * This parameter can be one of the following values: 1758 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1759 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1760 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1761 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1762 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1763 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1764 * @note When fast mode is disabled CCx output behaves normally depending 1765 * on counter and CCRx values even when the trigger is ON. The minimum 1766 * delay to activate CCx output when an active edge occurs on the 1767 * trigger input is 5 clock cycles. 1768 * @retval None 1769 */ 1770 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1771 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1772 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1773 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1774 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1775 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1776 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1777 1778 /** 1779 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1780 * @param __HANDLE__ TIM handle. 1781 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1782 * overflow/underflow generates an update interrupt or DMA request (if 1783 * enabled) 1784 * @retval None 1785 */ 1786 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1787 1788 /** 1789 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1790 * @param __HANDLE__ TIM handle. 1791 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1792 * following events generate an update interrupt or DMA request (if 1793 * enabled): 1794 * _ Counter overflow underflow 1795 * _ Setting the UG bit 1796 * _ Update generation through the slave mode controller 1797 * @retval None 1798 */ 1799 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1800 1801 /** 1802 * @brief Set the TIM Capture x input polarity on runtime. 1803 * @param __HANDLE__ TIM handle. 1804 * @param __CHANNEL__ TIM Channels to be configured. 1805 * This parameter can be one of the following values: 1806 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1807 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1808 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1809 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1810 * @param __POLARITY__ Polarity for TIx source 1811 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1812 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1813 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1814 * @retval None 1815 */ 1816 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1817 do{ \ 1818 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1819 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1820 }while(0) 1821 1822 /** 1823 * @} 1824 */ 1825 /* End of exported macros ----------------------------------------------------*/ 1826 1827 /* Private constants ---------------------------------------------------------*/ 1828 /** @defgroup TIM_Private_Constants TIM Private Constants 1829 * @{ 1830 */ 1831 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1832 channels have been disabled */ 1833 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1834 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) 1835 /** 1836 * @} 1837 */ 1838 /* End of private constants --------------------------------------------------*/ 1839 1840 /* Private macros ------------------------------------------------------------*/ 1841 /** @defgroup TIM_Private_Macros TIM Private Macros 1842 * @{ 1843 */ 1844 #if defined(COMP5) && defined(COMP6) && defined(COMP7) 1845 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1846 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ 1847 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ 1848 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ 1849 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \ 1850 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5) || \ 1851 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6) || \ 1852 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7) || \ 1853 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 1854 #else /* COMP5 && COMP6 && COMP7 */ 1855 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1856 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ 1857 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ 1858 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ 1859 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \ 1860 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 1861 #endif /* COMP5 && COMP6 && COMP7 */ 1862 1863 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1864 ((__BASE__) == TIM_DMABASE_CR2) || \ 1865 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1866 ((__BASE__) == TIM_DMABASE_DIER) || \ 1867 ((__BASE__) == TIM_DMABASE_SR) || \ 1868 ((__BASE__) == TIM_DMABASE_EGR) || \ 1869 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1870 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1871 ((__BASE__) == TIM_DMABASE_CCER) || \ 1872 ((__BASE__) == TIM_DMABASE_CNT) || \ 1873 ((__BASE__) == TIM_DMABASE_PSC) || \ 1874 ((__BASE__) == TIM_DMABASE_ARR) || \ 1875 ((__BASE__) == TIM_DMABASE_RCR) || \ 1876 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1877 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1878 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1879 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1880 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1881 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1882 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1883 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1884 ((__BASE__) == TIM_DMABASE_AF1) || \ 1885 ((__BASE__) == TIM_DMABASE_AF2) || \ 1886 ((__BASE__) == TIM_DMABASE_TISEL) || \ 1887 ((__BASE__) == TIM_DMABASE_DTR2) || \ 1888 ((__BASE__) == TIM_DMABASE_ECR) || \ 1889 ((__BASE__) == TIM_DMABASE_OR)) 1890 1891 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1892 1893 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1894 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1895 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1896 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1897 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1898 1899 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 1900 ((__MODE__) == TIM_UIFREMAP_ENALE)) 1901 1902 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1903 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1904 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1905 1906 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1907 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1908 1909 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1910 ((__STATE__) == TIM_OCFAST_ENABLE)) 1911 1912 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1913 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1914 1915 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1916 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1917 1918 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1919 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1920 1921 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1922 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1923 1924 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1925 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1926 1927 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1928 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1929 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1930 1931 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1932 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1933 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1934 1935 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1936 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1937 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1938 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1939 1940 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1941 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1942 1943 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1944 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1945 ((__MODE__) == TIM_ENCODERMODE_TI12) || \ 1946 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \ 1947 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \ 1948 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \ 1949 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \ 1950 ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \ 1951 ((__MODE__) == TIM_ENCODERMODE_X1_TI2)) 1952 1953 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1954 1955 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1956 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1957 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1958 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1959 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1960 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1961 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1962 1963 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1964 ((__CHANNEL__) == TIM_CHANNEL_2)) 1965 1966 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1967 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1968 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1969 ((__CHANNEL__) == TIM_CHANNEL_4)) 1970 1971 #if defined(TIM5) && defined(TIM20) 1972 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1973 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1974 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1975 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1976 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1977 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1978 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1979 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1980 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1981 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 1982 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 1983 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 1984 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 1985 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 1986 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 1987 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ 1988 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ 1989 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) 1990 #elif defined(TIM5) 1991 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1992 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1993 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1994 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1995 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1996 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1997 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1998 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1999 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 2000 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 2001 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 2002 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 2003 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 2004 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 2005 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 2006 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ 2007 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) 2008 #else 2009 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 2010 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 2011 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 2012 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 2013 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 2014 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 2015 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 2016 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 2017 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 2018 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 2019 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 2020 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 2021 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 2022 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 2023 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ 2024 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) 2025 #endif /* TIM5 && TIM20 */ 2026 2027 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 2028 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 2029 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 2030 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 2031 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 2032 2033 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 2034 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 2035 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 2036 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 2037 2038 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2039 2040 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 2041 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 2042 2043 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 2044 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 2045 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 2046 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 2047 2048 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2049 2050 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 2051 ((__STATE__) == TIM_OSSR_DISABLE)) 2052 2053 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 2054 ((__STATE__) == TIM_OSSI_DISABLE)) 2055 2056 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 2057 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 2058 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 2059 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 2060 2061 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 2062 2063 2064 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 2065 ((__STATE__) == TIM_BREAK_DISABLE)) 2066 2067 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 2068 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 2069 2070 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ 2071 ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) 2072 2073 2074 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 2075 ((__STATE__) == TIM_BREAK2_DISABLE)) 2076 2077 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 2078 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 2079 2080 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ 2081 ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) 2082 2083 2084 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 2085 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 2086 2087 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 2088 2089 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 2090 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 2091 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 2092 ((__SOURCE__) == TIM_TRGO_OC1) || \ 2093 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 2094 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 2095 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 2096 ((__SOURCE__) == TIM_TRGO_OC4REF) || \ 2097 ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) 2098 2099 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 2100 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 2101 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 2102 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 2103 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 2104 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 2105 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2106 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2107 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 2108 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 2109 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 2110 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 2111 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 2112 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 2113 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 2114 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 2115 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 2116 2117 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 2118 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 2119 2120 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 2121 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 2122 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 2123 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 2124 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 2125 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \ 2126 ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET)) 2127 2128 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 2129 ((__MODE__) == TIM_OCMODE_PWM2) || \ 2130 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 2131 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 2132 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 2133 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 2134 2135 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 2136 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 2137 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 2138 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 2139 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 2140 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 2141 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 2142 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \ 2143 ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ 2144 ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) 2145 2146 #if defined (TIM5) && defined(TIM20) 2147 2148 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2149 ((__SELECTION__) == TIM_TS_ITR1) || \ 2150 ((__SELECTION__) == TIM_TS_ITR2) || \ 2151 ((__SELECTION__) == TIM_TS_ITR3) || \ 2152 ((__SELECTION__) == TIM_TS_ITR4) || \ 2153 ((__SELECTION__) == TIM_TS_ITR5) || \ 2154 ((__SELECTION__) == TIM_TS_ITR6) || \ 2155 ((__SELECTION__) == TIM_TS_ITR7) || \ 2156 ((__SELECTION__) == TIM_TS_ITR8) || \ 2157 ((__SELECTION__) == TIM_TS_ITR9) || \ 2158 ((__SELECTION__) == TIM_TS_ITR10)|| \ 2159 ((__SELECTION__) == TIM_TS_ITR11)|| \ 2160 ((__SELECTION__) == TIM_TS_NONE)) 2161 #elif defined (TIM5) 2162 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2163 ((__SELECTION__) == TIM_TS_ITR1) || \ 2164 ((__SELECTION__) == TIM_TS_ITR2) || \ 2165 ((__SELECTION__) == TIM_TS_ITR3) || \ 2166 ((__SELECTION__) == TIM_TS_ITR4) || \ 2167 ((__SELECTION__) == TIM_TS_ITR5) || \ 2168 ((__SELECTION__) == TIM_TS_ITR6) || \ 2169 ((__SELECTION__) == TIM_TS_ITR7) || \ 2170 ((__SELECTION__) == TIM_TS_ITR8) || \ 2171 ((__SELECTION__) == TIM_TS_ITR10)|| \ 2172 ((__SELECTION__) == TIM_TS_ITR11)|| \ 2173 ((__SELECTION__) == TIM_TS_NONE)) 2174 #else 2175 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2176 ((__SELECTION__) == TIM_TS_ITR1) || \ 2177 ((__SELECTION__) == TIM_TS_ITR2) || \ 2178 ((__SELECTION__) == TIM_TS_ITR3) || \ 2179 ((__SELECTION__) == TIM_TS_ITR5) || \ 2180 ((__SELECTION__) == TIM_TS_ITR6) || \ 2181 ((__SELECTION__) == TIM_TS_ITR7) || \ 2182 ((__SELECTION__) == TIM_TS_ITR8) || \ 2183 ((__SELECTION__) == TIM_TS_ITR10)|| \ 2184 ((__SELECTION__) == TIM_TS_ITR11)|| \ 2185 ((__SELECTION__) == TIM_TS_NONE)) 2186 #endif /* TIM5 && TIM20 */ 2187 2188 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 2189 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 2190 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 2191 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 2192 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 2193 2194 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 2195 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 2196 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 2197 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 2198 2199 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2200 2201 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 2202 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 2203 2204 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 2205 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 2206 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 2207 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 2208 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 2209 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 2210 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 2211 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 2212 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 2213 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 2214 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 2215 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 2216 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 2217 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 2218 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 2219 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 2220 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 2221 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \ 2222 ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \ 2223 ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \ 2224 ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \ 2225 ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \ 2226 ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \ 2227 ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \ 2228 ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \ 2229 ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS)) 2230 2231 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 2232 2233 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2234 2235 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 2236 2237 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 2238 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 2239 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ 2240 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 2241 2242 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 2243 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2244 2245 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 2246 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 2247 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 2248 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 2249 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 2250 2251 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 2252 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 2253 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 2254 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 2255 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 2256 2257 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 2258 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 2259 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 2260 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 2261 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 2262 2263 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 2264 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 2265 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 2266 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 2267 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 2268 2269 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2270 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2271 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2272 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2273 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ 2274 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ 2275 (__HANDLE__)->ChannelState[5]) 2276 2277 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2278 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2279 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2280 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2281 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ 2282 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ 2283 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) 2284 2285 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2286 (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ 2287 (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ 2288 (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ 2289 (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ 2290 (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ 2291 (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ 2292 } while(0) 2293 2294 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 2295 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 2296 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 2297 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 2298 (__HANDLE__)->ChannelNState[3]) 2299 2300 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2301 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 2302 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 2303 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 2304 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 2305 2306 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2307 (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ 2308 (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ 2309 (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ 2310 (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ 2311 } while(0) 2312 2313 /** 2314 * @} 2315 */ 2316 /* End of private macros -----------------------------------------------------*/ 2317 2318 /* Include TIM HAL Extended module */ 2319 #include "stm32g4xx_hal_tim_ex.h" 2320 2321 /* Exported functions --------------------------------------------------------*/ 2322 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 2323 * @{ 2324 */ 2325 2326 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 2327 * @brief Time Base functions 2328 * @{ 2329 */ 2330 /* Time Base functions ********************************************************/ 2331 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 2332 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 2333 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 2334 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 2335 /* Blocking mode: Polling */ 2336 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 2337 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 2338 /* Non-Blocking mode: Interrupt */ 2339 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 2340 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 2341 /* Non-Blocking mode: DMA */ 2342 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 2343 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 2344 /** 2345 * @} 2346 */ 2347 2348 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 2349 * @brief TIM Output Compare functions 2350 * @{ 2351 */ 2352 /* Timer Output Compare functions *********************************************/ 2353 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 2354 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 2355 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 2356 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 2357 /* Blocking mode: Polling */ 2358 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2359 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2360 /* Non-Blocking mode: Interrupt */ 2361 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2362 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2363 /* Non-Blocking mode: DMA */ 2364 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2365 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2366 /** 2367 * @} 2368 */ 2369 2370 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2371 * @brief TIM PWM functions 2372 * @{ 2373 */ 2374 /* Timer PWM functions ********************************************************/ 2375 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2376 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2377 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2378 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2379 /* Blocking mode: Polling */ 2380 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2381 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2382 /* Non-Blocking mode: Interrupt */ 2383 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2384 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2385 /* Non-Blocking mode: DMA */ 2386 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2387 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2388 /** 2389 * @} 2390 */ 2391 2392 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2393 * @brief TIM Input Capture functions 2394 * @{ 2395 */ 2396 /* Timer Input Capture functions **********************************************/ 2397 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2398 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2399 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2400 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2401 /* Blocking mode: Polling */ 2402 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2403 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2404 /* Non-Blocking mode: Interrupt */ 2405 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2406 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2407 /* Non-Blocking mode: DMA */ 2408 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2409 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2410 /** 2411 * @} 2412 */ 2413 2414 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2415 * @brief TIM One Pulse functions 2416 * @{ 2417 */ 2418 /* Timer One Pulse functions **************************************************/ 2419 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2420 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2421 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2422 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2423 /* Blocking mode: Polling */ 2424 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2425 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2426 /* Non-Blocking mode: Interrupt */ 2427 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2428 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2429 /** 2430 * @} 2431 */ 2432 2433 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2434 * @brief TIM Encoder functions 2435 * @{ 2436 */ 2437 /* Timer Encoder functions ****************************************************/ 2438 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2439 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2440 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2441 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2442 /* Blocking mode: Polling */ 2443 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2444 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2445 /* Non-Blocking mode: Interrupt */ 2446 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2447 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2448 /* Non-Blocking mode: DMA */ 2449 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2450 uint32_t *pData2, uint16_t Length); 2451 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2452 /** 2453 * @} 2454 */ 2455 2456 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2457 * @brief IRQ handler management 2458 * @{ 2459 */ 2460 /* Interrupt Handler functions ***********************************************/ 2461 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2462 /** 2463 * @} 2464 */ 2465 2466 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2467 * @brief Peripheral Control functions 2468 * @{ 2469 */ 2470 /* Control functions *********************************************************/ 2471 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2472 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2473 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 2474 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2475 uint32_t OutputChannel, uint32_t InputChannel); 2476 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 2477 uint32_t Channel); 2478 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 2479 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2480 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2481 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2482 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2483 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2484 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2485 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, 2486 uint32_t DataLength); 2487 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2488 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2489 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2490 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2491 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, 2492 uint32_t DataLength); 2493 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2494 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2495 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 2496 /** 2497 * @} 2498 */ 2499 2500 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2501 * @brief TIM Callbacks functions 2502 * @{ 2503 */ 2504 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2505 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2506 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2507 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2508 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2509 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2510 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2511 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2512 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2513 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2514 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2515 2516 /* Callbacks Register/UnRegister functions ***********************************/ 2517 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2518 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2519 pTIM_CallbackTypeDef pCallback); 2520 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2521 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2522 2523 /** 2524 * @} 2525 */ 2526 2527 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2528 * @brief Peripheral State functions 2529 * @{ 2530 */ 2531 /* Peripheral State functions ************************************************/ 2532 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 2533 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 2534 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 2535 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 2536 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 2537 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 2538 2539 /* Peripheral Channel state functions ************************************************/ 2540 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); 2541 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); 2542 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); 2543 /** 2544 * @} 2545 */ 2546 2547 /** 2548 * @} 2549 */ 2550 /* End of exported functions -------------------------------------------------*/ 2551 2552 /* Private functions----------------------------------------------------------*/ 2553 /** @defgroup TIM_Private_Functions TIM Private Functions 2554 * @{ 2555 */ 2556 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 2557 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2558 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 2559 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2560 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2561 2562 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2563 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2564 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2565 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2566 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2567 2568 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2569 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2570 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2571 2572 /** 2573 * @} 2574 */ 2575 /* End of private functions --------------------------------------------------*/ 2576 2577 /** 2578 * @} 2579 */ 2580 2581 /** 2582 * @} 2583 */ 2584 2585 #ifdef __cplusplus 2586 } 2587 #endif 2588 2589 #endif /* STM32G4xx_HAL_TIM_H */ 2590 2591 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2592