1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The SPI HAL driver can be used as follows:
19
20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
21 SPI_HandleTypeDef hspi;
22
23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
24 (##) Enable the SPIx interface clock
25 (##) SPI pins configuration
26 (+++) Enable the clock for the SPI GPIOs
27 (+++) Configure these SPI pins as alternate function push-pull
28 (##) NVIC configuration if you need to use interrupt process
29 (+++) Configure the SPIx interrupt priority
30 (+++) Enable the NVIC SPI IRQ handle
31 (##) DMA Configuration if you need to use DMA process
32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
33 (+++) Enable the DMAx clock
34 (+++) Configure the DMA handle parameters
35 (+++) Configure the DMA Tx or Rx Stream/Channel
36 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
38
39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
41
42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
44 by calling the customized HAL_SPI_MspInit() API.
45 [..]
46 Circular mode restriction:
47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
48 (##) Master 2Lines RxOnly
49 (##) Master 1Line Rx
50 (#) The CRC feature is not managed when the DMA circular mode is enabled
51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
53 [..]
54 Master Receive mode restriction:
55 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
56 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
57 does not initiate a new transfer the following procedure has to be respected:
58 (##) HAL_SPI_DeInit()
59 (##) HAL_SPI_Init()
60 [..]
61 Callback registration:
62
63 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
64 allows the user to configure dynamically the driver callbacks.
65 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
66
67 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
68 (++) TxCpltCallback : SPI Tx Completed callback
69 (++) RxCpltCallback : SPI Rx Completed callback
70 (++) TxRxCpltCallback : SPI TxRx Completed callback
71 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
72 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
73 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
74 (++) ErrorCallback : SPI Error callback
75 (++) AbortCpltCallback : SPI Abort callback
76 (++) MspInitCallback : SPI Msp Init callback
77 (++) MspDeInitCallback : SPI Msp DeInit callback
78 This function takes as parameters the HAL peripheral handle, the Callback ID
79 and a pointer to the user callback function.
80
81
82 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
83 weak function.
84 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
85 and the Callback ID.
86 This function allows to reset following callbacks:
87 (++) TxCpltCallback : SPI Tx Completed callback
88 (++) RxCpltCallback : SPI Rx Completed callback
89 (++) TxRxCpltCallback : SPI TxRx Completed callback
90 (++) TxHalfCpltCallback : SPI Tx Half Completed callback
91 (++) RxHalfCpltCallback : SPI Rx Half Completed callback
92 (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
93 (++) ErrorCallback : SPI Error callback
94 (++) AbortCpltCallback : SPI Abort callback
95 (++) MspInitCallback : SPI Msp Init callback
96 (++) MspDeInitCallback : SPI Msp DeInit callback
97
98 [..]
99 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
100 all callbacks are set to the corresponding weak functions:
101 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
102 Exception done for MspInit and MspDeInit functions that are
103 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
104 these callbacks are null (not registered beforehand).
105 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
106 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
107
108 [..]
109 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
110 Exception done MspInit/MspDeInit functions that can be registered/unregistered
111 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
112 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
113 Then, the user first registers the MspInit/MspDeInit user callbacks
114 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
115 or HAL_SPI_Init() function.
116
117 [..]
118 When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
119 not defined, the callback registering feature is not available
120 and weak (surcharged) callbacks are used.
121
122 [..]
123 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
124 the following table resume the max SPI frequency reached with data size 8bits/16bits,
125 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
126
127 @endverbatim
128
129 Additional table :
130
131 DataSize = SPI_DATASIZE_8BIT:
132 +----------------------------------------------------------------------------------------------+
133 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
134 | Process | Tranfert mode |---------------------|----------------------|----------------------|
135 | | | Master | Slave | Master | Slave | Master | Slave |
136 |==============================================================================================|
137 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
138 | X |----------------|----------|----------|-----------|----------|-----------|----------|
139 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
140 | R |----------------|----------|----------|-----------|----------|-----------|----------|
141 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
142 |=========|================|==========|==========|===========|==========|===========|==========|
143 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
144 | |----------------|----------|----------|-----------|----------|-----------|----------|
145 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
146 | X |----------------|----------|----------|-----------|----------|-----------|----------|
147 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
148 |=========|================|==========|==========|===========|==========|===========|==========|
149 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
150 | |----------------|----------|----------|-----------|----------|-----------|----------|
151 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
152 | X |----------------|----------|----------|-----------|----------|-----------|----------|
153 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
154 +----------------------------------------------------------------------------------------------+
155
156 DataSize = SPI_DATASIZE_16BIT:
157 +----------------------------------------------------------------------------------------------+
158 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
159 | Process | Tranfert mode |---------------------|----------------------|----------------------|
160 | | | Master | Slave | Master | Slave | Master | Slave |
161 |==============================================================================================|
162 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
163 | X |----------------|----------|----------|-----------|----------|-----------|----------|
164 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
165 | R |----------------|----------|----------|-----------|----------|-----------|----------|
166 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
167 |=========|================|==========|==========|===========|==========|===========|==========|
168 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
169 | |----------------|----------|----------|-----------|----------|-----------|----------|
170 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
171 | X |----------------|----------|----------|-----------|----------|-----------|----------|
172 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
173 |=========|================|==========|==========|===========|==========|===========|==========|
174 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
175 | |----------------|----------|----------|-----------|----------|-----------|----------|
176 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
177 | X |----------------|----------|----------|-----------|----------|-----------|----------|
178 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
179 +----------------------------------------------------------------------------------------------+
180 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
181 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
182 @note
183 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
184 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
185 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
186
187 ******************************************************************************
188 * @attention
189 *
190 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
191 * All rights reserved.</center></h2>
192 *
193 * This software component is licensed by ST under BSD 3-Clause license,
194 * the "License"; You may not use this file except in compliance with the
195 * License. You may obtain a copy of the License at:
196 * opensource.org/licenses/BSD-3-Clause
197 *
198 ******************************************************************************
199 */
200
201 /* Includes ------------------------------------------------------------------*/
202 #include "stm32g4xx_hal.h"
203
204 /** @addtogroup STM32G4xx_HAL_Driver
205 * @{
206 */
207
208 /** @defgroup SPI SPI
209 * @brief SPI HAL module driver
210 * @{
211 */
212 #ifdef HAL_SPI_MODULE_ENABLED
213
214 /* Private typedef -----------------------------------------------------------*/
215 /* Private defines -----------------------------------------------------------*/
216 /** @defgroup SPI_Private_Constants SPI Private Constants
217 * @{
218 */
219 #define SPI_DEFAULT_TIMEOUT 100U
220 /**
221 * @}
222 */
223
224 /* Private macros ------------------------------------------------------------*/
225 /* Private variables ---------------------------------------------------------*/
226 /* Private function prototypes -----------------------------------------------*/
227 /** @defgroup SPI_Private_Functions SPI Private Functions
228 * @{
229 */
230 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
235 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
236 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
237 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
238 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
239 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
240 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
241 uint32_t Timeout, uint32_t Tickstart);
242 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
243 uint32_t Timeout, uint32_t Tickstart);
244 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
249 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
250 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
251 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
252 #if (USE_SPI_CRC != 0U)
253 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
254 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
255 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
256 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
257 #endif /* USE_SPI_CRC */
258 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
260 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
261 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
262 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
263 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
264 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
265 /**
266 * @}
267 */
268
269 /* Exported functions --------------------------------------------------------*/
270 /** @defgroup SPI_Exported_Functions SPI Exported Functions
271 * @{
272 */
273
274 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
275 * @brief Initialization and Configuration functions
276 *
277 @verbatim
278 ===============================================================================
279 ##### Initialization and de-initialization functions #####
280 ===============================================================================
281 [..] This subsection provides a set of functions allowing to initialize and
282 de-initialize the SPIx peripheral:
283
284 (+) User must implement HAL_SPI_MspInit() function in which he configures
285 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
286
287 (+) Call the function HAL_SPI_Init() to configure the selected device with
288 the selected configuration:
289 (++) Mode
290 (++) Direction
291 (++) Data Size
292 (++) Clock Polarity and Phase
293 (++) NSS Management
294 (++) BaudRate Prescaler
295 (++) FirstBit
296 (++) TIMode
297 (++) CRC Calculation
298 (++) CRC Polynomial if CRC enabled
299 (++) CRC Length, used only with Data8 and Data16
300 (++) FIFO reception threshold
301
302 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
303 of the selected SPIx peripheral.
304
305 @endverbatim
306 * @{
307 */
308
309 /**
310 * @brief Initialize the SPI according to the specified parameters
311 * in the SPI_InitTypeDef and initialize the associated handle.
312 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
313 * the configuration information for SPI module.
314 * @retval HAL status
315 */
HAL_SPI_Init(SPI_HandleTypeDef * hspi)316 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
317 {
318 uint32_t frxth;
319
320 /* Check the SPI handle allocation */
321 if (hspi == NULL)
322 {
323 return HAL_ERROR;
324 }
325
326 /* Check the parameters */
327 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
328 assert_param(IS_SPI_MODE(hspi->Init.Mode));
329 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
330 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
331 assert_param(IS_SPI_NSS(hspi->Init.NSS));
332 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
333 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
334 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
335 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
336 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
337 {
338 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
339 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
340 }
341 #if (USE_SPI_CRC != 0U)
342 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
343 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
344 {
345 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
346 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
347 }
348 #else
349 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
350 #endif /* USE_SPI_CRC */
351
352 if (hspi->State == HAL_SPI_STATE_RESET)
353 {
354 /* Allocate lock resource and initialize it */
355 hspi->Lock = HAL_UNLOCKED;
356
357 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
358 /* Init the SPI Callback settings */
359 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
360 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
361 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
362 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
363 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
364 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
365 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
366 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
367
368 if (hspi->MspInitCallback == NULL)
369 {
370 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
371 }
372
373 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
374 hspi->MspInitCallback(hspi);
375 #else
376 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
377 HAL_SPI_MspInit(hspi);
378 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
379 }
380
381 hspi->State = HAL_SPI_STATE_BUSY;
382
383 /* Disable the selected SPI peripheral */
384 __HAL_SPI_DISABLE(hspi);
385
386 /* Align by default the rs fifo threshold on the data size */
387 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
388 {
389 frxth = SPI_RXFIFO_THRESHOLD_HF;
390 }
391 else
392 {
393 frxth = SPI_RXFIFO_THRESHOLD_QF;
394 }
395
396 /* CRC calculation is valid only for 16Bit and 8 Bit */
397 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
398 {
399 /* CRC must be disabled */
400 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
401 }
402
403 /* Align the CRC Length on the data size */
404 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
405 {
406 /* CRC Length aligned on the data size : value set by default */
407 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
408 {
409 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
410 }
411 else
412 {
413 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
414 }
415 }
416
417 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
418 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
419 Communication speed, First bit and CRC calculation state */
420 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
421 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
422 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
423 #if (USE_SPI_CRC != 0U)
424 /* Configure : CRC Length */
425 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
426 {
427 hspi->Instance->CR1 |= SPI_CR1_CRCL;
428 }
429 #endif /* USE_SPI_CRC */
430
431 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
432 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
433 hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
434
435 #if (USE_SPI_CRC != 0U)
436 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
437 /* Configure : CRC Polynomial */
438 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
439 {
440 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
441 }
442 #endif /* USE_SPI_CRC */
443
444 #if defined(SPI_I2SCFGR_I2SMOD)
445 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
446 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
447 #endif /* SPI_I2SCFGR_I2SMOD */
448
449 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
450 hspi->State = HAL_SPI_STATE_READY;
451
452 return HAL_OK;
453 }
454
455 /**
456 * @brief De-Initialize the SPI peripheral.
457 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
458 * the configuration information for SPI module.
459 * @retval HAL status
460 */
HAL_SPI_DeInit(SPI_HandleTypeDef * hspi)461 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
462 {
463 /* Check the SPI handle allocation */
464 if (hspi == NULL)
465 {
466 return HAL_ERROR;
467 }
468
469 /* Check SPI Instance parameter */
470 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
471
472 hspi->State = HAL_SPI_STATE_BUSY;
473
474 /* Disable the SPI Peripheral Clock */
475 __HAL_SPI_DISABLE(hspi);
476
477 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
478 if (hspi->MspDeInitCallback == NULL)
479 {
480 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
481 }
482
483 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
484 hspi->MspDeInitCallback(hspi);
485 #else
486 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
487 HAL_SPI_MspDeInit(hspi);
488 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
489
490 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
491 hspi->State = HAL_SPI_STATE_RESET;
492
493 /* Release Lock */
494 __HAL_UNLOCK(hspi);
495
496 return HAL_OK;
497 }
498
499 /**
500 * @brief Initialize the SPI MSP.
501 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
502 * the configuration information for SPI module.
503 * @retval None
504 */
HAL_SPI_MspInit(SPI_HandleTypeDef * hspi)505 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
506 {
507 /* Prevent unused argument(s) compilation warning */
508 UNUSED(hspi);
509
510 /* NOTE : This function should not be modified, when the callback is needed,
511 the HAL_SPI_MspInit should be implemented in the user file
512 */
513 }
514
515 /**
516 * @brief De-Initialize the SPI MSP.
517 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
518 * the configuration information for SPI module.
519 * @retval None
520 */
HAL_SPI_MspDeInit(SPI_HandleTypeDef * hspi)521 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
522 {
523 /* Prevent unused argument(s) compilation warning */
524 UNUSED(hspi);
525
526 /* NOTE : This function should not be modified, when the callback is needed,
527 the HAL_SPI_MspDeInit should be implemented in the user file
528 */
529 }
530
531 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
532 /**
533 * @brief Register a User SPI Callback
534 * To be used instead of the weak predefined callback
535 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
536 * the configuration information for the specified SPI.
537 * @param CallbackID ID of the callback to be registered
538 * @param pCallback pointer to the Callback function
539 * @retval HAL status
540 */
HAL_SPI_RegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID,pSPI_CallbackTypeDef pCallback)541 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
542 pSPI_CallbackTypeDef pCallback)
543 {
544 HAL_StatusTypeDef status = HAL_OK;
545
546 if (pCallback == NULL)
547 {
548 /* Update the error code */
549 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
550
551 return HAL_ERROR;
552 }
553 /* Process locked */
554 __HAL_LOCK(hspi);
555
556 if (HAL_SPI_STATE_READY == hspi->State)
557 {
558 switch (CallbackID)
559 {
560 case HAL_SPI_TX_COMPLETE_CB_ID :
561 hspi->TxCpltCallback = pCallback;
562 break;
563
564 case HAL_SPI_RX_COMPLETE_CB_ID :
565 hspi->RxCpltCallback = pCallback;
566 break;
567
568 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
569 hspi->TxRxCpltCallback = pCallback;
570 break;
571
572 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
573 hspi->TxHalfCpltCallback = pCallback;
574 break;
575
576 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
577 hspi->RxHalfCpltCallback = pCallback;
578 break;
579
580 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
581 hspi->TxRxHalfCpltCallback = pCallback;
582 break;
583
584 case HAL_SPI_ERROR_CB_ID :
585 hspi->ErrorCallback = pCallback;
586 break;
587
588 case HAL_SPI_ABORT_CB_ID :
589 hspi->AbortCpltCallback = pCallback;
590 break;
591
592 case HAL_SPI_MSPINIT_CB_ID :
593 hspi->MspInitCallback = pCallback;
594 break;
595
596 case HAL_SPI_MSPDEINIT_CB_ID :
597 hspi->MspDeInitCallback = pCallback;
598 break;
599
600 default :
601 /* Update the error code */
602 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
603
604 /* Return error status */
605 status = HAL_ERROR;
606 break;
607 }
608 }
609 else if (HAL_SPI_STATE_RESET == hspi->State)
610 {
611 switch (CallbackID)
612 {
613 case HAL_SPI_MSPINIT_CB_ID :
614 hspi->MspInitCallback = pCallback;
615 break;
616
617 case HAL_SPI_MSPDEINIT_CB_ID :
618 hspi->MspDeInitCallback = pCallback;
619 break;
620
621 default :
622 /* Update the error code */
623 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
624
625 /* Return error status */
626 status = HAL_ERROR;
627 break;
628 }
629 }
630 else
631 {
632 /* Update the error code */
633 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
634
635 /* Return error status */
636 status = HAL_ERROR;
637 }
638
639 /* Release Lock */
640 __HAL_UNLOCK(hspi);
641 return status;
642 }
643
644 /**
645 * @brief Unregister an SPI Callback
646 * SPI callback is redirected to the weak predefined callback
647 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
648 * the configuration information for the specified SPI.
649 * @param CallbackID ID of the callback to be unregistered
650 * @retval HAL status
651 */
HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef * hspi,HAL_SPI_CallbackIDTypeDef CallbackID)652 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
653 {
654 HAL_StatusTypeDef status = HAL_OK;
655
656 /* Process locked */
657 __HAL_LOCK(hspi);
658
659 if (HAL_SPI_STATE_READY == hspi->State)
660 {
661 switch (CallbackID)
662 {
663 case HAL_SPI_TX_COMPLETE_CB_ID :
664 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
665 break;
666
667 case HAL_SPI_RX_COMPLETE_CB_ID :
668 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
669 break;
670
671 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
672 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
673 break;
674
675 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
676 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
677 break;
678
679 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
680 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
681 break;
682
683 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
684 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
685 break;
686
687 case HAL_SPI_ERROR_CB_ID :
688 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
689 break;
690
691 case HAL_SPI_ABORT_CB_ID :
692 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
693 break;
694
695 case HAL_SPI_MSPINIT_CB_ID :
696 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
697 break;
698
699 case HAL_SPI_MSPDEINIT_CB_ID :
700 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
701 break;
702
703 default :
704 /* Update the error code */
705 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
706
707 /* Return error status */
708 status = HAL_ERROR;
709 break;
710 }
711 }
712 else if (HAL_SPI_STATE_RESET == hspi->State)
713 {
714 switch (CallbackID)
715 {
716 case HAL_SPI_MSPINIT_CB_ID :
717 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
718 break;
719
720 case HAL_SPI_MSPDEINIT_CB_ID :
721 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
722 break;
723
724 default :
725 /* Update the error code */
726 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
727
728 /* Return error status */
729 status = HAL_ERROR;
730 break;
731 }
732 }
733 else
734 {
735 /* Update the error code */
736 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
737
738 /* Return error status */
739 status = HAL_ERROR;
740 }
741
742 /* Release Lock */
743 __HAL_UNLOCK(hspi);
744 return status;
745 }
746 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
747 /**
748 * @}
749 */
750
751 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
752 * @brief Data transfers functions
753 *
754 @verbatim
755 ==============================================================================
756 ##### IO operation functions #####
757 ===============================================================================
758 [..]
759 This subsection provides a set of functions allowing to manage the SPI
760 data transfers.
761
762 [..] The SPI supports master and slave mode :
763
764 (#) There are two modes of transfer:
765 (++) Blocking mode: The communication is performed in polling mode.
766 The HAL status of all data processing is returned by the same function
767 after finishing transfer.
768 (++) No-Blocking mode: The communication is performed using Interrupts
769 or DMA, These APIs return the HAL status.
770 The end of the data processing will be indicated through the
771 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
772 using DMA mode.
773 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
774 will be executed respectively at the end of the transmit or Receive process
775 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
776
777 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
778 exist for 1Line (simplex) and 2Lines (full duplex) modes.
779
780 @endverbatim
781 * @{
782 */
783
784 /**
785 * @brief Transmit an amount of data in blocking mode.
786 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
787 * the configuration information for SPI module.
788 * @param pData pointer to data buffer
789 * @param Size amount of data to be sent
790 * @param Timeout Timeout duration
791 * @retval HAL status
792 */
HAL_SPI_Transmit(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)793 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
794 {
795 uint32_t tickstart;
796 HAL_StatusTypeDef errorcode = HAL_OK;
797 uint16_t initial_TxXferCount;
798
799 /* Check Direction parameter */
800 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
801
802 /* Process Locked */
803 __HAL_LOCK(hspi);
804
805 /* Init tickstart for timeout management*/
806 tickstart = HAL_GetTick();
807 initial_TxXferCount = Size;
808
809 if (hspi->State != HAL_SPI_STATE_READY)
810 {
811 errorcode = HAL_BUSY;
812 goto error;
813 }
814
815 if ((pData == NULL) || (Size == 0U))
816 {
817 errorcode = HAL_ERROR;
818 goto error;
819 }
820
821 /* Set the transaction information */
822 hspi->State = HAL_SPI_STATE_BUSY_TX;
823 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
824 hspi->pTxBuffPtr = (uint8_t *)pData;
825 hspi->TxXferSize = Size;
826 hspi->TxXferCount = Size;
827
828 /*Init field not used in handle to zero */
829 hspi->pRxBuffPtr = (uint8_t *)NULL;
830 hspi->RxXferSize = 0U;
831 hspi->RxXferCount = 0U;
832 hspi->TxISR = NULL;
833 hspi->RxISR = NULL;
834
835 /* Configure communication direction : 1Line */
836 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
837 {
838 SPI_1LINE_TX(hspi);
839 }
840
841 #if (USE_SPI_CRC != 0U)
842 /* Reset CRC Calculation */
843 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
844 {
845 SPI_RESET_CRC(hspi);
846 }
847 #endif /* USE_SPI_CRC */
848
849 /* Check if the SPI is already enabled */
850 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
851 {
852 /* Enable SPI peripheral */
853 __HAL_SPI_ENABLE(hspi);
854 }
855
856 /* Transmit data in 16 Bit mode */
857 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
858 {
859 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
860 {
861 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
862 hspi->pTxBuffPtr += sizeof(uint16_t);
863 hspi->TxXferCount--;
864 }
865 /* Transmit data in 16 Bit mode */
866 while (hspi->TxXferCount > 0U)
867 {
868 /* Wait until TXE flag is set to send data */
869 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
870 {
871 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
872 hspi->pTxBuffPtr += sizeof(uint16_t);
873 hspi->TxXferCount--;
874 }
875 else
876 {
877 /* Timeout management */
878 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
879 {
880 errorcode = HAL_TIMEOUT;
881 goto error;
882 }
883 }
884 }
885 }
886 /* Transmit data in 8 Bit mode */
887 else
888 {
889 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
890 {
891 if (hspi->TxXferCount > 1U)
892 {
893 /* write on the data register in packing mode */
894 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
895 hspi->pTxBuffPtr += sizeof(uint16_t);
896 hspi->TxXferCount -= 2U;
897 }
898 else
899 {
900 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
901 hspi->pTxBuffPtr ++;
902 hspi->TxXferCount--;
903 }
904 }
905 while (hspi->TxXferCount > 0U)
906 {
907 /* Wait until TXE flag is set to send data */
908 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
909 {
910 if (hspi->TxXferCount > 1U)
911 {
912 /* write on the data register in packing mode */
913 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
914 hspi->pTxBuffPtr += sizeof(uint16_t);
915 hspi->TxXferCount -= 2U;
916 }
917 else
918 {
919 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
920 hspi->pTxBuffPtr++;
921 hspi->TxXferCount--;
922 }
923 }
924 else
925 {
926 /* Timeout management */
927 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
928 {
929 errorcode = HAL_TIMEOUT;
930 goto error;
931 }
932 }
933 }
934 }
935 #if (USE_SPI_CRC != 0U)
936 /* Enable CRC Transmission */
937 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
938 {
939 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
940 }
941 #endif /* USE_SPI_CRC */
942
943 /* Check the end of the transaction */
944 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
945 {
946 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
947 }
948
949 /* Clear overrun flag in 2 Lines communication mode because received is not read */
950 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
951 {
952 __HAL_SPI_CLEAR_OVRFLAG(hspi);
953 }
954
955 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
956 {
957 errorcode = HAL_ERROR;
958 }
959
960 error:
961 hspi->State = HAL_SPI_STATE_READY;
962 /* Process Unlocked */
963 __HAL_UNLOCK(hspi);
964 return errorcode;
965 }
966
967 /**
968 * @brief Receive an amount of data in blocking mode.
969 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
970 * the configuration information for SPI module.
971 * @param pData pointer to data buffer
972 * @param Size amount of data to be received
973 * @param Timeout Timeout duration
974 * @retval HAL status
975 */
HAL_SPI_Receive(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size,uint32_t Timeout)976 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
977 {
978 uint32_t tickstart;
979 HAL_StatusTypeDef errorcode = HAL_OK;
980
981 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
982 {
983 hspi->State = HAL_SPI_STATE_BUSY_RX;
984 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
985 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
986 }
987
988 /* Process Locked */
989 __HAL_LOCK(hspi);
990
991 /* Init tickstart for timeout management*/
992 tickstart = HAL_GetTick();
993
994 if (hspi->State != HAL_SPI_STATE_READY)
995 {
996 errorcode = HAL_BUSY;
997 goto error;
998 }
999
1000 if ((pData == NULL) || (Size == 0U))
1001 {
1002 errorcode = HAL_ERROR;
1003 goto error;
1004 }
1005
1006 /* Set the transaction information */
1007 hspi->State = HAL_SPI_STATE_BUSY_RX;
1008 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1009 hspi->pRxBuffPtr = (uint8_t *)pData;
1010 hspi->RxXferSize = Size;
1011 hspi->RxXferCount = Size;
1012
1013 /*Init field not used in handle to zero */
1014 hspi->pTxBuffPtr = (uint8_t *)NULL;
1015 hspi->TxXferSize = 0U;
1016 hspi->TxXferCount = 0U;
1017 hspi->RxISR = NULL;
1018 hspi->TxISR = NULL;
1019
1020 #if (USE_SPI_CRC != 0U)
1021 /* Reset CRC Calculation */
1022 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1023 {
1024 SPI_RESET_CRC(hspi);
1025 /* this is done to handle the CRCNEXT before the latest data */
1026 hspi->RxXferCount--;
1027 }
1028 #endif /* USE_SPI_CRC */
1029
1030 /* Set the Rx Fifo threshold */
1031 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1032 {
1033 /* Set RX Fifo threshold according the reception data length: 16bit */
1034 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1035 }
1036 else
1037 {
1038 /* Set RX Fifo threshold according the reception data length: 8bit */
1039 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1040 }
1041
1042 /* Configure communication direction: 1Line */
1043 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1044 {
1045 SPI_1LINE_RX(hspi);
1046 }
1047
1048 /* Check if the SPI is already enabled */
1049 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1050 {
1051 /* Enable SPI peripheral */
1052 __HAL_SPI_ENABLE(hspi);
1053 }
1054
1055 /* Receive data in 8 Bit mode */
1056 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1057 {
1058 /* Transfer loop */
1059 while (hspi->RxXferCount > 0U)
1060 {
1061 /* Check the RXNE flag */
1062 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1063 {
1064 /* read the received data */
1065 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1066 hspi->pRxBuffPtr += sizeof(uint8_t);
1067 hspi->RxXferCount--;
1068 }
1069 else
1070 {
1071 /* Timeout management */
1072 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1073 {
1074 errorcode = HAL_TIMEOUT;
1075 goto error;
1076 }
1077 }
1078 }
1079 }
1080 else
1081 {
1082 /* Transfer loop */
1083 while (hspi->RxXferCount > 0U)
1084 {
1085 /* Check the RXNE flag */
1086 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1087 {
1088 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1089 hspi->pRxBuffPtr += sizeof(uint16_t);
1090 hspi->RxXferCount--;
1091 }
1092 else
1093 {
1094 /* Timeout management */
1095 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1096 {
1097 errorcode = HAL_TIMEOUT;
1098 goto error;
1099 }
1100 }
1101 }
1102 }
1103
1104 #if (USE_SPI_CRC != 0U)
1105 /* Handle the CRC Transmission */
1106 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1107 {
1108 /* freeze the CRC before the latest data */
1109 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1110
1111 /* Read the latest data */
1112 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1113 {
1114 /* the latest data has not been received */
1115 errorcode = HAL_TIMEOUT;
1116 goto error;
1117 }
1118
1119 /* Receive last data in 16 Bit mode */
1120 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1121 {
1122 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1123 }
1124 /* Receive last data in 8 Bit mode */
1125 else
1126 {
1127 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1128 }
1129
1130 /* Wait the CRC data */
1131 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1132 {
1133 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1134 errorcode = HAL_TIMEOUT;
1135 goto error;
1136 }
1137
1138 /* Read CRC to Flush DR and RXNE flag */
1139 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1140 {
1141 /* Read 16bit CRC */
1142 READ_REG(hspi->Instance->DR);
1143 }
1144 else
1145 {
1146 /* Read 8bit CRC */
1147 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1148
1149 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1150 {
1151 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1152 {
1153 /* Error on the CRC reception */
1154 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1155 errorcode = HAL_TIMEOUT;
1156 goto error;
1157 }
1158 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1159 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1160 }
1161 }
1162 }
1163 #endif /* USE_SPI_CRC */
1164
1165 /* Check the end of the transaction */
1166 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1167 {
1168 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1169 }
1170
1171 #if (USE_SPI_CRC != 0U)
1172 /* Check if CRC error occurred */
1173 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1174 {
1175 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1176 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1177 }
1178 #endif /* USE_SPI_CRC */
1179
1180 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1181 {
1182 errorcode = HAL_ERROR;
1183 }
1184
1185 error :
1186 hspi->State = HAL_SPI_STATE_READY;
1187 __HAL_UNLOCK(hspi);
1188 return errorcode;
1189 }
1190
1191 /**
1192 * @brief Transmit and Receive an amount of data in blocking mode.
1193 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1194 * the configuration information for SPI module.
1195 * @param pTxData pointer to transmission data buffer
1196 * @param pRxData pointer to reception data buffer
1197 * @param Size amount of data to be sent and received
1198 * @param Timeout Timeout duration
1199 * @retval HAL status
1200 */
HAL_SPI_TransmitReceive(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size,uint32_t Timeout)1201 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1202 uint32_t Timeout)
1203 {
1204 uint16_t initial_TxXferCount;
1205 uint16_t initial_RxXferCount;
1206 uint32_t tmp_mode;
1207 HAL_SPI_StateTypeDef tmp_state;
1208 uint32_t tickstart;
1209 #if (USE_SPI_CRC != 0U)
1210 uint32_t spi_cr1;
1211 uint32_t spi_cr2;
1212 #endif /* USE_SPI_CRC */
1213
1214 /* Variable used to alternate Rx and Tx during transfer */
1215 uint32_t txallowed = 1U;
1216 HAL_StatusTypeDef errorcode = HAL_OK;
1217
1218 /* Check Direction parameter */
1219 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1220
1221 /* Process Locked */
1222 __HAL_LOCK(hspi);
1223
1224 /* Init tickstart for timeout management*/
1225 tickstart = HAL_GetTick();
1226
1227 /* Init temporary variables */
1228 tmp_state = hspi->State;
1229 tmp_mode = hspi->Init.Mode;
1230 initial_TxXferCount = Size;
1231 initial_RxXferCount = Size;
1232 #if (USE_SPI_CRC != 0U)
1233 spi_cr1 = READ_REG(hspi->Instance->CR1);
1234 spi_cr2 = READ_REG(hspi->Instance->CR2);
1235 #endif /* USE_SPI_CRC */
1236
1237 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1238 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1239 {
1240 errorcode = HAL_BUSY;
1241 goto error;
1242 }
1243
1244 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1245 {
1246 errorcode = HAL_ERROR;
1247 goto error;
1248 }
1249
1250 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1251 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1252 {
1253 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1254 }
1255
1256 /* Set the transaction information */
1257 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1258 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1259 hspi->RxXferCount = Size;
1260 hspi->RxXferSize = Size;
1261 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1262 hspi->TxXferCount = Size;
1263 hspi->TxXferSize = Size;
1264
1265 /*Init field not used in handle to zero */
1266 hspi->RxISR = NULL;
1267 hspi->TxISR = NULL;
1268
1269 #if (USE_SPI_CRC != 0U)
1270 /* Reset CRC Calculation */
1271 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1272 {
1273 SPI_RESET_CRC(hspi);
1274 }
1275 #endif /* USE_SPI_CRC */
1276
1277 /* Set the Rx Fifo threshold */
1278 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
1279 {
1280 /* Set fiforxthreshold according the reception data length: 16bit */
1281 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1282 }
1283 else
1284 {
1285 /* Set fiforxthreshold according the reception data length: 8bit */
1286 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1287 }
1288
1289 /* Check if the SPI is already enabled */
1290 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1291 {
1292 /* Enable SPI peripheral */
1293 __HAL_SPI_ENABLE(hspi);
1294 }
1295
1296 /* Transmit and Receive data in 16 Bit mode */
1297 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1298 {
1299 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1300 {
1301 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1302 hspi->pTxBuffPtr += sizeof(uint16_t);
1303 hspi->TxXferCount--;
1304 }
1305 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1306 {
1307 /* Check TXE flag */
1308 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1309 {
1310 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1311 hspi->pTxBuffPtr += sizeof(uint16_t);
1312 hspi->TxXferCount--;
1313 /* Next Data is a reception (Rx). Tx not allowed */
1314 txallowed = 0U;
1315
1316 #if (USE_SPI_CRC != 0U)
1317 /* Enable CRC Transmission */
1318 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1319 {
1320 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1321 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1322 {
1323 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1324 }
1325 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1326 }
1327 #endif /* USE_SPI_CRC */
1328 }
1329
1330 /* Check RXNE flag */
1331 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1332 {
1333 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1334 hspi->pRxBuffPtr += sizeof(uint16_t);
1335 hspi->RxXferCount--;
1336 /* Next Data is a Transmission (Tx). Tx is allowed */
1337 txallowed = 1U;
1338 }
1339 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1340 {
1341 errorcode = HAL_TIMEOUT;
1342 goto error;
1343 }
1344 }
1345 }
1346 /* Transmit and Receive data in 8 Bit mode */
1347 else
1348 {
1349 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1350 {
1351 if (hspi->TxXferCount > 1U)
1352 {
1353 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1354 hspi->pTxBuffPtr += sizeof(uint16_t);
1355 hspi->TxXferCount -= 2U;
1356 }
1357 else
1358 {
1359 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1360 hspi->pTxBuffPtr++;
1361 hspi->TxXferCount--;
1362 }
1363 }
1364 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1365 {
1366 /* Check TXE flag */
1367 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1368 {
1369 if (hspi->TxXferCount > 1U)
1370 {
1371 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1372 hspi->pTxBuffPtr += sizeof(uint16_t);
1373 hspi->TxXferCount -= 2U;
1374 }
1375 else
1376 {
1377 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1378 hspi->pTxBuffPtr++;
1379 hspi->TxXferCount--;
1380 }
1381 /* Next Data is a reception (Rx). Tx not allowed */
1382 txallowed = 0U;
1383
1384 #if (USE_SPI_CRC != 0U)
1385 /* Enable CRC Transmission */
1386 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1387 {
1388 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1389 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1390 {
1391 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1392 }
1393 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1394 }
1395 #endif /* USE_SPI_CRC */
1396 }
1397
1398 /* Wait until RXNE flag is reset */
1399 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1400 {
1401 if (hspi->RxXferCount > 1U)
1402 {
1403 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1404 hspi->pRxBuffPtr += sizeof(uint16_t);
1405 hspi->RxXferCount -= 2U;
1406 if (hspi->RxXferCount <= 1U)
1407 {
1408 /* Set RX Fifo threshold before to switch on 8 bit data size */
1409 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1410 }
1411 }
1412 else
1413 {
1414 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1415 hspi->pRxBuffPtr++;
1416 hspi->RxXferCount--;
1417 }
1418 /* Next Data is a Transmission (Tx). Tx is allowed */
1419 txallowed = 1U;
1420 }
1421 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1422 {
1423 errorcode = HAL_TIMEOUT;
1424 goto error;
1425 }
1426 }
1427 }
1428
1429 #if (USE_SPI_CRC != 0U)
1430 /* Read CRC from DR to close CRC calculation process */
1431 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1432 {
1433 /* Wait until TXE flag */
1434 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1435 {
1436 /* Error on the CRC reception */
1437 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1438 errorcode = HAL_TIMEOUT;
1439 goto error;
1440 }
1441 /* Read CRC */
1442 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1443 {
1444 /* Read 16bit CRC */
1445 READ_REG(hspi->Instance->DR);
1446 }
1447 else
1448 {
1449 /* Read 8bit CRC */
1450 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1451
1452 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1453 {
1454 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1455 {
1456 /* Error on the CRC reception */
1457 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1458 errorcode = HAL_TIMEOUT;
1459 goto error;
1460 }
1461 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1462 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1463 }
1464 }
1465 }
1466
1467 /* Check if CRC error occurred */
1468 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1469 {
1470 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1471 /* Clear CRC Flag */
1472 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1473
1474 errorcode = HAL_ERROR;
1475 }
1476 #endif /* USE_SPI_CRC */
1477
1478 /* Check the end of the transaction */
1479 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1480 {
1481 errorcode = HAL_ERROR;
1482 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1483 }
1484
1485 error :
1486 hspi->State = HAL_SPI_STATE_READY;
1487 __HAL_UNLOCK(hspi);
1488 return errorcode;
1489 }
1490
1491 /**
1492 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1493 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1494 * the configuration information for SPI module.
1495 * @param pData pointer to data buffer
1496 * @param Size amount of data to be sent
1497 * @retval HAL status
1498 */
HAL_SPI_Transmit_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1499 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1500 {
1501 HAL_StatusTypeDef errorcode = HAL_OK;
1502
1503 /* Check Direction parameter */
1504 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1505
1506 /* Process Locked */
1507 __HAL_LOCK(hspi);
1508
1509 if ((pData == NULL) || (Size == 0U))
1510 {
1511 errorcode = HAL_ERROR;
1512 goto error;
1513 }
1514
1515 if (hspi->State != HAL_SPI_STATE_READY)
1516 {
1517 errorcode = HAL_BUSY;
1518 goto error;
1519 }
1520
1521 /* Set the transaction information */
1522 hspi->State = HAL_SPI_STATE_BUSY_TX;
1523 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1524 hspi->pTxBuffPtr = (uint8_t *)pData;
1525 hspi->TxXferSize = Size;
1526 hspi->TxXferCount = Size;
1527
1528 /* Init field not used in handle to zero */
1529 hspi->pRxBuffPtr = (uint8_t *)NULL;
1530 hspi->RxXferSize = 0U;
1531 hspi->RxXferCount = 0U;
1532 hspi->RxISR = NULL;
1533
1534 /* Set the function for IT treatment */
1535 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1536 {
1537 hspi->TxISR = SPI_TxISR_16BIT;
1538 }
1539 else
1540 {
1541 hspi->TxISR = SPI_TxISR_8BIT;
1542 }
1543
1544 /* Configure communication direction : 1Line */
1545 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1546 {
1547 SPI_1LINE_TX(hspi);
1548 }
1549
1550 #if (USE_SPI_CRC != 0U)
1551 /* Reset CRC Calculation */
1552 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1553 {
1554 SPI_RESET_CRC(hspi);
1555 }
1556 #endif /* USE_SPI_CRC */
1557
1558 /* Enable TXE and ERR interrupt */
1559 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1560
1561
1562 /* Check if the SPI is already enabled */
1563 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1564 {
1565 /* Enable SPI peripheral */
1566 __HAL_SPI_ENABLE(hspi);
1567 }
1568
1569 error :
1570 __HAL_UNLOCK(hspi);
1571 return errorcode;
1572 }
1573
1574 /**
1575 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1576 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1577 * the configuration information for SPI module.
1578 * @param pData pointer to data buffer
1579 * @param Size amount of data to be sent
1580 * @retval HAL status
1581 */
HAL_SPI_Receive_IT(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1582 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1583 {
1584 HAL_StatusTypeDef errorcode = HAL_OK;
1585
1586 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1587 {
1588 hspi->State = HAL_SPI_STATE_BUSY_RX;
1589 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1590 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1591 }
1592
1593 /* Process Locked */
1594 __HAL_LOCK(hspi);
1595
1596 if (hspi->State != HAL_SPI_STATE_READY)
1597 {
1598 errorcode = HAL_BUSY;
1599 goto error;
1600 }
1601
1602 if ((pData == NULL) || (Size == 0U))
1603 {
1604 errorcode = HAL_ERROR;
1605 goto error;
1606 }
1607
1608 /* Set the transaction information */
1609 hspi->State = HAL_SPI_STATE_BUSY_RX;
1610 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1611 hspi->pRxBuffPtr = (uint8_t *)pData;
1612 hspi->RxXferSize = Size;
1613 hspi->RxXferCount = Size;
1614
1615 /* Init field not used in handle to zero */
1616 hspi->pTxBuffPtr = (uint8_t *)NULL;
1617 hspi->TxXferSize = 0U;
1618 hspi->TxXferCount = 0U;
1619 hspi->TxISR = NULL;
1620
1621 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1622 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1623 {
1624 /* Set RX Fifo threshold according the reception data length: 16 bit */
1625 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1626 hspi->RxISR = SPI_RxISR_16BIT;
1627 }
1628 else
1629 {
1630 /* Set RX Fifo threshold according the reception data length: 8 bit */
1631 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1632 hspi->RxISR = SPI_RxISR_8BIT;
1633 }
1634
1635 /* Configure communication direction : 1Line */
1636 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1637 {
1638 SPI_1LINE_RX(hspi);
1639 }
1640
1641 #if (USE_SPI_CRC != 0U)
1642 /* Reset CRC Calculation */
1643 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1644 {
1645 hspi->CRCSize = 1U;
1646 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1647 {
1648 hspi->CRCSize = 2U;
1649 }
1650 SPI_RESET_CRC(hspi);
1651 }
1652 else
1653 {
1654 hspi->CRCSize = 0U;
1655 }
1656 #endif /* USE_SPI_CRC */
1657
1658 /* Enable TXE and ERR interrupt */
1659 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1660
1661 /* Note : The SPI must be enabled after unlocking current process
1662 to avoid the risk of SPI interrupt handle execution before current
1663 process unlock */
1664
1665 /* Check if the SPI is already enabled */
1666 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1667 {
1668 /* Enable SPI peripheral */
1669 __HAL_SPI_ENABLE(hspi);
1670 }
1671
1672 error :
1673 /* Process Unlocked */
1674 __HAL_UNLOCK(hspi);
1675 return errorcode;
1676 }
1677
1678 /**
1679 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1680 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1681 * the configuration information for SPI module.
1682 * @param pTxData pointer to transmission data buffer
1683 * @param pRxData pointer to reception data buffer
1684 * @param Size amount of data to be sent and received
1685 * @retval HAL status
1686 */
HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)1687 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1688 {
1689 uint32_t tmp_mode;
1690 HAL_SPI_StateTypeDef tmp_state;
1691 HAL_StatusTypeDef errorcode = HAL_OK;
1692
1693 /* Check Direction parameter */
1694 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1695
1696 /* Process locked */
1697 __HAL_LOCK(hspi);
1698
1699 /* Init temporary variables */
1700 tmp_state = hspi->State;
1701 tmp_mode = hspi->Init.Mode;
1702
1703 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1704 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1705 {
1706 errorcode = HAL_BUSY;
1707 goto error;
1708 }
1709
1710 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1711 {
1712 errorcode = HAL_ERROR;
1713 goto error;
1714 }
1715
1716 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1717 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1718 {
1719 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1720 }
1721
1722 /* Set the transaction information */
1723 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1724 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1725 hspi->TxXferSize = Size;
1726 hspi->TxXferCount = Size;
1727 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1728 hspi->RxXferSize = Size;
1729 hspi->RxXferCount = Size;
1730
1731 /* Set the function for IT treatment */
1732 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1733 {
1734 hspi->RxISR = SPI_2linesRxISR_16BIT;
1735 hspi->TxISR = SPI_2linesTxISR_16BIT;
1736 }
1737 else
1738 {
1739 hspi->RxISR = SPI_2linesRxISR_8BIT;
1740 hspi->TxISR = SPI_2linesTxISR_8BIT;
1741 }
1742
1743 #if (USE_SPI_CRC != 0U)
1744 /* Reset CRC Calculation */
1745 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1746 {
1747 hspi->CRCSize = 1U;
1748 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1749 {
1750 hspi->CRCSize = 2U;
1751 }
1752 SPI_RESET_CRC(hspi);
1753 }
1754 else
1755 {
1756 hspi->CRCSize = 0U;
1757 }
1758 #endif /* USE_SPI_CRC */
1759
1760 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1761 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1762 {
1763 /* Set RX Fifo threshold according the reception data length: 16 bit */
1764 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1765 }
1766 else
1767 {
1768 /* Set RX Fifo threshold according the reception data length: 8 bit */
1769 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1770 }
1771
1772 /* Enable TXE, RXNE and ERR interrupt */
1773 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1774
1775 /* Check if the SPI is already enabled */
1776 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1777 {
1778 /* Enable SPI peripheral */
1779 __HAL_SPI_ENABLE(hspi);
1780 }
1781
1782 error :
1783 /* Process Unlocked */
1784 __HAL_UNLOCK(hspi);
1785 return errorcode;
1786 }
1787
1788 /**
1789 * @brief Transmit an amount of data in non-blocking mode with DMA.
1790 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1791 * the configuration information for SPI module.
1792 * @param pData pointer to data buffer
1793 * @param Size amount of data to be sent
1794 * @retval HAL status
1795 */
HAL_SPI_Transmit_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1796 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1797 {
1798 HAL_StatusTypeDef errorcode = HAL_OK;
1799
1800 /* Check tx dma handle */
1801 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1802
1803 /* Check Direction parameter */
1804 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1805
1806 /* Process Locked */
1807 __HAL_LOCK(hspi);
1808
1809 if (hspi->State != HAL_SPI_STATE_READY)
1810 {
1811 errorcode = HAL_BUSY;
1812 goto error;
1813 }
1814
1815 if ((pData == NULL) || (Size == 0U))
1816 {
1817 errorcode = HAL_ERROR;
1818 goto error;
1819 }
1820
1821 /* Set the transaction information */
1822 hspi->State = HAL_SPI_STATE_BUSY_TX;
1823 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1824 hspi->pTxBuffPtr = (uint8_t *)pData;
1825 hspi->TxXferSize = Size;
1826 hspi->TxXferCount = Size;
1827
1828 /* Init field not used in handle to zero */
1829 hspi->pRxBuffPtr = (uint8_t *)NULL;
1830 hspi->TxISR = NULL;
1831 hspi->RxISR = NULL;
1832 hspi->RxXferSize = 0U;
1833 hspi->RxXferCount = 0U;
1834
1835 /* Configure communication direction : 1Line */
1836 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1837 {
1838 SPI_1LINE_TX(hspi);
1839 }
1840
1841 #if (USE_SPI_CRC != 0U)
1842 /* Reset CRC Calculation */
1843 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1844 {
1845 SPI_RESET_CRC(hspi);
1846 }
1847 #endif /* USE_SPI_CRC */
1848
1849 /* Set the SPI TxDMA Half transfer complete callback */
1850 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1851
1852 /* Set the SPI TxDMA transfer complete callback */
1853 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1854
1855 /* Set the DMA error callback */
1856 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1857
1858 /* Set the DMA AbortCpltCallback */
1859 hspi->hdmatx->XferAbortCallback = NULL;
1860
1861 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1862 /* Packing mode is enabled only if the DMA setting is HALWORD */
1863 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1864 {
1865 /* Check the even/odd of the data size + crc if enabled */
1866 if ((hspi->TxXferCount & 0x1U) == 0U)
1867 {
1868 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1869 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1870 }
1871 else
1872 {
1873 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1874 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1875 }
1876 }
1877
1878 /* Enable the Tx DMA Stream/Channel */
1879 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1880 hspi->TxXferCount))
1881 {
1882 /* Update SPI error code */
1883 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1884 errorcode = HAL_ERROR;
1885
1886 hspi->State = HAL_SPI_STATE_READY;
1887 goto error;
1888 }
1889
1890 /* Check if the SPI is already enabled */
1891 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1892 {
1893 /* Enable SPI peripheral */
1894 __HAL_SPI_ENABLE(hspi);
1895 }
1896
1897 /* Enable the SPI Error Interrupt Bit */
1898 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1899
1900 /* Enable Tx DMA Request */
1901 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1902
1903 error :
1904 /* Process Unlocked */
1905 __HAL_UNLOCK(hspi);
1906 return errorcode;
1907 }
1908
1909 /**
1910 * @brief Receive an amount of data in non-blocking mode with DMA.
1911 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1912 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1913 * the configuration information for SPI module.
1914 * @param pData pointer to data buffer
1915 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1916 * @param Size amount of data to be sent
1917 * @retval HAL status
1918 */
HAL_SPI_Receive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pData,uint16_t Size)1919 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1920 {
1921 HAL_StatusTypeDef errorcode = HAL_OK;
1922
1923 /* Check rx dma handle */
1924 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1925
1926 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1927 {
1928 hspi->State = HAL_SPI_STATE_BUSY_RX;
1929
1930 /* Check tx dma handle */
1931 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1932
1933 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1934 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1935 }
1936
1937 /* Process Locked */
1938 __HAL_LOCK(hspi);
1939
1940 if (hspi->State != HAL_SPI_STATE_READY)
1941 {
1942 errorcode = HAL_BUSY;
1943 goto error;
1944 }
1945
1946 if ((pData == NULL) || (Size == 0U))
1947 {
1948 errorcode = HAL_ERROR;
1949 goto error;
1950 }
1951
1952 /* Set the transaction information */
1953 hspi->State = HAL_SPI_STATE_BUSY_RX;
1954 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1955 hspi->pRxBuffPtr = (uint8_t *)pData;
1956 hspi->RxXferSize = Size;
1957 hspi->RxXferCount = Size;
1958
1959 /*Init field not used in handle to zero */
1960 hspi->RxISR = NULL;
1961 hspi->TxISR = NULL;
1962 hspi->TxXferSize = 0U;
1963 hspi->TxXferCount = 0U;
1964
1965 /* Configure communication direction : 1Line */
1966 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1967 {
1968 SPI_1LINE_RX(hspi);
1969 }
1970
1971 #if (USE_SPI_CRC != 0U)
1972 /* Reset CRC Calculation */
1973 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1974 {
1975 SPI_RESET_CRC(hspi);
1976 }
1977 #endif /* USE_SPI_CRC */
1978
1979
1980 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1981 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1982 {
1983 /* Set RX Fifo threshold according the reception data length: 16bit */
1984 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1985 }
1986 else
1987 {
1988 /* Set RX Fifo threshold according the reception data length: 8bit */
1989 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1990
1991 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
1992 {
1993 /* Set RX Fifo threshold according the reception data length: 16bit */
1994 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1995
1996 if ((hspi->RxXferCount & 0x1U) == 0x0U)
1997 {
1998 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1999 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2000 }
2001 else
2002 {
2003 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2004 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2005 }
2006 }
2007 }
2008
2009 /* Set the SPI RxDMA Half transfer complete callback */
2010 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2011
2012 /* Set the SPI Rx DMA transfer complete callback */
2013 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2014
2015 /* Set the DMA error callback */
2016 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2017
2018 /* Set the DMA AbortCpltCallback */
2019 hspi->hdmarx->XferAbortCallback = NULL;
2020
2021 /* Enable the Rx DMA Stream/Channel */
2022 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2023 hspi->RxXferCount))
2024 {
2025 /* Update SPI error code */
2026 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2027 errorcode = HAL_ERROR;
2028
2029 hspi->State = HAL_SPI_STATE_READY;
2030 goto error;
2031 }
2032
2033 /* Check if the SPI is already enabled */
2034 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2035 {
2036 /* Enable SPI peripheral */
2037 __HAL_SPI_ENABLE(hspi);
2038 }
2039
2040 /* Enable the SPI Error Interrupt Bit */
2041 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2042
2043 /* Enable Rx DMA Request */
2044 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2045
2046 error:
2047 /* Process Unlocked */
2048 __HAL_UNLOCK(hspi);
2049 return errorcode;
2050 }
2051
2052 /**
2053 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2054 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2055 * the configuration information for SPI module.
2056 * @param pTxData pointer to transmission data buffer
2057 * @param pRxData pointer to reception data buffer
2058 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2059 * @param Size amount of data to be sent
2060 * @retval HAL status
2061 */
HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef * hspi,uint8_t * pTxData,uint8_t * pRxData,uint16_t Size)2062 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2063 uint16_t Size)
2064 {
2065 uint32_t tmp_mode;
2066 HAL_SPI_StateTypeDef tmp_state;
2067 HAL_StatusTypeDef errorcode = HAL_OK;
2068
2069 /* Check rx & tx dma handles */
2070 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2071 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2072
2073 /* Check Direction parameter */
2074 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2075
2076 /* Process locked */
2077 __HAL_LOCK(hspi);
2078
2079 /* Init temporary variables */
2080 tmp_state = hspi->State;
2081 tmp_mode = hspi->Init.Mode;
2082
2083 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2084 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2085 {
2086 errorcode = HAL_BUSY;
2087 goto error;
2088 }
2089
2090 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2091 {
2092 errorcode = HAL_ERROR;
2093 goto error;
2094 }
2095
2096 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2097 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2098 {
2099 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2100 }
2101
2102 /* Set the transaction information */
2103 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2104 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2105 hspi->TxXferSize = Size;
2106 hspi->TxXferCount = Size;
2107 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2108 hspi->RxXferSize = Size;
2109 hspi->RxXferCount = Size;
2110
2111 /* Init field not used in handle to zero */
2112 hspi->RxISR = NULL;
2113 hspi->TxISR = NULL;
2114
2115 #if (USE_SPI_CRC != 0U)
2116 /* Reset CRC Calculation */
2117 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2118 {
2119 SPI_RESET_CRC(hspi);
2120 }
2121 #endif /* USE_SPI_CRC */
2122
2123 /* Reset the threshold bit */
2124 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2125
2126 /* The packing mode management is enabled by the DMA settings according the spi data size */
2127 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2128 {
2129 /* Set fiforxthreshold according the reception data length: 16bit */
2130 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2131 }
2132 else
2133 {
2134 /* Set RX Fifo threshold according the reception data length: 8bit */
2135 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2136
2137 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2138 {
2139 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2140 {
2141 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2142 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2143 }
2144 else
2145 {
2146 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2147 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2148 }
2149 }
2150
2151 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2152 {
2153 /* Set RX Fifo threshold according the reception data length: 16bit */
2154 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2155
2156 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2157 {
2158 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2159 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2160 }
2161 else
2162 {
2163 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2164 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2165 }
2166 }
2167 }
2168
2169 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2170 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2171 {
2172 /* Set the SPI Rx DMA Half transfer complete callback */
2173 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2174 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2175 }
2176 else
2177 {
2178 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2179 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2180 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2181 }
2182
2183 /* Set the DMA error callback */
2184 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2185
2186 /* Set the DMA AbortCpltCallback */
2187 hspi->hdmarx->XferAbortCallback = NULL;
2188
2189 /* Enable the Rx DMA Stream/Channel */
2190 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2191 hspi->RxXferCount))
2192 {
2193 /* Update SPI error code */
2194 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2195 errorcode = HAL_ERROR;
2196
2197 hspi->State = HAL_SPI_STATE_READY;
2198 goto error;
2199 }
2200
2201 /* Enable Rx DMA Request */
2202 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2203
2204 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2205 is performed in DMA reception complete callback */
2206 hspi->hdmatx->XferHalfCpltCallback = NULL;
2207 hspi->hdmatx->XferCpltCallback = NULL;
2208 hspi->hdmatx->XferErrorCallback = NULL;
2209 hspi->hdmatx->XferAbortCallback = NULL;
2210
2211 /* Enable the Tx DMA Stream/Channel */
2212 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2213 hspi->TxXferCount))
2214 {
2215 /* Update SPI error code */
2216 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2217 errorcode = HAL_ERROR;
2218
2219 hspi->State = HAL_SPI_STATE_READY;
2220 goto error;
2221 }
2222
2223 /* Check if the SPI is already enabled */
2224 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2225 {
2226 /* Enable SPI peripheral */
2227 __HAL_SPI_ENABLE(hspi);
2228 }
2229 /* Enable the SPI Error Interrupt Bit */
2230 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2231
2232 /* Enable Tx DMA Request */
2233 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2234
2235 error :
2236 /* Process Unlocked */
2237 __HAL_UNLOCK(hspi);
2238 return errorcode;
2239 }
2240
2241 /**
2242 * @brief Abort ongoing transfer (blocking mode).
2243 * @param hspi SPI handle.
2244 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2245 * started in Interrupt or DMA mode.
2246 * This procedure performs following operations :
2247 * - Disable SPI Interrupts (depending of transfer direction)
2248 * - Disable the DMA transfer in the peripheral register (if enabled)
2249 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2250 * - Set handle State to READY
2251 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2252 * @retval HAL status
2253 */
HAL_SPI_Abort(SPI_HandleTypeDef * hspi)2254 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2255 {
2256 HAL_StatusTypeDef errorcode;
2257 __IO uint32_t count;
2258 __IO uint32_t resetcount;
2259
2260 /* Initialized local variable */
2261 errorcode = HAL_OK;
2262 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2263 count = resetcount;
2264
2265 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2266 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2267
2268 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2269 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2270 {
2271 hspi->TxISR = SPI_AbortTx_ISR;
2272 /* Wait HAL_SPI_STATE_ABORT state */
2273 do
2274 {
2275 if (count == 0U)
2276 {
2277 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2278 break;
2279 }
2280 count--;
2281 }
2282 while (hspi->State != HAL_SPI_STATE_ABORT);
2283 /* Reset Timeout Counter */
2284 count = resetcount;
2285 }
2286
2287 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2288 {
2289 hspi->RxISR = SPI_AbortRx_ISR;
2290 /* Wait HAL_SPI_STATE_ABORT state */
2291 do
2292 {
2293 if (count == 0U)
2294 {
2295 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2296 break;
2297 }
2298 count--;
2299 }
2300 while (hspi->State != HAL_SPI_STATE_ABORT);
2301 /* Reset Timeout Counter */
2302 count = resetcount;
2303 }
2304
2305 /* Disable the SPI DMA Tx request if enabled */
2306 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2307 {
2308 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2309 if (hspi->hdmatx != NULL)
2310 {
2311 /* Set the SPI DMA Abort callback :
2312 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2313 hspi->hdmatx->XferAbortCallback = NULL;
2314
2315 /* Abort DMA Tx Handle linked to SPI Peripheral */
2316 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2317 {
2318 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2319 }
2320
2321 /* Disable Tx DMA Request */
2322 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2323
2324 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2325 {
2326 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2327 }
2328
2329 /* Disable SPI Peripheral */
2330 __HAL_SPI_DISABLE(hspi);
2331
2332 /* Empty the FRLVL fifo */
2333 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2334 {
2335 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2336 }
2337 }
2338 }
2339
2340 /* Disable the SPI DMA Rx request if enabled */
2341 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2342 {
2343 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2344 if (hspi->hdmarx != NULL)
2345 {
2346 /* Set the SPI DMA Abort callback :
2347 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2348 hspi->hdmarx->XferAbortCallback = NULL;
2349
2350 /* Abort DMA Rx Handle linked to SPI Peripheral */
2351 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2352 {
2353 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2354 }
2355
2356 /* Disable peripheral */
2357 __HAL_SPI_DISABLE(hspi);
2358
2359 /* Control the BSY flag */
2360 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2361 {
2362 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2363 }
2364
2365 /* Empty the FRLVL fifo */
2366 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2367 {
2368 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2369 }
2370
2371 /* Disable Rx DMA Request */
2372 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2373 }
2374 }
2375 /* Reset Tx and Rx transfer counters */
2376 hspi->RxXferCount = 0U;
2377 hspi->TxXferCount = 0U;
2378
2379 /* Check error during Abort procedure */
2380 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2381 {
2382 /* return HAL_Error in case of error during Abort procedure */
2383 errorcode = HAL_ERROR;
2384 }
2385 else
2386 {
2387 /* Reset errorCode */
2388 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2389 }
2390
2391 /* Clear the Error flags in the SR register */
2392 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2393 __HAL_SPI_CLEAR_FREFLAG(hspi);
2394
2395 /* Restore hspi->state to ready */
2396 hspi->State = HAL_SPI_STATE_READY;
2397
2398 return errorcode;
2399 }
2400
2401 /**
2402 * @brief Abort ongoing transfer (Interrupt mode).
2403 * @param hspi SPI handle.
2404 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2405 * started in Interrupt or DMA mode.
2406 * This procedure performs following operations :
2407 * - Disable SPI Interrupts (depending of transfer direction)
2408 * - Disable the DMA transfer in the peripheral register (if enabled)
2409 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2410 * - Set handle State to READY
2411 * - At abort completion, call user abort complete callback
2412 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2413 * considered as completed only when user abort complete callback is executed (not when exiting function).
2414 * @retval HAL status
2415 */
HAL_SPI_Abort_IT(SPI_HandleTypeDef * hspi)2416 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2417 {
2418 HAL_StatusTypeDef errorcode;
2419 uint32_t abortcplt ;
2420 __IO uint32_t count;
2421 __IO uint32_t resetcount;
2422
2423 /* Initialized local variable */
2424 errorcode = HAL_OK;
2425 abortcplt = 1U;
2426 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2427 count = resetcount;
2428
2429 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2430 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2431
2432 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2433 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2434 {
2435 hspi->TxISR = SPI_AbortTx_ISR;
2436 /* Wait HAL_SPI_STATE_ABORT state */
2437 do
2438 {
2439 if (count == 0U)
2440 {
2441 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2442 break;
2443 }
2444 count--;
2445 }
2446 while (hspi->State != HAL_SPI_STATE_ABORT);
2447 /* Reset Timeout Counter */
2448 count = resetcount;
2449 }
2450
2451 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2452 {
2453 hspi->RxISR = SPI_AbortRx_ISR;
2454 /* Wait HAL_SPI_STATE_ABORT state */
2455 do
2456 {
2457 if (count == 0U)
2458 {
2459 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2460 break;
2461 }
2462 count--;
2463 }
2464 while (hspi->State != HAL_SPI_STATE_ABORT);
2465 /* Reset Timeout Counter */
2466 count = resetcount;
2467 }
2468
2469 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2470 before any call to DMA Abort functions */
2471 /* DMA Tx Handle is valid */
2472 if (hspi->hdmatx != NULL)
2473 {
2474 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2475 Otherwise, set it to NULL */
2476 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2477 {
2478 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2479 }
2480 else
2481 {
2482 hspi->hdmatx->XferAbortCallback = NULL;
2483 }
2484 }
2485 /* DMA Rx Handle is valid */
2486 if (hspi->hdmarx != NULL)
2487 {
2488 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2489 Otherwise, set it to NULL */
2490 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2491 {
2492 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2493 }
2494 else
2495 {
2496 hspi->hdmarx->XferAbortCallback = NULL;
2497 }
2498 }
2499
2500 /* Disable the SPI DMA Tx request if enabled */
2501 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2502 {
2503 /* Abort the SPI DMA Tx Stream/Channel */
2504 if (hspi->hdmatx != NULL)
2505 {
2506 /* Abort DMA Tx Handle linked to SPI Peripheral */
2507 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2508 {
2509 hspi->hdmatx->XferAbortCallback = NULL;
2510 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2511 }
2512 else
2513 {
2514 abortcplt = 0U;
2515 }
2516 }
2517 }
2518 /* Disable the SPI DMA Rx request if enabled */
2519 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2520 {
2521 /* Abort the SPI DMA Rx Stream/Channel */
2522 if (hspi->hdmarx != NULL)
2523 {
2524 /* Abort DMA Rx Handle linked to SPI Peripheral */
2525 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2526 {
2527 hspi->hdmarx->XferAbortCallback = NULL;
2528 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2529 }
2530 else
2531 {
2532 abortcplt = 0U;
2533 }
2534 }
2535 }
2536
2537 if (abortcplt == 1U)
2538 {
2539 /* Reset Tx and Rx transfer counters */
2540 hspi->RxXferCount = 0U;
2541 hspi->TxXferCount = 0U;
2542
2543 /* Check error during Abort procedure */
2544 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2545 {
2546 /* return HAL_Error in case of error during Abort procedure */
2547 errorcode = HAL_ERROR;
2548 }
2549 else
2550 {
2551 /* Reset errorCode */
2552 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2553 }
2554
2555 /* Clear the Error flags in the SR register */
2556 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2557 __HAL_SPI_CLEAR_FREFLAG(hspi);
2558
2559 /* Restore hspi->State to Ready */
2560 hspi->State = HAL_SPI_STATE_READY;
2561
2562 /* As no DMA to be aborted, call directly user Abort complete callback */
2563 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2564 hspi->AbortCpltCallback(hspi);
2565 #else
2566 HAL_SPI_AbortCpltCallback(hspi);
2567 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2568 }
2569
2570 return errorcode;
2571 }
2572
2573 /**
2574 * @brief Pause the DMA Transfer.
2575 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2576 * the configuration information for the specified SPI module.
2577 * @retval HAL status
2578 */
HAL_SPI_DMAPause(SPI_HandleTypeDef * hspi)2579 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2580 {
2581 /* Process Locked */
2582 __HAL_LOCK(hspi);
2583
2584 /* Disable the SPI DMA Tx & Rx requests */
2585 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2586
2587 /* Process Unlocked */
2588 __HAL_UNLOCK(hspi);
2589
2590 return HAL_OK;
2591 }
2592
2593 /**
2594 * @brief Resume the DMA Transfer.
2595 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2596 * the configuration information for the specified SPI module.
2597 * @retval HAL status
2598 */
HAL_SPI_DMAResume(SPI_HandleTypeDef * hspi)2599 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2600 {
2601 /* Process Locked */
2602 __HAL_LOCK(hspi);
2603
2604 /* Enable the SPI DMA Tx & Rx requests */
2605 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2606
2607 /* Process Unlocked */
2608 __HAL_UNLOCK(hspi);
2609
2610 return HAL_OK;
2611 }
2612
2613 /**
2614 * @brief Stop the DMA Transfer.
2615 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2616 * the configuration information for the specified SPI module.
2617 * @retval HAL status
2618 */
HAL_SPI_DMAStop(SPI_HandleTypeDef * hspi)2619 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2620 {
2621 HAL_StatusTypeDef errorcode = HAL_OK;
2622 /* The Lock is not implemented on this API to allow the user application
2623 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2624 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2625 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2626 */
2627
2628 /* Abort the SPI DMA tx Stream/Channel */
2629 if (hspi->hdmatx != NULL)
2630 {
2631 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2632 {
2633 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2634 errorcode = HAL_ERROR;
2635 }
2636 }
2637 /* Abort the SPI DMA rx Stream/Channel */
2638 if (hspi->hdmarx != NULL)
2639 {
2640 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2641 {
2642 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2643 errorcode = HAL_ERROR;
2644 }
2645 }
2646
2647 /* Disable the SPI DMA Tx & Rx requests */
2648 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2649 hspi->State = HAL_SPI_STATE_READY;
2650 return errorcode;
2651 }
2652
2653 /**
2654 * @brief Handle SPI interrupt request.
2655 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2656 * the configuration information for the specified SPI module.
2657 * @retval None
2658 */
HAL_SPI_IRQHandler(SPI_HandleTypeDef * hspi)2659 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2660 {
2661 uint32_t itsource = hspi->Instance->CR2;
2662 uint32_t itflag = hspi->Instance->SR;
2663
2664 /* SPI in mode Receiver ----------------------------------------------------*/
2665 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2666 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2667 {
2668 hspi->RxISR(hspi);
2669 return;
2670 }
2671
2672 /* SPI in mode Transmitter -------------------------------------------------*/
2673 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2674 {
2675 hspi->TxISR(hspi);
2676 return;
2677 }
2678
2679 /* SPI in Error Treatment --------------------------------------------------*/
2680 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2681 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2682 {
2683 /* SPI Overrun error interrupt occurred ----------------------------------*/
2684 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2685 {
2686 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2687 {
2688 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2689 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2690 }
2691 else
2692 {
2693 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2694 return;
2695 }
2696 }
2697
2698 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2699 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2700 {
2701 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2702 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2703 }
2704
2705 /* SPI Frame error interrupt occurred ------------------------------------*/
2706 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2707 {
2708 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2709 __HAL_SPI_CLEAR_FREFLAG(hspi);
2710 }
2711
2712 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2713 {
2714 /* Disable all interrupts */
2715 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2716
2717 hspi->State = HAL_SPI_STATE_READY;
2718 /* Disable the SPI DMA requests if enabled */
2719 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2720 {
2721 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2722
2723 /* Abort the SPI DMA Rx channel */
2724 if (hspi->hdmarx != NULL)
2725 {
2726 /* Set the SPI DMA Abort callback :
2727 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2728 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2729 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2730 {
2731 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2732 }
2733 }
2734 /* Abort the SPI DMA Tx channel */
2735 if (hspi->hdmatx != NULL)
2736 {
2737 /* Set the SPI DMA Abort callback :
2738 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2739 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2740 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2741 {
2742 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2743 }
2744 }
2745 }
2746 else
2747 {
2748 /* Call user error callback */
2749 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2750 hspi->ErrorCallback(hspi);
2751 #else
2752 HAL_SPI_ErrorCallback(hspi);
2753 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2754 }
2755 }
2756 return;
2757 }
2758 }
2759
2760 /**
2761 * @brief Tx Transfer completed callback.
2762 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2763 * the configuration information for SPI module.
2764 * @retval None
2765 */
HAL_SPI_TxCpltCallback(SPI_HandleTypeDef * hspi)2766 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2767 {
2768 /* Prevent unused argument(s) compilation warning */
2769 UNUSED(hspi);
2770
2771 /* NOTE : This function should not be modified, when the callback is needed,
2772 the HAL_SPI_TxCpltCallback should be implemented in the user file
2773 */
2774 }
2775
2776 /**
2777 * @brief Rx Transfer completed callback.
2778 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2779 * the configuration information for SPI module.
2780 * @retval None
2781 */
HAL_SPI_RxCpltCallback(SPI_HandleTypeDef * hspi)2782 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2783 {
2784 /* Prevent unused argument(s) compilation warning */
2785 UNUSED(hspi);
2786
2787 /* NOTE : This function should not be modified, when the callback is needed,
2788 the HAL_SPI_RxCpltCallback should be implemented in the user file
2789 */
2790 }
2791
2792 /**
2793 * @brief Tx and Rx Transfer completed callback.
2794 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2795 * the configuration information for SPI module.
2796 * @retval None
2797 */
HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef * hspi)2798 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2799 {
2800 /* Prevent unused argument(s) compilation warning */
2801 UNUSED(hspi);
2802
2803 /* NOTE : This function should not be modified, when the callback is needed,
2804 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2805 */
2806 }
2807
2808 /**
2809 * @brief Tx Half Transfer completed callback.
2810 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2811 * the configuration information for SPI module.
2812 * @retval None
2813 */
HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef * hspi)2814 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2815 {
2816 /* Prevent unused argument(s) compilation warning */
2817 UNUSED(hspi);
2818
2819 /* NOTE : This function should not be modified, when the callback is needed,
2820 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2821 */
2822 }
2823
2824 /**
2825 * @brief Rx Half Transfer completed callback.
2826 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2827 * the configuration information for SPI module.
2828 * @retval None
2829 */
HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef * hspi)2830 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2831 {
2832 /* Prevent unused argument(s) compilation warning */
2833 UNUSED(hspi);
2834
2835 /* NOTE : This function should not be modified, when the callback is needed,
2836 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2837 */
2838 }
2839
2840 /**
2841 * @brief Tx and Rx Half Transfer callback.
2842 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2843 * the configuration information for SPI module.
2844 * @retval None
2845 */
HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef * hspi)2846 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2847 {
2848 /* Prevent unused argument(s) compilation warning */
2849 UNUSED(hspi);
2850
2851 /* NOTE : This function should not be modified, when the callback is needed,
2852 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2853 */
2854 }
2855
2856 /**
2857 * @brief SPI error callback.
2858 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2859 * the configuration information for SPI module.
2860 * @retval None
2861 */
HAL_SPI_ErrorCallback(SPI_HandleTypeDef * hspi)2862 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2863 {
2864 /* Prevent unused argument(s) compilation warning */
2865 UNUSED(hspi);
2866
2867 /* NOTE : This function should not be modified, when the callback is needed,
2868 the HAL_SPI_ErrorCallback should be implemented in the user file
2869 */
2870 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2871 and user can use HAL_SPI_GetError() API to check the latest error occurred
2872 */
2873 }
2874
2875 /**
2876 * @brief SPI Abort Complete callback.
2877 * @param hspi SPI handle.
2878 * @retval None
2879 */
HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef * hspi)2880 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2881 {
2882 /* Prevent unused argument(s) compilation warning */
2883 UNUSED(hspi);
2884
2885 /* NOTE : This function should not be modified, when the callback is needed,
2886 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2887 */
2888 }
2889
2890 /**
2891 * @}
2892 */
2893
2894 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2895 * @brief SPI control functions
2896 *
2897 @verbatim
2898 ===============================================================================
2899 ##### Peripheral State and Errors functions #####
2900 ===============================================================================
2901 [..]
2902 This subsection provides a set of functions allowing to control the SPI.
2903 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2904 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2905 @endverbatim
2906 * @{
2907 */
2908
2909 /**
2910 * @brief Return the SPI handle state.
2911 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2912 * the configuration information for SPI module.
2913 * @retval SPI state
2914 */
HAL_SPI_GetState(SPI_HandleTypeDef * hspi)2915 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2916 {
2917 /* Return SPI handle state */
2918 return hspi->State;
2919 }
2920
2921 /**
2922 * @brief Return the SPI error code.
2923 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2924 * the configuration information for SPI module.
2925 * @retval SPI error code in bitmap format
2926 */
HAL_SPI_GetError(SPI_HandleTypeDef * hspi)2927 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2928 {
2929 /* Return SPI ErrorCode */
2930 return hspi->ErrorCode;
2931 }
2932
2933 /**
2934 * @}
2935 */
2936
2937 /**
2938 * @}
2939 */
2940
2941 /** @addtogroup SPI_Private_Functions
2942 * @brief Private functions
2943 * @{
2944 */
2945
2946 /**
2947 * @brief DMA SPI transmit process complete callback.
2948 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2949 * the configuration information for the specified DMA module.
2950 * @retval None
2951 */
SPI_DMATransmitCplt(DMA_HandleTypeDef * hdma)2952 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2953 {
2954 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2955 uint32_t tickstart;
2956
2957 /* Init tickstart for timeout management*/
2958 tickstart = HAL_GetTick();
2959
2960 /* DMA Normal Mode */
2961 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2962 {
2963 /* Disable ERR interrupt */
2964 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2965
2966 /* Disable Tx DMA Request */
2967 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2968
2969 /* Check the end of the transaction */
2970 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2971 {
2972 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2973 }
2974
2975 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2976 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
2977 {
2978 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2979 }
2980
2981 hspi->TxXferCount = 0U;
2982 hspi->State = HAL_SPI_STATE_READY;
2983
2984 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2985 {
2986 /* Call user error callback */
2987 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2988 hspi->ErrorCallback(hspi);
2989 #else
2990 HAL_SPI_ErrorCallback(hspi);
2991 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2992 return;
2993 }
2994 }
2995 /* Call user Tx complete callback */
2996 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2997 hspi->TxCpltCallback(hspi);
2998 #else
2999 HAL_SPI_TxCpltCallback(hspi);
3000 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3001 }
3002
3003 /**
3004 * @brief DMA SPI receive process complete callback.
3005 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3006 * the configuration information for the specified DMA module.
3007 * @retval None
3008 */
SPI_DMAReceiveCplt(DMA_HandleTypeDef * hdma)3009 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3010 {
3011 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3012 uint32_t tickstart;
3013
3014 /* Init tickstart for timeout management*/
3015 tickstart = HAL_GetTick();
3016
3017 /* DMA Normal Mode */
3018 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3019 {
3020 /* Disable ERR interrupt */
3021 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3022
3023 #if (USE_SPI_CRC != 0U)
3024 /* CRC handling */
3025 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3026 {
3027 /* Wait until RXNE flag */
3028 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3029 {
3030 /* Error on the CRC reception */
3031 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3032 }
3033 /* Read CRC */
3034 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3035 {
3036 /* Read 16bit CRC */
3037 READ_REG(hspi->Instance->DR);
3038 }
3039 else
3040 {
3041 /* Read 8bit CRC */
3042 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3043
3044 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3045 {
3046 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3047 {
3048 /* Error on the CRC reception */
3049 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3050 }
3051 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3052 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3053 }
3054 }
3055 }
3056 #endif /* USE_SPI_CRC */
3057
3058 /* Check if we are in Master RX 2 line mode */
3059 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
3060 {
3061 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3062 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3063 }
3064 else
3065 {
3066 /* Normal case */
3067 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3068 }
3069
3070 /* Check the end of the transaction */
3071 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3072 {
3073 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3074 }
3075
3076 hspi->RxXferCount = 0U;
3077 hspi->State = HAL_SPI_STATE_READY;
3078
3079 #if (USE_SPI_CRC != 0U)
3080 /* Check if CRC error occurred */
3081 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3082 {
3083 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3084 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3085 }
3086 #endif /* USE_SPI_CRC */
3087
3088 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3089 {
3090 /* Call user error callback */
3091 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3092 hspi->ErrorCallback(hspi);
3093 #else
3094 HAL_SPI_ErrorCallback(hspi);
3095 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3096 return;
3097 }
3098 }
3099 /* Call user Rx complete callback */
3100 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3101 hspi->RxCpltCallback(hspi);
3102 #else
3103 HAL_SPI_RxCpltCallback(hspi);
3104 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3105 }
3106
3107 /**
3108 * @brief DMA SPI transmit receive process complete callback.
3109 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3110 * the configuration information for the specified DMA module.
3111 * @retval None
3112 */
SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef * hdma)3113 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3114 {
3115 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3116 uint32_t tickstart;
3117
3118 /* Init tickstart for timeout management*/
3119 tickstart = HAL_GetTick();
3120
3121 /* DMA Normal Mode */
3122 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3123 {
3124 /* Disable ERR interrupt */
3125 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3126
3127 #if (USE_SPI_CRC != 0U)
3128 /* CRC handling */
3129 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3130 {
3131 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3132 {
3133 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3134 tickstart) != HAL_OK)
3135 {
3136 /* Error on the CRC reception */
3137 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3138 }
3139 /* Read CRC to Flush DR and RXNE flag */
3140 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3141 }
3142 else
3143 {
3144 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3145 {
3146 /* Error on the CRC reception */
3147 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3148 }
3149 /* Read CRC to Flush DR and RXNE flag */
3150 READ_REG(hspi->Instance->DR);
3151 }
3152 }
3153 #endif /* USE_SPI_CRC */
3154
3155 /* Check the end of the transaction */
3156 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3157 {
3158 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3159 }
3160
3161 /* Disable Rx/Tx DMA Request */
3162 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3163
3164 hspi->TxXferCount = 0U;
3165 hspi->RxXferCount = 0U;
3166 hspi->State = HAL_SPI_STATE_READY;
3167
3168 #if (USE_SPI_CRC != 0U)
3169 /* Check if CRC error occurred */
3170 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3171 {
3172 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3173 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3174 }
3175 #endif /* USE_SPI_CRC */
3176
3177 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3178 {
3179 /* Call user error callback */
3180 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3181 hspi->ErrorCallback(hspi);
3182 #else
3183 HAL_SPI_ErrorCallback(hspi);
3184 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3185 return;
3186 }
3187 }
3188 /* Call user TxRx complete callback */
3189 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3190 hspi->TxRxCpltCallback(hspi);
3191 #else
3192 HAL_SPI_TxRxCpltCallback(hspi);
3193 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3194 }
3195
3196 /**
3197 * @brief DMA SPI half transmit process complete callback.
3198 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3199 * the configuration information for the specified DMA module.
3200 * @retval None
3201 */
SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef * hdma)3202 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3203 {
3204 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3205
3206 /* Call user Tx half complete callback */
3207 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3208 hspi->TxHalfCpltCallback(hspi);
3209 #else
3210 HAL_SPI_TxHalfCpltCallback(hspi);
3211 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3212 }
3213
3214 /**
3215 * @brief DMA SPI half receive process complete callback
3216 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3217 * the configuration information for the specified DMA module.
3218 * @retval None
3219 */
SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef * hdma)3220 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3221 {
3222 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3223
3224 /* Call user Rx half complete callback */
3225 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3226 hspi->RxHalfCpltCallback(hspi);
3227 #else
3228 HAL_SPI_RxHalfCpltCallback(hspi);
3229 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3230 }
3231
3232 /**
3233 * @brief DMA SPI half transmit receive process complete callback.
3234 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3235 * the configuration information for the specified DMA module.
3236 * @retval None
3237 */
SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef * hdma)3238 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3239 {
3240 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3241
3242 /* Call user TxRx half complete callback */
3243 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3244 hspi->TxRxHalfCpltCallback(hspi);
3245 #else
3246 HAL_SPI_TxRxHalfCpltCallback(hspi);
3247 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3248 }
3249
3250 /**
3251 * @brief DMA SPI communication error callback.
3252 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3253 * the configuration information for the specified DMA module.
3254 * @retval None
3255 */
SPI_DMAError(DMA_HandleTypeDef * hdma)3256 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3257 {
3258 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3259
3260 /* Stop the disable DMA transfer on SPI side */
3261 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3262
3263 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3264 hspi->State = HAL_SPI_STATE_READY;
3265 /* Call user error callback */
3266 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3267 hspi->ErrorCallback(hspi);
3268 #else
3269 HAL_SPI_ErrorCallback(hspi);
3270 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3271 }
3272
3273 /**
3274 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3275 * (To be called at end of DMA Abort procedure following error occurrence).
3276 * @param hdma DMA handle.
3277 * @retval None
3278 */
SPI_DMAAbortOnError(DMA_HandleTypeDef * hdma)3279 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3280 {
3281 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3282 hspi->RxXferCount = 0U;
3283 hspi->TxXferCount = 0U;
3284
3285 /* Call user error callback */
3286 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3287 hspi->ErrorCallback(hspi);
3288 #else
3289 HAL_SPI_ErrorCallback(hspi);
3290 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3291 }
3292
3293 /**
3294 * @brief DMA SPI Tx communication abort callback, when initiated by user
3295 * (To be called at end of DMA Tx Abort procedure following user abort request).
3296 * @note When this callback is executed, User Abort complete call back is called only if no
3297 * Abort still ongoing for Rx DMA Handle.
3298 * @param hdma DMA handle.
3299 * @retval None
3300 */
SPI_DMATxAbortCallback(DMA_HandleTypeDef * hdma)3301 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3302 {
3303 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3304
3305 hspi->hdmatx->XferAbortCallback = NULL;
3306
3307 /* Disable Tx DMA Request */
3308 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3309
3310 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3311 {
3312 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3313 }
3314
3315 /* Disable SPI Peripheral */
3316 __HAL_SPI_DISABLE(hspi);
3317
3318 /* Empty the FRLVL fifo */
3319 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3320 {
3321 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3322 }
3323
3324 /* Check if an Abort process is still ongoing */
3325 if (hspi->hdmarx != NULL)
3326 {
3327 if (hspi->hdmarx->XferAbortCallback != NULL)
3328 {
3329 return;
3330 }
3331 }
3332
3333 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3334 hspi->RxXferCount = 0U;
3335 hspi->TxXferCount = 0U;
3336
3337 /* Check no error during Abort procedure */
3338 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3339 {
3340 /* Reset errorCode */
3341 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3342 }
3343
3344 /* Clear the Error flags in the SR register */
3345 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3346 __HAL_SPI_CLEAR_FREFLAG(hspi);
3347
3348 /* Restore hspi->State to Ready */
3349 hspi->State = HAL_SPI_STATE_READY;
3350
3351 /* Call user Abort complete callback */
3352 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3353 hspi->AbortCpltCallback(hspi);
3354 #else
3355 HAL_SPI_AbortCpltCallback(hspi);
3356 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3357 }
3358
3359 /**
3360 * @brief DMA SPI Rx communication abort callback, when initiated by user
3361 * (To be called at end of DMA Rx Abort procedure following user abort request).
3362 * @note When this callback is executed, User Abort complete call back is called only if no
3363 * Abort still ongoing for Tx DMA Handle.
3364 * @param hdma DMA handle.
3365 * @retval None
3366 */
SPI_DMARxAbortCallback(DMA_HandleTypeDef * hdma)3367 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3368 {
3369 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3370
3371 /* Disable SPI Peripheral */
3372 __HAL_SPI_DISABLE(hspi);
3373
3374 hspi->hdmarx->XferAbortCallback = NULL;
3375
3376 /* Disable Rx DMA Request */
3377 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3378
3379 /* Control the BSY flag */
3380 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3381 {
3382 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3383 }
3384
3385 /* Empty the FRLVL fifo */
3386 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3387 {
3388 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3389 }
3390
3391 /* Check if an Abort process is still ongoing */
3392 if (hspi->hdmatx != NULL)
3393 {
3394 if (hspi->hdmatx->XferAbortCallback != NULL)
3395 {
3396 return;
3397 }
3398 }
3399
3400 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3401 hspi->RxXferCount = 0U;
3402 hspi->TxXferCount = 0U;
3403
3404 /* Check no error during Abort procedure */
3405 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3406 {
3407 /* Reset errorCode */
3408 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3409 }
3410
3411 /* Clear the Error flags in the SR register */
3412 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3413 __HAL_SPI_CLEAR_FREFLAG(hspi);
3414
3415 /* Restore hspi->State to Ready */
3416 hspi->State = HAL_SPI_STATE_READY;
3417
3418 /* Call user Abort complete callback */
3419 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3420 hspi->AbortCpltCallback(hspi);
3421 #else
3422 HAL_SPI_AbortCpltCallback(hspi);
3423 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3424 }
3425
3426 /**
3427 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3428 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3429 * the configuration information for SPI module.
3430 * @retval None
3431 */
SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3432 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3433 {
3434 /* Receive data in packing mode */
3435 if (hspi->RxXferCount > 1U)
3436 {
3437 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3438 hspi->pRxBuffPtr += sizeof(uint16_t);
3439 hspi->RxXferCount -= 2U;
3440 if (hspi->RxXferCount == 1U)
3441 {
3442 /* Set RX Fifo threshold according the reception data length: 8bit */
3443 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3444 }
3445 }
3446 /* Receive data in 8 Bit mode */
3447 else
3448 {
3449 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3450 hspi->pRxBuffPtr++;
3451 hspi->RxXferCount--;
3452 }
3453
3454 /* Check end of the reception */
3455 if (hspi->RxXferCount == 0U)
3456 {
3457 #if (USE_SPI_CRC != 0U)
3458 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3459 {
3460 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3461 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3462 return;
3463 }
3464 #endif /* USE_SPI_CRC */
3465
3466 /* Disable RXNE and ERR interrupt */
3467 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3468
3469 if (hspi->TxXferCount == 0U)
3470 {
3471 SPI_CloseRxTx_ISR(hspi);
3472 }
3473 }
3474 }
3475
3476 #if (USE_SPI_CRC != 0U)
3477 /**
3478 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3479 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3480 * the configuration information for SPI module.
3481 * @retval None
3482 */
SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3483 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3484 {
3485 /* Read 8bit CRC to flush Data Regsiter */
3486 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3487
3488 hspi->CRCSize--;
3489
3490 /* Check end of the reception */
3491 if (hspi->CRCSize == 0U)
3492 {
3493 /* Disable RXNE and ERR interrupt */
3494 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3495
3496 if (hspi->TxXferCount == 0U)
3497 {
3498 SPI_CloseRxTx_ISR(hspi);
3499 }
3500 }
3501 }
3502 #endif /* USE_SPI_CRC */
3503
3504 /**
3505 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3506 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3507 * the configuration information for SPI module.
3508 * @retval None
3509 */
SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3510 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3511 {
3512 /* Transmit data in packing Bit mode */
3513 if (hspi->TxXferCount >= 2U)
3514 {
3515 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3516 hspi->pTxBuffPtr += sizeof(uint16_t);
3517 hspi->TxXferCount -= 2U;
3518 }
3519 /* Transmit data in 8 Bit mode */
3520 else
3521 {
3522 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3523 hspi->pTxBuffPtr++;
3524 hspi->TxXferCount--;
3525 }
3526
3527 /* Check the end of the transmission */
3528 if (hspi->TxXferCount == 0U)
3529 {
3530 #if (USE_SPI_CRC != 0U)
3531 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3532 {
3533 /* Set CRC Next Bit to send CRC */
3534 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3535 /* Disable TXE interrupt */
3536 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3537 return;
3538 }
3539 #endif /* USE_SPI_CRC */
3540
3541 /* Disable TXE interrupt */
3542 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3543
3544 if (hspi->RxXferCount == 0U)
3545 {
3546 SPI_CloseRxTx_ISR(hspi);
3547 }
3548 }
3549 }
3550
3551 /**
3552 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3553 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3554 * the configuration information for SPI module.
3555 * @retval None
3556 */
SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3557 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3558 {
3559 /* Receive data in 16 Bit mode */
3560 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3561 hspi->pRxBuffPtr += sizeof(uint16_t);
3562 hspi->RxXferCount--;
3563
3564 if (hspi->RxXferCount == 0U)
3565 {
3566 #if (USE_SPI_CRC != 0U)
3567 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3568 {
3569 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3570 return;
3571 }
3572 #endif /* USE_SPI_CRC */
3573
3574 /* Disable RXNE interrupt */
3575 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3576
3577 if (hspi->TxXferCount == 0U)
3578 {
3579 SPI_CloseRxTx_ISR(hspi);
3580 }
3581 }
3582 }
3583
3584 #if (USE_SPI_CRC != 0U)
3585 /**
3586 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3587 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3588 * the configuration information for SPI module.
3589 * @retval None
3590 */
SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3591 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3592 {
3593 /* Read 16bit CRC to flush Data Regsiter */
3594 READ_REG(hspi->Instance->DR);
3595
3596 /* Disable RXNE interrupt */
3597 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3598
3599 SPI_CloseRxTx_ISR(hspi);
3600 }
3601 #endif /* USE_SPI_CRC */
3602
3603 /**
3604 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3605 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3606 * the configuration information for SPI module.
3607 * @retval None
3608 */
SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3609 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3610 {
3611 /* Transmit data in 16 Bit mode */
3612 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3613 hspi->pTxBuffPtr += sizeof(uint16_t);
3614 hspi->TxXferCount--;
3615
3616 /* Enable CRC Transmission */
3617 if (hspi->TxXferCount == 0U)
3618 {
3619 #if (USE_SPI_CRC != 0U)
3620 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3621 {
3622 /* Set CRC Next Bit to send CRC */
3623 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3624 /* Disable TXE interrupt */
3625 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3626 return;
3627 }
3628 #endif /* USE_SPI_CRC */
3629
3630 /* Disable TXE interrupt */
3631 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3632
3633 if (hspi->RxXferCount == 0U)
3634 {
3635 SPI_CloseRxTx_ISR(hspi);
3636 }
3637 }
3638 }
3639
3640 #if (USE_SPI_CRC != 0U)
3641 /**
3642 * @brief Manage the CRC 8-bit receive in Interrupt context.
3643 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3644 * the configuration information for SPI module.
3645 * @retval None
3646 */
SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef * hspi)3647 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3648 {
3649 /* Read 8bit CRC to flush Data Register */
3650 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3651
3652 hspi->CRCSize--;
3653
3654 if (hspi->CRCSize == 0U)
3655 {
3656 SPI_CloseRx_ISR(hspi);
3657 }
3658 }
3659 #endif /* USE_SPI_CRC */
3660
3661 /**
3662 * @brief Manage the receive 8-bit in Interrupt context.
3663 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3664 * the configuration information for SPI module.
3665 * @retval None
3666 */
SPI_RxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3667 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3668 {
3669 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3670 hspi->pRxBuffPtr++;
3671 hspi->RxXferCount--;
3672
3673 #if (USE_SPI_CRC != 0U)
3674 /* Enable CRC Transmission */
3675 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3676 {
3677 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3678 }
3679 #endif /* USE_SPI_CRC */
3680
3681 if (hspi->RxXferCount == 0U)
3682 {
3683 #if (USE_SPI_CRC != 0U)
3684 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3685 {
3686 hspi->RxISR = SPI_RxISR_8BITCRC;
3687 return;
3688 }
3689 #endif /* USE_SPI_CRC */
3690 SPI_CloseRx_ISR(hspi);
3691 }
3692 }
3693
3694 #if (USE_SPI_CRC != 0U)
3695 /**
3696 * @brief Manage the CRC 16-bit receive in Interrupt context.
3697 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3698 * the configuration information for SPI module.
3699 * @retval None
3700 */
SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef * hspi)3701 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3702 {
3703 /* Read 16bit CRC to flush Data Register */
3704 READ_REG(hspi->Instance->DR);
3705
3706 /* Disable RXNE and ERR interrupt */
3707 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3708
3709 SPI_CloseRx_ISR(hspi);
3710 }
3711 #endif /* USE_SPI_CRC */
3712
3713 /**
3714 * @brief Manage the 16-bit receive in Interrupt context.
3715 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3716 * the configuration information for SPI module.
3717 * @retval None
3718 */
SPI_RxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3719 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3720 {
3721 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3722 hspi->pRxBuffPtr += sizeof(uint16_t);
3723 hspi->RxXferCount--;
3724
3725 #if (USE_SPI_CRC != 0U)
3726 /* Enable CRC Transmission */
3727 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3728 {
3729 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3730 }
3731 #endif /* USE_SPI_CRC */
3732
3733 if (hspi->RxXferCount == 0U)
3734 {
3735 #if (USE_SPI_CRC != 0U)
3736 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3737 {
3738 hspi->RxISR = SPI_RxISR_16BITCRC;
3739 return;
3740 }
3741 #endif /* USE_SPI_CRC */
3742 SPI_CloseRx_ISR(hspi);
3743 }
3744 }
3745
3746 /**
3747 * @brief Handle the data 8-bit transmit in Interrupt mode.
3748 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3749 * the configuration information for SPI module.
3750 * @retval None
3751 */
SPI_TxISR_8BIT(struct __SPI_HandleTypeDef * hspi)3752 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3753 {
3754 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3755 hspi->pTxBuffPtr++;
3756 hspi->TxXferCount--;
3757
3758 if (hspi->TxXferCount == 0U)
3759 {
3760 #if (USE_SPI_CRC != 0U)
3761 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3762 {
3763 /* Enable CRC Transmission */
3764 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3765 }
3766 #endif /* USE_SPI_CRC */
3767 SPI_CloseTx_ISR(hspi);
3768 }
3769 }
3770
3771 /**
3772 * @brief Handle the data 16-bit transmit in Interrupt mode.
3773 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3774 * the configuration information for SPI module.
3775 * @retval None
3776 */
SPI_TxISR_16BIT(struct __SPI_HandleTypeDef * hspi)3777 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3778 {
3779 /* Transmit data in 16 Bit mode */
3780 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3781 hspi->pTxBuffPtr += sizeof(uint16_t);
3782 hspi->TxXferCount--;
3783
3784 if (hspi->TxXferCount == 0U)
3785 {
3786 #if (USE_SPI_CRC != 0U)
3787 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3788 {
3789 /* Enable CRC Transmission */
3790 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3791 }
3792 #endif /* USE_SPI_CRC */
3793 SPI_CloseTx_ISR(hspi);
3794 }
3795 }
3796
3797 /**
3798 * @brief Handle SPI Communication Timeout.
3799 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3800 * the configuration information for SPI module.
3801 * @param Flag SPI flag to check
3802 * @param State flag state to check
3803 * @param Timeout Timeout duration
3804 * @param Tickstart tick start value
3805 * @retval HAL status
3806 */
SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Flag,FlagStatus State,uint32_t Timeout,uint32_t Tickstart)3807 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3808 uint32_t Timeout, uint32_t Tickstart)
3809 {
3810 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3811 {
3812 if (Timeout != HAL_MAX_DELAY)
3813 {
3814 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3815 {
3816 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3817 on both master and slave sides in order to resynchronize the master
3818 and slave for their respective CRC calculation */
3819
3820 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3821 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3822
3823 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3824 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3825 {
3826 /* Disable SPI peripheral */
3827 __HAL_SPI_DISABLE(hspi);
3828 }
3829
3830 /* Reset CRC Calculation */
3831 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3832 {
3833 SPI_RESET_CRC(hspi);
3834 }
3835
3836 hspi->State = HAL_SPI_STATE_READY;
3837
3838 /* Process Unlocked */
3839 __HAL_UNLOCK(hspi);
3840
3841 return HAL_TIMEOUT;
3842 }
3843 }
3844 }
3845
3846 return HAL_OK;
3847 }
3848
3849 /**
3850 * @brief Handle SPI FIFO Communication Timeout.
3851 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3852 * the configuration information for SPI module.
3853 * @param Fifo Fifo to check
3854 * @param State Fifo state to check
3855 * @param Timeout Timeout duration
3856 * @param Tickstart tick start value
3857 * @retval HAL status
3858 */
SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef * hspi,uint32_t Fifo,uint32_t State,uint32_t Timeout,uint32_t Tickstart)3859 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3860 uint32_t Timeout, uint32_t Tickstart)
3861 {
3862 while ((hspi->Instance->SR & Fifo) != State)
3863 {
3864 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
3865 {
3866 /* Read 8bit CRC to flush Data Register */
3867 READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
3868 }
3869
3870 if (Timeout != HAL_MAX_DELAY)
3871 {
3872 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3873 {
3874 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3875 on both master and slave sides in order to resynchronize the master
3876 and slave for their respective CRC calculation */
3877
3878 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3879 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3880
3881 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3882 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3883 {
3884 /* Disable SPI peripheral */
3885 __HAL_SPI_DISABLE(hspi);
3886 }
3887
3888 /* Reset CRC Calculation */
3889 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3890 {
3891 SPI_RESET_CRC(hspi);
3892 }
3893
3894 hspi->State = HAL_SPI_STATE_READY;
3895
3896 /* Process Unlocked */
3897 __HAL_UNLOCK(hspi);
3898
3899 return HAL_TIMEOUT;
3900 }
3901 }
3902 }
3903
3904 return HAL_OK;
3905 }
3906
3907 /**
3908 * @brief Handle the check of the RX transaction complete.
3909 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3910 * the configuration information for SPI module.
3911 * @param Timeout Timeout duration
3912 * @param Tickstart tick start value
3913 * @retval HAL status
3914 */
SPI_EndRxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3915 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3916 {
3917 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3918 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3919 {
3920 /* Disable SPI peripheral */
3921 __HAL_SPI_DISABLE(hspi);
3922 }
3923
3924 /* Control the BSY flag */
3925 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3926 {
3927 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3928 return HAL_TIMEOUT;
3929 }
3930
3931 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3932 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3933 {
3934 /* Empty the FRLVL fifo */
3935 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3936 {
3937 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3938 return HAL_TIMEOUT;
3939 }
3940 }
3941 return HAL_OK;
3942 }
3943
3944 /**
3945 * @brief Handle the check of the RXTX or TX transaction complete.
3946 * @param hspi SPI handle
3947 * @param Timeout Timeout duration
3948 * @param Tickstart tick start value
3949 * @retval HAL status
3950 */
SPI_EndRxTxTransaction(SPI_HandleTypeDef * hspi,uint32_t Timeout,uint32_t Tickstart)3951 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3952 {
3953 /* Control if the TX fifo is empty */
3954 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3955 {
3956 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3957 return HAL_TIMEOUT;
3958 }
3959
3960 /* Control the BSY flag */
3961 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3962 {
3963 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3964 return HAL_TIMEOUT;
3965 }
3966
3967 /* Control if the RX fifo is empty */
3968 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3969 {
3970 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3971 return HAL_TIMEOUT;
3972 }
3973
3974 return HAL_OK;
3975 }
3976
3977 /**
3978 * @brief Handle the end of the RXTX transaction.
3979 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3980 * the configuration information for SPI module.
3981 * @retval None
3982 */
SPI_CloseRxTx_ISR(SPI_HandleTypeDef * hspi)3983 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
3984 {
3985 uint32_t tickstart;
3986
3987 /* Init tickstart for timeout managment*/
3988 tickstart = HAL_GetTick();
3989
3990 /* Disable ERR interrupt */
3991 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3992
3993 /* Check the end of the transaction */
3994 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3995 {
3996 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3997 }
3998
3999 #if (USE_SPI_CRC != 0U)
4000 /* Check if CRC error occurred */
4001 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4002 {
4003 hspi->State = HAL_SPI_STATE_READY;
4004 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4005 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4006 /* Call user error callback */
4007 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4008 hspi->ErrorCallback(hspi);
4009 #else
4010 HAL_SPI_ErrorCallback(hspi);
4011 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4012 }
4013 else
4014 {
4015 #endif /* USE_SPI_CRC */
4016 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4017 {
4018 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4019 {
4020 hspi->State = HAL_SPI_STATE_READY;
4021 /* Call user Rx complete callback */
4022 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4023 hspi->RxCpltCallback(hspi);
4024 #else
4025 HAL_SPI_RxCpltCallback(hspi);
4026 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4027 }
4028 else
4029 {
4030 hspi->State = HAL_SPI_STATE_READY;
4031 /* Call user TxRx complete callback */
4032 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4033 hspi->TxRxCpltCallback(hspi);
4034 #else
4035 HAL_SPI_TxRxCpltCallback(hspi);
4036 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4037 }
4038 }
4039 else
4040 {
4041 hspi->State = HAL_SPI_STATE_READY;
4042 /* Call user error callback */
4043 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4044 hspi->ErrorCallback(hspi);
4045 #else
4046 HAL_SPI_ErrorCallback(hspi);
4047 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4048 }
4049 #if (USE_SPI_CRC != 0U)
4050 }
4051 #endif /* USE_SPI_CRC */
4052 }
4053
4054 /**
4055 * @brief Handle the end of the RX transaction.
4056 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4057 * the configuration information for SPI module.
4058 * @retval None
4059 */
SPI_CloseRx_ISR(SPI_HandleTypeDef * hspi)4060 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4061 {
4062 /* Disable RXNE and ERR interrupt */
4063 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4064
4065 /* Check the end of the transaction */
4066 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4067 {
4068 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4069 }
4070 hspi->State = HAL_SPI_STATE_READY;
4071
4072 #if (USE_SPI_CRC != 0U)
4073 /* Check if CRC error occurred */
4074 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4075 {
4076 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4077 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4078 /* Call user error callback */
4079 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4080 hspi->ErrorCallback(hspi);
4081 #else
4082 HAL_SPI_ErrorCallback(hspi);
4083 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4084 }
4085 else
4086 {
4087 #endif /* USE_SPI_CRC */
4088 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4089 {
4090 /* Call user Rx complete callback */
4091 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4092 hspi->RxCpltCallback(hspi);
4093 #else
4094 HAL_SPI_RxCpltCallback(hspi);
4095 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4096 }
4097 else
4098 {
4099 /* Call user error callback */
4100 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4101 hspi->ErrorCallback(hspi);
4102 #else
4103 HAL_SPI_ErrorCallback(hspi);
4104 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4105 }
4106 #if (USE_SPI_CRC != 0U)
4107 }
4108 #endif /* USE_SPI_CRC */
4109 }
4110
4111 /**
4112 * @brief Handle the end of the TX transaction.
4113 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4114 * the configuration information for SPI module.
4115 * @retval None
4116 */
SPI_CloseTx_ISR(SPI_HandleTypeDef * hspi)4117 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4118 {
4119 uint32_t tickstart;
4120
4121 /* Init tickstart for timeout management*/
4122 tickstart = HAL_GetTick();
4123
4124 /* Disable TXE and ERR interrupt */
4125 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4126
4127 /* Check the end of the transaction */
4128 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4129 {
4130 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4131 }
4132
4133 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4134 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4135 {
4136 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4137 }
4138
4139 hspi->State = HAL_SPI_STATE_READY;
4140 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4141 {
4142 /* Call user error callback */
4143 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4144 hspi->ErrorCallback(hspi);
4145 #else
4146 HAL_SPI_ErrorCallback(hspi);
4147 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4148 }
4149 else
4150 {
4151 /* Call user Rx complete callback */
4152 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4153 hspi->TxCpltCallback(hspi);
4154 #else
4155 HAL_SPI_TxCpltCallback(hspi);
4156 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4157 }
4158 }
4159
4160 /**
4161 * @brief Handle abort a Rx transaction.
4162 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4163 * the configuration information for SPI module.
4164 * @retval None
4165 */
SPI_AbortRx_ISR(SPI_HandleTypeDef * hspi)4166 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4167 {
4168 __IO uint32_t count;
4169
4170 /* Disable SPI Peripheral */
4171 __HAL_SPI_DISABLE(hspi);
4172
4173 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4174
4175 /* Disable RXNEIE interrupt */
4176 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4177
4178 /* Check RXNEIE is disabled */
4179 do
4180 {
4181 if (count == 0U)
4182 {
4183 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4184 break;
4185 }
4186 count--;
4187 }
4188 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4189
4190 /* Control the BSY flag */
4191 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4192 {
4193 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4194 }
4195
4196 /* Empty the FRLVL fifo */
4197 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4198 {
4199 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4200 }
4201
4202 hspi->State = HAL_SPI_STATE_ABORT;
4203 }
4204
4205 /**
4206 * @brief Handle abort a Tx or Rx/Tx transaction.
4207 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4208 * the configuration information for SPI module.
4209 * @retval None
4210 */
SPI_AbortTx_ISR(SPI_HandleTypeDef * hspi)4211 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4212 {
4213 __IO uint32_t count;
4214
4215 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4216
4217 /* Disable TXEIE interrupt */
4218 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4219
4220 /* Check TXEIE is disabled */
4221 do
4222 {
4223 if (count == 0U)
4224 {
4225 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4226 break;
4227 }
4228 count--;
4229 }
4230 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4231
4232 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4233 {
4234 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4235 }
4236
4237 /* Disable SPI Peripheral */
4238 __HAL_SPI_DISABLE(hspi);
4239
4240 /* Empty the FRLVL fifo */
4241 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4242 {
4243 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4244 }
4245
4246 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4247 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4248 {
4249 /* Disable RXNEIE interrupt */
4250 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4251
4252 /* Check RXNEIE is disabled */
4253 do
4254 {
4255 if (count == 0U)
4256 {
4257 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4258 break;
4259 }
4260 count--;
4261 }
4262 while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4263
4264 /* Control the BSY flag */
4265 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4266 {
4267 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4268 }
4269
4270 /* Empty the FRLVL fifo */
4271 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4272 {
4273 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4274 }
4275 }
4276 hspi->State = HAL_SPI_STATE_ABORT;
4277 }
4278
4279 /**
4280 * @}
4281 */
4282
4283 #endif /* HAL_SPI_MODULE_ENABLED */
4284
4285 /**
4286 * @}
4287 */
4288
4289 /**
4290 * @}
4291 */
4292
4293 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4294