1 /**************************************************************************//**
2 * @file core_cm0plus.h
3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4 * @version V4.00
5 * @date 22. August 2014
6 *
7 * @note
8 *
9 ******************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38 #if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41
42 #ifndef __CORE_CM0PLUS_H_GENERIC
43 #define __CORE_CM0PLUS_H_GENERIC
44
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63 /*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66 /** \ingroup Cortex-M0+
67 @{
68 */
69
70 /* CMSIS CM0P definitions */
71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
75
76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
77
78
79 #if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84 #elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89 #elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94 #elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98 #elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103 #elif defined ( __CSMC__ )
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109 #endif
110
111 /** __FPU_USED indicates whether an FPU is used or not.
112 This core does not support an FPU at all
113 */
114 #define __FPU_USED 0
115
116 #if defined ( __CC_ARM )
117 #if defined __TARGET_FPU_VFP
118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119 #endif
120
121 #elif defined ( __GNUC__ )
122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124 #endif
125
126 #elif defined ( __ICCARM__ )
127 #if defined __ARMVFP__
128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129 #endif
130
131 #elif defined ( __TMS470__ )
132 #if defined __TI__VFP_SUPPORT____
133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134 #endif
135
136 #elif defined ( __TASKING__ )
137 #if defined __FPU_VFP__
138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139 #endif
140
141 #elif defined ( __CSMC__ ) /* Cosmic */
142 #if ( __CSMC__ & 0x400) // FPU present for parser
143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #endif
145 #endif
146
147 #include <stdint.h> /* standard types definitions */
148 #include <core_cmInstr.h> /* Core Instruction Access */
149 #include <core_cmFunc.h> /* Core Function Access */
150
151 #ifdef __cplusplus
152 }
153 #endif
154
155 #endif /* __CORE_CM0PLUS_H_GENERIC */
156
157 #ifndef __CMSIS_GENERIC
158
159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
160 #define __CORE_CM0PLUS_H_DEPENDANT
161
162 #ifdef __cplusplus
163 extern "C" {
164 #endif
165
166 /* check device defines and use defaults */
167 #if defined __CHECK_DEVICE_DEFINES
168 #ifndef __CM0PLUS_REV
169 #define __CM0PLUS_REV 0x0000
170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
171 #endif
172
173 #ifndef __MPU_PRESENT
174 #define __MPU_PRESENT 0
175 #warning "__MPU_PRESENT not defined in device header file; using default!"
176 #endif
177
178 #ifndef __VTOR_PRESENT
179 #define __VTOR_PRESENT 0
180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
181 #endif
182
183 #ifndef __NVIC_PRIO_BITS
184 #define __NVIC_PRIO_BITS 2
185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
186 #endif
187
188 #ifndef __Vendor_SysTickConfig
189 #define __Vendor_SysTickConfig 0
190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
191 #endif
192 #endif
193
194 /* IO definitions (access restrictions to peripheral registers) */
195 /**
196 \defgroup CMSIS_glob_defs CMSIS Global Defines
197
198 <strong>IO Type Qualifiers</strong> are used
199 \li to specify the access to peripheral variables.
200 \li for automatic generation of peripheral register debug information.
201 */
202 #ifdef __cplusplus
203 #define __I volatile /*!< Defines 'read only' permissions */
204 #else
205 #define __I volatile const /*!< Defines 'read only' permissions */
206 #endif
207 #define __O volatile /*!< Defines 'write only' permissions */
208 #define __IO volatile /*!< Defines 'read / write' permissions */
209
210 /*@} end of group Cortex-M0+ */
211
212
213
214 /*******************************************************************************
215 * Register Abstraction
216 Core Register contain:
217 - Core Register
218 - Core NVIC Register
219 - Core SCB Register
220 - Core SysTick Register
221 - Core MPU Register
222 ******************************************************************************/
223 /** \defgroup CMSIS_core_register Defines and Type Definitions
224 \brief Type definitions and defines for Cortex-M processor based devices.
225 */
226
227 /** \ingroup CMSIS_core_register
228 \defgroup CMSIS_CORE Status and Control Registers
229 \brief Core Register type definitions.
230 @{
231 */
232
233 /** \brief Union type to access the Application Program Status Register (APSR).
234 */
235 typedef union
236 {
237 struct
238 {
239 #if (__CORTEX_M != 0x04)
240 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
241 #else
242 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
243 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
244 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
245 #endif
246 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
247 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
248 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
249 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
250 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
251 } b; /*!< Structure used for bit access */
252 uint32_t w; /*!< Type used for word access */
253 } APSR_Type;
254
255
256 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
257 */
258 typedef union
259 {
260 struct
261 {
262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
263 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
264 } b; /*!< Structure used for bit access */
265 uint32_t w; /*!< Type used for word access */
266 } IPSR_Type;
267
268
269 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
270 */
271 typedef union
272 {
273 struct
274 {
275 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
276 #if (__CORTEX_M != 0x04)
277 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
278 #else
279 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
280 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
281 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
282 #endif
283 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
284 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
285 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
290 } b; /*!< Structure used for bit access */
291 uint32_t w; /*!< Type used for word access */
292 } xPSR_Type;
293
294
295 /** \brief Union type to access the Control Registers (CONTROL).
296 */
297 typedef union
298 {
299 struct
300 {
301 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
303 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
304 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
305 } b; /*!< Structure used for bit access */
306 uint32_t w; /*!< Type used for word access */
307 } CONTROL_Type;
308
309 /*@} end of group CMSIS_CORE */
310
311
312 /** \ingroup CMSIS_core_register
313 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
314 \brief Type definitions for the NVIC Registers
315 @{
316 */
317
318 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
319 */
320 typedef struct
321 {
322 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
323 uint32_t RESERVED0[31];
324 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
325 uint32_t RSERVED1[31];
326 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
327 uint32_t RESERVED2[31];
328 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
329 uint32_t RESERVED3[31];
330 uint32_t RESERVED4[64];
331 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
332 } NVIC_Type;
333
334 /*@} end of group CMSIS_NVIC */
335
336
337 /** \ingroup CMSIS_core_register
338 \defgroup CMSIS_SCB System Control Block (SCB)
339 \brief Type definitions for the System Control Block Registers
340 @{
341 */
342
343 /** \brief Structure type to access the System Control Block (SCB).
344 */
345 typedef struct
346 {
347 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
348 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
349 #if (__VTOR_PRESENT == 1)
350 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
351 #else
352 uint32_t RESERVED0;
353 #endif
354 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
355 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
356 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
357 uint32_t RESERVED1;
358 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
359 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
360 } SCB_Type;
361
362 /* SCB CPUID Register Definitions */
363 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
365
366 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
368
369 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
371
372 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
374
375 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
376 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
377
378 /* SCB Interrupt Control State Register Definitions */
379 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
381
382 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
384
385 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
387
388 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
390
391 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
393
394 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
396
397 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
399
400 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
402
403 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
405
406 #if (__VTOR_PRESENT == 1)
407 /* SCB Interrupt Control State Register Definitions */
408 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
409 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
410 #endif
411
412 /* SCB Application Interrupt and Reset Control Register Definitions */
413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
415
416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
418
419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
421
422 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
423 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
424
425 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
426 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
427
428 /* SCB System Control Register Definitions */
429 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
430 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
431
432 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
433 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
434
435 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
436 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
437
438 /* SCB Configuration Control Register Definitions */
439 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
440 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
441
442 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
443 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
444
445 /* SCB System Handler Control and State Register Definitions */
446 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
447 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
448
449 /*@} end of group CMSIS_SCB */
450
451
452 /** \ingroup CMSIS_core_register
453 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
454 \brief Type definitions for the System Timer Registers.
455 @{
456 */
457
458 /** \brief Structure type to access the System Timer (SysTick).
459 */
460 typedef struct
461 {
462 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
463 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
464 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
465 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
466 } SysTick_Type;
467
468 /* SysTick Control / Status Register Definitions */
469 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
470 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
471
472 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
473 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
474
475 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
476 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
477
478 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
479 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
480
481 /* SysTick Reload Register Definitions */
482 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
483 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
484
485 /* SysTick Current Register Definitions */
486 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
487 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
488
489 /* SysTick Calibration Register Definitions */
490 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
491 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
492
493 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
494 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
495
496 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
497 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
498
499 /*@} end of group CMSIS_SysTick */
500
501 #if (__MPU_PRESENT == 1)
502 /** \ingroup CMSIS_core_register
503 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
504 \brief Type definitions for the Memory Protection Unit (MPU)
505 @{
506 */
507
508 /** \brief Structure type to access the Memory Protection Unit (MPU).
509 */
510 typedef struct
511 {
512 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
513 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
514 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
515 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
516 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
517 } MPU_Type;
518
519 /* MPU Type Register */
520 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
521 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
522
523 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
524 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
525
526 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
527 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
528
529 /* MPU Control Register */
530 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
531 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
532
533 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
534 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
535
536 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
537 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
538
539 /* MPU Region Number Register */
540 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
541 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
542
543 /* MPU Region Base Address Register */
544 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
545 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
546
547 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
548 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
549
550 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
551 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
552
553 /* MPU Region Attribute and Size Register */
554 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
555 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
556
557 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
558 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
559
560 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
561 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
562
563 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
564 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
565
566 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
567 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
568
569 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
570 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
571
572 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
573 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
574
575 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
576 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
577
578 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
579 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
580
581 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
582 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
583
584 /*@} end of group CMSIS_MPU */
585 #endif
586
587
588 /** \ingroup CMSIS_core_register
589 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
590 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
591 are only accessible over DAP and not via processor. Therefore
592 they are not covered by the Cortex-M0 header file.
593 @{
594 */
595 /*@} end of group CMSIS_CoreDebug */
596
597
598 /** \ingroup CMSIS_core_register
599 \defgroup CMSIS_core_base Core Definitions
600 \brief Definitions for base addresses, unions, and structures.
601 @{
602 */
603
604 /* Memory mapping of Cortex-M0+ Hardware */
605 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
606 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
607 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
608 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
609
610 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
611 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
612 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
613
614 #if (__MPU_PRESENT == 1)
615 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
616 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
617 #endif
618
619 /*@} */
620
621
622
623 /*******************************************************************************
624 * Hardware Abstraction Layer
625 Core Function Interface contains:
626 - Core NVIC Functions
627 - Core SysTick Functions
628 - Core Register Access Functions
629 ******************************************************************************/
630 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
631 */
632
633
634
635 /* ########################## NVIC functions #################################### */
636 /** \ingroup CMSIS_Core_FunctionInterface
637 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
638 \brief Functions that manage interrupts and exceptions via the NVIC.
639 @{
640 */
641
642 /* Interrupt Priorities are WORD accessible only under ARMv6M */
643 /* The following MACROS handle generation of the register offset and byte masks */
644 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
645 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
646 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
647
648
649 /** \brief Enable External Interrupt
650
651 The function enables a device-specific interrupt in the NVIC interrupt controller.
652
653 \param [in] IRQn External interrupt number. Value cannot be negative.
654 */
NVIC_EnableIRQ(IRQn_Type IRQn)655 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
656 {
657 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
658 }
659
660
661 /** \brief Disable External Interrupt
662
663 The function disables a device-specific interrupt in the NVIC interrupt controller.
664
665 \param [in] IRQn External interrupt number. Value cannot be negative.
666 */
NVIC_DisableIRQ(IRQn_Type IRQn)667 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
668 {
669 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
670 }
671
672
673 /** \brief Get Pending Interrupt
674
675 The function reads the pending register in the NVIC and returns the pending bit
676 for the specified interrupt.
677
678 \param [in] IRQn Interrupt number.
679
680 \return 0 Interrupt status is not pending.
681 \return 1 Interrupt status is pending.
682 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)683 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
684 {
685 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
686 }
687
688
689 /** \brief Set Pending Interrupt
690
691 The function sets the pending bit of an external interrupt.
692
693 \param [in] IRQn Interrupt number. Value cannot be negative.
694 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)695 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
696 {
697 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
698 }
699
700
701 /** \brief Clear Pending Interrupt
702
703 The function clears the pending bit of an external interrupt.
704
705 \param [in] IRQn External interrupt number. Value cannot be negative.
706 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)707 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
708 {
709 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
710 }
711
712
713 /** \brief Set Interrupt Priority
714
715 The function sets the priority of an interrupt.
716
717 \note The priority cannot be set for every core interrupt.
718
719 \param [in] IRQn Interrupt number.
720 \param [in] priority Priority to set.
721 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)722 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
723 {
724 if(IRQn < 0) {
725 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
726 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
727 else {
728 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
729 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
730 }
731
732
733 /** \brief Get Interrupt Priority
734
735 The function reads the priority of an interrupt. The interrupt
736 number can be positive to specify an external (device specific)
737 interrupt, or negative to specify an internal (core) interrupt.
738
739
740 \param [in] IRQn Interrupt number.
741 \return Interrupt Priority. Value is aligned automatically to the implemented
742 priority bits of the microcontroller.
743 */
NVIC_GetPriority(IRQn_Type IRQn)744 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
745 {
746
747 if(IRQn < 0) {
748 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
749 else {
750 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
751 }
752
753
754 /** \brief System Reset
755
756 The function initiates a system reset request to reset the MCU.
757 */
NVIC_SystemReset(void)758 __STATIC_INLINE void NVIC_SystemReset(void)
759 {
760 __DSB(); /* Ensure all outstanding memory accesses included
761 buffered write are completed before reset */
762 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
763 SCB_AIRCR_SYSRESETREQ_Msk);
764 __DSB(); /* Ensure completion of memory access */
765 while(1); /* wait until reset */
766 }
767
768 /*@} end of CMSIS_Core_NVICFunctions */
769
770
771
772 /* ################################## SysTick function ############################################ */
773 /** \ingroup CMSIS_Core_FunctionInterface
774 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
775 \brief Functions that configure the System.
776 @{
777 */
778
779 #if (__Vendor_SysTickConfig == 0)
780
781 /** \brief System Tick Configuration
782
783 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
784 Counter is in free running mode to generate periodic interrupts.
785
786 \param [in] ticks Number of ticks between two interrupts.
787
788 \return 0 Function succeeded.
789 \return 1 Function failed.
790
791 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
792 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
793 must contain a vendor-specific implementation of this function.
794
795 */
SysTick_Config(uint32_t ticks)796 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
797 {
798 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
799
800 SysTick->LOAD = ticks - 1; /* set reload register */
801 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
802 SysTick->VAL = 0; /* Load the SysTick Counter Value */
803 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
804 SysTick_CTRL_TICKINT_Msk |
805 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
806 return (0); /* Function successful */
807 }
808
809 #endif
810
811 /*@} end of CMSIS_Core_SysTickFunctions */
812
813
814
815
816 #ifdef __cplusplus
817 }
818 #endif
819
820 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
821
822 #endif /* __CMSIS_GENERIC */
823