1 /**************************************************************************//**
2 * @file core_cm3.h
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4 * @version V4.00
5 * @date 22. August 2014
6 *
7 * @note
8 *
9 ******************************************************************************/
10 /* Copyright (c) 2009 - 2014 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38 #if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41
42 #ifndef __CORE_CM3_H_GENERIC
43 #define __CORE_CM3_H_GENERIC
44
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63 /*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66 /** \ingroup Cortex_M3
67 @{
68 */
69
70 /* CMSIS CM3 definitions */
71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
77
78
79 #if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84 #elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89 #elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94 #elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98 #elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103 #elif defined ( __CSMC__ )
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109 #endif
110
111 /** __FPU_USED indicates whether an FPU is used or not.
112 This core does not support an FPU at all
113 */
114 #define __FPU_USED 0
115
116 #if defined ( __CC_ARM )
117 #if defined __TARGET_FPU_VFP
118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119 #endif
120
121 #elif defined ( __GNUC__ )
122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124 #endif
125
126 #elif defined ( __ICCARM__ )
127 #if defined __ARMVFP__
128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129 #endif
130
131 #elif defined ( __TMS470__ )
132 #if defined __TI__VFP_SUPPORT____
133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134 #endif
135
136 #elif defined ( __TASKING__ )
137 #if defined __FPU_VFP__
138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139 #endif
140
141 #elif defined ( __CSMC__ ) /* Cosmic */
142 #if ( __CSMC__ & 0x400) // FPU present for parser
143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #endif
145 #endif
146
147 #include <stdint.h> /* standard types definitions */
148 #include <core_cmInstr.h> /* Core Instruction Access */
149 #include <core_cmFunc.h> /* Core Function Access */
150
151 #ifdef __cplusplus
152 }
153 #endif
154
155 #endif /* __CORE_CM3_H_GENERIC */
156
157 #ifndef __CMSIS_GENERIC
158
159 #ifndef __CORE_CM3_H_DEPENDANT
160 #define __CORE_CM3_H_DEPENDANT
161
162 #ifdef __cplusplus
163 extern "C" {
164 #endif
165
166 /* check device defines and use defaults */
167 #if defined __CHECK_DEVICE_DEFINES
168 #ifndef __CM3_REV
169 #define __CM3_REV 0x0200
170 #warning "__CM3_REV not defined in device header file; using default!"
171 #endif
172
173 #ifndef __MPU_PRESENT
174 #define __MPU_PRESENT 0
175 #warning "__MPU_PRESENT not defined in device header file; using default!"
176 #endif
177
178 #ifndef __NVIC_PRIO_BITS
179 #define __NVIC_PRIO_BITS 4
180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
181 #endif
182
183 #ifndef __Vendor_SysTickConfig
184 #define __Vendor_SysTickConfig 0
185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
186 #endif
187 #endif
188
189 /* IO definitions (access restrictions to peripheral registers) */
190 /**
191 \defgroup CMSIS_glob_defs CMSIS Global Defines
192
193 <strong>IO Type Qualifiers</strong> are used
194 \li to specify the access to peripheral variables.
195 \li for automatic generation of peripheral register debug information.
196 */
197 #ifdef __cplusplus
198 #define __I volatile /*!< Defines 'read only' permissions */
199 #else
200 #define __I volatile const /*!< Defines 'read only' permissions */
201 #endif
202 #define __O volatile /*!< Defines 'write only' permissions */
203 #define __IO volatile /*!< Defines 'read / write' permissions */
204
205 /*@} end of group Cortex_M3 */
206
207
208
209 /*******************************************************************************
210 * Register Abstraction
211 Core Register contain:
212 - Core Register
213 - Core NVIC Register
214 - Core SCB Register
215 - Core SysTick Register
216 - Core Debug Register
217 - Core MPU Register
218 ******************************************************************************/
219 /** \defgroup CMSIS_core_register Defines and Type Definitions
220 \brief Type definitions and defines for Cortex-M processor based devices.
221 */
222
223 /** \ingroup CMSIS_core_register
224 \defgroup CMSIS_CORE Status and Control Registers
225 \brief Core Register type definitions.
226 @{
227 */
228
229 /** \brief Union type to access the Application Program Status Register (APSR).
230 */
231 typedef union
232 {
233 struct
234 {
235 #if (__CORTEX_M != 0x04)
236 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
237 #else
238 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
239 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
240 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
241 #endif
242 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
243 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
244 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
245 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
246 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
247 } b; /*!< Structure used for bit access */
248 uint32_t w; /*!< Type used for word access */
249 } APSR_Type;
250
251
252 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
253 */
254 typedef union
255 {
256 struct
257 {
258 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
259 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
260 } b; /*!< Structure used for bit access */
261 uint32_t w; /*!< Type used for word access */
262 } IPSR_Type;
263
264
265 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
266 */
267 typedef union
268 {
269 struct
270 {
271 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
272 #if (__CORTEX_M != 0x04)
273 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
274 #else
275 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
276 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
277 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
278 #endif
279 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
280 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
281 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
282 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
283 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
284 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
285 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
286 } b; /*!< Structure used for bit access */
287 uint32_t w; /*!< Type used for word access */
288 } xPSR_Type;
289
290
291 /** \brief Union type to access the Control Registers (CONTROL).
292 */
293 typedef union
294 {
295 struct
296 {
297 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
298 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
299 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
300 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
301 } b; /*!< Structure used for bit access */
302 uint32_t w; /*!< Type used for word access */
303 } CONTROL_Type;
304
305 /*@} end of group CMSIS_CORE */
306
307
308 /** \ingroup CMSIS_core_register
309 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
310 \brief Type definitions for the NVIC Registers
311 @{
312 */
313
314 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
315 */
316 typedef struct
317 {
318 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
319 uint32_t RESERVED0[24];
320 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
321 uint32_t RSERVED1[24];
322 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
323 uint32_t RESERVED2[24];
324 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
325 uint32_t RESERVED3[24];
326 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
327 uint32_t RESERVED4[56];
328 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
329 uint32_t RESERVED5[644];
330 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
331 } NVIC_Type;
332
333 /* Software Triggered Interrupt Register Definitions */
334 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
335 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
336
337 /*@} end of group CMSIS_NVIC */
338
339
340 /** \ingroup CMSIS_core_register
341 \defgroup CMSIS_SCB System Control Block (SCB)
342 \brief Type definitions for the System Control Block Registers
343 @{
344 */
345
346 /** \brief Structure type to access the System Control Block (SCB).
347 */
348 typedef struct
349 {
350 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
351 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
352 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
353 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
354 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
355 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
356 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
357 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
358 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
359 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
360 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
361 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
362 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
363 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
364 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
365 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
366 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
367 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
368 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
369 uint32_t RESERVED0[5];
370 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
371 } SCB_Type;
372
373 /* SCB CPUID Register Definitions */
374 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
375 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
376
377 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
378 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
379
380 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
381 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
382
383 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
384 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
385
386 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
387 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
388
389 /* SCB Interrupt Control State Register Definitions */
390 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
391 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
392
393 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
394 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
395
396 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
397 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
398
399 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
400 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
401
402 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
403 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
404
405 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
406 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
407
408 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
409 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
410
411 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
412 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
413
414 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
415 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
416
417 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
418 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
419
420 /* SCB Vector Table Offset Register Definitions */
421 #if (__CM3_REV < 0x0201) /* core r2p1 */
422 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
423 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
424
425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
426 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
427 #else
428 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
429 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
430 #endif
431
432 /* SCB Application Interrupt and Reset Control Register Definitions */
433 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
434 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
435
436 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
437 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
438
439 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
440 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
441
442 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
443 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
444
445 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
446 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
447
448 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
449 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
450
451 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
452 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
453
454 /* SCB System Control Register Definitions */
455 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
456 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
457
458 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
459 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
460
461 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
462 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
463
464 /* SCB Configuration Control Register Definitions */
465 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
466 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
467
468 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
469 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
470
471 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
472 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
473
474 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
475 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
476
477 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
478 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
479
480 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
481 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
482
483 /* SCB System Handler Control and State Register Definitions */
484 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
485 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
486
487 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
488 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
489
490 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
491 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
492
493 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
494 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
495
496 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
497 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
498
499 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
500 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
501
502 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
503 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
504
505 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
506 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
507
508 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
509 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
510
511 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
512 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
513
514 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
515 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
516
517 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
518 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
519
520 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
521 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
522
523 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
524 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
525
526 /* SCB Configurable Fault Status Registers Definitions */
527 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
528 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
529
530 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
531 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
532
533 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
534 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
535
536 /* SCB Hard Fault Status Registers Definitions */
537 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
538 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
539
540 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
541 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
542
543 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
544 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
545
546 /* SCB Debug Fault Status Register Definitions */
547 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
548 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
549
550 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
551 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
552
553 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
554 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
555
556 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
557 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
558
559 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
560 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
561
562 /*@} end of group CMSIS_SCB */
563
564
565 /** \ingroup CMSIS_core_register
566 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
567 \brief Type definitions for the System Control and ID Register not in the SCB
568 @{
569 */
570
571 /** \brief Structure type to access the System Control and ID Register not in the SCB.
572 */
573 typedef struct
574 {
575 uint32_t RESERVED0[1];
576 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
577 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
578 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
579 #else
580 uint32_t RESERVED1[1];
581 #endif
582 } SCnSCB_Type;
583
584 /* Interrupt Controller Type Register Definitions */
585 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
586 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
587
588 /* Auxiliary Control Register Definitions */
589
590 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
591 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
592
593 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
594 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
595
596 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
597 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
598
599 /*@} end of group CMSIS_SCnotSCB */
600
601
602 /** \ingroup CMSIS_core_register
603 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
604 \brief Type definitions for the System Timer Registers.
605 @{
606 */
607
608 /** \brief Structure type to access the System Timer (SysTick).
609 */
610 typedef struct
611 {
612 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
613 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
614 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
615 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
616 } SysTick_Type;
617
618 /* SysTick Control / Status Register Definitions */
619 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
620 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
621
622 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
623 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
624
625 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
626 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
627
628 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
629 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
630
631 /* SysTick Reload Register Definitions */
632 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
633 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
634
635 /* SysTick Current Register Definitions */
636 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
637 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
638
639 /* SysTick Calibration Register Definitions */
640 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
641 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
642
643 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
644 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
645
646 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
647 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
648
649 /*@} end of group CMSIS_SysTick */
650
651
652 /** \ingroup CMSIS_core_register
653 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
654 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
655 @{
656 */
657
658 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
659 */
660 typedef struct
661 {
662 __O union
663 {
664 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
665 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
666 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
667 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
668 uint32_t RESERVED0[864];
669 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
670 uint32_t RESERVED1[15];
671 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
672 uint32_t RESERVED2[15];
673 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
674 uint32_t RESERVED3[29];
675 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
676 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
677 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
678 uint32_t RESERVED4[43];
679 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
680 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
681 uint32_t RESERVED5[6];
682 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
683 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
684 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
685 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
686 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
687 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
688 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
689 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
690 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
691 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
692 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
693 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
694 } ITM_Type;
695
696 /* ITM Trace Privilege Register Definitions */
697 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
698 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
699
700 /* ITM Trace Control Register Definitions */
701 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
702 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
703
704 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
705 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
706
707 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
708 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
709
710 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
711 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
712
713 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
714 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
715
716 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
717 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
718
719 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
720 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
721
722 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
723 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
724
725 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
726 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
727
728 /* ITM Integration Write Register Definitions */
729 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
730 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
731
732 /* ITM Integration Read Register Definitions */
733 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
734 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
735
736 /* ITM Integration Mode Control Register Definitions */
737 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
738 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
739
740 /* ITM Lock Status Register Definitions */
741 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
742 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
743
744 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
745 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
746
747 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
748 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
749
750 /*@}*/ /* end of group CMSIS_ITM */
751
752
753 /** \ingroup CMSIS_core_register
754 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
755 \brief Type definitions for the Data Watchpoint and Trace (DWT)
756 @{
757 */
758
759 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
760 */
761 typedef struct
762 {
763 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
764 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
765 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
766 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
767 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
768 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
769 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
770 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
771 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
772 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
773 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
774 uint32_t RESERVED0[1];
775 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
776 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
777 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
778 uint32_t RESERVED1[1];
779 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
780 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
781 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
782 uint32_t RESERVED2[1];
783 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
784 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
785 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
786 } DWT_Type;
787
788 /* DWT Control Register Definitions */
789 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
790 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
791
792 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
793 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
794
795 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
796 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
797
798 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
799 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
800
801 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
802 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
803
804 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
805 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
806
807 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
808 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
809
810 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
811 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
812
813 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
814 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
815
816 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
817 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
818
819 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
820 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
821
822 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
823 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
824
825 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
826 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
827
828 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
829 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
830
831 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
832 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
833
834 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
835 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
836
837 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
838 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
839
840 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
841 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
842
843 /* DWT CPI Count Register Definitions */
844 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
845 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
846
847 /* DWT Exception Overhead Count Register Definitions */
848 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
849 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
850
851 /* DWT Sleep Count Register Definitions */
852 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
853 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
854
855 /* DWT LSU Count Register Definitions */
856 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
857 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
858
859 /* DWT Folded-instruction Count Register Definitions */
860 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
861 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
862
863 /* DWT Comparator Mask Register Definitions */
864 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
865 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
866
867 /* DWT Comparator Function Register Definitions */
868 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
869 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
870
871 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
872 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
873
874 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
875 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
876
877 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
878 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
879
880 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
881 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
882
883 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
884 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
885
886 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
887 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
888
889 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
890 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
891
892 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
893 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
894
895 /*@}*/ /* end of group CMSIS_DWT */
896
897
898 /** \ingroup CMSIS_core_register
899 \defgroup CMSIS_TPI Trace Port Interface (TPI)
900 \brief Type definitions for the Trace Port Interface (TPI)
901 @{
902 */
903
904 /** \brief Structure type to access the Trace Port Interface Register (TPI).
905 */
906 typedef struct
907 {
908 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
909 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
910 uint32_t RESERVED0[2];
911 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
912 uint32_t RESERVED1[55];
913 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
914 uint32_t RESERVED2[131];
915 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
916 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
917 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
918 uint32_t RESERVED3[759];
919 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
920 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
921 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
922 uint32_t RESERVED4[1];
923 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
924 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
925 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
926 uint32_t RESERVED5[39];
927 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
928 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
929 uint32_t RESERVED7[8];
930 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
931 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
932 } TPI_Type;
933
934 /* TPI Asynchronous Clock Prescaler Register Definitions */
935 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
936 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
937
938 /* TPI Selected Pin Protocol Register Definitions */
939 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
940 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
941
942 /* TPI Formatter and Flush Status Register Definitions */
943 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
944 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
945
946 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
947 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
948
949 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
950 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
951
952 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
953 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
954
955 /* TPI Formatter and Flush Control Register Definitions */
956 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
957 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
958
959 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
960 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
961
962 /* TPI TRIGGER Register Definitions */
963 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
964 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
965
966 /* TPI Integration ETM Data Register Definitions (FIFO0) */
967 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
968 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
969
970 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
971 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
972
973 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
974 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
975
976 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
977 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
978
979 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
980 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
981
982 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
983 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
984
985 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
986 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
987
988 /* TPI ITATBCTR2 Register Definitions */
989 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
990 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
991
992 /* TPI Integration ITM Data Register Definitions (FIFO1) */
993 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
994 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
995
996 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
997 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
998
999 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
1000 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1001
1002 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
1003 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1004
1005 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
1006 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1007
1008 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
1009 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1010
1011 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
1012 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
1013
1014 /* TPI ITATBCTR0 Register Definitions */
1015 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
1016 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
1017
1018 /* TPI Integration Mode Control Register Definitions */
1019 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
1020 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
1021
1022 /* TPI DEVID Register Definitions */
1023 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
1024 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1025
1026 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
1027 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1028
1029 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
1030 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1031
1032 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
1033 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1034
1035 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
1036 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1037
1038 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
1039 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
1040
1041 /* TPI DEVTYPE Register Definitions */
1042 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
1043 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
1044
1045 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
1046 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1047
1048 /*@}*/ /* end of group CMSIS_TPI */
1049
1050
1051 #if (__MPU_PRESENT == 1)
1052 /** \ingroup CMSIS_core_register
1053 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1054 \brief Type definitions for the Memory Protection Unit (MPU)
1055 @{
1056 */
1057
1058 /** \brief Structure type to access the Memory Protection Unit (MPU).
1059 */
1060 typedef struct
1061 {
1062 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1063 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1064 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1065 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1066 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1067 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1068 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1069 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1070 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1071 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1072 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1073 } MPU_Type;
1074
1075 /* MPU Type Register */
1076 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1077 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1078
1079 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1080 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1081
1082 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1083 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1084
1085 /* MPU Control Register */
1086 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1087 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1088
1089 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1090 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1091
1092 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1093 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1094
1095 /* MPU Region Number Register */
1096 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1097 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1098
1099 /* MPU Region Base Address Register */
1100 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1101 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1102
1103 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1104 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1105
1106 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1107 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1108
1109 /* MPU Region Attribute and Size Register */
1110 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1111 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1112
1113 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1114 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1115
1116 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1117 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1118
1119 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1120 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1121
1122 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1123 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1124
1125 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1126 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1127
1128 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1129 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1130
1131 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1132 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1133
1134 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1135 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1136
1137 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1138 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1139
1140 /*@} end of group CMSIS_MPU */
1141 #endif
1142
1143
1144 /** \ingroup CMSIS_core_register
1145 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1146 \brief Type definitions for the Core Debug Registers
1147 @{
1148 */
1149
1150 /** \brief Structure type to access the Core Debug Register (CoreDebug).
1151 */
1152 typedef struct
1153 {
1154 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1155 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1156 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1157 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1158 } CoreDebug_Type;
1159
1160 /* Debug Halting Control and Status Register */
1161 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1162 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1163
1164 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1165 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1166
1167 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1168 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1169
1170 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1171 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1172
1173 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1174 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1175
1176 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1177 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1178
1179 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1180 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1181
1182 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1183 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1184
1185 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1186 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1187
1188 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1189 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1190
1191 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1192 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1193
1194 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1195 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1196
1197 /* Debug Core Register Selector Register */
1198 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1199 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1200
1201 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1202 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1203
1204 /* Debug Exception and Monitor Control Register */
1205 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1206 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1207
1208 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1209 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1210
1211 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1212 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1213
1214 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1215 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1216
1217 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1218 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1219
1220 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1221 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1222
1223 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1224 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1225
1226 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1227 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1228
1229 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1230 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1231
1232 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1233 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1234
1235 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1236 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1237
1238 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1239 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1240
1241 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1242 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1243
1244 /*@} end of group CMSIS_CoreDebug */
1245
1246
1247 /** \ingroup CMSIS_core_register
1248 \defgroup CMSIS_core_base Core Definitions
1249 \brief Definitions for base addresses, unions, and structures.
1250 @{
1251 */
1252
1253 /* Memory mapping of Cortex-M3 Hardware */
1254 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1255 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1256 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1257 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1258 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1259 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1260 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1261 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1262
1263 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1264 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1265 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1266 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1267 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1268 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1269 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1270 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1271
1272 #if (__MPU_PRESENT == 1)
1273 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1274 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1275 #endif
1276
1277 /*@} */
1278
1279
1280
1281 /*******************************************************************************
1282 * Hardware Abstraction Layer
1283 Core Function Interface contains:
1284 - Core NVIC Functions
1285 - Core SysTick Functions
1286 - Core Debug Functions
1287 - Core Register Access Functions
1288 ******************************************************************************/
1289 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1290 */
1291
1292
1293
1294 /* ########################## NVIC functions #################################### */
1295 /** \ingroup CMSIS_Core_FunctionInterface
1296 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1297 \brief Functions that manage interrupts and exceptions via the NVIC.
1298 @{
1299 */
1300
1301 /** \brief Set Priority Grouping
1302
1303 The function sets the priority grouping field using the required unlock sequence.
1304 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1305 Only values from 0..7 are used.
1306 In case of a conflict between priority grouping and available
1307 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1308
1309 \param [in] PriorityGroup Priority grouping field.
1310 */
NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1311 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1312 {
1313 uint32_t reg_value;
1314 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1315
1316 reg_value = SCB->AIRCR; /* read old register configuration */
1317 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1318 reg_value = (reg_value |
1319 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1320 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1321 SCB->AIRCR = reg_value;
1322 }
1323
1324
1325 /** \brief Get Priority Grouping
1326
1327 The function reads the priority grouping field from the NVIC Interrupt Controller.
1328
1329 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1330 */
NVIC_GetPriorityGrouping(void)1331 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1332 {
1333 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1334 }
1335
1336
1337 /** \brief Enable External Interrupt
1338
1339 The function enables a device-specific interrupt in the NVIC interrupt controller.
1340
1341 \param [in] IRQn External interrupt number. Value cannot be negative.
1342 */
NVIC_EnableIRQ(IRQn_Type IRQn)1343 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1344 {
1345 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1346 }
1347
1348
1349 /** \brief Disable External Interrupt
1350
1351 The function disables a device-specific interrupt in the NVIC interrupt controller.
1352
1353 \param [in] IRQn External interrupt number. Value cannot be negative.
1354 */
NVIC_DisableIRQ(IRQn_Type IRQn)1355 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1356 {
1357 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1358 }
1359
1360
1361 /** \brief Get Pending Interrupt
1362
1363 The function reads the pending register in the NVIC and returns the pending bit
1364 for the specified interrupt.
1365
1366 \param [in] IRQn Interrupt number.
1367
1368 \return 0 Interrupt status is not pending.
1369 \return 1 Interrupt status is pending.
1370 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)1371 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1372 {
1373 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1374 }
1375
1376
1377 /** \brief Set Pending Interrupt
1378
1379 The function sets the pending bit of an external interrupt.
1380
1381 \param [in] IRQn Interrupt number. Value cannot be negative.
1382 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)1383 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1384 {
1385 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1386 }
1387
1388
1389 /** \brief Clear Pending Interrupt
1390
1391 The function clears the pending bit of an external interrupt.
1392
1393 \param [in] IRQn External interrupt number. Value cannot be negative.
1394 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)1395 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1396 {
1397 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1398 }
1399
1400
1401 /** \brief Get Active Interrupt
1402
1403 The function reads the active register in NVIC and returns the active bit.
1404
1405 \param [in] IRQn Interrupt number.
1406
1407 \return 0 Interrupt status is not active.
1408 \return 1 Interrupt status is active.
1409 */
NVIC_GetActive(IRQn_Type IRQn)1410 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1411 {
1412 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1413 }
1414
1415
1416 /** \brief Set Interrupt Priority
1417
1418 The function sets the priority of an interrupt.
1419
1420 \note The priority cannot be set for every core interrupt.
1421
1422 \param [in] IRQn Interrupt number.
1423 \param [in] priority Priority to set.
1424 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1425 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1426 {
1427 if(IRQn < 0) {
1428 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1429 else {
1430 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1431 }
1432
1433
1434 /** \brief Get Interrupt Priority
1435
1436 The function reads the priority of an interrupt. The interrupt
1437 number can be positive to specify an external (device specific)
1438 interrupt, or negative to specify an internal (core) interrupt.
1439
1440
1441 \param [in] IRQn Interrupt number.
1442 \return Interrupt Priority. Value is aligned automatically to the implemented
1443 priority bits of the microcontroller.
1444 */
NVIC_GetPriority(IRQn_Type IRQn)1445 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1446 {
1447
1448 if(IRQn < 0) {
1449 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1450 else {
1451 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1452 }
1453
1454
1455 /** \brief Encode Priority
1456
1457 The function encodes the priority for an interrupt with the given priority group,
1458 preemptive priority value, and subpriority value.
1459 In case of a conflict between priority grouping and available
1460 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1461
1462 \param [in] PriorityGroup Used priority group.
1463 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1464 \param [in] SubPriority Subpriority value (starting from 0).
1465 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1466 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1467 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1468 {
1469 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1470 uint32_t PreemptPriorityBits;
1471 uint32_t SubPriorityBits;
1472
1473 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1474 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1475
1476 return (
1477 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1478 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1479 );
1480 }
1481
1482
1483 /** \brief Decode Priority
1484
1485 The function decodes an interrupt priority value with a given priority group to
1486 preemptive priority value and subpriority value.
1487 In case of a conflict between priority grouping and available
1488 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1489
1490 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1491 \param [in] PriorityGroup Used priority group.
1492 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1493 \param [out] pSubPriority Subpriority value (starting from 0).
1494 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)1495 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1496 {
1497 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1498 uint32_t PreemptPriorityBits;
1499 uint32_t SubPriorityBits;
1500
1501 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1502 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1503
1504 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1505 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1506 }
1507
1508
1509 /** \brief System Reset
1510
1511 The function initiates a system reset request to reset the MCU.
1512 */
NVIC_SystemReset(void)1513 __STATIC_INLINE void NVIC_SystemReset(void)
1514 {
1515 __DSB(); /* Ensure all outstanding memory accesses included
1516 buffered write are completed before reset */
1517 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1518 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1519 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1520 __DSB(); /* Ensure completion of memory access */
1521 while(1); /* wait until reset */
1522 }
1523
1524 /*@} end of CMSIS_Core_NVICFunctions */
1525
1526
1527
1528 /* ################################## SysTick function ############################################ */
1529 /** \ingroup CMSIS_Core_FunctionInterface
1530 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1531 \brief Functions that configure the System.
1532 @{
1533 */
1534
1535 #if (__Vendor_SysTickConfig == 0)
1536
1537 /** \brief System Tick Configuration
1538
1539 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1540 Counter is in free running mode to generate periodic interrupts.
1541
1542 \param [in] ticks Number of ticks between two interrupts.
1543
1544 \return 0 Function succeeded.
1545 \return 1 Function failed.
1546
1547 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1548 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1549 must contain a vendor-specific implementation of this function.
1550
1551 */
SysTick_Config(uint32_t ticks)1552 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1553 {
1554 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1555
1556 SysTick->LOAD = ticks - 1; /* set reload register */
1557 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1558 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1559 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1560 SysTick_CTRL_TICKINT_Msk |
1561 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1562 return (0); /* Function successful */
1563 }
1564
1565 #endif
1566
1567 /*@} end of CMSIS_Core_SysTickFunctions */
1568
1569
1570
1571 /* ##################################### Debug In/Output function ########################################### */
1572 /** \ingroup CMSIS_Core_FunctionInterface
1573 \defgroup CMSIS_core_DebugFunctions ITM Functions
1574 \brief Functions that access the ITM debug interface.
1575 @{
1576 */
1577
1578 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1579 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1580
1581
1582 /** \brief ITM Send Character
1583
1584 The function transmits a character via the ITM channel 0, and
1585 \li Just returns when no debugger is connected that has booked the output.
1586 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1587
1588 \param [in] ch Character to transmit.
1589
1590 \returns Character to transmit.
1591 */
ITM_SendChar(uint32_t ch)1592 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1593 {
1594 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1595 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1596 {
1597 while (ITM->PORT[0].u32 == 0);
1598 ITM->PORT[0].u8 = (uint8_t) ch;
1599 }
1600 return (ch);
1601 }
1602
1603
1604 /** \brief ITM Receive Character
1605
1606 The function inputs a character via the external variable \ref ITM_RxBuffer.
1607
1608 \return Received character.
1609 \return -1 No character pending.
1610 */
ITM_ReceiveChar(void)1611 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1612 int32_t ch = -1; /* no character available */
1613
1614 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1615 ch = ITM_RxBuffer;
1616 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1617 }
1618
1619 return (ch);
1620 }
1621
1622
1623 /** \brief ITM Check Character
1624
1625 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1626
1627 \return 0 No character available.
1628 \return 1 Character available.
1629 */
ITM_CheckChar(void)1630 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1631
1632 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1633 return (0); /* no character available */
1634 } else {
1635 return (1); /* character available */
1636 }
1637 }
1638
1639 /*@} end of CMSIS_core_DebugFunctions */
1640
1641
1642
1643
1644 #ifdef __cplusplus
1645 }
1646 #endif
1647
1648 #endif /* __CORE_CM3_H_DEPENDANT */
1649
1650 #endif /* __CMSIS_GENERIC */
1651