1 /**************************************************************************//**
2 * @file core_cm3.h
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4 * @version V3.00
5 * @date 03. February 2012
6 *
7 * @note
8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 #ifndef __CORE_CM3_H_GENERIC
32 #define __CORE_CM3_H_GENERIC
33
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35 CMSIS violates the following MISRA-C:2004 rules:
36
37 \li Required Rule 8.5, object/function definition in header file.<br>
38 Function definitions in header files are used to allow 'inlining'.
39
40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41 Unions are used for effective representation of core registers.
42
43 \li Advisory Rule 19.7, Function-like macro defined.<br>
44 Function-like macros are used to allow more efficient code.
45 */
46
47
48 /*******************************************************************************
49 * CMSIS definitions
50 ******************************************************************************/
51 /** \ingroup Cortex_M3
52 @{
53 */
54
55 /* CMSIS CM3 definitions */
56 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
58 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
59 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60
61 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
62
63
64 #if defined ( __CC_ARM )
65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67 #define __STATIC_INLINE static __inline
68
69 #elif defined ( __ICCARM__ )
70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72 #define __STATIC_INLINE static inline
73
74 #elif defined ( __TMS470__ )
75 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
76 #define __STATIC_INLINE static inline
77
78 #elif defined ( __GNUC__ )
79 #define __ASM __asm /*!< asm keyword for GNU Compiler */
80 #define __INLINE inline /*!< inline keyword for GNU Compiler */
81 #define __STATIC_INLINE static inline
82
83 #elif defined ( __TASKING__ )
84 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
85 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
86 #define __STATIC_INLINE static inline
87
88 #endif
89
90 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
91 */
92 #define __FPU_USED 0
93
94 #if defined ( __CC_ARM )
95 #if defined __TARGET_FPU_VFP
96 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
97 #endif
98
99 #elif defined ( __ICCARM__ )
100 #if defined __ARMVFP__
101 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #endif
103
104 #elif defined ( __TMS470__ )
105 #if defined __TI__VFP_SUPPORT____
106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
107 #endif
108
109 #elif defined ( __GNUC__ )
110 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
112 #endif
113
114 #elif defined ( __TASKING__ )
115 /* add preprocessor checks */
116 #endif
117
118 #include <stdint.h> /* standard types definitions */
119 #include <core_cmInstr.h> /* Core Instruction Access */
120 #include <core_cmFunc.h> /* Core Function Access */
121
122 #endif /* __CORE_CM3_H_GENERIC */
123
124 #ifndef __CMSIS_GENERIC
125
126 #ifndef __CORE_CM3_H_DEPENDANT
127 #define __CORE_CM3_H_DEPENDANT
128
129 /* check device defines and use defaults */
130 #if defined __CHECK_DEVICE_DEFINES
131 #ifndef __CM3_REV
132 #define __CM3_REV 0x0200
133 #warning "__CM3_REV not defined in device header file; using default!"
134 #endif
135
136 #ifndef __MPU_PRESENT
137 #define __MPU_PRESENT 0
138 #warning "__MPU_PRESENT not defined in device header file; using default!"
139 #endif
140
141 #ifndef __NVIC_PRIO_BITS
142 #define __NVIC_PRIO_BITS 4
143 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
144 #endif
145
146 #ifndef __Vendor_SysTickConfig
147 #define __Vendor_SysTickConfig 0
148 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
149 #endif
150 #endif
151
152 /* IO definitions (access restrictions to peripheral registers) */
153 /**
154 \defgroup CMSIS_glob_defs CMSIS Global Defines
155
156 <strong>IO Type Qualifiers</strong> are used
157 \li to specify the access to peripheral variables.
158 \li for automatic generation of peripheral register debug information.
159 */
160 #ifdef __cplusplus
161 #define __I volatile /*!< Defines 'read only' permissions */
162 #else
163 #define __I volatile const /*!< Defines 'read only' permissions */
164 #endif
165 #define __O volatile /*!< Defines 'write only' permissions */
166 #define __IO volatile /*!< Defines 'read / write' permissions */
167
168 /*@} end of group Cortex_M3 */
169
170
171
172 /*******************************************************************************
173 * Register Abstraction
174 Core Register contain:
175 - Core Register
176 - Core NVIC Register
177 - Core SCB Register
178 - Core SysTick Register
179 - Core Debug Register
180 - Core MPU Register
181 ******************************************************************************/
182 /** \defgroup CMSIS_core_register Defines and Type Definitions
183 \brief Type definitions and defines for Cortex-M processor based devices.
184 */
185
186 /** \ingroup CMSIS_core_register
187 \defgroup CMSIS_CORE Status and Control Registers
188 \brief Core Register type definitions.
189 @{
190 */
191
192 /** \brief Union type to access the Application Program Status Register (APSR).
193 */
194 typedef union
195 {
196 struct
197 {
198 #if (__CORTEX_M != 0x04)
199 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
200 #else
201 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
202 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
203 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
204 #endif
205 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
206 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
207 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
208 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
209 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
210 } b; /*!< Structure used for bit access */
211 uint32_t w; /*!< Type used for word access */
212 } APSR_Type;
213
214
215 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
216 */
217 typedef union
218 {
219 struct
220 {
221 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
222 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
223 } b; /*!< Structure used for bit access */
224 uint32_t w; /*!< Type used for word access */
225 } IPSR_Type;
226
227
228 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
229 */
230 typedef union
231 {
232 struct
233 {
234 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
235 #if (__CORTEX_M != 0x04)
236 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
237 #else
238 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
239 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
240 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
241 #endif
242 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
243 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
249 } b; /*!< Structure used for bit access */
250 uint32_t w; /*!< Type used for word access */
251 } xPSR_Type;
252
253
254 /** \brief Union type to access the Control Registers (CONTROL).
255 */
256 typedef union
257 {
258 struct
259 {
260 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
261 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
262 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
263 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
264 } b; /*!< Structure used for bit access */
265 uint32_t w; /*!< Type used for word access */
266 } CONTROL_Type;
267
268 /*@} end of group CMSIS_CORE */
269
270
271 /** \ingroup CMSIS_core_register
272 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
273 \brief Type definitions for the NVIC Registers
274 @{
275 */
276
277 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
278 */
279 typedef struct
280 {
281 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
282 uint32_t RESERVED0[24];
283 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
284 uint32_t RSERVED1[24];
285 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
286 uint32_t RESERVED2[24];
287 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
288 uint32_t RESERVED3[24];
289 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
290 uint32_t RESERVED4[56];
291 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
292 uint32_t RESERVED5[644];
293 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
294 } NVIC_Type;
295
296 /* Software Triggered Interrupt Register Definitions */
297 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
298 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
299
300 /*@} end of group CMSIS_NVIC */
301
302
303 /** \ingroup CMSIS_core_register
304 \defgroup CMSIS_SCB System Control Block (SCB)
305 \brief Type definitions for the System Control Block Registers
306 @{
307 */
308
309 /** \brief Structure type to access the System Control Block (SCB).
310 */
311 typedef struct
312 {
313 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
314 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
315 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
316 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
317 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
318 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
319 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
320 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
321 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
322 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
323 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
324 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
325 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
326 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
327 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
328 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
329 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
330 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
331 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
332 uint32_t RESERVED0[5];
333 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
334 } SCB_Type;
335
336 /* SCB CPUID Register Definitions */
337 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
338 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
339
340 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
341 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
342
343 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
344 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
345
346 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
347 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
348
349 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
350 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
351
352 /* SCB Interrupt Control State Register Definitions */
353 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
354 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
355
356 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
357 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
358
359 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
360 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
361
362 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
363 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
364
365 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
366 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
367
368 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
369 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
370
371 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
372 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
373
374 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
375 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
376
377 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
378 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
379
380 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
381 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
382
383 /* SCB Vector Table Offset Register Definitions */
384 #if (__CM3_REV < 0x0201) /* core r2p1 */
385 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
386 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
387
388 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
389 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
390 #else
391 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
392 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
393 #endif
394
395 /* SCB Application Interrupt and Reset Control Register Definitions */
396 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
397 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
398
399 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
400 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
401
402 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
403 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
404
405 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
406 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
407
408 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
410
411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
413
414 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
415 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
416
417 /* SCB System Control Register Definitions */
418 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
419 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
420
421 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
422 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
423
424 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
425 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
426
427 /* SCB Configuration Control Register Definitions */
428 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
429 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
430
431 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
432 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
433
434 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
435 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
436
437 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
438 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
439
440 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
441 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
442
443 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
444 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
445
446 /* SCB System Handler Control and State Register Definitions */
447 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
448 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
449
450 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
451 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
452
453 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
454 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
455
456 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
458
459 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
460 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
461
462 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
463 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
464
465 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
466 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
467
468 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
469 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
470
471 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
472 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
473
474 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
475 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
476
477 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
478 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
479
480 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
481 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
482
483 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
484 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
485
486 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
487 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
488
489 /* SCB Configurable Fault Status Registers Definitions */
490 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
491 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
492
493 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
494 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
495
496 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
497 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
498
499 /* SCB Hard Fault Status Registers Definitions */
500 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
501 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
502
503 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
504 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
505
506 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
507 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
508
509 /* SCB Debug Fault Status Register Definitions */
510 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
511 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
512
513 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
514 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
515
516 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
517 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
518
519 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
520 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
521
522 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
523 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
524
525 /*@} end of group CMSIS_SCB */
526
527
528 /** \ingroup CMSIS_core_register
529 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
530 \brief Type definitions for the System Control and ID Register not in the SCB
531 @{
532 */
533
534 /** \brief Structure type to access the System Control and ID Register not in the SCB.
535 */
536 typedef struct
537 {
538 uint32_t RESERVED0[1];
539 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
540 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
541 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
542 #else
543 uint32_t RESERVED1[1];
544 #endif
545 } SCnSCB_Type;
546
547 /* Interrupt Controller Type Register Definitions */
548 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
549 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
550
551 /* Auxiliary Control Register Definitions */
552
553 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
554 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
555
556 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
557 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
558
559 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
560 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
561
562 /*@} end of group CMSIS_SCnotSCB */
563
564
565 /** \ingroup CMSIS_core_register
566 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
567 \brief Type definitions for the System Timer Registers.
568 @{
569 */
570
571 /** \brief Structure type to access the System Timer (SysTick).
572 */
573 typedef struct
574 {
575 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
576 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
577 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
578 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
579 } SysTick_Type;
580
581 /* SysTick Control / Status Register Definitions */
582 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
583 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
584
585 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
586 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
587
588 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
589 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
590
591 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
592 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
593
594 /* SysTick Reload Register Definitions */
595 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
596 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
597
598 /* SysTick Current Register Definitions */
599 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
600 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
601
602 /* SysTick Calibration Register Definitions */
603 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
604 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
605
606 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
607 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
608
609 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
610 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
611
612 /*@} end of group CMSIS_SysTick */
613
614
615 /** \ingroup CMSIS_core_register
616 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
617 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
618 @{
619 */
620
621 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
622 */
623 typedef struct
624 {
625 __O union
626 {
627 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
628 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
629 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
630 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
631 uint32_t RESERVED0[864];
632 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
633 uint32_t RESERVED1[15];
634 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
635 uint32_t RESERVED2[15];
636 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
637 } ITM_Type;
638
639 /* ITM Trace Privilege Register Definitions */
640 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
641 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
642
643 /* ITM Trace Control Register Definitions */
644 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
645 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
646
647 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
648 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
649
650 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
651 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
652
653 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
654 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
655
656 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
657 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
658
659 #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
660 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
661
662 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
663 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
664
665 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
666 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
667
668 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
669 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
670
671 /*@}*/ /* end of group CMSIS_ITM */
672
673
674 /** \ingroup CMSIS_core_register
675 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
676 \brief Type definitions for the Data Watchpoint and Trace (DWT)
677 @{
678 */
679
680 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
681 */
682 typedef struct
683 {
684 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
685 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
686 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
687 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
688 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
689 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
690 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
691 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
692 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
693 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
694 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
695 uint32_t RESERVED0[1];
696 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
697 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
698 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
699 uint32_t RESERVED1[1];
700 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
701 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
702 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
703 uint32_t RESERVED2[1];
704 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
705 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
706 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
707 } DWT_Type;
708
709 /* DWT Control Register Definitions */
710 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
711 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
712
713 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
714 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
715
716 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
717 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
718
719 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
720 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
721
722 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
723 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
724
725 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
726 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
727
728 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
729 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
730
731 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
732 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
733
734 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
735 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
736
737 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
738 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
739
740 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
741 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
742
743 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
744 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
745
746 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
747 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
748
749 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
750 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
751
752 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
753 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
754
755 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
756 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
757
758 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
759 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
760
761 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
762 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
763
764 /* DWT CPI Count Register Definitions */
765 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
766 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
767
768 /* DWT Exception Overhead Count Register Definitions */
769 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
770 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
771
772 /* DWT Sleep Count Register Definitions */
773 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
774 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
775
776 /* DWT LSU Count Register Definitions */
777 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
778 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
779
780 /* DWT Folded-instruction Count Register Definitions */
781 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
782 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
783
784 /* DWT Comparator Mask Register Definitions */
785 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
786 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
787
788 /* DWT Comparator Function Register Definitions */
789 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
790 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
791
792 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
793 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
794
795 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
796 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
797
798 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
799 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
800
801 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
802 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
803
804 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
805 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
806
807 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
808 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
809
810 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
811 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
812
813 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
814 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
815
816 /*@}*/ /* end of group CMSIS_DWT */
817
818
819 /** \ingroup CMSIS_core_register
820 \defgroup CMSIS_TPI Trace Port Interface (TPI)
821 \brief Type definitions for the Trace Port Interface (TPI)
822 @{
823 */
824
825 /** \brief Structure type to access the Trace Port Interface Register (TPI).
826 */
827 typedef struct
828 {
829 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
830 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
831 uint32_t RESERVED0[2];
832 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
833 uint32_t RESERVED1[55];
834 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
835 uint32_t RESERVED2[131];
836 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
837 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
838 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
839 uint32_t RESERVED3[759];
840 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
841 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
842 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
843 uint32_t RESERVED4[1];
844 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
845 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
846 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
847 uint32_t RESERVED5[39];
848 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
849 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
850 uint32_t RESERVED7[8];
851 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
852 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
853 } TPI_Type;
854
855 /* TPI Asynchronous Clock Prescaler Register Definitions */
856 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
857 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
858
859 /* TPI Selected Pin Protocol Register Definitions */
860 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
861 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
862
863 /* TPI Formatter and Flush Status Register Definitions */
864 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
865 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
866
867 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
868 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
869
870 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
871 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
872
873 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
874 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
875
876 /* TPI Formatter and Flush Control Register Definitions */
877 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
878 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
879
880 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
881 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
882
883 /* TPI TRIGGER Register Definitions */
884 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
885 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
886
887 /* TPI Integration ETM Data Register Definitions (FIFO0) */
888 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
889 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
890
891 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
892 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
893
894 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
895 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
896
897 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
898 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
899
900 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
901 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
902
903 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
904 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
905
906 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
907 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
908
909 /* TPI ITATBCTR2 Register Definitions */
910 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
911 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
912
913 /* TPI Integration ITM Data Register Definitions (FIFO1) */
914 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
915 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
916
917 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
918 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
919
920 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
921 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
922
923 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
924 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
925
926 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
927 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
928
929 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
930 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
931
932 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
933 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
934
935 /* TPI ITATBCTR0 Register Definitions */
936 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
937 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
938
939 /* TPI Integration Mode Control Register Definitions */
940 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
941 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
942
943 /* TPI DEVID Register Definitions */
944 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
945 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
946
947 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
948 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
949
950 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
951 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
952
953 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
954 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
955
956 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
957 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
958
959 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
960 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
961
962 /* TPI DEVTYPE Register Definitions */
963 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
964 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
965
966 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
967 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
968
969 /*@}*/ /* end of group CMSIS_TPI */
970
971
972 #if (__MPU_PRESENT == 1)
973 /** \ingroup CMSIS_core_register
974 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
975 \brief Type definitions for the Memory Protection Unit (MPU)
976 @{
977 */
978
979 /** \brief Structure type to access the Memory Protection Unit (MPU).
980 */
981 typedef struct
982 {
983 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
984 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
985 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
986 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
987 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
988 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
989 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
990 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
991 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
992 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
993 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
994 } MPU_Type;
995
996 /* MPU Type Register */
997 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
998 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
999
1000 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1001 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1002
1003 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1004 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1005
1006 /* MPU Control Register */
1007 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1008 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1009
1010 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1011 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1012
1013 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1014 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1015
1016 /* MPU Region Number Register */
1017 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1018 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1019
1020 /* MPU Region Base Address Register */
1021 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1022 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1023
1024 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1025 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1026
1027 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1028 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1029
1030 /* MPU Region Attribute and Size Register */
1031 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1032 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1033
1034 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1035 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1036
1037 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1038 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1039
1040 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1041 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1042
1043 /*@} end of group CMSIS_MPU */
1044 #endif
1045
1046
1047 /** \ingroup CMSIS_core_register
1048 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1049 \brief Type definitions for the Core Debug Registers
1050 @{
1051 */
1052
1053 /** \brief Structure type to access the Core Debug Register (CoreDebug).
1054 */
1055 typedef struct
1056 {
1057 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1058 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1059 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1060 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1061 } CoreDebug_Type;
1062
1063 /* Debug Halting Control and Status Register */
1064 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1065 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1066
1067 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1068 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1069
1070 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1071 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1072
1073 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1074 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1075
1076 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1077 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1078
1079 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1080 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1081
1082 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1083 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1084
1085 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1086 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1087
1088 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1089 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1090
1091 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1092 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1093
1094 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1095 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1096
1097 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1098 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1099
1100 /* Debug Core Register Selector Register */
1101 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1102 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1103
1104 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1105 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1106
1107 /* Debug Exception and Monitor Control Register */
1108 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1109 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1110
1111 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1112 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1113
1114 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1115 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1116
1117 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1118 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1119
1120 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1121 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1122
1123 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1124 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1125
1126 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1127 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1128
1129 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1130 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1131
1132 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1133 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1134
1135 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1136 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1137
1138 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1139 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1140
1141 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1142 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1143
1144 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1145 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1146
1147 /*@} end of group CMSIS_CoreDebug */
1148
1149
1150 /** \ingroup CMSIS_core_register
1151 \defgroup CMSIS_core_base Core Definitions
1152 \brief Definitions for base addresses, unions, and structures.
1153 @{
1154 */
1155
1156 /* Memory mapping of Cortex-M3 Hardware */
1157 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1158 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1165
1166 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1170 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1171 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1172 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1173 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1174
1175 #if (__MPU_PRESENT == 1)
1176 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1177 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1178 #endif
1179
1180 /*@} */
1181
1182
1183
1184 /*******************************************************************************
1185 * Hardware Abstraction Layer
1186 Core Function Interface contains:
1187 - Core NVIC Functions
1188 - Core SysTick Functions
1189 - Core Debug Functions
1190 - Core Register Access Functions
1191 ******************************************************************************/
1192 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1193 */
1194
1195
1196
1197 /* ########################## NVIC functions #################################### */
1198 /** \ingroup CMSIS_Core_FunctionInterface
1199 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1200 \brief Functions that manage interrupts and exceptions via the NVIC.
1201 @{
1202 */
1203
1204 /** \brief Set Priority Grouping
1205
1206 The function sets the priority grouping field using the required unlock sequence.
1207 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1208 Only values from 0..7 are used.
1209 In case of a conflict between priority grouping and available
1210 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1211
1212 \param [in] PriorityGroup Priority grouping field.
1213 */
NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1214 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1215 {
1216 uint32_t reg_value;
1217 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1218
1219 reg_value = SCB->AIRCR; /* read old register configuration */
1220 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1221 reg_value = (reg_value |
1222 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1223 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1224 SCB->AIRCR = reg_value;
1225 }
1226
1227
1228 /** \brief Get Priority Grouping
1229
1230 The function reads the priority grouping field from the NVIC Interrupt Controller.
1231
1232 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1233 */
NVIC_GetPriorityGrouping(void)1234 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1235 {
1236 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1237 }
1238
1239
1240 /** \brief Enable External Interrupt
1241
1242 The function enables a device-specific interrupt in the NVIC interrupt controller.
1243
1244 \param [in] IRQn External interrupt number. Value cannot be negative.
1245 */
NVIC_EnableIRQ(IRQn_Type IRQn)1246 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1247 {
1248 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1249 }
1250
1251
1252 /** \brief Disable External Interrupt
1253
1254 The function disables a device-specific interrupt in the NVIC interrupt controller.
1255
1256 \param [in] IRQn External interrupt number. Value cannot be negative.
1257 */
NVIC_DisableIRQ(IRQn_Type IRQn)1258 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1259 {
1260 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1261 }
1262
1263
1264 /** \brief Get Pending Interrupt
1265
1266 The function reads the pending register in the NVIC and returns the pending bit
1267 for the specified interrupt.
1268
1269 \param [in] IRQn Interrupt number.
1270
1271 \return 0 Interrupt status is not pending.
1272 \return 1 Interrupt status is pending.
1273 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)1274 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1275 {
1276 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1277 }
1278
1279
1280 /** \brief Set Pending Interrupt
1281
1282 The function sets the pending bit of an external interrupt.
1283
1284 \param [in] IRQn Interrupt number. Value cannot be negative.
1285 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)1286 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1287 {
1288 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1289 }
1290
1291
1292 /** \brief Clear Pending Interrupt
1293
1294 The function clears the pending bit of an external interrupt.
1295
1296 \param [in] IRQn External interrupt number. Value cannot be negative.
1297 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)1298 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1299 {
1300 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1301 }
1302
1303
1304 /** \brief Get Active Interrupt
1305
1306 The function reads the active register in NVIC and returns the active bit.
1307
1308 \param [in] IRQn Interrupt number.
1309
1310 \return 0 Interrupt status is not active.
1311 \return 1 Interrupt status is active.
1312 */
NVIC_GetActive(IRQn_Type IRQn)1313 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1314 {
1315 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1316 }
1317
1318
1319 /** \brief Set Interrupt Priority
1320
1321 The function sets the priority of an interrupt.
1322
1323 \note The priority cannot be set for every core interrupt.
1324
1325 \param [in] IRQn Interrupt number.
1326 \param [in] priority Priority to set.
1327 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1328 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1329 {
1330 if(IRQn < 0) {
1331 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1332 else {
1333 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1334 }
1335
1336
1337 /** \brief Get Interrupt Priority
1338
1339 The function reads the priority of an interrupt. The interrupt
1340 number can be positive to specify an external (device specific)
1341 interrupt, or negative to specify an internal (core) interrupt.
1342
1343
1344 \param [in] IRQn Interrupt number.
1345 \return Interrupt Priority. Value is aligned automatically to the implemented
1346 priority bits of the microcontroller.
1347 */
NVIC_GetPriority(IRQn_Type IRQn)1348 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1349 {
1350
1351 if(IRQn < 0) {
1352 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1353 else {
1354 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1355 }
1356
1357
1358 /** \brief Encode Priority
1359
1360 The function encodes the priority for an interrupt with the given priority group,
1361 preemptive priority value, and subpriority value.
1362 In case of a conflict between priority grouping and available
1363 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1364
1365 \param [in] PriorityGroup Used priority group.
1366 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1367 \param [in] SubPriority Subpriority value (starting from 0).
1368 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1369 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1370 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1371 {
1372 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1373 uint32_t PreemptPriorityBits;
1374 uint32_t SubPriorityBits;
1375
1376 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1377 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1378
1379 return (
1380 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1381 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1382 );
1383 }
1384
1385
1386 /** \brief Decode Priority
1387
1388 The function decodes an interrupt priority value with a given priority group to
1389 preemptive priority value and subpriority value.
1390 In case of a conflict between priority grouping and available
1391 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1392
1393 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1394 \param [in] PriorityGroup Used priority group.
1395 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1396 \param [out] pSubPriority Subpriority value (starting from 0).
1397 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)1398 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1399 {
1400 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1401 uint32_t PreemptPriorityBits;
1402 uint32_t SubPriorityBits;
1403
1404 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1405 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1406
1407 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1408 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1409 }
1410
1411
1412 /** \brief System Reset
1413
1414 The function initiates a system reset request to reset the MCU.
1415 */
NVIC_SystemReset(void)1416 __STATIC_INLINE void NVIC_SystemReset(void)
1417 {
1418 __DSB(); /* Ensure all outstanding memory accesses included
1419 buffered write are completed before reset */
1420 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1421 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1422 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1423 __DSB(); /* Ensure completion of memory access */
1424 while(1); /* wait until reset */
1425 }
1426
1427 /*@} end of CMSIS_Core_NVICFunctions */
1428
1429
1430
1431 /* ################################## SysTick function ############################################ */
1432 /** \ingroup CMSIS_Core_FunctionInterface
1433 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1434 \brief Functions that configure the System.
1435 @{
1436 */
1437
1438 #if (__Vendor_SysTickConfig == 0)
1439
1440 /** \brief System Tick Configuration
1441
1442 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1443 Counter is in free running mode to generate periodic interrupts.
1444
1445 \param [in] ticks Number of ticks between two interrupts.
1446
1447 \return 0 Function succeeded.
1448 \return 1 Function failed.
1449
1450 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1451 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1452 must contain a vendor-specific implementation of this function.
1453
1454 */
SysTick_Config(uint32_t ticks)1455 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1456 {
1457 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1458
1459 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1460 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1461 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1462 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1463 SysTick_CTRL_TICKINT_Msk |
1464 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1465 return (0); /* Function successful */
1466 }
1467
1468 #endif
1469
1470 /*@} end of CMSIS_Core_SysTickFunctions */
1471
1472
1473
1474 /* ##################################### Debug In/Output function ########################################### */
1475 /** \ingroup CMSIS_Core_FunctionInterface
1476 \defgroup CMSIS_core_DebugFunctions ITM Functions
1477 \brief Functions that access the ITM debug interface.
1478 @{
1479 */
1480
1481 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1482 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1483
1484
1485 /** \brief ITM Send Character
1486
1487 The function transmits a character via the ITM channel 0, and
1488 \li Just returns when no debugger is connected that has booked the output.
1489 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1490
1491 \param [in] ch Character to transmit.
1492
1493 \returns Character to transmit.
1494 */
ITM_SendChar(uint32_t ch)1495 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1496 {
1497 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1498 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1499 {
1500 while (ITM->PORT[0].u32 == 0);
1501 ITM->PORT[0].u8 = (uint8_t) ch;
1502 }
1503 return (ch);
1504 }
1505
1506
1507 /** \brief ITM Receive Character
1508
1509 The function inputs a character via the external variable \ref ITM_RxBuffer.
1510
1511 \return Received character.
1512 \return -1 No character pending.
1513 */
ITM_ReceiveChar(void)1514 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1515 int32_t ch = -1; /* no character available */
1516
1517 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1518 ch = ITM_RxBuffer;
1519 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1520 }
1521
1522 return (ch);
1523 }
1524
1525
1526 /** \brief ITM Check Character
1527
1528 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1529
1530 \return 0 No character available.
1531 \return 1 Character available.
1532 */
ITM_CheckChar(void)1533 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1534
1535 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1536 return (0); /* no character available */
1537 } else {
1538 return (1); /* character available */
1539 }
1540 }
1541
1542 /*@} end of CMSIS_core_DebugFunctions */
1543
1544 #endif /* __CORE_CM3_H_DEPENDANT */
1545
1546 #endif /* __CMSIS_GENERIC */
1547
1548 #ifdef __cplusplus
1549 }
1550 #endif
1551