1 /**************************************************************************//**
2 * @file core_sc000.h
3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4 * @version V3.00
5 * @date 27. January 2012
6 *
7 * @note
8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 #ifndef __CORE_SC000_H_GENERIC
32 #define __CORE_SC000_H_GENERIC
33
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35 CMSIS violates the following MISRA-C:2004 rules:
36
37 \li Required Rule 8.5, object/function definition in header file.<br>
38 Function definitions in header files are used to allow 'inlining'.
39
40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41 Unions are used for effective representation of core registers.
42
43 \li Advisory Rule 19.7, Function-like macro defined.<br>
44 Function-like macros are used to allow more efficient code.
45 */
46
47
48 /*******************************************************************************
49 * CMSIS definitions
50 ******************************************************************************/
51 /** \ingroup SC000
52 @{
53 */
54
55 /* CMSIS SC000 definitions */
56 #define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
58 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
59 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60
61 #define __CORTEX_SC (0) /*!< Cortex secure core */
62
63
64 #if defined ( __CC_ARM )
65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67 #define __STATIC_INLINE static __inline
68
69 #elif defined ( __ICCARM__ )
70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72 #define __STATIC_INLINE static inline
73
74 #elif defined ( __GNUC__ )
75 #define __ASM __asm /*!< asm keyword for GNU Compiler */
76 #define __INLINE inline /*!< inline keyword for GNU Compiler */
77 #define __STATIC_INLINE static inline
78
79 #elif defined ( __TASKING__ )
80 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
81 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
82 #define __STATIC_INLINE static inline
83
84 #endif
85
86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
87 */
88 #define __FPU_USED 0
89
90 #if defined ( __CC_ARM )
91 #if defined __TARGET_FPU_VFP
92 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93 #endif
94
95 #elif defined ( __ICCARM__ )
96 #if defined __ARMVFP__
97 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98 #endif
99
100 #elif defined ( __GNUC__ )
101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103 #endif
104
105 #elif defined ( __TASKING__ )
106 /* add preprocessor checks */
107 #endif
108
109 #include <stdint.h> /* standard types definitions */
110 #include <core_cmInstr.h> /* Core Instruction Access */
111 #include <core_cmFunc.h> /* Core Function Access */
112
113 #endif /* __CORE_SC000_H_GENERIC */
114
115 #ifndef __CMSIS_GENERIC
116
117 #ifndef __CORE_SC000_H_DEPENDANT
118 #define __CORE_SC000_H_DEPENDANT
119
120 /* check device defines and use defaults */
121 #if defined __CHECK_DEVICE_DEFINES
122 #ifndef __SC000_REV
123 #define __SC000_REV 0x0000
124 #warning "__SC000_REV not defined in device header file; using default!"
125 #endif
126
127 #ifndef __MPU_PRESENT
128 #define __MPU_PRESENT 0
129 #warning "__MPU_PRESENT not defined in device header file; using default!"
130 #endif
131
132 #ifndef __NVIC_PRIO_BITS
133 #define __NVIC_PRIO_BITS 2
134 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
135 #endif
136
137 #ifndef __Vendor_SysTickConfig
138 #define __Vendor_SysTickConfig 0
139 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
140 #endif
141 #endif
142
143 /* IO definitions (access restrictions to peripheral registers) */
144 /**
145 \defgroup CMSIS_glob_defs CMSIS Global Defines
146
147 <strong>IO Type Qualifiers</strong> are used
148 \li to specify the access to peripheral variables.
149 \li for automatic generation of peripheral register debug information.
150 */
151 #ifdef __cplusplus
152 #define __I volatile /*!< Defines 'read only' permissions */
153 #else
154 #define __I volatile const /*!< Defines 'read only' permissions */
155 #endif
156 #define __O volatile /*!< Defines 'write only' permissions */
157 #define __IO volatile /*!< Defines 'read / write' permissions */
158
159 /*@} end of group SC000 */
160
161
162
163 /*******************************************************************************
164 * Register Abstraction
165 Core Register contain:
166 - Core Register
167 - Core NVIC Register
168 - Core SCB Register
169 - Core SysTick Register
170 - Core MPU Register
171 ******************************************************************************/
172 /** \defgroup CMSIS_core_register Defines and Type Definitions
173 \brief Type definitions and defines for Cortex-M processor based devices.
174 */
175
176 /** \ingroup CMSIS_core_register
177 \defgroup CMSIS_CORE Status and Control Registers
178 \brief Core Register type definitions.
179 @{
180 */
181
182 /** \brief Union type to access the Application Program Status Register (APSR).
183 */
184 typedef union
185 {
186 struct
187 {
188 #if (__CORTEX_M != 0x04)
189 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
190 #else
191 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
192 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
193 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
194 #endif
195 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
196 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
197 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
198 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
199 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
200 } b; /*!< Structure used for bit access */
201 uint32_t w; /*!< Type used for word access */
202 } APSR_Type;
203
204
205 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
206 */
207 typedef union
208 {
209 struct
210 {
211 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
212 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
213 } b; /*!< Structure used for bit access */
214 uint32_t w; /*!< Type used for word access */
215 } IPSR_Type;
216
217
218 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
219 */
220 typedef union
221 {
222 struct
223 {
224 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
225 #if (__CORTEX_M != 0x04)
226 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
227 #else
228 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
229 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
230 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
231 #endif
232 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
233 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
234 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
239 } b; /*!< Structure used for bit access */
240 uint32_t w; /*!< Type used for word access */
241 } xPSR_Type;
242
243
244 /** \brief Union type to access the Control Registers (CONTROL).
245 */
246 typedef union
247 {
248 struct
249 {
250 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
251 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
252 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
253 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
254 } b; /*!< Structure used for bit access */
255 uint32_t w; /*!< Type used for word access */
256 } CONTROL_Type;
257
258 /*@} end of group CMSIS_CORE */
259
260
261 /** \ingroup CMSIS_core_register
262 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
263 \brief Type definitions for the NVIC Registers
264 @{
265 */
266
267 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
268 */
269 typedef struct
270 {
271 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
272 uint32_t RESERVED0[31];
273 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
274 uint32_t RSERVED1[31];
275 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
276 uint32_t RESERVED2[31];
277 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
278 uint32_t RESERVED3[31];
279 uint32_t RESERVED4[64];
280 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
281 } NVIC_Type;
282
283 /*@} end of group CMSIS_NVIC */
284
285
286 /** \ingroup CMSIS_core_register
287 \defgroup CMSIS_SCB System Control Block (SCB)
288 \brief Type definitions for the System Control Block Registers
289 @{
290 */
291
292 /** \brief Structure type to access the System Control Block (SCB).
293 */
294 typedef struct
295 {
296 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
297 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
298 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
299 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
300 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
301 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
302 uint32_t RESERVED0[1];
303 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
304 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
305 uint32_t RESERVED1[154];
306 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
307 } SCB_Type;
308
309 /* SCB CPUID Register Definitions */
310 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
311 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
312
313 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
314 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
315
316 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
317 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
318
319 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
320 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
321
322 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
323 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
324
325 /* SCB Interrupt Control State Register Definitions */
326 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
327 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
328
329 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
330 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
331
332 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
333 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
334
335 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
336 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
337
338 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
339 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
340
341 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
342 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
343
344 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
345 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
346
347 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
348 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
349
350 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
351 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
352
353 /* SCB Interrupt Control State Register Definitions */
354 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
355 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
356
357 /* SCB Application Interrupt and Reset Control Register Definitions */
358 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
359 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
360
361 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
362 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
363
364 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
365 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
366
367 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
368 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
369
370 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
371 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
372
373 /* SCB System Control Register Definitions */
374 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
375 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
376
377 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
378 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
379
380 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
381 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
382
383 /* SCB Configuration Control Register Definitions */
384 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
385 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
386
387 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
388 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
389
390 /* SCB System Handler Control and State Register Definitions */
391 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
392 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
393
394 /* SCB Security Features Register Definitions */
395 #define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
396 #define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
397
398 #define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
399 #define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
400
401 /*@} end of group CMSIS_SCB */
402
403
404 /** \ingroup CMSIS_core_register
405 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
406 \brief Type definitions for the System Control and ID Register not in the SCB
407 @{
408 */
409
410 /** \brief Structure type to access the System Control and ID Register not in the SCB.
411 */
412 typedef struct
413 {
414 uint32_t RESERVED0[2];
415 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
416 } SCnSCB_Type;
417
418 /* Auxiliary Control Register Definitions */
419 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
420 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
421
422 /*@} end of group CMSIS_SCnotSCB */
423
424
425 /** \ingroup CMSIS_core_register
426 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
427 \brief Type definitions for the System Timer Registers.
428 @{
429 */
430
431 /** \brief Structure type to access the System Timer (SysTick).
432 */
433 typedef struct
434 {
435 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
436 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
437 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
438 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
439 } SysTick_Type;
440
441 /* SysTick Control / Status Register Definitions */
442 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
443 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
444
445 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
446 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
447
448 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
449 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
450
451 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
452 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
453
454 /* SysTick Reload Register Definitions */
455 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
456 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
457
458 /* SysTick Current Register Definitions */
459 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
460 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
461
462 /* SysTick Calibration Register Definitions */
463 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
464 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
465
466 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
467 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
468
469 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
470 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
471
472 /*@} end of group CMSIS_SysTick */
473
474 #if (__MPU_PRESENT == 1)
475 /** \ingroup CMSIS_core_register
476 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
477 \brief Type definitions for the Memory Protection Unit (MPU)
478 @{
479 */
480
481 /** \brief Structure type to access the Memory Protection Unit (MPU).
482 */
483 typedef struct
484 {
485 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
486 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
487 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
488 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
489 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
490 } MPU_Type;
491
492 /* MPU Type Register */
493 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
494 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
495
496 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
497 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
498
499 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
500 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
501
502 /* MPU Control Register */
503 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
504 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
505
506 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
507 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
508
509 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
510 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
511
512 /* MPU Region Number Register */
513 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
514 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
515
516 /* MPU Region Base Address Register */
517 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
518 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
519
520 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
521 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
522
523 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
524 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
525
526 /* MPU Region Attribute and Size Register */
527 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
528 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
529
530 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
531 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
532
533 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
534 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
535
536 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
537 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
538
539 /*@} end of group CMSIS_MPU */
540 #endif
541
542
543 /** \ingroup CMSIS_core_register
544 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
545 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
546 are only accessible over DAP and not via processor. Therefore
547 they are not covered by the Cortex-M0 header file.
548 @{
549 */
550 /*@} end of group CMSIS_CoreDebug */
551
552
553 /** \ingroup CMSIS_core_register
554 \defgroup CMSIS_core_base Core Definitions
555 \brief Definitions for base addresses, unions, and structures.
556 @{
557 */
558
559 /* Memory mapping of SC000 Hardware */
560 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
561 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
562 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
563 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
564
565 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
566 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
567 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
568 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
569
570 #if (__MPU_PRESENT == 1)
571 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
572 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
573 #endif
574
575 /*@} */
576
577
578
579 /*******************************************************************************
580 * Hardware Abstraction Layer
581 Core Function Interface contains:
582 - Core NVIC Functions
583 - Core SysTick Functions
584 - Core Register Access Functions
585 ******************************************************************************/
586 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
587 */
588
589
590
591 /* ########################## NVIC functions #################################### */
592 /** \ingroup CMSIS_Core_FunctionInterface
593 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
594 \brief Functions that manage interrupts and exceptions via the NVIC.
595 @{
596 */
597
598 /* Interrupt Priorities are WORD accessible only under ARMv6M */
599 /* The following MACROS handle generation of the register offset and byte masks */
600 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
601 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
602 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
603
604
605 /** \brief Enable External Interrupt
606
607 The function enables a device-specific interrupt in the NVIC interrupt controller.
608
609 \param [in] IRQn External interrupt number. Value cannot be negative.
610 */
NVIC_EnableIRQ(IRQn_Type IRQn)611 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
612 {
613 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
614 }
615
616
617 /** \brief Disable External Interrupt
618
619 The function disables a device-specific interrupt in the NVIC interrupt controller.
620
621 \param [in] IRQn External interrupt number. Value cannot be negative.
622 */
NVIC_DisableIRQ(IRQn_Type IRQn)623 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
624 {
625 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
626 }
627
628
629 /** \brief Get Pending Interrupt
630
631 The function reads the pending register in the NVIC and returns the pending bit
632 for the specified interrupt.
633
634 \param [in] IRQn Interrupt number.
635
636 \return 0 Interrupt status is not pending.
637 \return 1 Interrupt status is pending.
638 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)639 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
640 {
641 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
642 }
643
644
645 /** \brief Set Pending Interrupt
646
647 The function sets the pending bit of an external interrupt.
648
649 \param [in] IRQn Interrupt number. Value cannot be negative.
650 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)651 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
652 {
653 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
654 }
655
656
657 /** \brief Clear Pending Interrupt
658
659 The function clears the pending bit of an external interrupt.
660
661 \param [in] IRQn External interrupt number. Value cannot be negative.
662 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)663 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
664 {
665 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
666 }
667
668
669 /** \brief Set Interrupt Priority
670
671 The function sets the priority of an interrupt.
672
673 \note The priority cannot be set for every core interrupt.
674
675 \param [in] IRQn Interrupt number.
676 \param [in] priority Priority to set.
677 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)678 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
679 {
680 if(IRQn < 0) {
681 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
682 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
683 else {
684 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
685 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
686 }
687
688
689 /** \brief Get Interrupt Priority
690
691 The function reads the priority of an interrupt. The interrupt
692 number can be positive to specify an external (device specific)
693 interrupt, or negative to specify an internal (core) interrupt.
694
695
696 \param [in] IRQn Interrupt number.
697 \return Interrupt Priority. Value is aligned automatically to the implemented
698 priority bits of the microcontroller.
699 */
NVIC_GetPriority(IRQn_Type IRQn)700 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
701 {
702
703 if(IRQn < 0) {
704 return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for SC000 system interrupts */
705 else {
706 return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
707 }
708
709
710 /** \brief System Reset
711
712 The function initiates a system reset request to reset the MCU.
713 */
NVIC_SystemReset(void)714 __STATIC_INLINE void NVIC_SystemReset(void)
715 {
716 __DSB(); /* Ensure all outstanding memory accesses included
717 buffered write are completed before reset */
718 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
719 SCB_AIRCR_SYSRESETREQ_Msk);
720 __DSB(); /* Ensure completion of memory access */
721 while(1); /* wait until reset */
722 }
723
724 /*@} end of CMSIS_Core_NVICFunctions */
725
726
727
728 /* ################################## SysTick function ############################################ */
729 /** \ingroup CMSIS_Core_FunctionInterface
730 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
731 \brief Functions that configure the System.
732 @{
733 */
734
735 #if (__Vendor_SysTickConfig == 0)
736
737 /** \brief System Tick Configuration
738
739 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
740 Counter is in free running mode to generate periodic interrupts.
741
742 \param [in] ticks Number of ticks between two interrupts.
743
744 \return 0 Function succeeded.
745 \return 1 Function failed.
746
747 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
748 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
749 must contain a vendor-specific implementation of this function.
750
751 */
SysTick_Config(uint32_t ticks)752 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
753 {
754 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
755
756 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
757 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
758 SysTick->VAL = 0; /* Load the SysTick Counter Value */
759 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
760 SysTick_CTRL_TICKINT_Msk |
761 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
762 return (0); /* Function successful */
763 }
764
765 #endif
766
767 /*@} end of CMSIS_Core_SysTickFunctions */
768
769
770
771
772 #endif /* __CORE_SC000_H_DEPENDANT */
773
774 #endif /* __CMSIS_GENERIC */
775
776 #ifdef __cplusplus
777 }
778 #endif
779