1 /** 2 ****************************************************************************** 3 * @file stm32f10x_adc.h 4 * @author MCD Application Team 5 * @version V3.1.2 6 * @date 09/28/2009 7 * @brief This file contains all the functions prototypes for the ADC firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2> 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __STM32F10x_ADC_H 24 #define __STM32F10x_ADC_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "stm32f10x.h" 32 33 /** @addtogroup STM32F10x_StdPeriph_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /** @defgroup ADC_Exported_Types 42 * @{ 43 */ 44 45 /** 46 * @brief ADC Init structure definition 47 */ 48 49 typedef struct 50 { 51 uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or 52 dual mode. 53 This parameter can be a value of @ref ADC_mode */ 54 55 FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in 56 Scan (multichannels) or Single (one channel) mode. 57 This parameter can be set to ENABLE or DISABLE */ 58 59 FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in 60 Continuous or Single mode. 61 This parameter can be set to ENABLE or DISABLE. */ 62 63 uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog 64 to digital conversion of regular channels. This parameter 65 can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ 66 67 uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. 68 This parameter can be a value of @ref ADC_data_align */ 69 70 uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted 71 using the sequencer for regular channel group. 72 This parameter must range from 1 to 16. */ 73 }ADC_InitTypeDef; 74 /** 75 * @} 76 */ 77 78 /** @defgroup ADC_Exported_Constants 79 * @{ 80 */ 81 82 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ 83 ((PERIPH) == ADC2) || \ 84 ((PERIPH) == ADC3)) 85 86 #define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ 87 ((PERIPH) == ADC3)) 88 89 /** @defgroup ADC_mode 90 * @{ 91 */ 92 93 #define ADC_Mode_Independent ((uint32_t)0x00000000) 94 #define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) 95 #define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) 96 #define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) 97 #define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) 98 #define ADC_Mode_InjecSimult ((uint32_t)0x00050000) 99 #define ADC_Mode_RegSimult ((uint32_t)0x00060000) 100 #define ADC_Mode_FastInterl ((uint32_t)0x00070000) 101 #define ADC_Mode_SlowInterl ((uint32_t)0x00080000) 102 #define ADC_Mode_AlterTrig ((uint32_t)0x00090000) 103 104 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ 105 ((MODE) == ADC_Mode_RegInjecSimult) || \ 106 ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ 107 ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ 108 ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ 109 ((MODE) == ADC_Mode_InjecSimult) || \ 110 ((MODE) == ADC_Mode_RegSimult) || \ 111 ((MODE) == ADC_Mode_FastInterl) || \ 112 ((MODE) == ADC_Mode_SlowInterl) || \ 113 ((MODE) == ADC_Mode_AlterTrig)) 114 /** 115 * @} 116 */ 117 118 /** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion 119 * @{ 120 */ 121 122 #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ 123 #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ 124 #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ 125 #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ 126 #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ 127 #define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ 128 129 #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ 130 #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ 131 132 #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ 133 #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ 134 #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ 135 #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ 136 #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ 137 #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ 138 139 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ 140 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ 141 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ 142 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ 143 ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ 144 ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ 145 ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ 146 ((REGTRIG) == ADC_ExternalTrigConv_None) || \ 147 ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ 148 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ 149 ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ 150 ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ 151 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ 152 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) 153 /** 154 * @} 155 */ 156 157 /** @defgroup ADC_data_align 158 * @{ 159 */ 160 161 #define ADC_DataAlign_Right ((uint32_t)0x00000000) 162 #define ADC_DataAlign_Left ((uint32_t)0x00000800) 163 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ 164 ((ALIGN) == ADC_DataAlign_Left)) 165 /** 166 * @} 167 */ 168 169 /** @defgroup ADC_channels 170 * @{ 171 */ 172 173 #define ADC_Channel_0 ((uint8_t)0x00) 174 #define ADC_Channel_1 ((uint8_t)0x01) 175 #define ADC_Channel_2 ((uint8_t)0x02) 176 #define ADC_Channel_3 ((uint8_t)0x03) 177 #define ADC_Channel_4 ((uint8_t)0x04) 178 #define ADC_Channel_5 ((uint8_t)0x05) 179 #define ADC_Channel_6 ((uint8_t)0x06) 180 #define ADC_Channel_7 ((uint8_t)0x07) 181 #define ADC_Channel_8 ((uint8_t)0x08) 182 #define ADC_Channel_9 ((uint8_t)0x09) 183 #define ADC_Channel_10 ((uint8_t)0x0A) 184 #define ADC_Channel_11 ((uint8_t)0x0B) 185 #define ADC_Channel_12 ((uint8_t)0x0C) 186 #define ADC_Channel_13 ((uint8_t)0x0D) 187 #define ADC_Channel_14 ((uint8_t)0x0E) 188 #define ADC_Channel_15 ((uint8_t)0x0F) 189 #define ADC_Channel_16 ((uint8_t)0x10) 190 #define ADC_Channel_17 ((uint8_t)0x11) 191 192 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ 193 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ 194 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ 195 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ 196 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ 197 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ 198 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ 199 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ 200 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) 201 /** 202 * @} 203 */ 204 205 /** @defgroup ADC_sampling_time 206 * @{ 207 */ 208 209 #define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) 210 #define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) 211 #define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) 212 #define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) 213 #define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) 214 #define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) 215 #define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) 216 #define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) 217 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ 218 ((TIME) == ADC_SampleTime_7Cycles5) || \ 219 ((TIME) == ADC_SampleTime_13Cycles5) || \ 220 ((TIME) == ADC_SampleTime_28Cycles5) || \ 221 ((TIME) == ADC_SampleTime_41Cycles5) || \ 222 ((TIME) == ADC_SampleTime_55Cycles5) || \ 223 ((TIME) == ADC_SampleTime_71Cycles5) || \ 224 ((TIME) == ADC_SampleTime_239Cycles5)) 225 /** 226 * @} 227 */ 228 229 /** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion 230 * @{ 231 */ 232 233 #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ 234 #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ 235 #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ 236 #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ 237 #define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ 238 239 #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ 240 #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ 241 #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ 242 243 #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ 244 #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ 245 #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ 246 #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ 247 #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ 248 249 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ 250 ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ 251 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ 252 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ 253 ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ 254 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ 255 ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ 256 ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ 257 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ 258 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ 259 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ 260 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ 261 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) 262 /** 263 * @} 264 */ 265 266 /** @defgroup ADC_injected_channel_selection 267 * @{ 268 */ 269 270 #define ADC_InjectedChannel_1 ((uint8_t)0x14) 271 #define ADC_InjectedChannel_2 ((uint8_t)0x18) 272 #define ADC_InjectedChannel_3 ((uint8_t)0x1C) 273 #define ADC_InjectedChannel_4 ((uint8_t)0x20) 274 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ 275 ((CHANNEL) == ADC_InjectedChannel_2) || \ 276 ((CHANNEL) == ADC_InjectedChannel_3) || \ 277 ((CHANNEL) == ADC_InjectedChannel_4)) 278 /** 279 * @} 280 */ 281 282 /** @defgroup ADC_analog_watchdog_selection 283 * @{ 284 */ 285 286 #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) 287 #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) 288 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) 289 #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) 290 #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) 291 #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) 292 #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) 293 294 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ 295 ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ 296 ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ 297 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ 298 ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ 299 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ 300 ((WATCHDOG) == ADC_AnalogWatchdog_None)) 301 /** 302 * @} 303 */ 304 305 /** @defgroup ADC_interrupts_definition 306 * @{ 307 */ 308 309 #define ADC_IT_EOC ((uint16_t)0x0220) 310 #define ADC_IT_AWD ((uint16_t)0x0140) 311 #define ADC_IT_JEOC ((uint16_t)0x0480) 312 313 #define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) 314 315 #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ 316 ((IT) == ADC_IT_JEOC)) 317 /** 318 * @} 319 */ 320 321 /** @defgroup ADC_flags_definition 322 * @{ 323 */ 324 325 #define ADC_FLAG_AWD ((uint8_t)0x01) 326 #define ADC_FLAG_EOC ((uint8_t)0x02) 327 #define ADC_FLAG_JEOC ((uint8_t)0x04) 328 #define ADC_FLAG_JSTRT ((uint8_t)0x08) 329 #define ADC_FLAG_STRT ((uint8_t)0x10) 330 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) 331 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ 332 ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ 333 ((FLAG) == ADC_FLAG_STRT)) 334 /** 335 * @} 336 */ 337 338 /** @defgroup ADC_thresholds 339 * @{ 340 */ 341 342 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) 343 344 /** 345 * @} 346 */ 347 348 /** @defgroup ADC_injected_offset 349 * @{ 350 */ 351 352 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) 353 354 /** 355 * @} 356 */ 357 358 /** @defgroup ADC_injected_length 359 * @{ 360 */ 361 362 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) 363 364 /** 365 * @} 366 */ 367 368 /** @defgroup ADC_injected_rank 369 * @{ 370 */ 371 372 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) 373 374 /** 375 * @} 376 */ 377 378 379 /** @defgroup ADC_regular_length 380 * @{ 381 */ 382 383 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) 384 /** 385 * @} 386 */ 387 388 /** @defgroup ADC_regular_rank 389 * @{ 390 */ 391 392 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) 393 394 /** 395 * @} 396 */ 397 398 /** @defgroup ADC_regular_discontinuous_mode_number 399 * @{ 400 */ 401 402 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) 403 404 /** 405 * @} 406 */ 407 408 /** 409 * @} 410 */ 411 412 /** @defgroup ADC_Exported_Macros 413 * @{ 414 */ 415 416 /** 417 * @} 418 */ 419 420 /** @defgroup ADC_Exported_Functions 421 * @{ 422 */ 423 424 void ADC_DeInit(ADC_TypeDef* ADCx); 425 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); 426 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); 427 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); 428 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); 429 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); 430 void ADC_ResetCalibration(ADC_TypeDef* ADCx); 431 FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); 432 void ADC_StartCalibration(ADC_TypeDef* ADCx); 433 FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); 434 void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 435 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); 436 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); 437 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 438 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 439 void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 440 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); 441 uint32_t ADC_GetDualModeConversionValue(void); 442 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 443 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 444 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); 445 void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 446 void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 447 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); 448 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 449 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); 450 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); 451 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); 452 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); 453 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); 454 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); 455 void ADC_TempSensorVrefintCmd(FunctionalState NewState); 456 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); 457 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); 458 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); 459 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); 460 461 #ifdef __cplusplus 462 } 463 #endif 464 465 #endif /*__STM32F10x_ADC_H */ 466 467 /** 468 * @} 469 */ 470 471 /** 472 * @} 473 */ 474 475 /** 476 * @} 477 */ 478 479 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ 480