1 /** 2 ****************************************************************************** 3 * @file stm32f30x_fmc.h 4 * @author MCD Application Team 5 * @version V1.2.3 6 * @date 10-July-2015 7 * @brief This file contains all the functions prototypes for the FMC firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 13 * 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 * You may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at: 17 * 18 * http://www.st.com/software_license_agreement_liberty_v2 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ****************************************************************************** 27 */ 28 29 /* Define to prevent recursive inclusion -------------------------------------*/ 30 #ifndef __STM32F30x_FMC_H 31 #define __STM32F30x_FMC_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* Includes ------------------------------------------------------------------*/ 38 #include "stm32f30x.h" 39 40 /** @addtogroup STM32F30x_StdPeriph_Driver 41 * @{ 42 */ 43 44 /** @addtogroup FMC 45 * @{ 46 */ 47 48 /* Exported types ------------------------------------------------------------*/ 49 50 /** 51 * @brief Timing parameters For NOR/SRAM Banks 52 */ 53 typedef struct 54 { 55 uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 56 the duration of the address setup time. 57 This parameter can be a value between 0 and 15. 58 @note This parameter is not used with synchronous NOR Flash memories. */ 59 60 uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 61 the duration of the address hold time. 62 This parameter can be a value between 1 and 15. 63 @note This parameter is not used with synchronous NOR Flash memories.*/ 64 65 uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure 66 the duration of the data setup time. 67 This parameter can be a value between 1 and 255. 68 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ 69 70 uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 71 the duration of the bus turnaround. 72 This parameter can be a value between 0 and 15. 73 @note This parameter is only used for multiplexed NOR Flash memories. */ 74 75 uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. 76 This parameter can be a value between 2 and 16. 77 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ 78 79 uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue 80 to the memory before getting the first data. 81 The parameter value depends on the memory type as shown below: 82 - It must be set to 0 in case of a CRAM 83 - It is don't care in asynchronous NOR, SRAM or ROM accesses 84 - It may assume a value between 2 and 17 in NOR Flash memories 85 with synchronous burst mode enable */ 86 87 uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode. 88 This parameter can be a value of @ref FMC_Access_Mode */ 89 }FMC_NORSRAMTimingInitTypeDef; 90 91 /** 92 * @brief FMC NOR/SRAM Init structure definition 93 */ 94 typedef struct 95 { 96 uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. 97 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 98 99 uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are 100 multiplexed on the databus or not. 101 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 102 103 uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to 104 the corresponding memory bank. 105 This parameter can be a value of @ref FMC_Memory_Type */ 106 107 uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. 108 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 109 110 uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 111 valid only with synchronous burst Flash memories. 112 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 113 114 uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 115 the Flash memory in burst mode. 116 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 117 118 uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 119 memory, valid only when accessing Flash memories in burst mode. 120 This parameter can be a value of @ref FMC_Wrap_Mode */ 121 122 uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 123 clock cycle before the wait state or during the wait state, 124 valid only when accessing memories in burst mode. 125 This parameter can be a value of @ref FMC_Wait_Timing */ 126 127 uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC. 128 This parameter can be a value of @ref FMC_Write_Operation */ 129 130 uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait 131 signal, valid for Flash memory access in burst mode. 132 This parameter can be a value of @ref FMC_Wait_Signal */ 133 134 uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode. 135 This parameter can be a value of @ref FMC_Extended_Mode */ 136 137 uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 138 valid only with asynchronous Flash memories. 139 This parameter can be a value of @ref FMC_AsynchronousWait */ 140 141 uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation. 142 This parameter can be a value of @ref FMC_Write_Burst */ 143 144 145 FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ 146 147 FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ 148 }FMC_NORSRAMInitTypeDef; 149 150 /** 151 * @brief Timing parameters For FMC NAND and PCCARD Banks 152 */ 153 typedef struct 154 { 155 uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before 156 the command assertion for NAND-Flash read or write access 157 to common/Attribute or I/O memory space (depending on 158 the memory space timing to be configured). 159 This parameter can be a value between 0 and 255.*/ 160 161 uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 162 command for NAND-Flash read or write access to 163 common/Attribute or I/O memory space (depending on the 164 memory space timing to be configured). 165 This parameter can be a number between 0 and 255 */ 166 167 uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 168 (and data for write access) after the command de-assertion 169 for NAND-Flash read or write access to common/Attribute 170 or I/O memory space (depending on the memory space timing 171 to be configured). 172 This parameter can be a number between 0 and 255 */ 173 174 uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 175 databus is kept in HiZ after the start of a NAND-Flash 176 write access to common/Attribute or I/O memory space (depending 177 on the memory space timing to be configured). 178 This parameter can be a number between 0 and 255 */ 179 }FMC_NAND_PCCARDTimingInitTypeDef; 180 181 /** 182 * @brief FMC NAND Init structure definition 183 */ 184 typedef struct 185 { 186 uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used. 187 This parameter can be a value of @ref FMC_NAND_Bank */ 188 189 uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. 190 This parameter can be any value of @ref FMC_Wait_feature */ 191 192 uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. 193 This parameter can be any value of @ref FMC_NAND_Data_Width */ 194 195 uint32_t FMC_ECC; /*!< Enables or disables the ECC computation. 196 This parameter can be any value of @ref FMC_ECC */ 197 198 uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC. 199 This parameter can be any value of @ref FMC_ECC_Page_Size */ 200 201 uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 202 delay between CLE low and RE low. 203 This parameter can be a value between 0 and 255. */ 204 205 uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 206 delay between ALE low and RE low. 207 This parameter can be a number between 0 and 255 */ 208 209 FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ 210 211 FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ 212 }FMC_NANDInitTypeDef; 213 214 /** 215 * @brief FMC PCCARD Init structure definition 216 */ 217 218 typedef struct 219 { 220 uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. 221 This parameter can be any value of @ref FMC_Wait_feature */ 222 223 uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 224 delay between CLE low and RE low. 225 This parameter can be a value between 0 and 255. */ 226 227 uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 228 delay between ALE low and RE low. 229 This parameter can be a number between 0 and 255 */ 230 231 232 FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ 233 234 FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ 235 236 FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */ 237 }FMC_PCCARDInitTypeDef; 238 239 240 /* Exported constants --------------------------------------------------------*/ 241 242 /** @defgroup FMC_Exported_Constants 243 * @{ 244 */ 245 246 /** @defgroup FMC_NORSRAM_Bank 247 * @{ 248 */ 249 #define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) 250 #define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) 251 #define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) 252 #define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) 253 254 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \ 255 ((BANK) == FMC_Bank1_NORSRAM2) || \ 256 ((BANK) == FMC_Bank1_NORSRAM3) || \ 257 ((BANK) == FMC_Bank1_NORSRAM4)) 258 /** 259 * @} 260 */ 261 262 /** @defgroup FMC_NAND_Bank 263 * @{ 264 */ 265 #define FMC_Bank2_NAND ((uint32_t)0x00000010) 266 #define FMC_Bank3_NAND ((uint32_t)0x00000100) 267 268 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ 269 ((BANK) == FMC_Bank3_NAND)) 270 /** 271 * @} 272 */ 273 274 /** @defgroup FMC_PCCARD_Bank 275 * @{ 276 */ 277 #define FMC_Bank4_PCCARD ((uint32_t)0x00001000) 278 /** 279 * @} 280 */ 281 282 283 /** @defgroup FMC_NOR_SRAM_Controller 284 * @{ 285 */ 286 287 /** @defgroup FMC_Data_Address_Bus_Multiplexing 288 * @{ 289 */ 290 291 #define FMC_DataAddressMux_Disable ((uint32_t)0x00000000) 292 #define FMC_DataAddressMux_Enable ((uint32_t)0x00000002) 293 294 #define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \ 295 ((MUX) == FMC_DataAddressMux_Enable)) 296 /** 297 * @} 298 */ 299 300 /** @defgroup FMC_Memory_Type 301 * @{ 302 */ 303 304 #define FMC_MemoryType_SRAM ((uint32_t)0x00000000) 305 #define FMC_MemoryType_PSRAM ((uint32_t)0x00000004) 306 #define FMC_MemoryType_NOR ((uint32_t)0x00000008) 307 308 #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \ 309 ((MEMORY) == FMC_MemoryType_PSRAM)|| \ 310 ((MEMORY) == FMC_MemoryType_NOR)) 311 /** 312 * @} 313 */ 314 315 /** @defgroup FMC_NORSRAM_Data_Width 316 * @{ 317 */ 318 319 #define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000) 320 #define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010) 321 322 #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \ 323 ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b)) 324 /** 325 * @} 326 */ 327 328 /** @defgroup FMC_Burst_Access_Mode 329 * @{ 330 */ 331 332 #define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000) 333 #define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100) 334 335 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \ 336 ((STATE) == FMC_BurstAccessMode_Enable)) 337 /** 338 * @} 339 */ 340 341 /** @defgroup FMC_AsynchronousWait 342 * @{ 343 */ 344 #define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000) 345 #define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000) 346 347 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \ 348 ((STATE) == FMC_AsynchronousWait_Enable)) 349 /** 350 * @} 351 */ 352 353 /** @defgroup FMC_Wait_Signal_Polarity 354 * @{ 355 */ 356 #define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) 357 #define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200) 358 359 #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \ 360 ((POLARITY) == FMC_WaitSignalPolarity_High)) 361 /** 362 * @} 363 */ 364 365 /** @defgroup FMC_Wrap_Mode 366 * @{ 367 */ 368 #define FMC_WrapMode_Disable ((uint32_t)0x00000000) 369 #define FMC_WrapMode_Enable ((uint32_t)0x00000400) 370 371 #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \ 372 ((MODE) == FMC_WrapMode_Enable)) 373 /** 374 * @} 375 */ 376 377 /** @defgroup FMC_Wait_Timing 378 * @{ 379 */ 380 #define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) 381 #define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) 382 383 #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \ 384 ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState)) 385 /** 386 * @} 387 */ 388 389 /** @defgroup FMC_Write_Operation 390 * @{ 391 */ 392 #define FMC_WriteOperation_Disable ((uint32_t)0x00000000) 393 #define FMC_WriteOperation_Enable ((uint32_t)0x00001000) 394 395 #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \ 396 ((OPERATION) == FMC_WriteOperation_Enable)) 397 /** 398 * @} 399 */ 400 401 /** @defgroup FMC_Wait_Signal 402 * @{ 403 */ 404 #define FMC_WaitSignal_Disable ((uint32_t)0x00000000) 405 #define FMC_WaitSignal_Enable ((uint32_t)0x00002000) 406 407 #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \ 408 ((SIGNAL) == FMC_WaitSignal_Enable)) 409 /** 410 * @} 411 */ 412 413 /** @defgroup FMC_Extended_Mode 414 * @{ 415 */ 416 #define FMC_ExtendedMode_Disable ((uint32_t)0x00000000) 417 #define FMC_ExtendedMode_Enable ((uint32_t)0x00004000) 418 419 #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \ 420 ((MODE) == FMC_ExtendedMode_Enable)) 421 /** 422 * @} 423 */ 424 425 /** @defgroup FMC_Write_Burst 426 * @{ 427 */ 428 429 #define FMC_WriteBurst_Disable ((uint32_t)0x00000000) 430 #define FMC_WriteBurst_Enable ((uint32_t)0x00080000) 431 432 #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \ 433 ((BURST) == FMC_WriteBurst_Enable)) 434 /** 435 * @} 436 */ 437 438 /** @defgroup FMC_Continous_Clock 439 * @{ 440 */ 441 442 #define FMC_CClock_SyncOnly ((uint32_t)0x00000000) 443 #define FMC_CClock_SyncAsync ((uint32_t)0x00100000) 444 445 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \ 446 ((CCLOCK) == FMC_CClock_SyncAsync)) 447 /** 448 * @} 449 */ 450 451 /** @defgroup FMC_Address_Setup_Time 452 * @{ 453 */ 454 #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15) 455 /** 456 * @} 457 */ 458 459 /** @defgroup FMC_Address_Hold_Time 460 * @{ 461 */ 462 #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15)) 463 /** 464 * @} 465 */ 466 467 /** @defgroup FMC_Data_Setup_Time 468 * @{ 469 */ 470 #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255)) 471 /** 472 * @} 473 */ 474 475 /** @defgroup FMC_Bus_Turn_around_Duration 476 * @{ 477 */ 478 #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15) 479 /** 480 * @} 481 */ 482 483 /** @defgroup FMC_CLK_Division 484 * @{ 485 */ 486 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) 487 /** 488 * @} 489 */ 490 491 /** @defgroup FMC_Data_Latency 492 * @{ 493 */ 494 #define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17)) 495 /** 496 * @} 497 */ 498 499 /** @defgroup FMC_Access_Mode 500 * @{ 501 */ 502 #define FMC_AccessMode_A ((uint32_t)0x00000000) 503 #define FMC_AccessMode_B ((uint32_t)0x10000000) 504 #define FMC_AccessMode_C ((uint32_t)0x20000000) 505 #define FMC_AccessMode_D ((uint32_t)0x30000000) 506 507 #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \ 508 ((MODE) == FMC_AccessMode_B) || \ 509 ((MODE) == FMC_AccessMode_C) || \ 510 ((MODE) == FMC_AccessMode_D)) 511 /** 512 * @} 513 */ 514 515 /** 516 * @} 517 */ 518 519 /** @defgroup FMC_NAND_PCCARD_Controller 520 * @{ 521 */ 522 523 /** @defgroup FMC_Wait_feature 524 * @{ 525 */ 526 #define FMC_Waitfeature_Disable ((uint32_t)0x00000000) 527 #define FMC_Waitfeature_Enable ((uint32_t)0x00000002) 528 529 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \ 530 ((FEATURE) == FMC_Waitfeature_Enable)) 531 /** 532 * @} 533 */ 534 535 /** @defgroup FMC_NAND_Data_Width 536 * @{ 537 */ 538 #define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000) 539 #define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010) 540 541 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \ 542 ((WIDTH) == FMC_NAND_MemoryDataWidth_16b)) 543 /** 544 * @} 545 */ 546 547 /** @defgroup FMC_ECC 548 * @{ 549 */ 550 #define FMC_ECC_Disable ((uint32_t)0x00000000) 551 #define FMC_ECC_Enable ((uint32_t)0x00000040) 552 553 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \ 554 ((STATE) == FMC_ECC_Enable)) 555 /** 556 * @} 557 */ 558 559 /** @defgroup FMC_ECC_Page_Size 560 * @{ 561 */ 562 #define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) 563 #define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) 564 #define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) 565 #define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) 566 #define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) 567 #define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) 568 569 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \ 570 ((SIZE) == FMC_ECCPageSize_512Bytes) || \ 571 ((SIZE) == FMC_ECCPageSize_1024Bytes) || \ 572 ((SIZE) == FMC_ECCPageSize_2048Bytes) || \ 573 ((SIZE) == FMC_ECCPageSize_4096Bytes) || \ 574 ((SIZE) == FMC_ECCPageSize_8192Bytes)) 575 /** 576 * @} 577 */ 578 579 /** @defgroup FMC_TCLR_Setup_Time 580 * @{ 581 */ 582 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255) 583 /** 584 * @} 585 */ 586 587 /** @defgroup FMC_TAR_Setup_Time 588 * @{ 589 */ 590 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) 591 /** 592 * @} 593 */ 594 595 /** @defgroup FMC_Setup_Time 596 * @{ 597 */ 598 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255) 599 /** 600 * @} 601 */ 602 603 /** @defgroup FMC_Wait_Setup_Time 604 * @{ 605 */ 606 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255) 607 /** 608 * @} 609 */ 610 611 /** @defgroup FMC_Hold_Setup_Time 612 * @{ 613 */ 614 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255) 615 /** 616 * @} 617 */ 618 619 /** @defgroup FMC_HiZ_Setup_Time 620 * @{ 621 */ 622 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255) 623 /** 624 * @} 625 */ 626 627 /** 628 * @} 629 */ 630 631 /** @defgroup FMC_Interrupt_sources 632 * @{ 633 */ 634 #define FMC_IT_RisingEdge ((uint32_t)0x00000008) 635 #define FMC_IT_Level ((uint32_t)0x00000010) 636 #define FMC_IT_FallingEdge ((uint32_t)0x00000020) 637 638 #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000)) 639 #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \ 640 ((IT) == FMC_IT_Level) || \ 641 ((IT) == FMC_IT_FallingEdge)) 642 643 #define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ 644 ((BANK) == FMC_Bank3_NAND) || \ 645 ((BANK) == FMC_Bank4_PCCARD)) 646 /** 647 * @} 648 */ 649 650 /** @defgroup FMC_Flags 651 * @{ 652 */ 653 #define FMC_FLAG_RisingEdge ((uint32_t)0x00000001) 654 #define FMC_FLAG_Level ((uint32_t)0x00000002) 655 #define FMC_FLAG_FallingEdge ((uint32_t)0x00000004) 656 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040) 657 658 #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \ 659 ((FLAG) == FMC_FLAG_Level) || \ 660 ((FLAG) == FMC_FLAG_FallingEdge) || \ 661 ((FLAG) == FMC_FLAG_FEMPT)) 662 663 #define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ 664 ((BANK) == FMC_Bank3_NAND) || \ 665 ((BANK) == FMC_Bank4_PCCARD)) 666 667 #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) 668 669 670 /** 671 * @} 672 */ 673 674 /** 675 * @} 676 */ 677 678 679 /* Exported macro ------------------------------------------------------------*/ 680 /* Exported functions --------------------------------------------------------*/ 681 682 /* NOR/SRAM Controller functions **********************************************/ 683 void FMC_NORSRAMDeInit(uint32_t FMC_Bank); 684 void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); 685 void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); 686 void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState); 687 688 /* NAND Controller functions **************************************************/ 689 void FMC_NANDDeInit(uint32_t FMC_Bank); 690 void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); 691 void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); 692 void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState); 693 void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState); 694 uint32_t FMC_GetECC(uint32_t FMC_Bank); 695 696 /* PCCARD Controller functions ************************************************/ 697 void FMC_PCCARDDeInit(void); 698 void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); 699 void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); 700 void FMC_PCCARDCmd(FunctionalState NewState); 701 702 /* Interrupts and flags management functions **********************************/ 703 void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState); 704 FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG); 705 void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG); 706 ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT); 707 void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT); 708 709 #ifdef __cplusplus 710 } 711 #endif 712 713 #endif /*__STM32F30x_FMC_H */ 714 /** 715 * @} 716 */ 717 718 /** 719 * @} 720 */ 721 722 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 723