1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_fsmc.h 4 * @author MCD Application Team 5 * @version V1.6.1 6 * @date 21-October-2015 7 * @brief This file contains all the functions prototypes for the FSMC firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 13 * 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 * You may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at: 17 * 18 * http://www.st.com/software_license_agreement_liberty_v2 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ****************************************************************************** 27 */ 28 29 /* Define to prevent recursive inclusion -------------------------------------*/ 30 #ifndef __STM32F4xx_FSMC_H 31 #define __STM32F4xx_FSMC_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* Includes ------------------------------------------------------------------*/ 38 #include "stm32f4xx.h" 39 40 /** @addtogroup STM32F4xx_StdPeriph_Driver 41 * @{ 42 */ 43 44 /** @addtogroup FSMC 45 * @{ 46 */ 47 48 /* Exported types ------------------------------------------------------------*/ 49 50 /** 51 * @brief Timing parameters For NOR/SRAM Banks 52 */ 53 typedef struct 54 { 55 uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 56 the duration of the address setup time. 57 This parameter can be a value between 0 and 0xF. 58 @note This parameter is not used with synchronous NOR Flash memories. */ 59 60 uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 61 the duration of the address hold time. 62 This parameter can be a value between 0 and 0xF. 63 @note This parameter is not used with synchronous NOR Flash memories.*/ 64 65 uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure 66 the duration of the data setup time. 67 This parameter can be a value between 0 and 0xFF. 68 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ 69 70 uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 71 the duration of the bus turnaround. 72 This parameter can be a value between 0 and 0xF. 73 @note This parameter is only used for multiplexed NOR Flash memories. */ 74 75 uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. 76 This parameter can be a value between 1 and 0xF. 77 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ 78 79 uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue 80 to the memory before getting the first data. 81 The parameter value depends on the memory type as shown below: 82 - It must be set to 0 in case of a CRAM 83 - It is don't care in asynchronous NOR, SRAM or ROM accesses 84 - It may assume a value between 0 and 0xF in NOR Flash memories 85 with synchronous burst mode enable */ 86 87 uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. 88 This parameter can be a value of @ref FSMC_Access_Mode */ 89 }FSMC_NORSRAMTimingInitTypeDef; 90 91 /** 92 * @brief FSMC NOR/SRAM Init structure definition 93 */ 94 typedef struct 95 { 96 uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. 97 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ 98 99 uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are 100 multiplexed on the data bus or not. 101 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ 102 103 uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to 104 the corresponding memory bank. 105 This parameter can be a value of @ref FSMC_Memory_Type */ 106 107 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. 108 This parameter can be a value of @ref FSMC_Data_Width */ 109 110 uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 111 valid only with synchronous burst Flash memories. 112 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ 113 114 uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 115 valid only with asynchronous Flash memories. 116 This parameter can be a value of @ref FSMC_AsynchronousWait */ 117 118 uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 119 the Flash memory in burst mode. 120 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ 121 122 uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash 123 memory, valid only when accessing Flash memories in burst mode. 124 This parameter can be a value of @ref FSMC_Wrap_Mode */ 125 126 uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 127 clock cycle before the wait state or during the wait state, 128 valid only when accessing memories in burst mode. 129 This parameter can be a value of @ref FSMC_Wait_Timing */ 130 131 uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. 132 This parameter can be a value of @ref FSMC_Write_Operation */ 133 134 uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait 135 signal, valid for Flash memory access in burst mode. 136 This parameter can be a value of @ref FSMC_Wait_Signal */ 137 138 uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. 139 This parameter can be a value of @ref FSMC_Extended_Mode */ 140 141 uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. 142 This parameter can be a value of @ref FSMC_Write_Burst */ 143 144 FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ 145 146 FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ 147 }FSMC_NORSRAMInitTypeDef; 148 149 /** 150 * @brief Timing parameters For FSMC NAND and PCCARD Banks 151 */ 152 typedef struct 153 { 154 uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before 155 the command assertion for NAND Flash read or write access 156 to common/Attribute or I/O memory space (depending on 157 the memory space timing to be configured). 158 This parameter can be a value between 0 and 0xFF.*/ 159 160 uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 161 command for NAND Flash read or write access to 162 common/Attribute or I/O memory space (depending on the 163 memory space timing to be configured). 164 This parameter can be a number between 0x00 and 0xFF */ 165 166 uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 167 (and data for write access) after the command de-assertion 168 for NAND Flash read or write access to common/Attribute 169 or I/O memory space (depending on the memory space timing 170 to be configured). 171 This parameter can be a number between 0x00 and 0xFF */ 172 173 uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 174 data bus is kept in HiZ after the start of a NAND Flash 175 write access to common/Attribute or I/O memory space (depending 176 on the memory space timing to be configured). 177 This parameter can be a number between 0x00 and 0xFF */ 178 }FSMC_NAND_PCCARDTimingInitTypeDef; 179 180 /** 181 * @brief FSMC NAND Init structure definition 182 */ 183 typedef struct 184 { 185 uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. 186 This parameter can be a value of @ref FSMC_NAND_Bank */ 187 188 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. 189 This parameter can be any value of @ref FSMC_Wait_feature */ 190 191 uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. 192 This parameter can be any value of @ref FSMC_Data_Width */ 193 194 uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. 195 This parameter can be any value of @ref FSMC_ECC */ 196 197 uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. 198 This parameter can be any value of @ref FSMC_ECC_Page_Size */ 199 200 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 201 delay between CLE low and RE low. 202 This parameter can be a value between 0 and 0xFF. */ 203 204 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 205 delay between ALE low and RE low. 206 This parameter can be a number between 0x0 and 0xFF */ 207 208 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ 209 210 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ 211 }FSMC_NANDInitTypeDef; 212 213 /** 214 * @brief FSMC PCCARD Init structure definition 215 */ 216 217 typedef struct 218 { 219 uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. 220 This parameter can be any value of @ref FSMC_Wait_feature */ 221 222 uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 223 delay between CLE low and RE low. 224 This parameter can be a value between 0 and 0xFF. */ 225 226 uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 227 delay between ALE low and RE low. 228 This parameter can be a number between 0x0 and 0xFF */ 229 230 231 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ 232 233 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ 234 235 FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ 236 }FSMC_PCCARDInitTypeDef; 237 238 /* Exported constants --------------------------------------------------------*/ 239 240 /** @defgroup FSMC_Exported_Constants 241 * @{ 242 */ 243 244 /** @defgroup FSMC_NORSRAM_Bank 245 * @{ 246 */ 247 #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) 248 #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) 249 #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) 250 #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) 251 /** 252 * @} 253 */ 254 255 /** @defgroup FSMC_NAND_Bank 256 * @{ 257 */ 258 #define FSMC_Bank2_NAND ((uint32_t)0x00000010) 259 #define FSMC_Bank3_NAND ((uint32_t)0x00000100) 260 /** 261 * @} 262 */ 263 264 /** @defgroup FSMC_PCCARD_Bank 265 * @{ 266 */ 267 #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) 268 /** 269 * @} 270 */ 271 272 #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ 273 ((BANK) == FSMC_Bank1_NORSRAM2) || \ 274 ((BANK) == FSMC_Bank1_NORSRAM3) || \ 275 ((BANK) == FSMC_Bank1_NORSRAM4)) 276 277 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ 278 ((BANK) == FSMC_Bank3_NAND)) 279 280 #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ 281 ((BANK) == FSMC_Bank3_NAND) || \ 282 ((BANK) == FSMC_Bank4_PCCARD)) 283 284 #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ 285 ((BANK) == FSMC_Bank3_NAND) || \ 286 ((BANK) == FSMC_Bank4_PCCARD)) 287 288 /** @defgroup FSMC_NOR_SRAM_Controller 289 * @{ 290 */ 291 292 /** @defgroup FSMC_Data_Address_Bus_Multiplexing 293 * @{ 294 */ 295 296 #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) 297 #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) 298 #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ 299 ((MUX) == FSMC_DataAddressMux_Enable)) 300 /** 301 * @} 302 */ 303 304 /** @defgroup FSMC_Memory_Type 305 * @{ 306 */ 307 308 #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) 309 #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) 310 #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) 311 #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ 312 ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ 313 ((MEMORY) == FSMC_MemoryType_NOR)) 314 /** 315 * @} 316 */ 317 318 /** @defgroup FSMC_Data_Width 319 * @{ 320 */ 321 322 #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) 323 #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) 324 #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ 325 ((WIDTH) == FSMC_MemoryDataWidth_16b)) 326 /** 327 * @} 328 */ 329 330 /** @defgroup FSMC_Burst_Access_Mode 331 * @{ 332 */ 333 334 #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) 335 #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) 336 #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ 337 ((STATE) == FSMC_BurstAccessMode_Enable)) 338 /** 339 * @} 340 */ 341 342 /** @defgroup FSMC_AsynchronousWait 343 * @{ 344 */ 345 #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) 346 #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) 347 #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ 348 ((STATE) == FSMC_AsynchronousWait_Enable)) 349 /** 350 * @} 351 */ 352 353 /** @defgroup FSMC_Wait_Signal_Polarity 354 * @{ 355 */ 356 #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) 357 #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) 358 #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ 359 ((POLARITY) == FSMC_WaitSignalPolarity_High)) 360 /** 361 * @} 362 */ 363 364 /** @defgroup FSMC_Wrap_Mode 365 * @{ 366 */ 367 #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) 368 #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) 369 #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ 370 ((MODE) == FSMC_WrapMode_Enable)) 371 /** 372 * @} 373 */ 374 375 /** @defgroup FSMC_Wait_Timing 376 * @{ 377 */ 378 #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) 379 #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) 380 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ 381 ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) 382 /** 383 * @} 384 */ 385 386 /** @defgroup FSMC_Write_Operation 387 * @{ 388 */ 389 #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) 390 #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) 391 #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ 392 ((OPERATION) == FSMC_WriteOperation_Enable)) 393 /** 394 * @} 395 */ 396 397 /** @defgroup FSMC_Wait_Signal 398 * @{ 399 */ 400 #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) 401 #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) 402 #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ 403 ((SIGNAL) == FSMC_WaitSignal_Enable)) 404 /** 405 * @} 406 */ 407 408 /** @defgroup FSMC_Extended_Mode 409 * @{ 410 */ 411 #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) 412 #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) 413 414 #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ 415 ((MODE) == FSMC_ExtendedMode_Enable)) 416 /** 417 * @} 418 */ 419 420 /** @defgroup FSMC_Write_Burst 421 * @{ 422 */ 423 424 #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) 425 #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) 426 #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ 427 ((BURST) == FSMC_WriteBurst_Enable)) 428 /** 429 * @} 430 */ 431 432 /** @defgroup FSMC_Address_Setup_Time 433 * @{ 434 */ 435 #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) 436 /** 437 * @} 438 */ 439 440 /** @defgroup FSMC_Address_Hold_Time 441 * @{ 442 */ 443 #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) 444 /** 445 * @} 446 */ 447 448 /** @defgroup FSMC_Data_Setup_Time 449 * @{ 450 */ 451 #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) 452 /** 453 * @} 454 */ 455 456 /** @defgroup FSMC_Bus_Turn_around_Duration 457 * @{ 458 */ 459 #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) 460 /** 461 * @} 462 */ 463 464 /** @defgroup FSMC_CLK_Division 465 * @{ 466 */ 467 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) 468 /** 469 * @} 470 */ 471 472 /** @defgroup FSMC_Data_Latency 473 * @{ 474 */ 475 #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) 476 /** 477 * @} 478 */ 479 480 /** @defgroup FSMC_Access_Mode 481 * @{ 482 */ 483 #define FSMC_AccessMode_A ((uint32_t)0x00000000) 484 #define FSMC_AccessMode_B ((uint32_t)0x10000000) 485 #define FSMC_AccessMode_C ((uint32_t)0x20000000) 486 #define FSMC_AccessMode_D ((uint32_t)0x30000000) 487 #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ 488 ((MODE) == FSMC_AccessMode_B) || \ 489 ((MODE) == FSMC_AccessMode_C) || \ 490 ((MODE) == FSMC_AccessMode_D)) 491 /** 492 * @} 493 */ 494 495 /** 496 * @} 497 */ 498 499 /** @defgroup FSMC_NAND_PCCARD_Controller 500 * @{ 501 */ 502 503 /** @defgroup FSMC_Wait_feature 504 * @{ 505 */ 506 #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) 507 #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) 508 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ 509 ((FEATURE) == FSMC_Waitfeature_Enable)) 510 /** 511 * @} 512 */ 513 514 515 /** @defgroup FSMC_ECC 516 * @{ 517 */ 518 #define FSMC_ECC_Disable ((uint32_t)0x00000000) 519 #define FSMC_ECC_Enable ((uint32_t)0x00000040) 520 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ 521 ((STATE) == FSMC_ECC_Enable)) 522 /** 523 * @} 524 */ 525 526 /** @defgroup FSMC_ECC_Page_Size 527 * @{ 528 */ 529 #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) 530 #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) 531 #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) 532 #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) 533 #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) 534 #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) 535 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ 536 ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ 537 ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ 538 ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ 539 ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ 540 ((SIZE) == FSMC_ECCPageSize_8192Bytes)) 541 /** 542 * @} 543 */ 544 545 /** @defgroup FSMC_TCLR_Setup_Time 546 * @{ 547 */ 548 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) 549 /** 550 * @} 551 */ 552 553 /** @defgroup FSMC_TAR_Setup_Time 554 * @{ 555 */ 556 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) 557 /** 558 * @} 559 */ 560 561 /** @defgroup FSMC_Setup_Time 562 * @{ 563 */ 564 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) 565 /** 566 * @} 567 */ 568 569 /** @defgroup FSMC_Wait_Setup_Time 570 * @{ 571 */ 572 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) 573 /** 574 * @} 575 */ 576 577 /** @defgroup FSMC_Hold_Setup_Time 578 * @{ 579 */ 580 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) 581 /** 582 * @} 583 */ 584 585 /** @defgroup FSMC_HiZ_Setup_Time 586 * @{ 587 */ 588 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) 589 /** 590 * @} 591 */ 592 593 /** @defgroup FSMC_Interrupt_sources 594 * @{ 595 */ 596 #define FSMC_IT_RisingEdge ((uint32_t)0x00000008) 597 #define FSMC_IT_Level ((uint32_t)0x00000010) 598 #define FSMC_IT_FallingEdge ((uint32_t)0x00000020) 599 #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) 600 #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ 601 ((IT) == FSMC_IT_Level) || \ 602 ((IT) == FSMC_IT_FallingEdge)) 603 /** 604 * @} 605 */ 606 607 /** @defgroup FSMC_Flags 608 * @{ 609 */ 610 #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) 611 #define FSMC_FLAG_Level ((uint32_t)0x00000002) 612 #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) 613 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) 614 #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ 615 ((FLAG) == FSMC_FLAG_Level) || \ 616 ((FLAG) == FSMC_FLAG_FallingEdge) || \ 617 ((FLAG) == FSMC_FLAG_FEMPT)) 618 619 #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) 620 /** 621 * @} 622 */ 623 624 /** 625 * @} 626 */ 627 628 /** 629 * @} 630 */ 631 632 /* Exported macro ------------------------------------------------------------*/ 633 /* Exported functions --------------------------------------------------------*/ 634 635 /* NOR/SRAM Controller functions **********************************************/ 636 void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); 637 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); 638 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); 639 void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); 640 641 /* NAND Controller functions **************************************************/ 642 void FSMC_NANDDeInit(uint32_t FSMC_Bank); 643 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); 644 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); 645 void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); 646 void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); 647 uint32_t FSMC_GetECC(uint32_t FSMC_Bank); 648 649 /* PCCARD Controller functions ************************************************/ 650 void FSMC_PCCARDDeInit(void); 651 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); 652 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); 653 void FSMC_PCCARDCmd(FunctionalState NewState); 654 655 /* Interrupts and flags management functions **********************************/ 656 void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); 657 FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); 658 void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); 659 ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); 660 void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); 661 662 #ifdef __cplusplus 663 } 664 #endif 665 666 #endif /*__STM32F4xx_FSMC_H */ 667 /** 668 * @} 669 */ 670 671 /** 672 * @} 673 */ 674 675 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 676