1 // 2 // Copyright (C) 2017 Alexey Khokholov (Nuke.YKT) 3 // 4 // This program is free software; you can redistribute it and/or 5 // modify it under the terms of the GNU General Public License 6 // as published by the Free Software Foundation; either version 2 7 // of the License, or (at your option) any later version. 8 // 9 // This program is distributed in the hope that it will be useful, 10 // but WITHOUT ANY WARRANTY; without even the implied warranty of 11 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 // GNU General Public License for more details. 13 // 14 // You should have received a copy of the GNU General Public License 15 // along with this program; if not, write to the Free Software 16 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 // 18 // 19 // Nuked OPN2(Yamaha YM3438) emulator. 20 // Thanks: 21 // Silicon Pr0n: 22 // Yamaha YM3438 decap and die shot(digshadow). 23 // OPLx decapsulated(Matthew Gambrell, Olli Niemitalo): 24 // OPL2 ROMs. 25 // 26 // version: 1.0.7 27 // 28 29 #ifndef YM3438_H 30 #define YM3438_H 31 32 #define RSM_FRAC 10 33 #define OPN_WRITEBUF_SIZE 2048 34 #define OPN_WRITEBUF_DELAY 15 35 36 enum { 37 ym3438_type_discrete = 0, /* Discrete YM3438 (Teradrive) */ 38 ym3438_type_asic = 1, /* ASIC YM3438 (MD1 VA7, MD2, MD3, etc) */ 39 ym3438_type_ym2612 = 2, /* YM2612 (MD1, MD2 VA2) */ 40 ym3438_type_ym2612_u = 3 /* YM2612 without lowpass filter */ 41 }; 42 43 #include "mamedef.h" 44 45 typedef UINT64 Bit64u; 46 typedef INT64 Bit64s; 47 typedef UINT32 Bit32u; 48 typedef INT32 Bit32s; 49 typedef UINT16 Bit16u; 50 typedef INT16 Bit16s; 51 typedef UINT8 Bit8u; 52 typedef INT8 Bit8s; 53 54 typedef struct _opn2_writebuf { 55 Bit64u time; 56 Bit8u port; 57 Bit8u data; 58 } opn2_writebuf; 59 60 typedef struct 61 { 62 Bit32u cycles; 63 Bit32u slot; 64 Bit32u channel; 65 Bit16s mol, mor; 66 /* IO */ 67 Bit16u write_data; 68 Bit8u write_a; 69 Bit8u write_d; 70 Bit8u write_a_en; 71 Bit8u write_d_en; 72 Bit8u write_busy; 73 Bit8u write_busy_cnt; 74 Bit8u write_fm_address; 75 Bit8u write_fm_data; 76 Bit8u write_fm_mode_a; 77 Bit16u address; 78 Bit8u data; 79 Bit8u pin_test_in; 80 Bit8u pin_irq; 81 Bit8u busy; 82 /* LFO */ 83 Bit8u lfo_en; 84 Bit8u lfo_freq; 85 Bit8u lfo_pm; 86 Bit8u lfo_am; 87 Bit8u lfo_cnt; 88 Bit8u lfo_inc; 89 Bit8u lfo_quotient; 90 /* Phase generator */ 91 Bit16u pg_fnum; 92 Bit8u pg_block; 93 Bit8u pg_kcode; 94 Bit32u pg_inc[24]; 95 Bit32u pg_phase[24]; 96 Bit8u pg_reset[24]; 97 Bit32u pg_read; 98 /* Envelope generator */ 99 Bit8u eg_cycle; 100 Bit8u eg_cycle_stop; 101 Bit8u eg_shift; 102 Bit8u eg_shift_lock; 103 Bit8u eg_timer_low_lock; 104 Bit16u eg_timer; 105 Bit8u eg_timer_inc; 106 Bit16u eg_quotient; 107 Bit8u eg_custom_timer; 108 Bit8u eg_rate; 109 Bit8u eg_ksv; 110 Bit8u eg_inc; 111 Bit8u eg_ratemax; 112 Bit8u eg_sl[2]; 113 Bit8u eg_lfo_am; 114 Bit8u eg_tl[2]; 115 Bit8u eg_state[24]; 116 Bit16u eg_level[24]; 117 Bit16u eg_out[24]; 118 Bit8u eg_kon[24]; 119 Bit8u eg_kon_csm[24]; 120 Bit8u eg_kon_latch[24]; 121 Bit8u eg_csm_mode[24]; 122 Bit8u eg_ssg_enable[24]; 123 Bit8u eg_ssg_pgrst_latch[24]; 124 Bit8u eg_ssg_repeat_latch[24]; 125 Bit8u eg_ssg_hold_up_latch[24]; 126 Bit8u eg_ssg_dir[24]; 127 Bit8u eg_ssg_inv[24]; 128 Bit32u eg_read[2]; 129 Bit8u eg_read_inc; 130 /* FM */ 131 Bit16s fm_op1[6][2]; 132 Bit16s fm_op2[6]; 133 Bit16s fm_out[24]; 134 Bit16u fm_mod[24]; 135 /* Channel */ 136 Bit16s ch_acc[6]; 137 Bit16s ch_out[6]; 138 Bit16s ch_lock; 139 Bit8u ch_lock_l; 140 Bit8u ch_lock_r; 141 Bit16s ch_read; 142 /* Timer */ 143 Bit16u timer_a_cnt; 144 Bit16u timer_a_reg; 145 Bit8u timer_a_load_lock; 146 Bit8u timer_a_load; 147 Bit8u timer_a_enable; 148 Bit8u timer_a_reset; 149 Bit8u timer_a_load_latch; 150 Bit8u timer_a_overflow_flag; 151 Bit8u timer_a_overflow; 152 153 Bit16u timer_b_cnt; 154 Bit8u timer_b_subcnt; 155 Bit16u timer_b_reg; 156 Bit8u timer_b_load_lock; 157 Bit8u timer_b_load; 158 Bit8u timer_b_enable; 159 Bit8u timer_b_reset; 160 Bit8u timer_b_load_latch; 161 Bit8u timer_b_overflow_flag; 162 Bit8u timer_b_overflow; 163 164 /* Register set */ 165 Bit8u mode_test_21[8]; 166 Bit8u mode_test_2c[8]; 167 Bit8u mode_ch3; 168 Bit8u mode_kon_channel; 169 Bit8u mode_kon_operator[4]; 170 Bit8u mode_kon[24]; 171 Bit8u mode_csm; 172 Bit8u mode_kon_csm; 173 Bit8u dacen; 174 Bit16s dacdata; 175 176 Bit8u ks[24]; 177 Bit8u ar[24]; 178 Bit8u sr[24]; 179 Bit8u dt[24]; 180 Bit8u multi[24]; 181 Bit8u sl[24]; 182 Bit8u rr[24]; 183 Bit8u dr[24]; 184 Bit8u am[24]; 185 Bit8u tl[24]; 186 Bit8u ssg_eg[24]; 187 188 Bit16u fnum[6]; 189 Bit8u block[6]; 190 Bit8u kcode[6]; 191 Bit16u fnum_3ch[6]; 192 Bit8u block_3ch[6]; 193 Bit8u kcode_3ch[6]; 194 Bit8u reg_a4; 195 Bit8u reg_ac; 196 Bit8u connect[6]; 197 Bit8u fb[6]; 198 Bit8u pan_l[6], pan_r[6]; 199 Bit8u ams[6]; 200 Bit8u pms[6]; 201 202 Bit32u mute[7]; 203 Bit32s rateratio; 204 Bit32s samplecnt; 205 Bit32s oldsamples[2]; 206 Bit32s samples[2]; 207 208 Bit64u writebuf_samplecnt; 209 Bit32u writebuf_cur; 210 Bit32u writebuf_last; 211 Bit64u writebuf_lasttime; 212 opn2_writebuf writebuf[OPN_WRITEBUF_SIZE]; 213 } ym3438_t; 214 215 void OPN2_Reset(ym3438_t *chip, Bit32u rate, Bit32u clock); 216 void OPN2_SetChipType(Bit32u type); 217 void OPN2_Clock(ym3438_t *chip, Bit32s *buffer); 218 void OPN2_Write(ym3438_t *chip, Bit32u port, Bit8u data); 219 void OPN2_SetTestPin(ym3438_t *chip, Bit32u value); 220 Bit32u OPN2_ReadTestPin(ym3438_t *chip); 221 Bit32u OPN2_ReadIRQPin(ym3438_t *chip); 222 Bit8u OPN2_Read(ym3438_t *chip, Bit32u port); 223 void OPN2_WriteBuffered(ym3438_t *chip, Bit32u port, Bit8u data); 224 void OPN2_GenerateStream(ym3438_t *chip, Bit32s **sndptr, Bit32u numsamples); 225 void OPN2_SetOptions(Bit8u flags); 226 void OPN2_SetMute(ym3438_t *chip, Bit32u mute); 227 #endif 228