1 /*
2 **
3 ** File: ymf262.c - software implementation of YMF262
4 ** FM sound generator type OPL3
5 **
6 ** Copyright Jarek Burczynski
7 **
8 ** Version 0.2
9 **
10
11 Revision History:
12
13 03-03-2003: initial release
14 - thanks to Olivier Galibert and Chris Hardy for YMF262 and YAC512 chips
15 - thanks to Stiletto for the datasheets
16
17 Features as listed in 4MF262A6 data sheet:
18 1. Registers are compatible with YM3812 (OPL2) FM sound source.
19 2. Up to six sounds can be used as four-operator melody sounds for variety.
20 3. 18 simultaneous melody sounds, or 15 melody sounds with 5 rhythm sounds (with two operators).
21 4. 6 four-operator melody sounds and 6 two-operator melody sounds, or 6 four-operator melody
22 sounds, 3 two-operator melody sounds and 5 rhythm sounds (with four operators).
23 5. 8 selectable waveforms.
24 6. 4-channel sound output.
25 7. YMF262 compabile DAC (YAC512) is available.
26 8. LFO for vibrato and tremolo effedts.
27 9. 2 programable timers.
28 10. Shorter register access time compared with YM3812.
29 11. 5V single supply silicon gate CMOS process.
30 12. 24 Pin SOP Package (YMF262-M), 48 Pin SQFP Package (YMF262-S).
31
32
33 differences between OPL2 and OPL3 not documented in Yamaha datahasheets:
34 - sinus table is a little different: the negative part is off by one...
35
36 - in order to enable selection of four different waveforms on OPL2
37 one must set bit 5 in register 0x01(test).
38 on OPL3 this bit is ignored and 4-waveform select works *always*.
39 (Don't confuse this with OPL3's 8-waveform select.)
40
41 - Envelope Generator: all 15 x rates take zero time on OPL3
42 (on OPL2 15 0 and 15 1 rates take some time while 15 2 and 15 3 rates
43 take zero time)
44
45 - channel calculations: output of operator 1 is in perfect sync with
46 output of operator 2 on OPL3; on OPL and OPL2 output of operator 1
47 is always delayed by one sample compared to output of operator 2
48
49
50 differences between OPL2 and OPL3 shown in datasheets:
51 - YMF262 does not support CSM mode
52
53
54 */
55
56 #include <math.h>
57 #include "mamedef.h"
58 #include <stdlib.h>
59 #include <string.h> // for memset
60 #include <stddef.h> // for NULL
61 //#include "sndintrf.h"
62 #include "ymf262.h"
63
64
65 /* output final shift */
66 #if (OPL3_SAMPLE_BITS==16)
67 #define FINAL_SH (0)
68 #define MAXOUT (+32767)
69 #define MINOUT (-32768)
70 #else
71 #define FINAL_SH (8)
72 #define MAXOUT (+127)
73 #define MINOUT (-128)
74 #endif
75
76
77 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
78 #define EG_SH 16 /* 16.16 fixed point (EG timing) */
79 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
80 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
81
82 #define FREQ_MASK ((1<<FREQ_SH)-1)
83
84 /* envelope output entries */
85 #define ENV_BITS 10
86 #define ENV_LEN (1<<ENV_BITS)
87 #define ENV_STEP (128.0/ENV_LEN)
88
89 #define MAX_ATT_INDEX ((1<<(ENV_BITS-1))-1) /*511*/
90 #define MIN_ATT_INDEX (0)
91
92 /* sinwave entries */
93 #define SIN_BITS 10
94 #define SIN_LEN (1<<SIN_BITS)
95 #define SIN_MASK (SIN_LEN-1)
96
97 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
98
99
100
101 /* register number to channel number , slot offset */
102 #define SLOT1 0
103 #define SLOT2 1
104
105 /* Envelope Generator phases */
106
107 #define EG_ATT 4
108 #define EG_DEC 3
109 #define EG_SUS 2
110 #define EG_REL 1
111 #define EG_OFF 0
112
113
114 /* save output as raw 16-bit sample */
115
116 /*#define SAVE_SAMPLE*/
117
118 #ifdef SAVE_SAMPLE
119 static FILE *sample[1];
120 #if 1 /*save to MONO file */
121 #define SAVE_ALL_CHANNELS \
122 { signed int pom = a; \
123 fputc((unsigned short)pom&0xff,sample[0]); \
124 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
125 }
126 #else /*save to STEREO file */
127 #define SAVE_ALL_CHANNELS \
128 { signed int pom = a; \
129 fputc((unsigned short)pom&0xff,sample[0]); \
130 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
131 pom = b; \
132 fputc((unsigned short)pom&0xff,sample[0]); \
133 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
134 }
135 #endif
136 #endif
137
138 //#define LOG_CYM_FILE 0
139 //static FILE * cymfile = NULL;
140
141
142
143
144
145 #define OPL3_TYPE_YMF262 (0) /* 36 operators, 8 waveforms */
146
147
148 typedef struct{
149 UINT32 ar; /* attack rate: AR<<2 */
150 UINT32 dr; /* decay rate: DR<<2 */
151 UINT32 rr; /* release rate:RR<<2 */
152 UINT8 KSR; /* key scale rate */
153 UINT8 ksl; /* keyscale level */
154 UINT8 ksr; /* key scale rate: kcode>>KSR */
155 UINT8 mul; /* multiple: mul_tab[ML] */
156
157 /* Phase Generator */
158 UINT32 Cnt; /* frequency counter */
159 UINT32 Incr; /* frequency counter step */
160 UINT8 FB; /* feedback shift value */
161 INT32 *connect; /* slot output pointer */
162 INT32 op1_out[2]; /* slot1 output for feedback */
163 UINT8 CON; /* connection (algorithm) type */
164
165 /* Envelope Generator */
166 UINT8 eg_type; /* percussive/non-percussive mode */
167 UINT8 state; /* phase type */
168 UINT32 TL; /* total level: TL << 2 */
169 INT32 TLL; /* adjusted now TL */
170 INT32 volume; /* envelope counter */
171 UINT32 sl; /* sustain level: sl_tab[SL] */
172
173 UINT32 eg_m_ar; /* (attack state) */
174 UINT8 eg_sh_ar; /* (attack state) */
175 UINT8 eg_sel_ar; /* (attack state) */
176 UINT32 eg_m_dr; /* (decay state) */
177 UINT8 eg_sh_dr; /* (decay state) */
178 UINT8 eg_sel_dr; /* (decay state) */
179 UINT32 eg_m_rr; /* (release state) */
180 UINT8 eg_sh_rr; /* (release state) */
181 UINT8 eg_sel_rr; /* (release state) */
182
183 UINT32 key; /* 0 = KEY OFF, >0 = KEY ON */
184
185 /* LFO */
186 UINT32 AMmask; /* LFO Amplitude Modulation enable mask */
187 UINT8 vib; /* LFO Phase Modulation enable flag (active high)*/
188
189 /* waveform select */
190 UINT8 waveform_number;
191 unsigned int wavetable;
192
193 //unsigned char reserved[128-84];//speedup: pump up the struct size to power of 2
194 unsigned char reserved[128-100];//speedup: pump up the struct size to power of 2
195
196 } OPL3_SLOT;
197
198 typedef struct{
199 OPL3_SLOT SLOT[2];
200
201 UINT32 block_fnum; /* block+fnum */
202 UINT32 fc; /* Freq. Increment base */
203 UINT32 ksl_base; /* KeyScaleLevel Base step */
204 UINT8 kcode; /* key code (for key scaling) */
205
206 /*
207 there are 12 2-operator channels which can be combined in pairs
208 to form six 4-operator channel, they are:
209 0 and 3,
210 1 and 4,
211 2 and 5,
212 9 and 12,
213 10 and 13,
214 11 and 14
215 */
216 UINT8 extended; /* set to 1 if this channel forms up a 4op channel with another channel(only used by first of pair of channels, ie 0,1,2 and 9,10,11) */
217 UINT8 Muted;
218
219 unsigned char reserved[512-272];//speedup:pump up the struct size to power of 2
220
221 } OPL3_CH;
222
223 /* OPL3 state */
224 typedef struct {
225 OPL3_CH P_CH[18]; /* OPL3 chips have 18 channels */
226
227 UINT32 pan[18*4]; /* channels output masks (0xffffffff = enable); 4 masks per one channel */
228 UINT32 pan_ctrl_value[18]; /* output control values 1 per one channel (1 value contains 4 masks) */
229 UINT8 MuteSpc[5]; /* for the 5 Rhythm Channels */
230
231 signed int chanout[18]; /* 18 channels */
232 signed int phase_modulation; /* phase modulation input (SLOT 2) */
233 signed int phase_modulation2; /* phase modulation input (SLOT 3 in 4 operator channels) */
234
235 UINT32 eg_cnt; /* global envelope generator counter */
236 UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/288 (288=8*36) */
237 UINT32 eg_timer_add; /* step of eg_timer */
238 UINT32 eg_timer_overflow; /* envelope generator timer overlfows every 1 sample (on real chip) */
239
240 UINT32 fn_tab[1024]; /* fnumber->increment counter */
241
242 /* LFO */
243 UINT32 LFO_AM;
244 INT32 LFO_PM;
245 UINT8 lfo_am_depth;
246 UINT8 lfo_pm_depth_range;
247 UINT32 lfo_am_cnt;
248 UINT32 lfo_am_inc;
249 UINT32 lfo_pm_cnt;
250 UINT32 lfo_pm_inc;
251
252 UINT32 noise_rng; /* 23 bit noise shift register */
253 UINT32 noise_p; /* current noise 'phase' */
254 UINT32 noise_f; /* current noise period */
255
256 UINT8 OPL3_mode; /* OPL3 extension enable flag */
257
258 UINT8 rhythm; /* Rhythm mode */
259
260 int T[2]; /* timer counters */
261 UINT8 st[2]; /* timer enable */
262
263 UINT32 address; /* address register */
264 UINT8 status; /* status flag */
265 UINT8 statusmask; /* status mask */
266
267 UINT8 nts; /* NTS (note select) */
268
269 /* external event callback handlers */
270 OPL3_TIMERHANDLER timer_handler;/* TIMER handler */
271 void *TimerParam; /* TIMER parameter */
272 OPL3_IRQHANDLER IRQHandler; /* IRQ handler */
273 void *IRQParam; /* IRQ parameter */
274 OPL3_UPDATEHANDLER UpdateHandler;/* stream update handler */
275 void *UpdateParam; /* stream update parameter */
276
277 UINT8 type; /* chip type */
278 int clock; /* master clock (Hz) */
279 int rate; /* sampling rate (Hz) */
280 double freqbase; /* frequency base */
281 //attotime TimerBase; /* Timer base time (==sampling time)*/
282 } OPL3;
283
284
285
286 /* mapping of register number (offset) to slot number used by the emulator */
287 static const int slot_array[32]=
288 {
289 0, 2, 4, 1, 3, 5,-1,-1,
290 6, 8,10, 7, 9,11,-1,-1,
291 12,14,16,13,15,17,-1,-1,
292 -1,-1,-1,-1,-1,-1,-1,-1
293 };
294
295 /* key scale level */
296 /* table is 3dB/octave , DV converts this into 6dB/octave */
297 /* 0.1875 is bit 0 weight of the envelope counter (volume) expressed in the 'decibel' scale */
298 #define DV (0.1875/2.0)
299 static const UINT32 ksl_tab[8*16]=
300 {
301 /* OCT 0 */
302 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
303 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
304 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
305 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
306 /* OCT 1 */
307 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
308 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
309 0.000/DV, 0.750/DV, 1.125/DV, 1.500/DV,
310 1.875/DV, 2.250/DV, 2.625/DV, 3.000/DV,
311 /* OCT 2 */
312 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
313 0.000/DV, 1.125/DV, 1.875/DV, 2.625/DV,
314 3.000/DV, 3.750/DV, 4.125/DV, 4.500/DV,
315 4.875/DV, 5.250/DV, 5.625/DV, 6.000/DV,
316 /* OCT 3 */
317 0.000/DV, 0.000/DV, 0.000/DV, 1.875/DV,
318 3.000/DV, 4.125/DV, 4.875/DV, 5.625/DV,
319 6.000/DV, 6.750/DV, 7.125/DV, 7.500/DV,
320 7.875/DV, 8.250/DV, 8.625/DV, 9.000/DV,
321 /* OCT 4 */
322 0.000/DV, 0.000/DV, 3.000/DV, 4.875/DV,
323 6.000/DV, 7.125/DV, 7.875/DV, 8.625/DV,
324 9.000/DV, 9.750/DV,10.125/DV,10.500/DV,
325 10.875/DV,11.250/DV,11.625/DV,12.000/DV,
326 /* OCT 5 */
327 0.000/DV, 3.000/DV, 6.000/DV, 7.875/DV,
328 9.000/DV,10.125/DV,10.875/DV,11.625/DV,
329 12.000/DV,12.750/DV,13.125/DV,13.500/DV,
330 13.875/DV,14.250/DV,14.625/DV,15.000/DV,
331 /* OCT 6 */
332 0.000/DV, 6.000/DV, 9.000/DV,10.875/DV,
333 12.000/DV,13.125/DV,13.875/DV,14.625/DV,
334 15.000/DV,15.750/DV,16.125/DV,16.500/DV,
335 16.875/DV,17.250/DV,17.625/DV,18.000/DV,
336 /* OCT 7 */
337 0.000/DV, 9.000/DV,12.000/DV,13.875/DV,
338 15.000/DV,16.125/DV,16.875/DV,17.625/DV,
339 18.000/DV,18.750/DV,19.125/DV,19.500/DV,
340 19.875/DV,20.250/DV,20.625/DV,21.000/DV
341 };
342 #undef DV
343
344 /* 0 / 3.0 / 1.5 / 6.0 dB/OCT */
345 static const UINT32 ksl_shift[4] = { 31, 1, 2, 0 };
346
347
348 /* sustain level table (3dB per step) */
349 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
350 #define SC(db) (UINT32) ( db * (2.0/ENV_STEP) )
351 static const UINT32 sl_tab[16]={
352 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
353 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
354 };
355 #undef SC
356
357
358 #define RATE_STEPS (8)
359 static const unsigned char eg_inc[15*RATE_STEPS]={
360
361 /*cycle:0 1 2 3 4 5 6 7*/
362
363 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
364 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
365 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
366 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
367
368 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
369 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
370 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
371 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
372
373 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
374 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
375 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
376 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
377
378 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 for decay */
379 /*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 for attack (zero time) */
380 /*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
381 };
382
383
384 #define O(a) (a*RATE_STEPS)
385
386 /* note that there is no O(13) in this table - it's directly in the code */
387 static const unsigned char eg_rate_select[16+64+16]={ /* Envelope Generator rates (16 + 64 rates + 16 RKS) */
388 /* 16 infinite time rates */
389 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
390 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
391
392 /* rates 00-12 */
393 O( 0),O( 1),O( 2),O( 3),
394 O( 0),O( 1),O( 2),O( 3),
395 O( 0),O( 1),O( 2),O( 3),
396 O( 0),O( 1),O( 2),O( 3),
397 O( 0),O( 1),O( 2),O( 3),
398 O( 0),O( 1),O( 2),O( 3),
399 O( 0),O( 1),O( 2),O( 3),
400 O( 0),O( 1),O( 2),O( 3),
401 O( 0),O( 1),O( 2),O( 3),
402 O( 0),O( 1),O( 2),O( 3),
403 O( 0),O( 1),O( 2),O( 3),
404 O( 0),O( 1),O( 2),O( 3),
405 O( 0),O( 1),O( 2),O( 3),
406
407 /* rate 13 */
408 O( 4),O( 5),O( 6),O( 7),
409
410 /* rate 14 */
411 O( 8),O( 9),O(10),O(11),
412
413 /* rate 15 */
414 O(12),O(12),O(12),O(12),
415
416 /* 16 dummy rates (same as 15 3) */
417 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
418 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
419
420 };
421 #undef O
422
423 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
424 /*shift 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0 */
425 /*mask 4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0 */
426
427 #define O(a) (a*1)
428 static const unsigned char eg_rate_shift[16+64+16]={ /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */
429 /* 16 infinite time rates */
430 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
431 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
432
433 /* rates 00-12 */
434 O(12),O(12),O(12),O(12),
435 O(11),O(11),O(11),O(11),
436 O(10),O(10),O(10),O(10),
437 O( 9),O( 9),O( 9),O( 9),
438 O( 8),O( 8),O( 8),O( 8),
439 O( 7),O( 7),O( 7),O( 7),
440 O( 6),O( 6),O( 6),O( 6),
441 O( 5),O( 5),O( 5),O( 5),
442 O( 4),O( 4),O( 4),O( 4),
443 O( 3),O( 3),O( 3),O( 3),
444 O( 2),O( 2),O( 2),O( 2),
445 O( 1),O( 1),O( 1),O( 1),
446 O( 0),O( 0),O( 0),O( 0),
447
448 /* rate 13 */
449 O( 0),O( 0),O( 0),O( 0),
450
451 /* rate 14 */
452 O( 0),O( 0),O( 0),O( 0),
453
454 /* rate 15 */
455 O( 0),O( 0),O( 0),O( 0),
456
457 /* 16 dummy rates (same as 15 3) */
458 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
459 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
460
461 };
462 #undef O
463
464
465 /* multiple table */
466 #define ML 2
467 static const UINT8 mul_tab[16]= {
468 /* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,12,12,15,15 */
469 0.50*ML, 1.00*ML, 2.00*ML, 3.00*ML, 4.00*ML, 5.00*ML, 6.00*ML, 7.00*ML,
470 8.00*ML, 9.00*ML,10.00*ML,10.00*ML,12.00*ML,12.00*ML,15.00*ML,15.00*ML
471 };
472 #undef ML
473
474 /* TL_TAB_LEN is calculated as:
475
476 * (12+1)=13 - sinus amplitude bits (Y axis)
477 * additional 1: to compensate for calculations of negative part of waveform
478 * (if we don't add it then the greatest possible _negative_ value would be -2
479 * and we really need -1 for waveform #7)
480 * 2 - sinus sign bit (Y axis)
481 * TL_RES_LEN - sinus resolution (X axis)
482 */
483 #define TL_TAB_LEN (13*2*TL_RES_LEN)
484 static signed int tl_tab[TL_TAB_LEN];
485
486 #define ENV_QUIET (TL_TAB_LEN>>4)
487
488 /* sin waveform table in 'decibel' scale */
489 /* there are eight waveforms on OPL3 chips */
490 static unsigned int sin_tab[SIN_LEN * 8];
491
492
493 /* LFO Amplitude Modulation table (verified on real YM3812)
494 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples
495
496 Length: 210 elements.
497
498 Each of the elements has to be repeated
499 exactly 64 times (on 64 consecutive samples).
500 The whole table takes: 64 * 210 = 13440 samples.
501
502 When AM = 1 data is used directly
503 When AM = 0 data is divided by 4 before being used (losing precision is important)
504 */
505
506 #define LFO_AM_TAB_ELEMENTS 210
507
508 static const UINT8 lfo_am_table[LFO_AM_TAB_ELEMENTS] = {
509 0,0,0,0,0,0,0,
510 1,1,1,1,
511 2,2,2,2,
512 3,3,3,3,
513 4,4,4,4,
514 5,5,5,5,
515 6,6,6,6,
516 7,7,7,7,
517 8,8,8,8,
518 9,9,9,9,
519 10,10,10,10,
520 11,11,11,11,
521 12,12,12,12,
522 13,13,13,13,
523 14,14,14,14,
524 15,15,15,15,
525 16,16,16,16,
526 17,17,17,17,
527 18,18,18,18,
528 19,19,19,19,
529 20,20,20,20,
530 21,21,21,21,
531 22,22,22,22,
532 23,23,23,23,
533 24,24,24,24,
534 25,25,25,25,
535 26,26,26,
536 25,25,25,25,
537 24,24,24,24,
538 23,23,23,23,
539 22,22,22,22,
540 21,21,21,21,
541 20,20,20,20,
542 19,19,19,19,
543 18,18,18,18,
544 17,17,17,17,
545 16,16,16,16,
546 15,15,15,15,
547 14,14,14,14,
548 13,13,13,13,
549 12,12,12,12,
550 11,11,11,11,
551 10,10,10,10,
552 9,9,9,9,
553 8,8,8,8,
554 7,7,7,7,
555 6,6,6,6,
556 5,5,5,5,
557 4,4,4,4,
558 3,3,3,3,
559 2,2,2,2,
560 1,1,1,1
561 };
562
563 /* LFO Phase Modulation table (verified on real YM3812) */
564 static const INT8 lfo_pm_table[8*8*2] = {
565
566 /* FNUM2/FNUM = 00 0xxxxxxx (0x0000) */
567 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
568 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 1*/
569
570 /* FNUM2/FNUM = 00 1xxxxxxx (0x0080) */
571 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
572 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 1*/
573
574 /* FNUM2/FNUM = 01 0xxxxxxx (0x0100) */
575 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
576 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 1*/
577
578 /* FNUM2/FNUM = 01 1xxxxxxx (0x0180) */
579 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
580 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 1*/
581
582 /* FNUM2/FNUM = 10 0xxxxxxx (0x0200) */
583 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
584 4, 2, 0,-2,-4,-2, 0, 2, /*LFO PM depth = 1*/
585
586 /* FNUM2/FNUM = 10 1xxxxxxx (0x0280) */
587 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
588 5, 2, 0,-2,-5,-2, 0, 2, /*LFO PM depth = 1*/
589
590 /* FNUM2/FNUM = 11 0xxxxxxx (0x0300) */
591 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
592 6, 3, 0,-3,-6,-3, 0, 3, /*LFO PM depth = 1*/
593
594 /* FNUM2/FNUM = 11 1xxxxxxx (0x0380) */
595 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
596 7, 3, 0,-3,-7,-3, 0, 3 /*LFO PM depth = 1*/
597 };
598
599
600 /* lock level of common table */
601 static int num_lock = 0;
602
603 /* work table */
604 #define SLOT7_1 (&chip->P_CH[7].SLOT[SLOT1])
605 #define SLOT7_2 (&chip->P_CH[7].SLOT[SLOT2])
606 #define SLOT8_1 (&chip->P_CH[8].SLOT[SLOT1])
607 #define SLOT8_2 (&chip->P_CH[8].SLOT[SLOT2])
608
609
610
611 /*INLINE int limit( int val, int max, int min ) {
612 if ( val > max )
613 val = max;
614 else if ( val < min )
615 val = min;
616
617 return val;
618 }*/
619
620
621 /* status set and IRQ handling */
OPL3_STATUS_SET(OPL3 * chip,int flag)622 INLINE void OPL3_STATUS_SET(OPL3 *chip,int flag)
623 {
624 /* set status flag masking out disabled IRQs */
625 chip->status |= (flag & chip->statusmask);
626 if(!(chip->status & 0x80))
627 {
628 if(chip->status & 0x7f)
629 { /* IRQ on */
630 chip->status |= 0x80;
631 /* callback user interrupt handler (IRQ is OFF to ON) */
632 if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,1);
633 }
634 }
635 }
636
637 /* status reset and IRQ handling */
OPL3_STATUS_RESET(OPL3 * chip,int flag)638 INLINE void OPL3_STATUS_RESET(OPL3 *chip,int flag)
639 {
640 /* reset status flag */
641 chip->status &= ~flag;
642 if(chip->status & 0x80)
643 {
644 if (!(chip->status & 0x7f))
645 {
646 chip->status &= 0x7f;
647 /* callback user interrupt handler (IRQ is ON to OFF) */
648 if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,0);
649 }
650 }
651 }
652
653 /* IRQ mask set */
OPL3_STATUSMASK_SET(OPL3 * chip,int flag)654 INLINE void OPL3_STATUSMASK_SET(OPL3 *chip,int flag)
655 {
656 chip->statusmask = flag;
657 /* IRQ handling check */
658 OPL3_STATUS_SET(chip,0);
659 OPL3_STATUS_RESET(chip,0);
660 }
661
662
663 /* advance LFO to next sample */
advance_lfo(OPL3 * chip)664 INLINE void advance_lfo(OPL3 *chip)
665 {
666 UINT8 tmp;
667
668 /* LFO */
669 chip->lfo_am_cnt += chip->lfo_am_inc;
670 if (chip->lfo_am_cnt >= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH) ) /* lfo_am_table is 210 elements long */
671 chip->lfo_am_cnt -= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH);
672
673 tmp = lfo_am_table[ chip->lfo_am_cnt >> LFO_SH ];
674
675 if (chip->lfo_am_depth)
676 chip->LFO_AM = tmp;
677 else
678 chip->LFO_AM = tmp>>2;
679
680 chip->lfo_pm_cnt += chip->lfo_pm_inc;
681 chip->LFO_PM = ((chip->lfo_pm_cnt>>LFO_SH) & 7) | chip->lfo_pm_depth_range;
682 }
683
684 /* advance to next sample */
advance(OPL3 * chip)685 INLINE void advance(OPL3 *chip)
686 {
687 OPL3_CH *CH;
688 OPL3_SLOT *op;
689 int i;
690
691 chip->eg_timer += chip->eg_timer_add;
692
693 while (chip->eg_timer >= chip->eg_timer_overflow)
694 {
695 chip->eg_timer -= chip->eg_timer_overflow;
696
697 chip->eg_cnt++;
698
699 for (i=0; i<9*2*2; i++)
700 {
701 CH = &chip->P_CH[i/2];
702 op = &CH->SLOT[i&1];
703 #if 1
704 /* Envelope Generator */
705 switch(op->state)
706 {
707 case EG_ATT: /* attack phase */
708 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
709 if ( !(chip->eg_cnt & op->eg_m_ar) )
710 {
711 op->volume += (~op->volume *
712 (eg_inc[op->eg_sel_ar + ((chip->eg_cnt>>op->eg_sh_ar)&7)])
713 ) >>3;
714
715 if (op->volume <= MIN_ATT_INDEX)
716 {
717 op->volume = MIN_ATT_INDEX;
718 op->state = EG_DEC;
719 }
720
721 }
722 break;
723
724 case EG_DEC: /* decay phase */
725 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
726 if ( !(chip->eg_cnt & op->eg_m_dr) )
727 {
728 op->volume += eg_inc[op->eg_sel_dr + ((chip->eg_cnt>>op->eg_sh_dr)&7)];
729
730 if ( op->volume >= op->sl )
731 op->state = EG_SUS;
732
733 }
734 break;
735
736 case EG_SUS: /* sustain phase */
737
738 /* this is important behaviour:
739 one can change percusive/non-percussive modes on the fly and
740 the chip will remain in sustain phase - verified on real YM3812 */
741
742 if(op->eg_type) /* non-percussive mode */
743 {
744 /* do nothing */
745 }
746 else /* percussive mode */
747 {
748 /* during sustain phase chip adds Release Rate (in percussive mode) */
749 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
750 if ( !(chip->eg_cnt & op->eg_m_rr) )
751 {
752 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
753
754 if ( op->volume >= MAX_ATT_INDEX )
755 op->volume = MAX_ATT_INDEX;
756 }
757 /* else do nothing in sustain phase */
758 }
759 break;
760
761 case EG_REL: /* release phase */
762 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
763 if ( !(chip->eg_cnt & op->eg_m_rr) )
764 {
765 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
766
767 if ( op->volume >= MAX_ATT_INDEX )
768 {
769 op->volume = MAX_ATT_INDEX;
770 op->state = EG_OFF;
771 }
772
773 }
774 break;
775
776 default:
777 break;
778 }
779 #endif
780 }
781 }
782
783 for (i=0; i<9*2*2; i++)
784 {
785 CH = &chip->P_CH[i/2];
786 op = &CH->SLOT[i&1];
787
788 /* Phase Generator */
789 if(op->vib)
790 {
791 UINT8 block;
792 unsigned int block_fnum = CH->block_fnum;
793
794 unsigned int fnum_lfo = (block_fnum&0x0380) >> 7;
795
796 signed int lfo_fn_table_index_offset = lfo_pm_table[chip->LFO_PM + 16*fnum_lfo ];
797
798 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
799 {
800 block_fnum += lfo_fn_table_index_offset;
801 block = (block_fnum&0x1c00) >> 10;
802 op->Cnt += (chip->fn_tab[block_fnum&0x03ff] >> (7-block)) * op->mul;
803 }
804 else /* LFO phase modulation = zero */
805 {
806 op->Cnt += op->Incr;
807 }
808 }
809 else /* LFO phase modulation disabled for this operator */
810 {
811 op->Cnt += op->Incr;
812 }
813 }
814
815 /* The Noise Generator of the YM3812 is 23-bit shift register.
816 * Period is equal to 2^23-2 samples.
817 * Register works at sampling frequency of the chip, so output
818 * can change on every sample.
819 *
820 * Output of the register and input to the bit 22 is:
821 * bit0 XOR bit14 XOR bit15 XOR bit22
822 *
823 * Simply use bit 22 as the noise output.
824 */
825
826 chip->noise_p += chip->noise_f;
827 i = chip->noise_p >> FREQ_SH; /* number of events (shifts of the shift register) */
828 chip->noise_p &= FREQ_MASK;
829 while (i)
830 {
831 /*
832 UINT32 j;
833 j = ( (chip->noise_rng) ^ (chip->noise_rng>>14) ^ (chip->noise_rng>>15) ^ (chip->noise_rng>>22) ) & 1;
834 chip->noise_rng = (j<<22) | (chip->noise_rng>>1);
835 */
836
837 /*
838 Instead of doing all the logic operations above, we
839 use a trick here (and use bit 0 as the noise output).
840 The difference is only that the noise bit changes one
841 step ahead. This doesn't matter since we don't know
842 what is real state of the noise_rng after the reset.
843 */
844
845 if (chip->noise_rng & 1) chip->noise_rng ^= 0x800302;
846 chip->noise_rng >>= 1;
847
848 i--;
849 }
850 }
851
852
op_calc(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)853 INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
854 {
855 UINT32 p;
856
857 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + (pm<<16))) >> FREQ_SH ) & SIN_MASK) ];
858
859 if (p >= TL_TAB_LEN)
860 return 0;
861 return tl_tab[p];
862 }
863
op_calc1(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)864 INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
865 {
866 UINT32 p;
867
868 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + pm))>>FREQ_SH) & SIN_MASK)];
869
870 if (p >= TL_TAB_LEN)
871 return 0;
872 return tl_tab[p];
873 }
874
875
876 #define volume_calc(OP) ((OP)->TLL + ((UINT32)(OP)->volume) + (chip->LFO_AM & (OP)->AMmask))
877
878 /* calculate output of a standard 2 operator channel
879 (or 1st part of a 4-op channel) */
chan_calc(OPL3 * chip,OPL3_CH * CH)880 INLINE void chan_calc( OPL3 *chip, OPL3_CH *CH )
881 {
882 OPL3_SLOT *SLOT;
883 unsigned int env;
884 signed int out;
885
886 if (CH->Muted)
887 return;
888
889 chip->phase_modulation = 0;
890 chip->phase_modulation2= 0;
891
892 /* SLOT 1 */
893 SLOT = &CH->SLOT[SLOT1];
894 env = volume_calc(SLOT);
895 out = SLOT->op1_out[0] + SLOT->op1_out[1];
896 SLOT->op1_out[0] = SLOT->op1_out[1];
897 SLOT->op1_out[1] = 0;
898 if( env < ENV_QUIET )
899 {
900 if (!SLOT->FB)
901 out = 0;
902 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
903 }
904 *SLOT->connect += SLOT->op1_out[1];
905 //logerror("out0=%5i vol0=%4i ", SLOT->op1_out[1], env );
906
907 /* SLOT 2 */
908 SLOT++;
909 env = volume_calc(SLOT);
910 if( env < ENV_QUIET )
911 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable);
912
913 //logerror("out1=%5i vol1=%4i\n", op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable), env );
914
915 }
916
917 /* calculate output of a 2nd part of 4-op channel */
chan_calc_ext(OPL3 * chip,OPL3_CH * CH)918 INLINE void chan_calc_ext( OPL3 *chip, OPL3_CH *CH )
919 {
920 OPL3_SLOT *SLOT;
921 unsigned int env;
922
923 if (CH->Muted)
924 return;
925
926 chip->phase_modulation = 0;
927
928 /* SLOT 1 */
929 SLOT = &CH->SLOT[SLOT1];
930 env = volume_calc(SLOT);
931 if( env < ENV_QUIET )
932 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation2, SLOT->wavetable );
933
934 /* SLOT 2 */
935 SLOT++;
936 env = volume_calc(SLOT);
937 if( env < ENV_QUIET )
938 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable);
939
940 }
941
942 /*
943 operators used in the rhythm sounds generation process:
944
945 Envelope Generator:
946
947 channel operator register number Bass High Snare Tom Top
948 / slot number TL ARDR SLRR Wave Drum Hat Drum Tom Cymbal
949 6 / 0 12 50 70 90 f0 +
950 6 / 1 15 53 73 93 f3 +
951 7 / 0 13 51 71 91 f1 +
952 7 / 1 16 54 74 94 f4 +
953 8 / 0 14 52 72 92 f2 +
954 8 / 1 17 55 75 95 f5 +
955
956 Phase Generator:
957
958 channel operator register number Bass High Snare Tom Top
959 / slot number MULTIPLE Drum Hat Drum Tom Cymbal
960 6 / 0 12 30 +
961 6 / 1 15 33 +
962 7 / 0 13 31 + + +
963 7 / 1 16 34 ----- n o t u s e d -----
964 8 / 0 14 32 +
965 8 / 1 17 35 + +
966
967 channel operator register number Bass High Snare Tom Top
968 number number BLK/FNUM2 FNUM Drum Hat Drum Tom Cymbal
969 6 12,15 B6 A6 +
970
971 7 13,16 B7 A7 + + +
972
973 8 14,17 B8 A8 + + +
974
975 */
976
977 /* calculate rhythm */
978
chan_calc_rhythm(OPL3 * chip,OPL3_CH * CH,unsigned int noise)979 INLINE void chan_calc_rhythm( OPL3 *chip, OPL3_CH *CH, unsigned int noise )
980 {
981 OPL3_SLOT *SLOT;
982 signed int *chanout = chip->chanout;
983 signed int out;
984 unsigned int env;
985
986
987 /* Bass Drum (verified on real YM3812):
988 - depends on the channel 6 'connect' register:
989 when connect = 0 it works the same as in normal (non-rhythm) mode (op1->op2->out)
990 when connect = 1 _only_ operator 2 is present on output (op2->out), operator 1 is ignored
991 - output sample always is multiplied by 2
992 */
993
994 chip->phase_modulation = 0;
995
996 /* SLOT 1 */
997 SLOT = &CH[6].SLOT[SLOT1];
998 env = volume_calc(SLOT);
999
1000 out = SLOT->op1_out[0] + SLOT->op1_out[1];
1001 SLOT->op1_out[0] = SLOT->op1_out[1];
1002
1003 if (!SLOT->CON)
1004 chip->phase_modulation = SLOT->op1_out[0];
1005 //else ignore output of operator 1
1006
1007 SLOT->op1_out[1] = 0;
1008 if( env < ENV_QUIET )
1009 {
1010 if (!SLOT->FB)
1011 out = 0;
1012 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
1013 }
1014
1015 /* SLOT 2 */
1016 SLOT++;
1017 env = volume_calc(SLOT);
1018 if( env < ENV_QUIET && ! chip->MuteSpc[0] )
1019 chanout[6] += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable) * 2;
1020
1021
1022 /* Phase generation is based on: */
1023 // HH (13) channel 7->slot 1 combined with channel 8->slot 2 (same combination as TOP CYMBAL but different output phases)
1024 // SD (16) channel 7->slot 1
1025 // TOM (14) channel 8->slot 1
1026 // TOP (17) channel 7->slot 1 combined with channel 8->slot 2 (same combination as HIGH HAT but different output phases)
1027
1028 /* Envelope generation based on: */
1029 // HH channel 7->slot1
1030 // SD channel 7->slot2
1031 // TOM channel 8->slot1
1032 // TOP channel 8->slot2
1033
1034
1035 /* The following formulas can be well optimized.
1036 I leave them in direct form for now (in case I've missed something).
1037 */
1038
1039 /* High Hat (verified on real YM3812) */
1040 env = volume_calc(SLOT7_1);
1041 if( env < ENV_QUIET && ! chip->MuteSpc[4] )
1042 {
1043
1044 /* high hat phase generation:
1045 phase = d0 or 234 (based on frequency only)
1046 phase = 34 or 2d0 (based on noise)
1047 */
1048
1049 /* base frequency derived from operator 1 in channel 7 */
1050 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1051 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1052 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1053
1054 unsigned char res1 = (bit2 ^ bit7) | bit3;
1055
1056 /* when res1 = 0 phase = 0x000 | 0xd0; */
1057 /* when res1 = 1 phase = 0x200 | (0xd0>>2); */
1058 UINT32 phase = res1 ? (0x200|(0xd0>>2)) : 0xd0;
1059
1060 /* enable gate based on frequency of operator 2 in channel 8 */
1061 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1062 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1063
1064 unsigned char res2 = (bit3e ^ bit5e);
1065
1066 /* when res2 = 0 pass the phase from calculation above (res1); */
1067 /* when res2 = 1 phase = 0x200 | (0xd0>>2); */
1068 if (res2)
1069 phase = (0x200|(0xd0>>2));
1070
1071
1072 /* when phase & 0x200 is set and noise=1 then phase = 0x200|0xd0 */
1073 /* when phase & 0x200 is set and noise=0 then phase = 0x200|(0xd0>>2), ie no change */
1074 if (phase&0x200)
1075 {
1076 if (noise)
1077 phase = 0x200|0xd0;
1078 }
1079 else
1080 /* when phase & 0x200 is clear and noise=1 then phase = 0xd0>>2 */
1081 /* when phase & 0x200 is clear and noise=0 then phase = 0xd0, ie no change */
1082 {
1083 if (noise)
1084 phase = 0xd0>>2;
1085 }
1086
1087 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_1->wavetable) * 2;
1088 }
1089
1090 /* Snare Drum (verified on real YM3812) */
1091 env = volume_calc(SLOT7_2);
1092 if( env < ENV_QUIET && ! chip->MuteSpc[1] )
1093 {
1094 /* base frequency derived from operator 1 in channel 7 */
1095 unsigned char bit8 = ((SLOT7_1->Cnt>>FREQ_SH)>>8)&1;
1096
1097 /* when bit8 = 0 phase = 0x100; */
1098 /* when bit8 = 1 phase = 0x200; */
1099 UINT32 phase = bit8 ? 0x200 : 0x100;
1100
1101 /* Noise bit XOR'es phase by 0x100 */
1102 /* when noisebit = 0 pass the phase from calculation above */
1103 /* when noisebit = 1 phase ^= 0x100; */
1104 /* in other words: phase ^= (noisebit<<8); */
1105 if (noise)
1106 phase ^= 0x100;
1107
1108 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_2->wavetable) * 2;
1109 }
1110
1111 /* Tom Tom (verified on real YM3812) */
1112 env = volume_calc(SLOT8_1);
1113 if( env < ENV_QUIET && ! chip->MuteSpc[2] )
1114 chanout[8] += op_calc(SLOT8_1->Cnt, env, 0, SLOT8_1->wavetable) * 2;
1115
1116 /* Top Cymbal (verified on real YM3812) */
1117 env = volume_calc(SLOT8_2);
1118 if( env < ENV_QUIET && ! chip->MuteSpc[3] )
1119 {
1120 /* base frequency derived from operator 1 in channel 7 */
1121 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1122 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1123 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1124
1125 unsigned char res1 = (bit2 ^ bit7) | bit3;
1126
1127 /* when res1 = 0 phase = 0x000 | 0x100; */
1128 /* when res1 = 1 phase = 0x200 | 0x100; */
1129 UINT32 phase = res1 ? 0x300 : 0x100;
1130
1131 /* enable gate based on frequency of operator 2 in channel 8 */
1132 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1133 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1134
1135 unsigned char res2 = (bit3e ^ bit5e);
1136 /* when res2 = 0 pass the phase from calculation above (res1); */
1137 /* when res2 = 1 phase = 0x200 | 0x100; */
1138 if (res2)
1139 phase = 0x300;
1140
1141 chanout[8] += op_calc(phase<<FREQ_SH, env, 0, SLOT8_2->wavetable) * 2;
1142 }
1143
1144 }
1145
1146
1147 /* generic table initialize */
init_tables(void)1148 static int init_tables(void)
1149 {
1150 signed int i,x;
1151 signed int n;
1152 double o,m;
1153
1154
1155 for (x=0; x<TL_RES_LEN; x++)
1156 {
1157 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
1158 m = floor(m);
1159
1160 /* we never reach (1<<16) here due to the (x+1) */
1161 /* result fits within 16 bits at maximum */
1162
1163 n = (int)m; /* 16 bits here */
1164 n >>= 4; /* 12 bits here */
1165 if (n&1) /* round to nearest */
1166 n = (n>>1)+1;
1167 else
1168 n = n>>1;
1169 /* 11 bits here (rounded) */
1170 n <<= 1; /* 12 bits here (as in real chip) */
1171 tl_tab[ x*2 + 0 ] = n;
1172 tl_tab[ x*2 + 1 ] = ~tl_tab[ x*2 + 0 ]; /* this *is* different from OPL2 (verified on real YMF262) */
1173
1174 for (i=1; i<13; i++)
1175 {
1176 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
1177 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = ~tl_tab[ x*2+0 + i*2*TL_RES_LEN ]; /* this *is* different from OPL2 (verified on real YMF262) */
1178 }
1179 #if 0
1180 logerror("tl %04i", x*2);
1181 for (i=0; i<13; i++)
1182 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +0 + i*2*TL_RES_LEN ] ); /* positive */
1183 logerror("\n");
1184
1185 logerror("tl %04i", x*2);
1186 for (i=0; i<13; i++)
1187 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +1 + i*2*TL_RES_LEN ] ); /* negative */
1188 logerror("\n");
1189 #endif
1190 }
1191
1192 for (i=0; i<SIN_LEN; i++)
1193 {
1194 /* non-standard sinus */
1195 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
1196
1197 /* we never reach zero here due to ((i*2)+1) */
1198
1199 if (m>0.0)
1200 o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
1201 else
1202 o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
1203
1204 o = o / (ENV_STEP/4);
1205
1206 n = (int)(2.0*o);
1207 if (n&1) /* round to nearest */
1208 n = (n>>1)+1;
1209 else
1210 n = n>>1;
1211
1212 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
1213
1214 /*logerror("YMF262.C: sin [%4i (hex=%03x)]= %4i (tl_tab value=%5i)\n", i, i, sin_tab[i], tl_tab[sin_tab[i]] );*/
1215 }
1216
1217 for (i=0; i<SIN_LEN; i++)
1218 {
1219 /* these 'pictures' represent _two_ cycles */
1220 /* waveform 1: __ __ */
1221 /* / \____/ \____*/
1222 /* output only first half of the sinus waveform (positive one) */
1223
1224 if (i & (1<<(SIN_BITS-1)) )
1225 sin_tab[1*SIN_LEN+i] = TL_TAB_LEN;
1226 else
1227 sin_tab[1*SIN_LEN+i] = sin_tab[i];
1228
1229 /* waveform 2: __ __ __ __ */
1230 /* / \/ \/ \/ \*/
1231 /* abs(sin) */
1232
1233 sin_tab[2*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>1) ];
1234
1235 /* waveform 3: _ _ _ _ */
1236 /* / |_/ |_/ |_/ |_*/
1237 /* abs(output only first quarter of the sinus waveform) */
1238
1239 if (i & (1<<(SIN_BITS-2)) )
1240 sin_tab[3*SIN_LEN+i] = TL_TAB_LEN;
1241 else
1242 sin_tab[3*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>2)];
1243
1244 /* waveform 4: */
1245 /* /\ ____/\ ____*/
1246 /* \/ \/ */
1247 /* output whole sinus waveform in half the cycle(step=2) and output 0 on the other half of cycle */
1248
1249 if (i & (1<<(SIN_BITS-1)) )
1250 sin_tab[4*SIN_LEN+i] = TL_TAB_LEN;
1251 else
1252 sin_tab[4*SIN_LEN+i] = sin_tab[i*2];
1253
1254 /* waveform 5: */
1255 /* /\/\____/\/\____*/
1256 /* */
1257 /* output abs(whole sinus) waveform in half the cycle(step=2) and output 0 on the other half of cycle */
1258
1259 if (i & (1<<(SIN_BITS-1)) )
1260 sin_tab[5*SIN_LEN+i] = TL_TAB_LEN;
1261 else
1262 sin_tab[5*SIN_LEN+i] = sin_tab[(i*2) & (SIN_MASK>>1) ];
1263
1264 /* waveform 6: ____ ____ */
1265 /* */
1266 /* ____ ____*/
1267 /* output maximum in half the cycle and output minimum on the other half of cycle */
1268
1269 if (i & (1<<(SIN_BITS-1)) )
1270 sin_tab[6*SIN_LEN+i] = 1; /* negative */
1271 else
1272 sin_tab[6*SIN_LEN+i] = 0; /* positive */
1273
1274 /* waveform 7: */
1275 /* |\____ |\____ */
1276 /* \| \|*/
1277 /* output sawtooth waveform */
1278
1279 if (i & (1<<(SIN_BITS-1)) )
1280 x = ((SIN_LEN-1)-i)*16 + 1; /* negative: from 8177 to 1 */
1281 else
1282 x = i*16; /*positive: from 0 to 8176 */
1283
1284 if (x > TL_TAB_LEN)
1285 x = TL_TAB_LEN; /* clip to the allowed range */
1286
1287 sin_tab[7*SIN_LEN+i] = x;
1288
1289 //logerror("YMF262.C: sin1[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[1*SIN_LEN+i], tl_tab[sin_tab[1*SIN_LEN+i]] );
1290 //logerror("YMF262.C: sin2[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[2*SIN_LEN+i], tl_tab[sin_tab[2*SIN_LEN+i]] );
1291 //logerror("YMF262.C: sin3[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[3*SIN_LEN+i], tl_tab[sin_tab[3*SIN_LEN+i]] );
1292 //logerror("YMF262.C: sin4[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[4*SIN_LEN+i], tl_tab[sin_tab[4*SIN_LEN+i]] );
1293 //logerror("YMF262.C: sin5[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[5*SIN_LEN+i], tl_tab[sin_tab[5*SIN_LEN+i]] );
1294 //logerror("YMF262.C: sin6[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[6*SIN_LEN+i], tl_tab[sin_tab[6*SIN_LEN+i]] );
1295 //logerror("YMF262.C: sin7[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[7*SIN_LEN+i], tl_tab[sin_tab[7*SIN_LEN+i]] );
1296 }
1297 /*logerror("YMF262.C: ENV_QUIET= %08x (dec*8=%i)\n", ENV_QUIET, ENV_QUIET*8 );*/
1298
1299 #ifdef SAVE_SAMPLE
1300 sample[0]=fopen("sampsum.pcm","wb");
1301 #endif
1302
1303 return 1;
1304 }
1305
OPLCloseTable(void)1306 static void OPLCloseTable( void )
1307 {
1308 #ifdef SAVE_SAMPLE
1309 fclose(sample[0]);
1310 #endif
1311 }
1312
1313
1314
OPL3_initalize(OPL3 * chip)1315 static void OPL3_initalize(OPL3 *chip)
1316 {
1317 int i;
1318
1319 /* frequency base */
1320 chip->freqbase = (chip->rate) ? ((double)chip->clock / (8.0*36)) / chip->rate : 0;
1321 #if 0
1322 chip->rate = (double)chip->clock / (8.0*36);
1323 chip->freqbase = 1.0;
1324 #endif
1325
1326 /* logerror("YMF262: freqbase=%f\n", chip->freqbase); */
1327
1328 /* Timer base time */
1329 //chip->TimerBase = attotime_mul(ATTOTIME_IN_HZ(chip->clock), 8*36);
1330
1331 /* make fnumber -> increment counter table */
1332 for( i=0 ; i < 1024 ; i++ )
1333 {
1334 /* opn phase increment counter = 20bit */
1335 chip->fn_tab[i] = (UINT32)( (double)i * 64 * chip->freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
1336 #if 0
1337 logerror("YMF262.C: fn_tab[%4i] = %08x (dec=%8i)\n",
1338 i, chip->fn_tab[i]>>6, chip->fn_tab[i]>>6 );
1339 #endif
1340 }
1341
1342 #if 0
1343 for( i=0 ; i < 16 ; i++ )
1344 {
1345 logerror("YMF262.C: sl_tab[%i] = %08x\n",
1346 i, sl_tab[i] );
1347 }
1348 for( i=0 ; i < 8 ; i++ )
1349 {
1350 int j;
1351 logerror("YMF262.C: ksl_tab[oct=%2i] =",i);
1352 for (j=0; j<16; j++)
1353 {
1354 logerror("%08x ", ksl_tab[i*16+j] );
1355 }
1356 logerror("\n");
1357 }
1358 #endif
1359
1360
1361 /* Amplitude modulation: 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples */
1362 /* One entry from LFO_AM_TABLE lasts for 64 samples */
1363 chip->lfo_am_inc = (1.0 / 64.0 ) * (1<<LFO_SH) * chip->freqbase;
1364
1365 /* Vibrato: 8 output levels (triangle waveform); 1 level takes 1024 samples */
1366 chip->lfo_pm_inc = (1.0 / 1024.0) * (1<<LFO_SH) * chip->freqbase;
1367
1368 /*logerror ("chip->lfo_am_inc = %8x ; chip->lfo_pm_inc = %8x\n", chip->lfo_am_inc, chip->lfo_pm_inc);*/
1369
1370 /* Noise generator: a step takes 1 sample */
1371 chip->noise_f = (1.0 / 1.0) * (1<<FREQ_SH) * chip->freqbase;
1372
1373 chip->eg_timer_add = (1<<EG_SH) * chip->freqbase;
1374 chip->eg_timer_overflow = ( 1 ) * (1<<EG_SH);
1375 /*logerror("YMF262init eg_timer_add=%8x eg_timer_overflow=%8x\n", chip->eg_timer_add, chip->eg_timer_overflow);*/
1376
1377 }
1378
FM_KEYON(OPL3_SLOT * SLOT,UINT32 key_set)1379 INLINE void FM_KEYON(OPL3_SLOT *SLOT, UINT32 key_set)
1380 {
1381 if( !SLOT->key )
1382 {
1383 /* restart Phase Generator */
1384 SLOT->Cnt = 0;
1385 /* phase -> Attack */
1386 SLOT->state = EG_ATT;
1387 }
1388 SLOT->key |= key_set;
1389 }
1390
FM_KEYOFF(OPL3_SLOT * SLOT,UINT32 key_clr)1391 INLINE void FM_KEYOFF(OPL3_SLOT *SLOT, UINT32 key_clr)
1392 {
1393 if( SLOT->key )
1394 {
1395 SLOT->key &= key_clr;
1396
1397 if( !SLOT->key )
1398 {
1399 /* phase -> Release */
1400 if (SLOT->state>EG_REL)
1401 SLOT->state = EG_REL;
1402 }
1403 }
1404 }
1405
1406 /* update phase increment counter of operator (also update the EG rates if necessary) */
CALC_FCSLOT(OPL3_CH * CH,OPL3_SLOT * SLOT)1407 INLINE void CALC_FCSLOT(OPL3_CH *CH,OPL3_SLOT *SLOT)
1408 {
1409 int ksr;
1410
1411 /* (frequency) phase increment counter */
1412 SLOT->Incr = CH->fc * SLOT->mul;
1413 ksr = CH->kcode >> SLOT->KSR;
1414
1415 if( SLOT->ksr != ksr )
1416 {
1417 SLOT->ksr = ksr;
1418
1419 /* calculate envelope generator rates */
1420 if ((SLOT->ar + SLOT->ksr) < 16+60)
1421 {
1422 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1423 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1424 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1425 }
1426 else
1427 {
1428 SLOT->eg_sh_ar = 0;
1429 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1430 SLOT->eg_sel_ar = 13*RATE_STEPS;
1431 }
1432 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1433 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1;
1434 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1435 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1436 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1;
1437 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1438 }
1439 }
1440
1441 /* set multi,am,vib,EG-TYP,KSR,mul */
set_mul(OPL3 * chip,int slot,int v)1442 INLINE void set_mul(OPL3 *chip,int slot,int v)
1443 {
1444 OPL3_CH *CH = &chip->P_CH[slot/2];
1445 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1446
1447 SLOT->mul = mul_tab[v&0x0f];
1448 SLOT->KSR = (v&0x10) ? 0 : 2;
1449 SLOT->eg_type = (v&0x20);
1450 SLOT->vib = (v&0x40);
1451 SLOT->AMmask = (v&0x80) ? ~0 : 0;
1452
1453 if (chip->OPL3_mode & 1)
1454 {
1455 int chan_no = slot/2;
1456
1457 /* in OPL3 mode */
1458 //DO THIS:
1459 //if this is one of the slots of 1st channel forming up a 4-op channel
1460 //do normal operation
1461 //else normal 2 operator function
1462 //OR THIS:
1463 //if this is one of the slots of 2nd channel forming up a 4-op channel
1464 //update it using channel data of 1st channel of a pair
1465 //else normal 2 operator function
1466 switch(chan_no)
1467 {
1468 case 0: case 1: case 2:
1469 case 9: case 10: case 11:
1470 if (CH->extended)
1471 {
1472 /* normal */
1473 CALC_FCSLOT(CH,SLOT);
1474 }
1475 else
1476 {
1477 /* normal */
1478 CALC_FCSLOT(CH,SLOT);
1479 }
1480 break;
1481 case 3: case 4: case 5:
1482 case 12: case 13: case 14:
1483 if ((CH-3)->extended)
1484 {
1485 /* update this SLOT using frequency data for 1st channel of a pair */
1486 CALC_FCSLOT(CH-3,SLOT);
1487 }
1488 else
1489 {
1490 /* normal */
1491 CALC_FCSLOT(CH,SLOT);
1492 }
1493 break;
1494 default:
1495 /* normal */
1496 CALC_FCSLOT(CH,SLOT);
1497 break;
1498 }
1499 }
1500 else
1501 {
1502 /* in OPL2 mode */
1503 CALC_FCSLOT(CH,SLOT);
1504 }
1505 }
1506
1507 /* set ksl & tl */
set_ksl_tl(OPL3 * chip,int slot,int v)1508 INLINE void set_ksl_tl(OPL3 *chip,int slot,int v)
1509 {
1510 OPL3_CH *CH = &chip->P_CH[slot/2];
1511 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1512
1513 SLOT->ksl = ksl_shift[v >> 6];
1514 SLOT->TL = (v&0x3f)<<(ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */
1515
1516 if (chip->OPL3_mode & 1)
1517 {
1518 int chan_no = slot/2;
1519
1520 /* in OPL3 mode */
1521 //DO THIS:
1522 //if this is one of the slots of 1st channel forming up a 4-op channel
1523 //do normal operation
1524 //else normal 2 operator function
1525 //OR THIS:
1526 //if this is one of the slots of 2nd channel forming up a 4-op channel
1527 //update it using channel data of 1st channel of a pair
1528 //else normal 2 operator function
1529 switch(chan_no)
1530 {
1531 case 0: case 1: case 2:
1532 case 9: case 10: case 11:
1533 if (CH->extended)
1534 {
1535 /* normal */
1536 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1537 }
1538 else
1539 {
1540 /* normal */
1541 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1542 }
1543 break;
1544 case 3: case 4: case 5:
1545 case 12: case 13: case 14:
1546 if ((CH-3)->extended)
1547 {
1548 /* update this SLOT using frequency data for 1st channel of a pair */
1549 SLOT->TLL = SLOT->TL + ((CH-3)->ksl_base>>SLOT->ksl);
1550 }
1551 else
1552 {
1553 /* normal */
1554 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1555 }
1556 break;
1557 default:
1558 /* normal */
1559 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1560 break;
1561 }
1562 }
1563 else
1564 {
1565 /* in OPL2 mode */
1566 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1567 }
1568
1569 }
1570
1571 /* set attack rate & decay rate */
set_ar_dr(OPL3 * chip,int slot,int v)1572 INLINE void set_ar_dr(OPL3 *chip,int slot,int v)
1573 {
1574 OPL3_CH *CH = &chip->P_CH[slot/2];
1575 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1576
1577 SLOT->ar = (v>>4) ? 16 + ((v>>4) <<2) : 0;
1578
1579 if ((SLOT->ar + SLOT->ksr) < 16+60) /* verified on real YMF262 - all 15 x rates take "zero" time */
1580 {
1581 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1582 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1583 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1584 }
1585 else
1586 {
1587 SLOT->eg_sh_ar = 0;
1588 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1589 SLOT->eg_sel_ar = 13*RATE_STEPS;
1590 }
1591
1592 SLOT->dr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1593 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1594 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1;
1595 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1596 }
1597
1598 /* set sustain level & release rate */
set_sl_rr(OPL3 * chip,int slot,int v)1599 INLINE void set_sl_rr(OPL3 *chip,int slot,int v)
1600 {
1601 OPL3_CH *CH = &chip->P_CH[slot/2];
1602 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1603
1604 SLOT->sl = sl_tab[ v>>4 ];
1605
1606 SLOT->rr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1607 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1608 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1;
1609 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1610 }
1611
1612
update_channels(OPL3 * chip,OPL3_CH * CH)1613 static void update_channels(OPL3 *chip, OPL3_CH *CH)
1614 {
1615 /* update channel passed as a parameter and a channel at CH+=3; */
1616 if (CH->extended)
1617 { /* we've just switched to combined 4 operator mode */
1618
1619 }
1620 else
1621 { /* we've just switched to normal 2 operator mode */
1622
1623 }
1624
1625 }
1626
1627 /* write a value v to register r on OPL chip */
OPL3WriteReg(OPL3 * chip,int r,int v)1628 static void OPL3WriteReg(OPL3 *chip, int r, int v)
1629 {
1630 OPL3_CH *CH;
1631 signed int *chanout = chip->chanout;
1632 unsigned int ch_offset = 0;
1633 int slot;
1634 int block_fnum;
1635
1636
1637
1638 /*if (LOG_CYM_FILE && (cymfile) && ((r&255)!=0) && (r!=255) )
1639 {
1640 if (r>0xff)
1641 fputc( (unsigned char)0xff, cymfile );//mark writes to second register set
1642
1643 fputc( (unsigned char)r&0xff, cymfile );
1644 fputc( (unsigned char)v, cymfile );
1645 }*/
1646
1647 if(r&0x100)
1648 {
1649 switch(r)
1650 {
1651 case 0x101: /* test register */
1652 return;
1653
1654 case 0x104: /* 6 channels enable */
1655 {
1656 UINT8 prev;
1657
1658 CH = &chip->P_CH[0]; /* channel 0 */
1659 prev = CH->extended;
1660 CH->extended = (v>>0) & 1;
1661 if(prev != CH->extended)
1662 update_channels(chip, CH);
1663 CH++; /* channel 1 */
1664 prev = CH->extended;
1665 CH->extended = (v>>1) & 1;
1666 if(prev != CH->extended)
1667 update_channels(chip, CH);
1668 CH++; /* channel 2 */
1669 prev = CH->extended;
1670 CH->extended = (v>>2) & 1;
1671 if(prev != CH->extended)
1672 update_channels(chip, CH);
1673
1674
1675 CH = &chip->P_CH[9]; /* channel 9 */
1676 prev = CH->extended;
1677 CH->extended = (v>>3) & 1;
1678 if(prev != CH->extended)
1679 update_channels(chip, CH);
1680 CH++; /* channel 10 */
1681 prev = CH->extended;
1682 CH->extended = (v>>4) & 1;
1683 if(prev != CH->extended)
1684 update_channels(chip, CH);
1685 CH++; /* channel 11 */
1686 prev = CH->extended;
1687 CH->extended = (v>>5) & 1;
1688 if(prev != CH->extended)
1689 update_channels(chip, CH);
1690
1691 }
1692 return;
1693
1694 case 0x105: /* OPL3 extensions enable register */
1695
1696 chip->OPL3_mode = v&0x01; /* OPL3 mode when bit0=1 otherwise it is OPL2 mode */
1697
1698 /* following behaviour was tested on real YMF262,
1699 switching OPL3/OPL2 modes on the fly:
1700 - does not change the waveform previously selected (unless when ....)
1701 - does not update CH.A, CH.B, CH.C and CH.D output selectors (registers c0-c8) (unless when ....)
1702 - does not disable channels 9-17 on OPL3->OPL2 switch
1703 - does not switch 4 operator channels back to 2 operator channels
1704 */
1705
1706 return;
1707
1708 default:
1709 #ifdef _DEBUG
1710 if (r < 0x120)
1711 logerror("YMF262: write to unknown register (set#2): %03x value=%02x\n",r,v);
1712 #endif
1713 break;
1714 }
1715
1716 ch_offset = 9; /* register page #2 starts from channel 9 (counting from 0) */
1717 }
1718
1719 /* adjust bus to 8 bits */
1720 r &= 0xff;
1721 v &= 0xff;
1722
1723
1724 switch(r&0xe0)
1725 {
1726 case 0x00: /* 00-1f:control */
1727 switch(r&0x1f)
1728 {
1729 case 0x01: /* test register */
1730 break;
1731 case 0x02: /* Timer 1 */
1732 chip->T[0] = (256-v)*4;
1733 break;
1734 case 0x03: /* Timer 2 */
1735 chip->T[1] = (256-v)*16;
1736 break;
1737 case 0x04: /* IRQ clear / mask and Timer enable */
1738 if(v&0x80)
1739 { /* IRQ flags clear */
1740 OPL3_STATUS_RESET(chip,0x60);
1741 }
1742 else
1743 { /* set IRQ mask ,timer enable */
1744 UINT8 st1 = v & 1;
1745 UINT8 st2 = (v>>1) & 1;
1746
1747 /* IRQRST,T1MSK,t2MSK,x,x,x,ST2,ST1 */
1748 OPL3_STATUS_RESET(chip, v & 0x60);
1749 OPL3_STATUSMASK_SET(chip, (~v) & 0x60 );
1750
1751 /* timer 2 */
1752 if(chip->st[1] != st2)
1753 {
1754 //attotime period = st2 ? attotime_mul(chip->TimerBase, chip->T[1]) : attotime_zero;
1755 chip->st[1] = st2;
1756 //if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,1,period);
1757 }
1758 /* timer 1 */
1759 if(chip->st[0] != st1)
1760 {
1761 //attotime period = st1 ? attotime_mul(chip->TimerBase, chip->T[0]) : attotime_zero;
1762 chip->st[0] = st1;
1763 //if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,0,period);
1764 }
1765 }
1766 break;
1767 case 0x08: /* x,NTS,x,x, x,x,x,x */
1768 chip->nts = v;
1769 break;
1770
1771 default:
1772 #ifdef _DEBUG
1773 logerror("YMF262: write to unknown register: %02x value=%02x\n",r,v);
1774 #endif
1775 break;
1776 }
1777 break;
1778 case 0x20: /* am ON, vib ON, ksr, eg_type, mul */
1779 slot = slot_array[r&0x1f];
1780 if(slot < 0) return;
1781 set_mul(chip, slot + ch_offset*2, v);
1782 break;
1783 case 0x40:
1784 slot = slot_array[r&0x1f];
1785 if(slot < 0) return;
1786 set_ksl_tl(chip, slot + ch_offset*2, v);
1787 break;
1788 case 0x60:
1789 slot = slot_array[r&0x1f];
1790 if(slot < 0) return;
1791 set_ar_dr(chip, slot + ch_offset*2, v);
1792 break;
1793 case 0x80:
1794 slot = slot_array[r&0x1f];
1795 if(slot < 0) return;
1796 set_sl_rr(chip, slot + ch_offset*2, v);
1797 break;
1798 case 0xa0:
1799 if (r == 0xbd) /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */
1800 {
1801 if (ch_offset != 0) /* 0xbd register is present in set #1 only */
1802 return;
1803
1804 chip->lfo_am_depth = v & 0x80;
1805 chip->lfo_pm_depth_range = (v&0x40) ? 8 : 0;
1806
1807 chip->rhythm = v&0x3f;
1808
1809 if(chip->rhythm&0x20)
1810 {
1811 /* BD key on/off */
1812 if(v&0x10)
1813 {
1814 FM_KEYON (&chip->P_CH[6].SLOT[SLOT1], 2);
1815 FM_KEYON (&chip->P_CH[6].SLOT[SLOT2], 2);
1816 }
1817 else
1818 {
1819 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
1820 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
1821 }
1822 /* HH key on/off */
1823 if(v&0x01) FM_KEYON (&chip->P_CH[7].SLOT[SLOT1], 2);
1824 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
1825 /* SD key on/off */
1826 if(v&0x08) FM_KEYON (&chip->P_CH[7].SLOT[SLOT2], 2);
1827 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
1828 /* TOM key on/off */
1829 if(v&0x04) FM_KEYON (&chip->P_CH[8].SLOT[SLOT1], 2);
1830 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
1831 /* TOP-CY key on/off */
1832 if(v&0x02) FM_KEYON (&chip->P_CH[8].SLOT[SLOT2], 2);
1833 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
1834 }
1835 else
1836 {
1837 /* BD key off */
1838 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
1839 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
1840 /* HH key off */
1841 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
1842 /* SD key off */
1843 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
1844 /* TOM key off */
1845 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
1846 /* TOP-CY off */
1847 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
1848 }
1849 return;
1850 }
1851
1852 /* keyon,block,fnum */
1853 if( (r&0x0f) > 8) return;
1854 CH = &chip->P_CH[(r&0x0f) + ch_offset];
1855
1856 if(!(r&0x10))
1857 { /* a0-a8 */
1858 block_fnum = (CH->block_fnum&0x1f00) | v;
1859 }
1860 else
1861 { /* b0-b8 */
1862 block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff);
1863
1864 if (chip->OPL3_mode & 1)
1865 {
1866 int chan_no = (r&0x0f) + ch_offset;
1867
1868 /* in OPL3 mode */
1869 //DO THIS:
1870 //if this is 1st channel forming up a 4-op channel
1871 //ALSO keyon/off slots of 2nd channel forming up 4-op channel
1872 //else normal 2 operator function keyon/off
1873 //OR THIS:
1874 //if this is 2nd channel forming up 4-op channel just do nothing
1875 //else normal 2 operator function keyon/off
1876 switch(chan_no)
1877 {
1878 case 0: case 1: case 2:
1879 case 9: case 10: case 11:
1880 if (CH->extended)
1881 {
1882 //if this is 1st channel forming up a 4-op channel
1883 //ALSO keyon/off slots of 2nd channel forming up 4-op channel
1884 if(v&0x20)
1885 {
1886 FM_KEYON (&CH->SLOT[SLOT1], 1);
1887 FM_KEYON (&CH->SLOT[SLOT2], 1);
1888 FM_KEYON (&(CH+3)->SLOT[SLOT1], 1);
1889 FM_KEYON (&(CH+3)->SLOT[SLOT2], 1);
1890 }
1891 else
1892 {
1893 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1894 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1895 FM_KEYOFF(&(CH+3)->SLOT[SLOT1],~1);
1896 FM_KEYOFF(&(CH+3)->SLOT[SLOT2],~1);
1897 }
1898 }
1899 else
1900 {
1901 //else normal 2 operator function keyon/off
1902 if(v&0x20)
1903 {
1904 FM_KEYON (&CH->SLOT[SLOT1], 1);
1905 FM_KEYON (&CH->SLOT[SLOT2], 1);
1906 }
1907 else
1908 {
1909 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1910 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1911 }
1912 }
1913 break;
1914
1915 case 3: case 4: case 5:
1916 case 12: case 13: case 14:
1917 if ((CH-3)->extended)
1918 {
1919 //if this is 2nd channel forming up 4-op channel just do nothing
1920 }
1921 else
1922 {
1923 //else normal 2 operator function keyon/off
1924 if(v&0x20)
1925 {
1926 FM_KEYON (&CH->SLOT[SLOT1], 1);
1927 FM_KEYON (&CH->SLOT[SLOT2], 1);
1928 }
1929 else
1930 {
1931 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1932 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1933 }
1934 }
1935 break;
1936
1937 default:
1938 if(v&0x20)
1939 {
1940 FM_KEYON (&CH->SLOT[SLOT1], 1);
1941 FM_KEYON (&CH->SLOT[SLOT2], 1);
1942 }
1943 else
1944 {
1945 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1946 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1947 }
1948 break;
1949 }
1950 }
1951 else
1952 {
1953 if(v&0x20)
1954 {
1955 FM_KEYON (&CH->SLOT[SLOT1], 1);
1956 FM_KEYON (&CH->SLOT[SLOT2], 1);
1957 }
1958 else
1959 {
1960 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1961 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1962 }
1963 }
1964 }
1965 /* update */
1966 if(CH->block_fnum != block_fnum)
1967 {
1968 UINT8 block = block_fnum >> 10;
1969
1970 CH->block_fnum = block_fnum;
1971
1972 CH->ksl_base = ksl_tab[block_fnum>>6];
1973 CH->fc = chip->fn_tab[block_fnum&0x03ff] >> (7-block);
1974
1975 /* BLK 2,1,0 bits -> bits 3,2,1 of kcode */
1976 CH->kcode = (CH->block_fnum&0x1c00)>>9;
1977
1978 /* the info below is actually opposite to what is stated in the Manuals (verifed on real YMF262) */
1979 /* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum */
1980 /* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */
1981 if (chip->nts&0x40)
1982 CH->kcode |= (CH->block_fnum&0x100)>>8; /* notesel == 1 */
1983 else
1984 CH->kcode |= (CH->block_fnum&0x200)>>9; /* notesel == 0 */
1985
1986 if (chip->OPL3_mode & 1)
1987 {
1988 int chan_no = (r&0x0f) + ch_offset;
1989 /* in OPL3 mode */
1990 //DO THIS:
1991 //if this is 1st channel forming up a 4-op channel
1992 //ALSO update slots of 2nd channel forming up 4-op channel
1993 //else normal 2 operator function keyon/off
1994 //OR THIS:
1995 //if this is 2nd channel forming up 4-op channel just do nothing
1996 //else normal 2 operator function keyon/off
1997 switch(chan_no)
1998 {
1999 case 0: case 1: case 2:
2000 case 9: case 10: case 11:
2001 if (CH->extended)
2002 {
2003 //if this is 1st channel forming up a 4-op channel
2004 //ALSO update slots of 2nd channel forming up 4-op channel
2005
2006 /* refresh Total Level in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
2007 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2008 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2009 (CH+3)->SLOT[SLOT1].TLL = (CH+3)->SLOT[SLOT1].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT1].ksl);
2010 (CH+3)->SLOT[SLOT2].TLL = (CH+3)->SLOT[SLOT2].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT2].ksl);
2011
2012 /* refresh frequency counter in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
2013 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2014 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2015 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT1]);
2016 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT2]);
2017 }
2018 else
2019 {
2020 //else normal 2 operator function
2021 /* refresh Total Level in both SLOTs of this channel */
2022 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2023 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2024
2025 /* refresh frequency counter in both SLOTs of this channel */
2026 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2027 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2028 }
2029 break;
2030
2031 case 3: case 4: case 5:
2032 case 12: case 13: case 14:
2033 if ((CH-3)->extended)
2034 {
2035 //if this is 2nd channel forming up 4-op channel just do nothing
2036 }
2037 else
2038 {
2039 //else normal 2 operator function
2040 /* refresh Total Level in both SLOTs of this channel */
2041 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2042 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2043
2044 /* refresh frequency counter in both SLOTs of this channel */
2045 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2046 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2047 }
2048 break;
2049
2050 default:
2051 /* refresh Total Level in both SLOTs of this channel */
2052 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2053 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2054
2055 /* refresh frequency counter in both SLOTs of this channel */
2056 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2057 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2058 break;
2059 }
2060 }
2061 else
2062 {
2063 /* in OPL2 mode */
2064
2065 /* refresh Total Level in both SLOTs of this channel */
2066 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2067 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2068
2069 /* refresh frequency counter in both SLOTs of this channel */
2070 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2071 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2072 }
2073 }
2074 break;
2075
2076 case 0xc0:
2077 /* CH.D, CH.C, CH.B, CH.A, FB(3bits), C */
2078 if( (r&0xf) > 8) return;
2079
2080 CH = &chip->P_CH[(r&0xf) + ch_offset];
2081
2082 if( chip->OPL3_mode & 1 )
2083 {
2084 int base = ((r&0xf) + ch_offset) * 4;
2085
2086 /* OPL3 mode */
2087 chip->pan[ base ] = (v & 0x10) ? ~0 : 0; /* ch.A */
2088 chip->pan[ base +1 ] = (v & 0x20) ? ~0 : 0; /* ch.B */
2089 chip->pan[ base +2 ] = (v & 0x40) ? ~0 : 0; /* ch.C */
2090 chip->pan[ base +3 ] = (v & 0x80) ? ~0 : 0; /* ch.D */
2091 }
2092 else
2093 {
2094 int base = ((r&0xf) + ch_offset) * 4;
2095
2096 /* OPL2 mode - always enabled */
2097 chip->pan[ base ] = ~0; /* ch.A */
2098 chip->pan[ base +1 ] = ~0; /* ch.B */
2099 chip->pan[ base +2 ] = ~0; /* ch.C */
2100 chip->pan[ base +3 ] = ~0; /* ch.D */
2101 }
2102
2103 chip->pan_ctrl_value[ (r&0xf) + ch_offset ] = v; /* store control value for OPL3/OPL2 mode switching on the fly */
2104
2105 CH->SLOT[SLOT1].FB = (v>>1)&7 ? ((v>>1)&7) + 7 : 0;
2106 CH->SLOT[SLOT1].CON = v&1;
2107
2108 if( chip->OPL3_mode & 1 )
2109 {
2110 int chan_no = (r&0x0f) + ch_offset;
2111
2112 switch(chan_no)
2113 {
2114 case 0: case 1: case 2:
2115 case 9: case 10: case 11:
2116 if (CH->extended)
2117 {
2118 UINT8 conn = (CH->SLOT[SLOT1].CON<<1) | ((CH+3)->SLOT[SLOT1].CON<<0);
2119 switch(conn)
2120 {
2121 case 0:
2122 /* 1 -> 2 -> 3 -> 4 - out */
2123
2124 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2125 CH->SLOT[SLOT2].connect = &chip->phase_modulation2;
2126 (CH+3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2127 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2128 break;
2129 case 1:
2130 /* 1 -> 2 -\
2131 3 -> 4 -+- out */
2132
2133 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2134 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2135 (CH+3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2136 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2137 break;
2138 case 2:
2139 /* 1 -----------\
2140 2 -> 3 -> 4 -+- out */
2141
2142 CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
2143 CH->SLOT[SLOT2].connect = &chip->phase_modulation2;
2144 (CH+3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2145 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2146 break;
2147 case 3:
2148 /* 1 ------\
2149 2 -> 3 -+- out
2150 4 ------/ */
2151 CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
2152 CH->SLOT[SLOT2].connect = &chip->phase_modulation2;
2153 (CH+3)->SLOT[SLOT1].connect = &chanout[ chan_no + 3 ];
2154 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2155 break;
2156 }
2157 }
2158 else
2159 {
2160 /* 2 operators mode */
2161 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
2162 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2163 }
2164 break;
2165
2166 case 3: case 4: case 5:
2167 case 12: case 13: case 14:
2168 if ((CH-3)->extended)
2169 {
2170 UINT8 conn = ((CH-3)->SLOT[SLOT1].CON<<1) | (CH->SLOT[SLOT1].CON<<0);
2171 switch(conn)
2172 {
2173 case 0:
2174 /* 1 -> 2 -> 3 -> 4 - out */
2175
2176 (CH-3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2177 (CH-3)->SLOT[SLOT2].connect = &chip->phase_modulation2;
2178 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2179 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2180 break;
2181 case 1:
2182 /* 1 -> 2 -\
2183 3 -> 4 -+- out */
2184
2185 (CH-3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2186 (CH-3)->SLOT[SLOT2].connect = &chanout[ chan_no - 3 ];
2187 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2188 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2189 break;
2190 case 2:
2191 /* 1 -----------\
2192 2 -> 3 -> 4 -+- out */
2193
2194 (CH-3)->SLOT[SLOT1].connect = &chanout[ chan_no - 3 ];
2195 (CH-3)->SLOT[SLOT2].connect = &chip->phase_modulation2;
2196 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2197 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2198 break;
2199 case 3:
2200 /* 1 ------\
2201 2 -> 3 -+- out
2202 4 ------/ */
2203 (CH-3)->SLOT[SLOT1].connect = &chanout[ chan_no - 3 ];
2204 (CH-3)->SLOT[SLOT2].connect = &chip->phase_modulation2;
2205 CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
2206 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2207 break;
2208 }
2209 }
2210 else
2211 {
2212 /* 2 operators mode */
2213 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
2214 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2215 }
2216 break;
2217
2218 default:
2219 /* 2 operators mode */
2220 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
2221 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2222 break;
2223 }
2224 }
2225 else
2226 {
2227 /* OPL2 mode - always 2 operators mode */
2228 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
2229 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2230 }
2231 break;
2232
2233 case 0xe0: /* waveform select */
2234 slot = slot_array[r&0x1f];
2235 if(slot < 0) return;
2236
2237 slot += ch_offset*2;
2238
2239 CH = &chip->P_CH[slot/2];
2240
2241
2242 /* store 3-bit value written regardless of current OPL2 or OPL3 mode... (verified on real YMF262) */
2243 v &= 7;
2244 CH->SLOT[slot&1].waveform_number = v;
2245
2246 /* ... but select only waveforms 0-3 in OPL2 mode */
2247 if( !(chip->OPL3_mode & 1) )
2248 {
2249 v &= 3; /* we're in OPL2 mode */
2250 }
2251 CH->SLOT[slot&1].wavetable = v * SIN_LEN;
2252 break;
2253 }
2254 }
2255
2256 /*static TIMER_CALLBACK( cymfile_callback )
2257 {
2258 if (cymfile)
2259 {
2260 fputc( (unsigned char)0, cymfile );
2261 }
2262 }*/
2263
2264 /* lock/unlock for common table */
OPL3_LockTable()2265 static int OPL3_LockTable()
2266 {
2267 num_lock++;
2268 if(num_lock>1) return 0;
2269
2270 /* first time */
2271
2272 if( !init_tables() )
2273 {
2274 num_lock--;
2275 return -1;
2276 }
2277
2278 /*if (LOG_CYM_FILE)
2279 {
2280 cymfile = fopen("ymf262_.cym","wb");
2281 if (cymfile)
2282 timer_pulse ( device->machine, ATTOTIME_IN_HZ(110), NULL, 0, cymfile_callback); //110 Hz pulse timer
2283 else
2284 logerror("Could not create ymf262_.cym file\n");
2285 }*/
2286
2287 return 0;
2288 }
2289
OPL3_UnLockTable(void)2290 static void OPL3_UnLockTable(void)
2291 {
2292 if(num_lock) num_lock--;
2293 if(num_lock) return;
2294
2295 /* last time */
2296
2297 OPLCloseTable();
2298
2299 /*if (LOG_CYM_FILE)
2300 fclose (cymfile);
2301 cymfile = NULL;*/
2302 }
2303
OPL3ResetChip(OPL3 * chip)2304 static void OPL3ResetChip(OPL3 *chip)
2305 {
2306 int c,s;
2307
2308 chip->eg_timer = 0;
2309 chip->eg_cnt = 0;
2310
2311 chip->noise_rng = 1; /* noise shift register */
2312 chip->nts = 0; /* note split */
2313 OPL3_STATUS_RESET(chip,0x60);
2314
2315 /* reset with register write */
2316 OPL3WriteReg(chip,0x01,0); /* test register */
2317 OPL3WriteReg(chip,0x02,0); /* Timer1 */
2318 OPL3WriteReg(chip,0x03,0); /* Timer2 */
2319 OPL3WriteReg(chip,0x04,0); /* IRQ mask clear */
2320
2321
2322 //FIX IT registers 101, 104 and 105
2323
2324
2325 //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)
2326 for(c = 0xff ; c >= 0x20 ; c-- )
2327 OPL3WriteReg(chip,c,0);
2328 //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)
2329 for(c = 0x1ff ; c >= 0x120 ; c-- )
2330 OPL3WriteReg(chip,c,0);
2331
2332
2333
2334 /* reset operator parameters */
2335 for( c = 0 ; c < 9*2 ; c++ )
2336 {
2337 OPL3_CH *CH = &chip->P_CH[c];
2338 for(s = 0 ; s < 2 ; s++ )
2339 {
2340 CH->SLOT[s].state = EG_OFF;
2341 CH->SLOT[s].volume = MAX_ATT_INDEX;
2342 }
2343 }
2344 }
2345
2346 /* Create one of virtual YMF262 */
2347 /* 'clock' is chip clock in Hz */
2348 /* 'rate' is sampling rate */
OPL3Create(int clock,int rate,int type)2349 static OPL3 *OPL3Create(int clock, int rate, int type)
2350 {
2351 OPL3 *chip;
2352
2353 if (OPL3_LockTable() == -1) return NULL;
2354
2355 /* allocate memory block */
2356 chip = (OPL3 *)malloc(sizeof(OPL3));
2357
2358 if (chip==NULL)
2359 return NULL;
2360
2361 /* clear */
2362 memset(chip, 0, sizeof(OPL3));
2363
2364 chip->type = type;
2365 chip->clock = clock;
2366 chip->rate = rate;
2367
2368 /* init global tables */
2369 OPL3_initalize(chip);
2370
2371 /* reset chip */
2372 OPL3ResetChip(chip);
2373 return chip;
2374 }
2375
2376 /* Destroy one of virtual YMF262 */
OPL3Destroy(OPL3 * chip)2377 static void OPL3Destroy(OPL3 *chip)
2378 {
2379 OPL3_UnLockTable();
2380 free(chip);
2381 }
2382
2383
2384 /* Optional handlers */
2385
OPL3SetTimerHandler(OPL3 * chip,OPL3_TIMERHANDLER timer_handler,void * param)2386 static void OPL3SetTimerHandler(OPL3 *chip,OPL3_TIMERHANDLER timer_handler,void *param)
2387 {
2388 chip->timer_handler = timer_handler;
2389 chip->TimerParam = param;
2390 }
OPL3SetIRQHandler(OPL3 * chip,OPL3_IRQHANDLER IRQHandler,void * param)2391 static void OPL3SetIRQHandler(OPL3 *chip,OPL3_IRQHANDLER IRQHandler,void *param)
2392 {
2393 chip->IRQHandler = IRQHandler;
2394 chip->IRQParam = param;
2395 }
OPL3SetUpdateHandler(OPL3 * chip,OPL3_UPDATEHANDLER UpdateHandler,void * param)2396 static void OPL3SetUpdateHandler(OPL3 *chip,OPL3_UPDATEHANDLER UpdateHandler,void *param)
2397 {
2398 chip->UpdateHandler = UpdateHandler;
2399 chip->UpdateParam = param;
2400 }
2401
2402 /* YMF262 I/O interface */
OPL3Write(OPL3 * chip,int a,int v)2403 static int OPL3Write(OPL3 *chip, int a, int v)
2404 {
2405 /* data bus is 8 bits */
2406 v &= 0xff;
2407
2408 switch(a&3)
2409 {
2410 case 0: /* address port 0 (register set #1) */
2411 chip->address = v;
2412 break;
2413
2414 case 1: /* data port - ignore A1 */
2415 case 3: /* data port - ignore A1 */
2416 if(chip->UpdateHandler) chip->UpdateHandler(chip->UpdateParam/*,0*/);
2417 OPL3WriteReg(chip,chip->address,v);
2418 break;
2419
2420 case 2: /* address port 1 (register set #2) */
2421
2422 /* verified on real YMF262:
2423 in OPL3 mode:
2424 address line A1 is stored during *address* write and ignored during *data* write.
2425
2426 in OPL2 mode:
2427 register set#2 writes go to register set#1 (ignoring A1)
2428 verified on registers from set#2: 0x01, 0x04, 0x20-0xef
2429 The only exception is register 0x05.
2430 */
2431 if( chip->OPL3_mode & 1 )
2432 {
2433 /* OPL3 mode */
2434 chip->address = v | 0x100;
2435 }
2436 else
2437 {
2438 /* in OPL2 mode the only accessible in set #2 is register 0x05 */
2439 if( v==5 )
2440 chip->address = v | 0x100;
2441 else
2442 chip->address = v; /* verified range: 0x01, 0x04, 0x20-0xef(set #2 becomes set #1 in opl2 mode) */
2443 }
2444 break;
2445 }
2446
2447 return chip->status>>7;
2448 }
2449
OPL3Read(OPL3 * chip,int a)2450 static unsigned char OPL3Read(OPL3 *chip,int a)
2451 {
2452 if( a==0 )
2453 {
2454 /* status port */
2455 return chip->status;
2456 }
2457
2458 return 0x00; /* verified on real YMF262 */
2459 }
2460
2461
2462
OPL3TimerOver(OPL3 * chip,int c)2463 static int OPL3TimerOver(OPL3 *chip,int c)
2464 {
2465 if( c )
2466 { /* Timer B */
2467 OPL3_STATUS_SET(chip,0x20);
2468 }
2469 else
2470 { /* Timer A */
2471 OPL3_STATUS_SET(chip,0x40);
2472 }
2473 /* reload timer */
2474 //if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,c,attotime_mul(chip->TimerBase, chip->T[c]));
2475 return chip->status>>7;
2476 }
2477
2478
2479
2480
ymf262_init(int clock,int rate)2481 void * ymf262_init(int clock, int rate)
2482 {
2483 return OPL3Create(clock,rate,OPL3_TYPE_YMF262);
2484 }
2485
ymf262_shutdown(void * chip)2486 void ymf262_shutdown(void *chip)
2487 {
2488 OPL3Destroy((OPL3 *)chip);
2489 }
ymf262_reset_chip(void * chip)2490 void ymf262_reset_chip(void *chip)
2491 {
2492 OPL3ResetChip((OPL3 *)chip);
2493 }
2494
ymf262_write(void * chip,int a,int v)2495 int ymf262_write(void *chip, int a, int v)
2496 {
2497 return OPL3Write((OPL3 *)chip, a, v);
2498 }
2499
ymf262_read(void * chip,int a)2500 unsigned char ymf262_read(void *chip, int a)
2501 {
2502 /* Note on status register: */
2503
2504 /* YM3526(OPL) and YM3812(OPL2) return bit2 and bit1 in HIGH state */
2505
2506 /* YMF262(OPL3) always returns bit2 and bit1 in LOW state */
2507 /* which can be used to identify the chip */
2508
2509 /* YMF278(OPL4) returns bit2 in LOW and bit1 in HIGH state ??? info from manual - not verified */
2510
2511 return OPL3Read((OPL3 *)chip, a);
2512 }
ymf262_timer_over(void * chip,int c)2513 int ymf262_timer_over(void *chip, int c)
2514 {
2515 return OPL3TimerOver((OPL3 *)chip, c);
2516 }
2517
ymf262_set_timer_handler(void * chip,OPL3_TIMERHANDLER timer_handler,void * param)2518 void ymf262_set_timer_handler(void *chip, OPL3_TIMERHANDLER timer_handler, void *param)
2519 {
2520 OPL3SetTimerHandler((OPL3 *)chip, timer_handler, param);
2521 }
ymf262_set_irq_handler(void * chip,OPL3_IRQHANDLER IRQHandler,void * param)2522 void ymf262_set_irq_handler(void *chip,OPL3_IRQHANDLER IRQHandler,void *param)
2523 {
2524 OPL3SetIRQHandler((OPL3 *)chip, IRQHandler, param);
2525 }
ymf262_set_update_handler(void * chip,OPL3_UPDATEHANDLER UpdateHandler,void * param)2526 void ymf262_set_update_handler(void *chip,OPL3_UPDATEHANDLER UpdateHandler,void *param)
2527 {
2528 OPL3SetUpdateHandler((OPL3 *)chip, UpdateHandler, param);
2529 }
2530
ymf262_set_mutemask(void * chip,UINT32 MuteMask)2531 void ymf262_set_mutemask(void *chip, UINT32 MuteMask)
2532 {
2533 OPL3 *opl3 = (OPL3 *)chip;
2534 UINT8 CurChn;
2535
2536 for (CurChn = 0; CurChn < 18; CurChn ++)
2537 opl3->P_CH[CurChn].Muted = (MuteMask >> CurChn) & 0x01;
2538 for (CurChn = 0; CurChn < 5; CurChn ++)
2539 opl3->MuteSpc[CurChn] = (MuteMask >> (CurChn + 18)) & 0x01;
2540
2541 return;
2542 }
2543
2544
2545 /*
2546 ** Generate samples for one of the YMF262's
2547 **
2548 ** 'which' is the virtual YMF262 number
2549 ** '**buffers' is table of 4 pointers to the buffers: CH.A, CH.B, CH.C and CH.D
2550 ** 'length' is the number of samples that should be generated
2551 */
ymf262_update_one(void * _chip,OPL3SAMPLE ** buffers,int length)2552 void ymf262_update_one(void *_chip, OPL3SAMPLE **buffers, int length)
2553 {
2554 OPL3 *chip = (OPL3 *)_chip;
2555 UINT8 rhythm = chip->rhythm&0x20;
2556
2557 OPL3SAMPLE *ch_a = buffers[0];
2558 OPL3SAMPLE *ch_b = buffers[1];
2559 //OPL3SAMPLE *ch_c = buffers[2];
2560 //OPL3SAMPLE *ch_d = buffers[3];
2561
2562 int i;
2563 int chn;
2564
2565 for( i=0; i < length ; i++ )
2566 {
2567 int a,b,c,d;
2568
2569
2570 advance_lfo(chip);
2571
2572 /* clear channel outputs */
2573 memset(chip->chanout, 0, sizeof(signed int) * 18);
2574
2575 #if 1
2576 /* register set #1 */
2577 chan_calc(chip, &chip->P_CH[0]); /* extended 4op ch#0 part 1 or 2op ch#0 */
2578 if (chip->P_CH[0].extended)
2579 chan_calc_ext(chip, &chip->P_CH[3]); /* extended 4op ch#0 part 2 */
2580 else
2581 chan_calc(chip, &chip->P_CH[3]); /* standard 2op ch#3 */
2582
2583
2584 chan_calc(chip, &chip->P_CH[1]); /* extended 4op ch#1 part 1 or 2op ch#1 */
2585 if (chip->P_CH[1].extended)
2586 chan_calc_ext(chip, &chip->P_CH[4]); /* extended 4op ch#1 part 2 */
2587 else
2588 chan_calc(chip, &chip->P_CH[4]); /* standard 2op ch#4 */
2589
2590
2591 chan_calc(chip, &chip->P_CH[2]); /* extended 4op ch#2 part 1 or 2op ch#2 */
2592 if (chip->P_CH[2].extended)
2593 chan_calc_ext(chip, &chip->P_CH[5]); /* extended 4op ch#2 part 2 */
2594 else
2595 chan_calc(chip, &chip->P_CH[5]); /* standard 2op ch#5 */
2596
2597
2598 if(!rhythm)
2599 {
2600 chan_calc(chip, &chip->P_CH[6]);
2601 chan_calc(chip, &chip->P_CH[7]);
2602 chan_calc(chip, &chip->P_CH[8]);
2603 }
2604 else /* Rhythm part */
2605 {
2606 chan_calc_rhythm(chip, &chip->P_CH[0], (chip->noise_rng>>0)&1 );
2607 }
2608
2609 /* register set #2 */
2610 chan_calc(chip, &chip->P_CH[ 9]);
2611 if (chip->P_CH[9].extended)
2612 chan_calc_ext(chip, &chip->P_CH[12]);
2613 else
2614 chan_calc(chip, &chip->P_CH[12]);
2615
2616
2617 chan_calc(chip, &chip->P_CH[10]);
2618 if (chip->P_CH[10].extended)
2619 chan_calc_ext(chip, &chip->P_CH[13]);
2620 else
2621 chan_calc(chip, &chip->P_CH[13]);
2622
2623
2624 chan_calc(chip, &chip->P_CH[11]);
2625 if (chip->P_CH[11].extended)
2626 chan_calc_ext(chip, &chip->P_CH[14]);
2627 else
2628 chan_calc(chip, &chip->P_CH[14]);
2629
2630
2631 /* channels 15,16,17 are fixed 2-operator channels only */
2632 chan_calc(chip, &chip->P_CH[15]);
2633 chan_calc(chip, &chip->P_CH[16]);
2634 chan_calc(chip, &chip->P_CH[17]);
2635 #endif
2636
2637 /* accumulator register set #1 */
2638 a = chip->chanout[0] & chip->pan[0];
2639 b = chip->chanout[0] & chip->pan[1];
2640 c = chip->chanout[0] & chip->pan[2];
2641 d = chip->chanout[0] & chip->pan[3];
2642 #if 1
2643 a += chip->chanout[1] & chip->pan[4];
2644 b += chip->chanout[1] & chip->pan[5];
2645 c += chip->chanout[1] & chip->pan[6];
2646 d += chip->chanout[1] & chip->pan[7];
2647 a += chip->chanout[2] & chip->pan[8];
2648 b += chip->chanout[2] & chip->pan[9];
2649 c += chip->chanout[2] & chip->pan[10];
2650 d += chip->chanout[2] & chip->pan[11];
2651
2652 a += chip->chanout[3] & chip->pan[12];
2653 b += chip->chanout[3] & chip->pan[13];
2654 c += chip->chanout[3] & chip->pan[14];
2655 d += chip->chanout[3] & chip->pan[15];
2656 a += chip->chanout[4] & chip->pan[16];
2657 b += chip->chanout[4] & chip->pan[17];
2658 c += chip->chanout[4] & chip->pan[18];
2659 d += chip->chanout[4] & chip->pan[19];
2660 a += chip->chanout[5] & chip->pan[20];
2661 b += chip->chanout[5] & chip->pan[21];
2662 c += chip->chanout[5] & chip->pan[22];
2663 d += chip->chanout[5] & chip->pan[23];
2664
2665 a += chip->chanout[6] & chip->pan[24];
2666 b += chip->chanout[6] & chip->pan[25];
2667 c += chip->chanout[6] & chip->pan[26];
2668 d += chip->chanout[6] & chip->pan[27];
2669 a += chip->chanout[7] & chip->pan[28];
2670 b += chip->chanout[7] & chip->pan[29];
2671 c += chip->chanout[7] & chip->pan[30];
2672 d += chip->chanout[7] & chip->pan[31];
2673 a += chip->chanout[8] & chip->pan[32];
2674 b += chip->chanout[8] & chip->pan[33];
2675 c += chip->chanout[8] & chip->pan[34];
2676 d += chip->chanout[8] & chip->pan[35];
2677
2678 /* accumulator register set #2 */
2679 a += chip->chanout[9] & chip->pan[36];
2680 b += chip->chanout[9] & chip->pan[37];
2681 c += chip->chanout[9] & chip->pan[38];
2682 d += chip->chanout[9] & chip->pan[39];
2683 a += chip->chanout[10] & chip->pan[40];
2684 b += chip->chanout[10] & chip->pan[41];
2685 c += chip->chanout[10] & chip->pan[42];
2686 d += chip->chanout[10] & chip->pan[43];
2687 a += chip->chanout[11] & chip->pan[44];
2688 b += chip->chanout[11] & chip->pan[45];
2689 c += chip->chanout[11] & chip->pan[46];
2690 d += chip->chanout[11] & chip->pan[47];
2691
2692 a += chip->chanout[12] & chip->pan[48];
2693 b += chip->chanout[12] & chip->pan[49];
2694 c += chip->chanout[12] & chip->pan[50];
2695 d += chip->chanout[12] & chip->pan[51];
2696 a += chip->chanout[13] & chip->pan[52];
2697 b += chip->chanout[13] & chip->pan[53];
2698 c += chip->chanout[13] & chip->pan[54];
2699 d += chip->chanout[13] & chip->pan[55];
2700 a += chip->chanout[14] & chip->pan[56];
2701 b += chip->chanout[14] & chip->pan[57];
2702 c += chip->chanout[14] & chip->pan[58];
2703 d += chip->chanout[14] & chip->pan[59];
2704
2705 a += chip->chanout[15] & chip->pan[60];
2706 b += chip->chanout[15] & chip->pan[61];
2707 c += chip->chanout[15] & chip->pan[62];
2708 d += chip->chanout[15] & chip->pan[63];
2709 a += chip->chanout[16] & chip->pan[64];
2710 b += chip->chanout[16] & chip->pan[65];
2711 c += chip->chanout[16] & chip->pan[66];
2712 d += chip->chanout[16] & chip->pan[67];
2713 a += chip->chanout[17] & chip->pan[68];
2714 b += chip->chanout[17] & chip->pan[69];
2715 c += chip->chanout[17] & chip->pan[70];
2716 d += chip->chanout[17] & chip->pan[71];
2717 #endif
2718 a >>= FINAL_SH;
2719 b >>= FINAL_SH;
2720 c >>= FINAL_SH;
2721 d >>= FINAL_SH;
2722
2723 /* limit check */
2724 //a = limit( a , MAXOUT, MINOUT );
2725 //b = limit( b , MAXOUT, MINOUT );
2726 //c = limit( c , MAXOUT, MINOUT );
2727 //d = limit( d , MAXOUT, MINOUT );
2728
2729 #ifdef SAVE_SAMPLE
2730 if (which==0)
2731 {
2732 SAVE_ALL_CHANNELS
2733 }
2734 #endif
2735
2736 /* store to sound buffer */
2737 ch_a[i] = a+c;
2738 ch_b[i] = b+d;
2739 //ch_c[i] = c;
2740 //ch_d[i] = d;
2741
2742 advance(chip);
2743 }
2744
2745 }
2746
2747