1 // license:GPL-2.0+
2 // copyright-holders:Jarek Burczynski,Tatsuyuki Satoh
3 /*
4 **
5 ** File: fm.c -- software implementation of Yamaha FM sound generator
6 **
7 ** Copyright Jarek Burczynski (bujar at mame dot net)
8 ** Copyright Tatsuyuki Satoh , MultiArcadeMachineEmulator development
9 **
10 ** Version 1.4.2 (final beta)
11 **
12 */
13
14 /*
15 ** History:
16 **
17 ** 2018 Jean Pierre Cimalando (libOPNMIDI)
18 ** - rewrote pooled memory allocations as ordinary new and delete
19 **
20 ** 2006-2008 Eke-Eke (Genesis Plus GX), MAME backport by R. Belmont.
21 ** - implemented PG overflow, aka "detune bug" (Ariel, Comix Zone, Shaq Fu, Spiderman,...), credits to Nemesis
22 ** - fixed SSG-EG support, credits to Nemesis and additional fixes from Alone Coder
23 ** - modified EG rates and frequency, tested by Nemesis on real hardware
24 ** - implemented LFO phase update for CH3 special mode (Warlock birds, Alladin bug sound)
25 ** - fixed Attack Rate update (Batman & Robin intro)
26 ** - fixed attenuation level at the start of Substain (Gynoug explosions)
27 ** - fixed EG decay->substain transition to handle special cases, like SL=0 and Decay rate is very slow (Mega Turrican tracks 03,09...)
28 **
29 ** 06-23-2007 Zsolt Vasvari:
30 ** - changed the timing not to require the use of floating point calculations
31 **
32 ** 03-08-2003 Jarek Burczynski:
33 ** - fixed YM2608 initial values (after the reset)
34 ** - fixed flag and irqmask handling (YM2608)
35 ** - fixed BUFRDY flag handling (YM2608)
36 **
37 ** 14-06-2003 Jarek Burczynski:
38 ** - implemented all of the YM2608 status register flags
39 ** - implemented support for external memory read/write via YM2608
40 ** - implemented support for deltat memory limit register in YM2608 emulation
41 **
42 ** 22-05-2003 Jarek Burczynski:
43 ** - fixed LFO PM calculations (copy&paste bugfix)
44 **
45 ** 08-05-2003 Jarek Burczynski:
46 ** - fixed SSG support
47 **
48 ** 22-04-2003 Jarek Burczynski:
49 ** - implemented 100% correct LFO generator (verified on real YM2610 and YM2608)
50 **
51 ** 15-04-2003 Jarek Burczynski:
52 ** - added support for YM2608's register 0x110 - status mask
53 **
54 ** 01-12-2002 Jarek Burczynski:
55 ** - fixed register addressing in YM2608, YM2610, YM2610B chips. (verified on real YM2608)
56 ** The addressing patch used for early Neo-Geo games can be removed now.
57 **
58 ** 26-11-2002 Jarek Burczynski, Nicola Salmoria:
59 ** - recreated YM2608 ADPCM ROM using data from real YM2608's output which leads to:
60 ** - added emulation of YM2608 drums.
61 ** - output of YM2608 is two times lower now - same as YM2610 (verified on real YM2608)
62 **
63 ** 16-08-2002 Jarek Burczynski:
64 ** - binary exact Envelope Generator (verified on real YM2203);
65 ** identical to YM2151
66 ** - corrected 'off by one' error in feedback calculations (when feedback is off)
67 ** - corrected connection (algorithm) calculation (verified on real YM2203 and YM2610)
68 **
69 ** 18-12-2001 Jarek Burczynski:
70 ** - added SSG-EG support (verified on real YM2203)
71 **
72 ** 12-08-2001 Jarek Burczynski:
73 ** - corrected sin_tab and tl_tab data (verified on real chip)
74 ** - corrected feedback calculations (verified on real chip)
75 ** - corrected phase generator calculations (verified on real chip)
76 ** - corrected envelope generator calculations (verified on real chip)
77 ** - corrected FM volume level (YM2610 and YM2610B).
78 ** - changed YMxxxUpdateOne() functions (YM2203, YM2608, YM2610, YM2610B, YM2612) :
79 ** this was needed to calculate YM2610 FM channels output correctly.
80 ** (Each FM channel is calculated as in other chips, but the output of the channel
81 ** gets shifted right by one *before* sending to accumulator. That was impossible to do
82 ** with previous implementation).
83 **
84 ** 23-07-2001 Jarek Burczynski, Nicola Salmoria:
85 ** - corrected YM2610 ADPCM type A algorithm and tables (verified on real chip)
86 **
87 ** 11-06-2001 Jarek Burczynski:
88 ** - corrected end of sample bug in ADPCMA_calc_cha().
89 ** Real YM2610 checks for equality between current and end addresses (only 20 LSB bits).
90 **
91 ** 08-12-98 hiro-shi:
92 ** rename ADPCMA -> ADPCMB, ADPCMB -> ADPCMA
93 ** move ROM limit check.(CALC_CH? -> 2610Write1/2)
94 ** test program (ADPCMB_TEST)
95 ** move ADPCM A/B end check.
96 ** ADPCMB repeat flag(no check)
97 ** change ADPCM volume rate (8->16) (32->48).
98 **
99 ** 09-12-98 hiro-shi:
100 ** change ADPCM volume. (8->16, 48->64)
101 ** replace ym2610 ch0/3 (YM-2610B)
102 ** change ADPCM_SHIFT (10->8) missing bank change 0x4000-0xffff.
103 ** add ADPCM_SHIFT_MASK
104 ** change ADPCMA_DECODE_MIN/MAX.
105 */
106
107
108
109
110 /************************************************************************/
111 /* comment of hiro-shi(Hiromitsu Shioya) */
112 /* YM2610(B) = OPN-B */
113 /* YM2610 : PSG:3ch FM:4ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
114 /* YM2610B : PSG:3ch FM:6ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
115 /************************************************************************/
116
117 #include "emu.h"
118
119 #define YM2610B_WARNING
120 #include "fm.h"
121
122
123 /* include external DELTA-T unit (when needed) */
124 #if (BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B)
125 #include "ymdeltat.h"
126 #endif
127
128
129 #if BUILD_YM2203
130 #include "2203intf.h"
131 #endif /* BUILD_YM2203 */
132
133 #if BUILD_YM2608
134 #include "2608intf.h"
135 #endif /* BUILD_YM2608 */
136
137 #if (BUILD_YM2610||BUILD_YM2610B)
138 #include "2610intf.h"
139 #endif /* (BUILD_YM2610||BUILD_YM2610B) */
140
141
142 /* shared function building option */
143 #define BUILD_OPN (BUILD_YM2203||BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B)
144 #define BUILD_OPN_PRESCALER (BUILD_YM2203||BUILD_YM2608)
145
146
147 /* globals */
148 #define TYPE_SSG 0x01 /* SSG support */
149 #define TYPE_LFOPAN 0x02 /* OPN type LFO and PAN */
150 #define TYPE_6CH 0x04 /* FM 6CH / 3CH */
151 #define TYPE_DAC 0x08 /* YM2612's DAC device */
152 #define TYPE_ADPCM 0x10 /* two ADPCM units */
153 #define TYPE_2610 0x20 /* bogus flag to differentiate 2608 from 2610 */
154
155
156 #define TYPE_YM2203 (TYPE_SSG)
157 #define TYPE_YM2608 (TYPE_SSG |TYPE_LFOPAN |TYPE_6CH |TYPE_ADPCM)
158 #define TYPE_YM2610 (TYPE_SSG |TYPE_LFOPAN |TYPE_6CH |TYPE_ADPCM |TYPE_2610)
159
160
161
162 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
163 #define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
164 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
165 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
166
167 #define FREQ_MASK ((1<<FREQ_SH)-1)
168
169 #define ENV_BITS 10
170 #define ENV_LEN (1<<ENV_BITS)
171 #define ENV_STEP (128.0/ENV_LEN)
172
173 #define MAX_ATT_INDEX (ENV_LEN-1) /* 1023 */
174 #define MIN_ATT_INDEX (0) /* 0 */
175
176 #define EG_ATT 4
177 #define EG_DEC 3
178 #define EG_SUS 2
179 #define EG_REL 1
180 #define EG_OFF 0
181
182 #define SIN_BITS 10
183 #define SIN_LEN (1<<SIN_BITS)
184 #define SIN_MASK (SIN_LEN-1)
185
186 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
187
188
189 #if (FM_SAMPLE_BITS==16)
190 #define FINAL_SH (0)
191 #define MAXOUT (+32767)
192 #define MINOUT (-32768)
193 #else
194 #define FINAL_SH (8)
195 #define MAXOUT (+127)
196 #define MINOUT (-128)
197 #endif
198
199
200 /* TL_TAB_LEN is calculated as:
201 * 13 - sinus amplitude bits (Y axis)
202 * 2 - sinus sign bit (Y axis)
203 * TL_RES_LEN - sinus resolution (X axis)
204 */
205 #define TL_TAB_LEN (13*2*TL_RES_LEN)
206 static signed int tl_tab[TL_TAB_LEN];
207
208 #define ENV_QUIET (TL_TAB_LEN>>3)
209
210 /* sin waveform table in 'decibel' scale */
211 static unsigned int sin_tab[SIN_LEN];
212
213 /* sustain level table (3dB per step) */
214 /* bit0, bit1, bit2, bit3, bit4, bit5, bit6 */
215 /* 1, 2, 4, 8, 16, 32, 64 (value)*/
216 /* 0.75, 1.5, 3, 6, 12, 24, 48 (dB)*/
217
218 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
219 #define SC(db) (uint32_t) ( db * (4.0/ENV_STEP) )
220 static const uint32_t sl_table[16]={
221 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
222 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
223 };
224 #undef SC
225
226
227 #define RATE_STEPS (8)
228 static const uint8_t eg_inc[19*RATE_STEPS]={
229 /*cycle:0 1 2 3 4 5 6 7*/
230
231 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..11 0 (increment by 0 or 1) */
232 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..11 1 */
233 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..11 2 */
234 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..11 3 */
235
236 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 12 0 (increment by 1) */
237 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 12 1 */
238 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 12 2 */
239 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 12 3 */
240
241 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 13 0 (increment by 2) */
242 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 13 1 */
243 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 13 2 */
244 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 13 3 */
245
246 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rate 14 0 (increment by 4) */
247 /*13 */ 4,4, 4,8, 4,4, 4,8, /* rate 14 1 */
248 /*14 */ 4,8, 4,8, 4,8, 4,8, /* rate 14 2 */
249 /*15 */ 4,8, 8,8, 4,8, 8,8, /* rate 14 3 */
250
251 /*16 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
252 /*17 */ 16,16,16,16,16,16,16,16, /* rates 15 2, 15 3 for attack */
253 /*18 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
254 };
255
256
257 #define O(a) (a*RATE_STEPS)
258
259 /*note that there is no O(17) in this table - it's directly in the code */
260 static const uint8_t eg_rate_select[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
261 /* 32 infinite time rates */
262 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
263 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
264 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
265 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
266
267 /* rates 00-11 */
268 O( 0),O( 1),O( 2),O( 3),
269 O( 0),O( 1),O( 2),O( 3),
270 O( 0),O( 1),O( 2),O( 3),
271 O( 0),O( 1),O( 2),O( 3),
272 O( 0),O( 1),O( 2),O( 3),
273 O( 0),O( 1),O( 2),O( 3),
274 O( 0),O( 1),O( 2),O( 3),
275 O( 0),O( 1),O( 2),O( 3),
276 O( 0),O( 1),O( 2),O( 3),
277 O( 0),O( 1),O( 2),O( 3),
278 O( 0),O( 1),O( 2),O( 3),
279 O( 0),O( 1),O( 2),O( 3),
280
281 /* rate 12 */
282 O( 4),O( 5),O( 6),O( 7),
283
284 /* rate 13 */
285 O( 8),O( 9),O(10),O(11),
286
287 /* rate 14 */
288 O(12),O(13),O(14),O(15),
289
290 /* rate 15 */
291 O(16),O(16),O(16),O(16),
292
293 /* 32 dummy rates (same as 15 3) */
294 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
295 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
296 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
297 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
298
299 };
300
301 #undef O
302
303 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15*/
304 /*shift 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0 */
305 /*mask 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0, 0 */
306
307 #define O(a) (a*1)
308 static const uint8_t eg_rate_shift[32+64+32]={ /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
309 /* 32 infinite time rates */
310 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
311 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
312 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
313 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
314
315 /* rates 00-11 */
316 O(11),O(11),O(11),O(11),
317 O(10),O(10),O(10),O(10),
318 O( 9),O( 9),O( 9),O( 9),
319 O( 8),O( 8),O( 8),O( 8),
320 O( 7),O( 7),O( 7),O( 7),
321 O( 6),O( 6),O( 6),O( 6),
322 O( 5),O( 5),O( 5),O( 5),
323 O( 4),O( 4),O( 4),O( 4),
324 O( 3),O( 3),O( 3),O( 3),
325 O( 2),O( 2),O( 2),O( 2),
326 O( 1),O( 1),O( 1),O( 1),
327 O( 0),O( 0),O( 0),O( 0),
328
329 /* rate 12 */
330 O( 0),O( 0),O( 0),O( 0),
331
332 /* rate 13 */
333 O( 0),O( 0),O( 0),O( 0),
334
335 /* rate 14 */
336 O( 0),O( 0),O( 0),O( 0),
337
338 /* rate 15 */
339 O( 0),O( 0),O( 0),O( 0),
340
341 /* 32 dummy rates (same as 15 3) */
342 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
343 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
344 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
345 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0)
346
347 };
348 #undef O
349
350 static const uint8_t dt_tab[4 * 32]={
351 /* this is YM2151 and YM2612 phase increment data (in 10.10 fixed point format)*/
352 /* FD=0 */
353 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
354 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
355 /* FD=1 */
356 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
357 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
358 /* FD=2 */
359 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
360 5, 6, 6, 7, 8, 8, 9,10,11,12,13,14,16,16,16,16,
361 /* FD=3 */
362 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
363 8 , 8, 9,10,11,12,13,14,16,17,19,20,22,22,22,22
364 };
365
366
367 /* OPN key frequency number -> key code follow table */
368 /* fnum higher 4bit -> keycode lower 2bit */
369 static const uint8_t opn_fktable[16] = {0,0,0,0,0,0,0,1,2,3,3,3,3,3,3,3};
370
371
372 /* 8 LFO speed parameters */
373 /* each value represents number of samples that one LFO level will last for */
374 static const uint32_t lfo_samples_per_step[8] = {108, 77, 71, 67, 62, 44, 8, 5};
375
376
377
378 /*There are 4 different LFO AM depths available, they are:
379 0 dB, 1.4 dB, 5.9 dB, 11.8 dB
380 Here is how it is generated (in EG steps):
381
382 11.8 dB = 0, 2, 4, 6, 8, 10,12,14,16...126,126,124,122,120,118,....4,2,0
383 5.9 dB = 0, 1, 2, 3, 4, 5, 6, 7, 8....63, 63, 62, 61, 60, 59,.....2,1,0
384 1.4 dB = 0, 0, 0, 0, 1, 1, 1, 1, 2,...15, 15, 15, 15, 14, 14,.....0,0,0
385
386 (1.4 dB is losing precision as you can see)
387
388 It's implemented as generator from 0..126 with step 2 then a shift
389 right N times, where N is:
390 8 for 0 dB
391 3 for 1.4 dB
392 1 for 5.9 dB
393 0 for 11.8 dB
394 */
395 static const uint8_t lfo_ams_depth_shift[4] = {8, 3, 1, 0};
396
397
398
399 /*There are 8 different LFO PM depths available, they are:
400 0, 3.4, 6.7, 10, 14, 20, 40, 80 (cents)
401
402 Modulation level at each depth depends on F-NUMBER bits: 4,5,6,7,8,9,10
403 (bits 8,9,10 = FNUM MSB from OCT/FNUM register)
404
405 Here we store only first quarter (positive one) of full waveform.
406 Full table (lfo_pm_table) containing all 128 waveforms is build
407 at run (init) time.
408
409 One value in table below represents 4 (four) basic LFO steps
410 (1 PM step = 4 AM steps).
411
412 For example:
413 at LFO SPEED=0 (which is 108 samples per basic LFO step)
414 one value from "lfo_pm_output" table lasts for 432 consecutive
415 samples (4*108=432) and one full LFO waveform cycle lasts for 13824
416 samples (32*432=13824; 32 because we store only a quarter of whole
417 waveform in the table below)
418 */
419 static const uint8_t lfo_pm_output[7*8][8]={ /* 7 bits meaningful (of F-NUMBER), 8 LFO output levels per one depth (out of 32), 8 LFO depths */
420 /* FNUM BIT 4: 000 0001xxxx */
421 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
422 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
423 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
424 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
425 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
426 /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
427 /* DEPTH 6 */ {0, 0, 0, 0, 0, 0, 0, 0},
428 /* DEPTH 7 */ {0, 0, 0, 0, 1, 1, 1, 1},
429
430 /* FNUM BIT 5: 000 0010xxxx */
431 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
432 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
433 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
434 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
435 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
436 /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
437 /* DEPTH 6 */ {0, 0, 0, 0, 1, 1, 1, 1},
438 /* DEPTH 7 */ {0, 0, 1, 1, 2, 2, 2, 3},
439
440 /* FNUM BIT 6: 000 0100xxxx */
441 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
442 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
443 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
444 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
445 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 1},
446 /* DEPTH 5 */ {0, 0, 0, 0, 1, 1, 1, 1},
447 /* DEPTH 6 */ {0, 0, 1, 1, 2, 2, 2, 3},
448 /* DEPTH 7 */ {0, 0, 2, 3, 4, 4, 5, 6},
449
450 /* FNUM BIT 7: 000 1000xxxx */
451 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
452 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
453 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 1, 1},
454 /* DEPTH 3 */ {0, 0, 0, 0, 1, 1, 1, 1},
455 /* DEPTH 4 */ {0, 0, 0, 1, 1, 1, 1, 2},
456 /* DEPTH 5 */ {0, 0, 1, 1, 2, 2, 2, 3},
457 /* DEPTH 6 */ {0, 0, 2, 3, 4, 4, 5, 6},
458 /* DEPTH 7 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
459
460 /* FNUM BIT 8: 001 0000xxxx */
461 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
462 /* DEPTH 1 */ {0, 0, 0, 0, 1, 1, 1, 1},
463 /* DEPTH 2 */ {0, 0, 0, 1, 1, 1, 2, 2},
464 /* DEPTH 3 */ {0, 0, 1, 1, 2, 2, 3, 3},
465 /* DEPTH 4 */ {0, 0, 1, 2, 2, 2, 3, 4},
466 /* DEPTH 5 */ {0, 0, 2, 3, 4, 4, 5, 6},
467 /* DEPTH 6 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
468 /* DEPTH 7 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
469
470 /* FNUM BIT 9: 010 0000xxxx */
471 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
472 /* DEPTH 1 */ {0, 0, 0, 0, 2, 2, 2, 2},
473 /* DEPTH 2 */ {0, 0, 0, 2, 2, 2, 4, 4},
474 /* DEPTH 3 */ {0, 0, 2, 2, 4, 4, 6, 6},
475 /* DEPTH 4 */ {0, 0, 2, 4, 4, 4, 6, 8},
476 /* DEPTH 5 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
477 /* DEPTH 6 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
478 /* DEPTH 7 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
479
480 /* FNUM BIT10: 100 0000xxxx */
481 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
482 /* DEPTH 1 */ {0, 0, 0, 0, 4, 4, 4, 4},
483 /* DEPTH 2 */ {0, 0, 0, 4, 4, 4, 8, 8},
484 /* DEPTH 3 */ {0, 0, 4, 4, 8, 8, 0xc, 0xc},
485 /* DEPTH 4 */ {0, 0, 4, 8, 8, 8, 0xc,0x10},
486 /* DEPTH 5 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
487 /* DEPTH 6 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
488 /* DEPTH 7 */ {0, 0,0x20,0x30,0x40,0x40,0x50,0x60},
489
490 };
491
492 /* all 128 LFO PM waveforms */
493 static int32_t lfo_pm_table[128*8*32]; /* 128 combinations of 7 bits meaningful (of F-NUMBER), 8 LFO depths, 32 LFO output levels per one depth */
494
495
496 // libOPNMIDI: pan law table
497 static const uint16_t panlawtable[] =
498 {
499 65535, 65529, 65514, 65489, 65454, 65409, 65354, 65289,
500 65214, 65129, 65034, 64929, 64814, 64689, 64554, 64410,
501 64255, 64091, 63917, 63733, 63540, 63336, 63123, 62901,
502 62668, 62426, 62175, 61914, 61644, 61364, 61075, 60776,
503 60468, 60151, 59825, 59489, 59145, 58791, 58428, 58057,
504 57676, 57287, 56889, 56482, 56067, 55643, 55211, 54770,
505 54320, 53863, 53397, 52923, 52441, 51951, 51453, 50947,
506 50433, 49912, 49383, 48846, 48302, 47750, 47191,
507 46340, /* Center left */
508 46340, /* Center right */
509 45472, 44885, 44291, 43690, 43083, 42469, 41848, 41221,
510 40588, 39948, 39303, 38651, 37994, 37330, 36661, 35986,
511 35306, 34621, 33930, 33234, 32533, 31827, 31116, 30400,
512 29680, 28955, 28225, 27492, 26754, 26012, 25266, 24516,
513 23762, 23005, 22244, 21480, 20713, 19942, 19169, 18392,
514 17613, 16831, 16046, 15259, 14469, 13678, 12884, 12088,
515 11291, 10492, 9691, 8888, 8085, 7280, 6473, 5666,
516 4858, 4050, 3240, 2431, 1620, 810, 0
517 };
518
519
520 /* register number to channel number , slot offset */
521 #define OPN_CHAN(N) (N&3)
522 #define OPN_SLOT(N) ((N>>2)&3)
523
524 /* slot number */
525 #define SLOT1 0
526 #define SLOT2 2
527 #define SLOT3 1
528 #define SLOT4 3
529
530 /* bit0 = Right enable , bit1 = Left enable */
531 #define OUTD_RIGHT 1
532 #define OUTD_LEFT 2
533 #define OUTD_CENTER 3
534
535
536 /* save output as raw 16-bit sample */
537 /* #define SAVE_SAMPLE */
538
539 #ifdef SAVE_SAMPLE
540 static FILE *sample[1];
541 #if 1 /*save to MONO file */
542 #define SAVE_ALL_CHANNELS \
543 { signed int pom = lt; \
544 fputc((unsigned short)pom&0xff,sample[0]); \
545 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
546 }
547 #else /*save to STEREO file */
548 #define SAVE_ALL_CHANNELS \
549 { signed int pom = lt; \
550 fputc((unsigned short)pom&0xff,sample[0]); \
551 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
552 pom = rt; \
553 fputc((unsigned short)pom&0xff,sample[0]); \
554 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
555 }
556 #endif
557 #endif
558
559
560 /* struct describing a single operator (SLOT) */
561 struct FM_SLOT
562 {
563 int32_t *DT; /* detune :dt_tab[DT] */
564 uint8_t KSR; /* key scale rate :3-KSR */
565 uint32_t ar; /* attack rate */
566 uint32_t d1r; /* decay rate */
567 uint32_t d2r; /* sustain rate */
568 uint32_t rr; /* release rate */
569 uint8_t ksr; /* key scale rate :kcode>>(3-KSR) */
570 uint32_t mul; /* multiple :ML_TABLE[ML] */
571
572 /* Phase Generator */
573 uint32_t phase; /* phase counter */
574 int32_t Incr; /* phase step */
575
576 /* Envelope Generator */
577 uint8_t state; /* phase type */
578 uint32_t tl; /* total level: TL << 3 */
579 int32_t volume; /* envelope counter */
580 uint32_t sl; /* sustain level:sl_table[SL] */
581 uint32_t vol_out; /* current output from EG circuit (without AM from LFO) */
582
583 uint8_t eg_sh_ar; /* (attack state) */
584 uint8_t eg_sel_ar; /* (attack state) */
585 uint8_t eg_sh_d1r; /* (decay state) */
586 uint8_t eg_sel_d1r; /* (decay state) */
587 uint8_t eg_sh_d2r; /* (sustain state) */
588 uint8_t eg_sel_d2r; /* (sustain state) */
589 uint8_t eg_sh_rr; /* (release state) */
590 uint8_t eg_sel_rr; /* (release state) */
591
592 uint8_t ssg; /* SSG-EG waveform */
593 uint8_t ssgn; /* SSG-EG negated output */
594
595 uint32_t key; /* 0=last key was KEY OFF, 1=KEY ON */
596
597 /* LFO */
598 uint32_t AMmask; /* AM enable flag */
599
600 };
601
602 struct FM_CH
603 {
604 FM_SLOT SLOT[4]; /* four SLOTs (operators) */
605
606 uint8_t ALGO; /* algorithm */
607 uint8_t FB; /* feedback shift */
608 int32_t op1_out[2]; /* op1 output for feedback */
609
610 int32_t *connect1; /* SLOT1 output pointer */
611 int32_t *connect3; /* SLOT3 output pointer */
612 int32_t *connect2; /* SLOT2 output pointer */
613 int32_t *connect4; /* SLOT4 output pointer */
614
615 int32_t *mem_connect;/* where to put the delayed sample (MEM) */
616 int32_t mem_value; /* delayed sample (MEM) value */
617
618 int32_t pms; /* channel PMS */
619 uint8_t ams; /* channel AMS */
620
621 uint32_t fc; /* fnum,blk:adjusted to sample rate */
622 uint8_t kcode; /* key code: */
623 uint32_t block_fnum; /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
624
625 int32_t pan_volume_l; /* libOPNMIDI: left panning amount */
626 int32_t pan_volume_r; /* libOPNMIDI: right panning amount */
627 };
628
629
630 struct FM_ST
631 {
632 device_t *device;
633 int clock; /* master clock (Hz) */
634 int rate; /* sampling rate (Hz) */
635 double freqbase; /* frequency base */
636 int timer_prescaler; /* timer prescaler */
637 #if FM_BUSY_FLAG_SUPPORT
638 TIME_TYPE busy_expiry_time; /* expiry time of the busy status */
639 #endif
640 uint8_t address; /* address register */
641 uint8_t irq; /* interrupt level */
642 uint8_t irqmask; /* irq mask */
643 uint8_t status; /* status flag */
644 uint32_t mode; /* mode CSM / 3SLOT */
645 uint8_t prescaler_sel; /* prescaler selector */
646 uint8_t fn_h; /* freq latch */
647 int32_t TA; /* timer a */
648 int32_t TAC; /* timer a counter */
649 uint8_t TB; /* timer b */
650 int32_t TBC; /* timer b counter */
651 /* local time tables */
652 int32_t dt_tab[8][32]; /* DeTune table */
653 /* Extention Timer and IRQ handler */
654 FM_TIMERHANDLER timer_handler;
655 FM_IRQHANDLER IRQ_Handler;
656 const ssg_callbacks *SSG;
657 };
658
659
660
661 /***********************************************************/
662 /* OPN unit */
663 /***********************************************************/
664
665 /* OPN 3slot struct */
666 struct FM_3SLOT
667 {
668 uint32_t fc[3]; /* fnum3,blk3: calculated */
669 uint8_t fn_h; /* freq3 latch */
670 uint8_t kcode[3]; /* key code */
671 uint32_t block_fnum[3]; /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
672 };
673
674 /* OPN/A/B common state */
675 struct FM_OPN
676 {
677 uint8_t type; /* chip type */
678 FM_ST ST; /* general state */
679 FM_3SLOT SL3; /* 3 slot mode state */
680 FM_CH *P_CH; /* pointer of CH */
681 unsigned int pan[6*2]; /* fm channels output masks (0xffffffff = enable) */
682
683 uint32_t eg_cnt; /* global envelope generator counter */
684 uint32_t eg_timer; /* global envelope generator counter works at frequency = chipclock/64/3 */
685 uint32_t eg_timer_add; /* step of eg_timer */
686 uint32_t eg_timer_overflow;/* envelope generator timer overflows every 3 samples (on real chip) */
687
688
689 /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
690 but LFO works with one more bit of a precision so we really need 4096 elements */
691
692 uint32_t fn_table[4096]; /* fnumber->increment counter */
693 uint32_t fn_max; /* maximal phase increment (used for phase overflow) */
694
695 /* LFO */
696 uint32_t LFO_AM; /* runtime LFO calculations helper */
697 int32_t LFO_PM; /* runtime LFO calculations helper */
698
699 uint32_t lfo_cnt;
700 uint32_t lfo_inc;
701
702 uint32_t lfo_freq[8]; /* LFO FREQ table */
703
704 int32_t m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
705 int32_t mem; /* one sample delay memory */
706
707 int32_t out_fm[8]; /* outputs of working channels */
708
709 #if (BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B)
710 int32_t out_adpcm[4]; /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 ADPCM */
711 int32_t out_delta[4]; /* channel output NONE,LEFT,RIGHT or CENTER for YM2608/YM2610 DELTAT*/
712 #endif
713 };
714
715
716
717 /* current chip state */
718
719 /* log output level */
720 #define LOG_ERR 3 /* ERROR */
721 #define LOG_WAR 2 /* WARNING */
722 #define LOG_INF 1 /* INFORMATION */
723 #define LOG_LEVEL LOG_INF
724
725 #ifndef __RAINE__
726 #define LOG(d,n,x) do { if( (n)>=LOG_LEVEL ) d->logerror x; } while (0)
727 #endif
728
729 /* limitter */
730 #define Limit(val, max,min) { \
731 if ( val > max ) val = max; \
732 else if ( val < min ) val = min; \
733 }
734
735
736 /* status set and IRQ handling */
FM_STATUS_SET(FM_ST * ST,int flag)737 static inline void FM_STATUS_SET(FM_ST *ST,int flag)
738 {
739 /* set status flag */
740 ST->status |= flag;
741 if ( !(ST->irq) && (ST->status & ST->irqmask) )
742 {
743 ST->irq = 1;
744 /* callback user interrupt handler (IRQ is OFF to ON) */
745 if(ST->IRQ_Handler) (ST->IRQ_Handler)(ST->device,1);
746 }
747 }
748
749 /* status reset and IRQ handling */
FM_STATUS_RESET(FM_ST * ST,int flag)750 static inline void FM_STATUS_RESET(FM_ST *ST,int flag)
751 {
752 /* reset status flag */
753 ST->status &=~flag;
754 if ( (ST->irq) && !(ST->status & ST->irqmask) )
755 {
756 ST->irq = 0;
757 /* callback user interrupt handler (IRQ is ON to OFF) */
758 if(ST->IRQ_Handler) (ST->IRQ_Handler)(ST->device,0);
759 }
760 }
761
762 /* IRQ mask set */
FM_IRQMASK_SET(FM_ST * ST,int flag)763 static inline void FM_IRQMASK_SET(FM_ST *ST,int flag)
764 {
765 ST->irqmask = flag;
766 /* IRQ handling check */
767 FM_STATUS_SET(ST,0);
768 FM_STATUS_RESET(ST,0);
769 }
770
771 /* OPN Mode Register Write */
set_timers(FM_ST * ST,device_t * n,int v)772 static inline void set_timers( FM_ST *ST, device_t *n, int v )
773 {
774 /* b7 = CSM MODE */
775 /* b6 = 3 slot mode */
776 /* b5 = reset b */
777 /* b4 = reset a */
778 /* b3 = timer enable b */
779 /* b2 = timer enable a */
780 /* b1 = load b */
781 /* b0 = load a */
782 ST->mode = v;
783
784 /* reset Timer b flag */
785 if( v & 0x20 )
786 FM_STATUS_RESET(ST,0x02);
787 /* reset Timer a flag */
788 if( v & 0x10 )
789 FM_STATUS_RESET(ST,0x01);
790 /* load b */
791 if( v & 0x02 )
792 {
793 if( ST->TBC == 0 )
794 {
795 ST->TBC = ( 256-ST->TB)<<4;
796 /* External timer handler */
797 if (ST->timer_handler) (ST->timer_handler)(n,1,ST->TBC * ST->timer_prescaler,ST->clock);
798 }
799 }
800 else
801 { /* stop timer b */
802 if( ST->TBC != 0 )
803 {
804 ST->TBC = 0;
805 if (ST->timer_handler) (ST->timer_handler)(n,1,0,ST->clock);
806 }
807 }
808 /* load a */
809 if( v & 0x01 )
810 {
811 if( ST->TAC == 0 )
812 {
813 ST->TAC = (1024-ST->TA);
814 /* External timer handler */
815 if (ST->timer_handler) (ST->timer_handler)(n,0,ST->TAC * ST->timer_prescaler,ST->clock);
816 }
817 }
818 else
819 { /* stop timer a */
820 if( ST->TAC != 0 )
821 {
822 ST->TAC = 0;
823 if (ST->timer_handler) (ST->timer_handler)(n,0,0,ST->clock);
824 }
825 }
826 }
827
828
829 /* Timer A Overflow */
TimerAOver(FM_ST * ST)830 static inline void TimerAOver(FM_ST *ST)
831 {
832 /* set status (if enabled) */
833 if(ST->mode & 0x04) FM_STATUS_SET(ST,0x01);
834 /* clear or reload the counter */
835 ST->TAC = (1024-ST->TA);
836 if (ST->timer_handler) (ST->timer_handler)(ST->device,0,ST->TAC * ST->timer_prescaler,ST->clock);
837 }
838 /* Timer B Overflow */
TimerBOver(FM_ST * ST)839 static inline void TimerBOver(FM_ST *ST)
840 {
841 /* set status (if enabled) */
842 if(ST->mode & 0x08) FM_STATUS_SET(ST,0x02);
843 /* clear or reload the counter */
844 ST->TBC = ( 256-ST->TB)<<4;
845 if (ST->timer_handler) (ST->timer_handler)(ST->device,1,ST->TBC * ST->timer_prescaler,ST->clock);
846 }
847
848
849 #if FM_INTERNAL_TIMER
850 /* ----- internal timer mode , update timer */
851
852 /* ---------- calculate timer A ---------- */
853 #define INTERNAL_TIMER_A(ST,CSM_CH) \
854 { \
855 if( ST->TAC && (ST->timer_handler==0) ) \
856 if( (ST->TAC -= (int)(ST->freqbase*4096)) <= 0 ) \
857 { \
858 TimerAOver( ST ); \
859 /* CSM mode total level latch and auto key on */ \
860 if( ST->mode & 0x80 ) \
861 CSMKeyControll( CSM_CH ); \
862 } \
863 }
864 /* ---------- calculate timer B ---------- */
865 #define INTERNAL_TIMER_B(ST,step) \
866 { \
867 if( ST->TBC && (ST->timer_handler==0) ) \
868 if( (ST->TBC -= (int)(ST->freqbase*4096*step)) <= 0 ) \
869 TimerBOver( ST ); \
870 }
871 #else /* FM_INTERNAL_TIMER */
872 /* external timer mode */
873 #define INTERNAL_TIMER_A(ST,CSM_CH)
874 #define INTERNAL_TIMER_B(ST,step)
875 #endif /* FM_INTERNAL_TIMER */
876
877
878
879 #if FM_BUSY_FLAG_SUPPORT
880 #define FM_BUSY_CLEAR(ST) ((ST)->busy_expiry_time = UNDEFINED_TIME)
FM_STATUS_FLAG(FM_ST * ST)881 static inline uint8_t FM_STATUS_FLAG(FM_ST *ST)
882 {
883 if( COMPARE_TIMES(ST->busy_expiry_time, UNDEFINED_TIME) != 0 )
884 {
885 if (COMPARE_TIMES(ST->busy_expiry_time, FM_GET_TIME_NOW(&ST->device->machine())) > 0)
886 return ST->status | 0x80; /* with busy */
887 /* expire */
888 FM_BUSY_CLEAR(ST);
889 }
890 return ST->status;
891 }
FM_BUSY_SET(FM_ST * ST,int busyclock)892 static inline void FM_BUSY_SET(FM_ST *ST,int busyclock )
893 {
894 TIME_TYPE expiry_period = MULTIPLY_TIME_BY_INT(attotime::from_hz(ST->clock), busyclock * ST->timer_prescaler);
895 ST->busy_expiry_time = ADD_TIMES(FM_GET_TIME_NOW(&ST->device->machine()), expiry_period);
896 }
897 #else
898 #define FM_STATUS_FLAG(ST) ((ST)->status)
899 #define FM_BUSY_SET(ST,bclock) {}
900 #define FM_BUSY_CLEAR(ST) {}
901 #endif
902
903
904
905
FM_KEYON(uint8_t type,FM_CH * CH,int s)906 static inline void FM_KEYON(uint8_t type, FM_CH *CH , int s )
907 {
908 FM_SLOT *SLOT = &CH->SLOT[s];
909 (void)type;
910 if( !SLOT->key )
911 {
912 SLOT->key = 1;
913 SLOT->phase = 0; /* restart Phase Generator */
914 SLOT->ssgn = (SLOT->ssg & 0x04) >> 1;
915 SLOT->state = EG_ATT;
916 }
917 }
918
FM_KEYOFF(FM_CH * CH,int s)919 static inline void FM_KEYOFF(FM_CH *CH , int s )
920 {
921 FM_SLOT *SLOT = &CH->SLOT[s];
922 if( SLOT->key )
923 {
924 SLOT->key = 0;
925 if (SLOT->state>EG_REL)
926 SLOT->state = EG_REL;/* phase -> Release */
927 }
928 }
929
930 /* set algorithm connection */
setup_connection(FM_OPN * OPN,FM_CH * CH,int ch)931 static void setup_connection( FM_OPN *OPN, FM_CH *CH, int ch )
932 {
933 int32_t *carrier = &OPN->out_fm[ch];
934
935 int32_t **om1 = &CH->connect1;
936 int32_t **om2 = &CH->connect3;
937 int32_t **oc1 = &CH->connect2;
938
939 int32_t **memc = &CH->mem_connect;
940
941 switch( CH->ALGO )
942 {
943 case 0:
944 /* M1---C1---MEM---M2---C2---OUT */
945 *om1 = &OPN->c1;
946 *oc1 = &OPN->mem;
947 *om2 = &OPN->c2;
948 *memc= &OPN->m2;
949 break;
950 case 1:
951 /* M1------+-MEM---M2---C2---OUT */
952 /* C1-+ */
953 *om1 = &OPN->mem;
954 *oc1 = &OPN->mem;
955 *om2 = &OPN->c2;
956 *memc= &OPN->m2;
957 break;
958 case 2:
959 /* M1-----------------+-C2---OUT */
960 /* C1---MEM---M2-+ */
961 *om1 = &OPN->c2;
962 *oc1 = &OPN->mem;
963 *om2 = &OPN->c2;
964 *memc= &OPN->m2;
965 break;
966 case 3:
967 /* M1---C1---MEM------+-C2---OUT */
968 /* M2-+ */
969 *om1 = &OPN->c1;
970 *oc1 = &OPN->mem;
971 *om2 = &OPN->c2;
972 *memc= &OPN->c2;
973 break;
974 case 4:
975 /* M1---C1-+-OUT */
976 /* M2---C2-+ */
977 /* MEM: not used */
978 *om1 = &OPN->c1;
979 *oc1 = carrier;
980 *om2 = &OPN->c2;
981 *memc= &OPN->mem; /* store it anywhere where it will not be used */
982 break;
983 case 5:
984 /* +----C1----+ */
985 /* M1-+-MEM---M2-+-OUT */
986 /* +----C2----+ */
987 *om1 = NULLPTR; /* special mark */
988 *oc1 = carrier;
989 *om2 = carrier;
990 *memc= &OPN->m2;
991 break;
992 case 6:
993 /* M1---C1-+ */
994 /* M2-+-OUT */
995 /* C2-+ */
996 /* MEM: not used */
997 *om1 = &OPN->c1;
998 *oc1 = carrier;
999 *om2 = carrier;
1000 *memc= &OPN->mem; /* store it anywhere where it will not be used */
1001 break;
1002 case 7:
1003 /* M1-+ */
1004 /* C1-+-OUT */
1005 /* M2-+ */
1006 /* C2-+ */
1007 /* MEM: not used*/
1008 *om1 = carrier;
1009 *oc1 = carrier;
1010 *om2 = carrier;
1011 *memc= &OPN->mem; /* store it anywhere where it will not be used */
1012 break;
1013 }
1014
1015 CH->connect4 = carrier;
1016 }
1017
1018 /* set detune & multiple */
set_det_mul(FM_ST * ST,FM_CH * CH,FM_SLOT * SLOT,int v)1019 static inline void set_det_mul(FM_ST *ST,FM_CH *CH,FM_SLOT *SLOT,int v)
1020 {
1021 SLOT->mul = (v&0x0f)? (v&0x0f)*2 : 1;
1022 SLOT->DT = ST->dt_tab[(v>>4)&7];
1023 CH->SLOT[SLOT1].Incr=-1;
1024 }
1025
1026 /* set total level */
set_tl(FM_CH * CH,FM_SLOT * SLOT,int v)1027 static inline void set_tl(FM_CH *CH,FM_SLOT *SLOT , int v)
1028 {
1029 (void)CH;
1030 SLOT->tl = (v&0x7f)<<(ENV_BITS-7); /* 7bit TL */
1031 }
1032
1033 /* set attack rate & key scale */
set_ar_ksr(uint8_t type,FM_CH * CH,FM_SLOT * SLOT,int v)1034 static inline void set_ar_ksr(uint8_t type, FM_CH *CH,FM_SLOT *SLOT,int v)
1035 {
1036 uint8_t old_KSR = SLOT->KSR;
1037 (void)type;
1038
1039 SLOT->ar = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1040
1041 SLOT->KSR = 3-(v>>6);
1042 if (SLOT->KSR != old_KSR)
1043 {
1044 CH->SLOT[SLOT1].Incr=-1;
1045 }
1046
1047 /* refresh Attack rate */
1048 if ((SLOT->ar + SLOT->ksr) < 32+62)
1049 {
1050 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1051 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1052 }
1053 else
1054 {
1055 SLOT->eg_sh_ar = 0;
1056 SLOT->eg_sel_ar = 17*RATE_STEPS;
1057 }
1058 }
1059
1060 /* set decay rate */
set_dr(uint8_t type,FM_SLOT * SLOT,int v)1061 static inline void set_dr(uint8_t type, FM_SLOT *SLOT,int v)
1062 {
1063 (void)type;
1064 SLOT->d1r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1065
1066 SLOT->eg_sh_d1r = eg_rate_shift [SLOT->d1r + SLOT->ksr];
1067 SLOT->eg_sel_d1r= eg_rate_select[SLOT->d1r + SLOT->ksr];
1068 }
1069
1070 /* set sustain rate */
set_sr(uint8_t type,FM_SLOT * SLOT,int v)1071 static inline void set_sr(uint8_t type, FM_SLOT *SLOT,int v)
1072 {
1073 (void)type;
1074 SLOT->d2r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1075
1076 SLOT->eg_sh_d2r = eg_rate_shift [SLOT->d2r + SLOT->ksr];
1077 SLOT->eg_sel_d2r= eg_rate_select[SLOT->d2r + SLOT->ksr];
1078 }
1079
1080 /* set release rate */
set_sl_rr(uint8_t type,FM_SLOT * SLOT,int v)1081 static inline void set_sl_rr(uint8_t type, FM_SLOT *SLOT,int v)
1082 {
1083 (void)type;
1084 SLOT->sl = sl_table[ v>>4 ];
1085
1086 SLOT->rr = 34 + ((v&0x0f)<<2);
1087
1088 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr];
1089 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr];
1090 }
1091
1092
1093
op_calc(uint32_t phase,unsigned int env,signed int pm)1094 static inline signed int op_calc(uint32_t phase, unsigned int env, signed int pm)
1095 {
1096 uint32_t p;
1097
1098 p = (env<<3) + sin_tab[ ( ((signed int)((phase & ~FREQ_MASK) + (pm<<15))) >> FREQ_SH ) & SIN_MASK ];
1099
1100 if (p >= TL_TAB_LEN)
1101 return 0;
1102 return tl_tab[p];
1103 }
1104
op_calc1(uint32_t phase,unsigned int env,signed int pm)1105 static inline signed int op_calc1(uint32_t phase, unsigned int env, signed int pm)
1106 {
1107 uint32_t p;
1108
1109 p = (env<<3) + sin_tab[ ( ((signed int)((phase & ~FREQ_MASK) + pm )) >> FREQ_SH ) & SIN_MASK ];
1110
1111 if (p >= TL_TAB_LEN)
1112 return 0;
1113 return tl_tab[p];
1114 }
1115
1116 /* advance LFO to next sample */
advance_lfo(FM_OPN * OPN)1117 static inline void advance_lfo(FM_OPN *OPN)
1118 {
1119 uint8_t pos;
1120
1121 if (OPN->lfo_inc) /* LFO enabled ? */
1122 {
1123 OPN->lfo_cnt += OPN->lfo_inc;
1124
1125 pos = (OPN->lfo_cnt >> LFO_SH) & 127;
1126
1127
1128 /* update AM when LFO output changes */
1129
1130 /* actually I can't optimize is this way without rewriting chan_calc()
1131 to use chip->lfo_am instead of global lfo_am */
1132 {
1133 /* triangle */
1134 /* AM: 0 to 126 step +2, 126 to 0 step -2 */
1135 if (pos<64)
1136 OPN->LFO_AM = (pos&63) * 2;
1137 else
1138 OPN->LFO_AM = 126 - ((pos&63) * 2);
1139 }
1140
1141 /* PM works with 4 times slower clock */
1142 pos >>= 2;
1143 /* update PM when LFO output changes */
1144 /*if (prev_pos != pos)*/ /* can't use global lfo_pm for this optimization, must be chip->lfo_pm instead*/
1145 {
1146 OPN->LFO_PM = pos;
1147 }
1148
1149 }
1150 else
1151 {
1152 OPN->LFO_AM = 0;
1153 OPN->LFO_PM = 0;
1154 }
1155 }
1156
1157 /* changed from static inline to static here to work around gcc 4.2.1 codegen bug */
advance_eg_channel(FM_OPN * OPN,FM_SLOT * SLOT)1158 static void advance_eg_channel(FM_OPN *OPN, FM_SLOT *SLOT)
1159 {
1160 unsigned int out;
1161 unsigned int swap_flag;
1162 unsigned int i;
1163
1164
1165 i = 4; /* four operators per channel */
1166 do
1167 {
1168 /* reset SSG-EG swap flag */
1169 swap_flag = 0;
1170
1171 switch(SLOT->state)
1172 {
1173 case EG_ATT: /* attack phase */
1174 if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_ar)-1) ) )
1175 {
1176 SLOT->volume += (~SLOT->volume *
1177 (eg_inc[SLOT->eg_sel_ar + ((OPN->eg_cnt>>SLOT->eg_sh_ar)&7)])
1178 ) >>4;
1179
1180 if (SLOT->volume <= MIN_ATT_INDEX)
1181 {
1182 SLOT->volume = MIN_ATT_INDEX;
1183 SLOT->state = EG_DEC;
1184 }
1185 }
1186 break;
1187
1188 case EG_DEC: /* decay phase */
1189 {
1190 if (SLOT->ssg&0x08) /* SSG EG type envelope selected */
1191 {
1192 if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_d1r)-1) ) )
1193 {
1194 SLOT->volume += 4 * eg_inc[SLOT->eg_sel_d1r + ((OPN->eg_cnt>>SLOT->eg_sh_d1r)&7)];
1195
1196 if ( SLOT->volume >= (int32_t)(SLOT->sl) )
1197 SLOT->state = EG_SUS;
1198 }
1199 }
1200 else
1201 {
1202 if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_d1r)-1) ) )
1203 {
1204 SLOT->volume += eg_inc[SLOT->eg_sel_d1r + ((OPN->eg_cnt>>SLOT->eg_sh_d1r)&7)];
1205
1206 if ( SLOT->volume >= (int32_t)(SLOT->sl) )
1207 SLOT->state = EG_SUS;
1208 }
1209 }
1210 }
1211 break;
1212
1213 case EG_SUS: /* sustain phase */
1214 if (SLOT->ssg&0x08) /* SSG EG type envelope selected */
1215 {
1216 if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_d2r)-1) ) )
1217 {
1218 SLOT->volume += 4 * eg_inc[SLOT->eg_sel_d2r + ((OPN->eg_cnt>>SLOT->eg_sh_d2r)&7)];
1219
1220 if ( SLOT->volume >= ENV_QUIET )
1221 {
1222 SLOT->volume = MAX_ATT_INDEX;
1223
1224 if (SLOT->ssg&0x01) /* bit 0 = hold */
1225 {
1226 if (SLOT->ssgn&1) /* have we swapped once ??? */
1227 {
1228 /* yes, so do nothing, just hold current level */
1229 }
1230 else
1231 swap_flag = (SLOT->ssg&0x02) | 1 ; /* bit 1 = alternate */
1232
1233 }
1234 else
1235 {
1236 /* same as KEY-ON operation */
1237
1238 /* restart of the Phase Generator should be here */
1239 SLOT->phase = 0;
1240
1241 {
1242 /* phase -> Attack */
1243 SLOT->volume = 511;
1244 SLOT->state = EG_ATT;
1245 }
1246
1247 swap_flag = (SLOT->ssg&0x02); /* bit 1 = alternate */
1248 }
1249 }
1250 }
1251 }
1252 else
1253 {
1254 if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_d2r)-1) ) )
1255 {
1256 SLOT->volume += eg_inc[SLOT->eg_sel_d2r + ((OPN->eg_cnt>>SLOT->eg_sh_d2r)&7)];
1257
1258 if ( SLOT->volume >= MAX_ATT_INDEX )
1259 {
1260 SLOT->volume = MAX_ATT_INDEX;
1261 /* do not change SLOT->state (verified on real chip) */
1262 }
1263 }
1264
1265 }
1266 break;
1267
1268 case EG_REL: /* release phase */
1269 if ( !(OPN->eg_cnt & ((1<<SLOT->eg_sh_rr)-1) ) )
1270 {
1271 /* SSG-EG affects Release phase also (Nemesis) */
1272 SLOT->volume += eg_inc[SLOT->eg_sel_rr + ((OPN->eg_cnt>>SLOT->eg_sh_rr)&7)];
1273
1274 if ( SLOT->volume >= MAX_ATT_INDEX )
1275 {
1276 SLOT->volume = MAX_ATT_INDEX;
1277 SLOT->state = EG_OFF;
1278 }
1279 }
1280 break;
1281
1282 }
1283
1284
1285 out = ((uint32_t)SLOT->volume);
1286
1287 /* negate output (changes come from alternate bit, init comes from attack bit) */
1288 if ((SLOT->ssg&0x08) && (SLOT->ssgn&2) && (SLOT->state > EG_REL))
1289 out ^= MAX_ATT_INDEX;
1290
1291 /* we need to store the result here because we are going to change ssgn
1292 in next instruction */
1293 SLOT->vol_out = out + SLOT->tl;
1294
1295 /* reverse SLOT inversion flag */
1296 SLOT->ssgn ^= swap_flag;
1297
1298 SLOT++;
1299 i--;
1300 }while (i);
1301
1302 }
1303
1304
1305
1306 #define volume_calc(OP) ((OP)->vol_out + (AM & (OP)->AMmask))
1307
update_phase_lfo_slot(FM_OPN * OPN,FM_SLOT * SLOT,int32_t pms,uint32_t block_fnum)1308 static inline void update_phase_lfo_slot(FM_OPN *OPN, FM_SLOT *SLOT, int32_t pms, uint32_t block_fnum)
1309 {
1310 uint32_t fnum_lfo = ((block_fnum & 0x7f0) >> 4) * 32 * 8;
1311 int32_t lfo_fn_table_index_offset = lfo_pm_table[ fnum_lfo + pms + OPN->LFO_PM ];
1312
1313 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
1314 {
1315 uint8_t blk;
1316 uint32_t fn;
1317 int kc, fc;
1318
1319 block_fnum = block_fnum*2 + lfo_fn_table_index_offset;
1320
1321 blk = (block_fnum&0x7000) >> 12;
1322 fn = block_fnum & 0xfff;
1323
1324 /* keyscale code */
1325 kc = (blk<<2) | opn_fktable[fn >> 8];
1326
1327 /* phase increment counter */
1328 fc = (OPN->fn_table[fn]>>(7-blk)) + SLOT->DT[kc];
1329
1330 /* detects frequency overflow (credits to Nemesis) */
1331 if (fc < 0) fc += OPN->fn_max;
1332
1333 /* update phase */
1334 SLOT->phase += (fc * SLOT->mul) >> 1;
1335 }
1336 else /* LFO phase modulation = zero */
1337 {
1338 SLOT->phase += SLOT->Incr;
1339 }
1340 }
1341
update_phase_lfo_channel(FM_OPN * OPN,FM_CH * CH)1342 static inline void update_phase_lfo_channel(FM_OPN *OPN, FM_CH *CH)
1343 {
1344 uint32_t block_fnum = CH->block_fnum;
1345
1346 uint32_t fnum_lfo = ((block_fnum & 0x7f0) >> 4) * 32 * 8;
1347 int32_t lfo_fn_table_index_offset = lfo_pm_table[ fnum_lfo + CH->pms + OPN->LFO_PM ];
1348
1349 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
1350 {
1351 uint8_t blk;
1352 uint32_t fn;
1353 int kc, fc, finc;
1354
1355 block_fnum = block_fnum*2 + lfo_fn_table_index_offset;
1356
1357 blk = (block_fnum&0x7000) >> 12;
1358 fn = block_fnum & 0xfff;
1359
1360 /* keyscale code */
1361 kc = (blk<<2) | opn_fktable[fn >> 8];
1362
1363 /* phase increment counter */
1364 fc = (OPN->fn_table[fn]>>(7-blk));
1365
1366 /* detects frequency overflow (credits to Nemesis) */
1367 finc = fc + CH->SLOT[SLOT1].DT[kc];
1368
1369 if (finc < 0) finc += OPN->fn_max;
1370 CH->SLOT[SLOT1].phase += (finc*CH->SLOT[SLOT1].mul) >> 1;
1371
1372 finc = fc + CH->SLOT[SLOT2].DT[kc];
1373 if (finc < 0) finc += OPN->fn_max;
1374 CH->SLOT[SLOT2].phase += (finc*CH->SLOT[SLOT2].mul) >> 1;
1375
1376 finc = fc + CH->SLOT[SLOT3].DT[kc];
1377 if (finc < 0) finc += OPN->fn_max;
1378 CH->SLOT[SLOT3].phase += (finc*CH->SLOT[SLOT3].mul) >> 1;
1379
1380 finc = fc + CH->SLOT[SLOT4].DT[kc];
1381 if (finc < 0) finc += OPN->fn_max;
1382 CH->SLOT[SLOT4].phase += (finc*CH->SLOT[SLOT4].mul) >> 1;
1383 }
1384 else /* LFO phase modulation = zero */
1385 {
1386 CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
1387 CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
1388 CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
1389 CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
1390 }
1391 }
1392
chan_calc(FM_OPN * OPN,FM_CH * CH,int chnum)1393 static inline void chan_calc(FM_OPN *OPN, FM_CH *CH, int chnum)
1394 {
1395 unsigned int eg_out;
1396
1397 uint32_t AM = OPN->LFO_AM >> CH->ams;
1398
1399
1400 OPN->m2 = OPN->c1 = OPN->c2 = OPN->mem = 0;
1401
1402 *CH->mem_connect = CH->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
1403
1404 eg_out = volume_calc(&CH->SLOT[SLOT1]);
1405 {
1406 int32_t out = CH->op1_out[0] + CH->op1_out[1];
1407 CH->op1_out[0] = CH->op1_out[1];
1408
1409 if( !CH->connect1 )
1410 {
1411 /* algorithm 5 */
1412 OPN->mem = OPN->c1 = OPN->c2 = CH->op1_out[0];
1413 }
1414 else
1415 {
1416 /* other algorithms */
1417 *CH->connect1 += CH->op1_out[0];
1418 }
1419
1420 CH->op1_out[1] = 0;
1421 if( eg_out < ENV_QUIET ) /* SLOT 1 */
1422 {
1423 if (!CH->FB)
1424 out=0;
1425
1426 CH->op1_out[1] = op_calc1(CH->SLOT[SLOT1].phase, eg_out, (out<<CH->FB) );
1427 }
1428 }
1429
1430 eg_out = volume_calc(&CH->SLOT[SLOT3]);
1431 if( eg_out < ENV_QUIET ) /* SLOT 3 */
1432 *CH->connect3 += op_calc(CH->SLOT[SLOT3].phase, eg_out, OPN->m2);
1433
1434 eg_out = volume_calc(&CH->SLOT[SLOT2]);
1435 if( eg_out < ENV_QUIET ) /* SLOT 2 */
1436 *CH->connect2 += op_calc(CH->SLOT[SLOT2].phase, eg_out, OPN->c1);
1437
1438 eg_out = volume_calc(&CH->SLOT[SLOT4]);
1439 if( eg_out < ENV_QUIET ) /* SLOT 4 */
1440 *CH->connect4 += op_calc(CH->SLOT[SLOT4].phase, eg_out, OPN->c2);
1441
1442
1443 /* store current MEM */
1444 CH->mem_value = OPN->mem;
1445
1446 /* update phase counters AFTER output calculations */
1447 if(CH->pms)
1448 {
1449 /* add support for 3 slot mode */
1450 if ((OPN->ST.mode & 0xC0) && (chnum == 2))
1451 {
1452 update_phase_lfo_slot(OPN, &CH->SLOT[SLOT1], CH->pms, OPN->SL3.block_fnum[1]);
1453 update_phase_lfo_slot(OPN, &CH->SLOT[SLOT2], CH->pms, OPN->SL3.block_fnum[2]);
1454 update_phase_lfo_slot(OPN, &CH->SLOT[SLOT3], CH->pms, OPN->SL3.block_fnum[0]);
1455 update_phase_lfo_slot(OPN, &CH->SLOT[SLOT4], CH->pms, CH->block_fnum);
1456 }
1457 else update_phase_lfo_channel(OPN, CH);
1458 }
1459 else /* no LFO phase modulation */
1460 {
1461 CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
1462 CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
1463 CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
1464 CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
1465 }
1466 }
1467
1468 /* update phase increment and envelope generator */
refresh_fc_eg_slot(FM_OPN * OPN,FM_SLOT * SLOT,int fc,int kc)1469 static inline void refresh_fc_eg_slot(FM_OPN *OPN, FM_SLOT *SLOT , int fc , int kc )
1470 {
1471 int ksr = kc >> SLOT->KSR;
1472
1473 fc += SLOT->DT[kc];
1474
1475 /* detects frequency overflow (credits to Nemesis) */
1476 if (fc < 0) fc += OPN->fn_max;
1477
1478 /* (frequency) phase increment counter */
1479 SLOT->Incr = (fc * SLOT->mul) >> 1;
1480
1481 if( SLOT->ksr != ksr )
1482 {
1483 SLOT->ksr = ksr;
1484
1485 /* calculate envelope generator rates */
1486 if ((SLOT->ar + SLOT->ksr) < 32+62)
1487 {
1488 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1489 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1490 }
1491 else
1492 {
1493 SLOT->eg_sh_ar = 0;
1494 SLOT->eg_sel_ar = 17*RATE_STEPS;
1495 }
1496
1497 SLOT->eg_sh_d1r = eg_rate_shift [SLOT->d1r + SLOT->ksr];
1498 SLOT->eg_sh_d2r = eg_rate_shift [SLOT->d2r + SLOT->ksr];
1499 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr];
1500
1501 SLOT->eg_sel_d1r= eg_rate_select[SLOT->d1r + SLOT->ksr];
1502 SLOT->eg_sel_d2r= eg_rate_select[SLOT->d2r + SLOT->ksr];
1503 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr];
1504 }
1505 }
1506
1507 /* update phase increment counters */
1508 /* Changed from static inline to static to work around gcc 4.2.1 codegen bug */
refresh_fc_eg_chan(FM_OPN * OPN,FM_CH * CH)1509 static void refresh_fc_eg_chan(FM_OPN *OPN, FM_CH *CH )
1510 {
1511 if( CH->SLOT[SLOT1].Incr==-1)
1512 {
1513 int fc = CH->fc;
1514 int kc = CH->kcode;
1515 refresh_fc_eg_slot(OPN, &CH->SLOT[SLOT1] , fc , kc );
1516 refresh_fc_eg_slot(OPN, &CH->SLOT[SLOT2] , fc , kc );
1517 refresh_fc_eg_slot(OPN, &CH->SLOT[SLOT3] , fc , kc );
1518 refresh_fc_eg_slot(OPN, &CH->SLOT[SLOT4] , fc , kc );
1519 }
1520 }
1521
1522 /* initialize time tables */
init_timetables(FM_ST * ST,const uint8_t * dttable)1523 static void init_timetables( FM_ST *ST , const uint8_t *dttable )
1524 {
1525 int i,d;
1526 double rate;
1527
1528 #if 0
1529 logerror("FM.C: samplerate=%8i chip clock=%8i freqbase=%f \n",
1530 ST->rate, ST->clock, ST->freqbase );
1531 #endif
1532
1533 /* DeTune table */
1534 for (d = 0;d <= 3;d++)
1535 {
1536 for (i = 0;i <= 31;i++)
1537 {
1538 rate = ((double)dttable[d*32 + i]) * SIN_LEN * ST->freqbase * (1<<FREQ_SH) / ((double)(1<<20));
1539 ST->dt_tab[d][i] = (int32_t) rate;
1540 ST->dt_tab[d+4][i] = -ST->dt_tab[d][i];
1541 #if 0
1542 logerror("FM.C: DT [%2i %2i] = %8x \n", d, i, ST->dt_tab[d][i] );
1543 #endif
1544 }
1545 }
1546
1547 }
1548
1549
reset_channels(FM_ST * ST,FM_CH * CH,int num)1550 static void reset_channels( FM_ST *ST , FM_CH *CH , int num )
1551 {
1552 int c,s;
1553
1554 ST->mode = 0; /* normal mode */
1555 ST->TA = 0;
1556 ST->TAC = 0;
1557 ST->TB = 0;
1558 ST->TBC = 0;
1559
1560 for( c = 0 ; c < num ; c++ )
1561 {
1562 CH[c].fc = 0;
1563 for(s = 0 ; s < 4 ; s++ )
1564 {
1565 CH[c].SLOT[s].ssg = 0;
1566 CH[c].SLOT[s].ssgn = 0;
1567 CH[c].SLOT[s].state= EG_OFF;
1568 CH[c].SLOT[s].volume = MAX_ATT_INDEX;
1569 CH[c].SLOT[s].vol_out= MAX_ATT_INDEX;
1570 }
1571 }
1572 }
1573
1574 /* initialize generic tables */
init_tables(void)1575 static int init_tables(void)
1576 {
1577 signed int i,x;
1578 signed int n;
1579 double o,m;
1580
1581 for (x=0; x<TL_RES_LEN; x++)
1582 {
1583 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
1584 m = floor(m);
1585
1586 /* we never reach (1<<16) here due to the (x+1) */
1587 /* result fits within 16 bits at maximum */
1588
1589 n = (int)m; /* 16 bits here */
1590 n >>= 4; /* 12 bits here */
1591 if (n&1) /* round to nearest */
1592 n = (n>>1)+1;
1593 else
1594 n = n>>1;
1595 /* 11 bits here (rounded) */
1596 n <<= 2; /* 13 bits here (as in real chip) */
1597 tl_tab[ x*2 + 0 ] = n;
1598 tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
1599
1600 for (i=1; i<13; i++)
1601 {
1602 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
1603 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
1604 }
1605 #if 0
1606 logerror("tl %04i", x);
1607 for (i=0; i<13; i++)
1608 logerror(", [%02i] %4x", i*2, tl_tab[ x*2 /*+1*/ + i*2*TL_RES_LEN ]);
1609 logerror("\n");
1610 #endif
1611 }
1612 /*logerror("FM.C: TL_TAB_LEN = %i elements (%i bytes)\n",TL_TAB_LEN, (int)sizeof(tl_tab));*/
1613
1614
1615 for (i=0; i<SIN_LEN; i++)
1616 {
1617 /* non-standard sinus */
1618 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
1619
1620 /* we never reach zero here due to ((i*2)+1) */
1621
1622 if (m>0.0)
1623 o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
1624 else
1625 o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
1626
1627 o = o / (ENV_STEP/4);
1628
1629 n = (int)(2.0*o);
1630 if (n&1) /* round to nearest */
1631 n = (n>>1)+1;
1632 else
1633 n = n>>1;
1634
1635 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
1636 /*logerror("FM.C: sin [%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[i],tl_tab[sin_tab[i]]);*/
1637 }
1638
1639 /*logerror("FM.C: ENV_QUIET= %08x\n",ENV_QUIET );*/
1640
1641
1642 /* build LFO PM modulation table */
1643 for(i = 0; i < 8; i++) /* 8 PM depths */
1644 {
1645 uint8_t fnum;
1646 for (fnum=0; fnum<128; fnum++) /* 7 bits meaningful of F-NUMBER */
1647 {
1648 uint8_t value;
1649 uint8_t step;
1650 uint32_t offset_depth = i;
1651 uint32_t offset_fnum_bit;
1652 uint32_t bit_tmp;
1653
1654 for (step=0; step<8; step++)
1655 {
1656 value = 0;
1657 for (bit_tmp=0; bit_tmp<7; bit_tmp++) /* 7 bits */
1658 {
1659 if (fnum & (1<<bit_tmp)) /* only if bit "bit_tmp" is set */
1660 {
1661 offset_fnum_bit = bit_tmp * 8;
1662 value += lfo_pm_output[offset_fnum_bit + offset_depth][step];
1663 }
1664 }
1665 lfo_pm_table[(fnum*32*8) + (i*32) + step + 0] = value;
1666 lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+ 8] = value;
1667 lfo_pm_table[(fnum*32*8) + (i*32) + step +16] = -value;
1668 lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+24] = -value;
1669 }
1670 #if 0
1671 logerror("LFO depth=%1x FNUM=%04x (<<4=%4x): ", i, fnum, fnum<<4);
1672 for (step=0; step<16; step++) /* dump only positive part of waveforms */
1673 logerror("%02x ", lfo_pm_table[(fnum*32*8) + (i*32) + step] );
1674 logerror("\n");
1675 #endif
1676
1677 }
1678 }
1679
1680
1681
1682 #ifdef SAVE_SAMPLE
1683 sample[0]=fopen("sampsum.pcm","wb");
1684 #endif
1685
1686 return 1;
1687
1688 }
1689
1690
1691
FMCloseTable(void)1692 static void FMCloseTable( void )
1693 {
1694 #ifdef SAVE_SAMPLE
1695 fclose(sample[0]);
1696 #endif
1697 return;
1698 }
1699
1700
1701 /* CSM Key Controll */
CSMKeyControll(uint8_t type,FM_CH * CH)1702 static inline void CSMKeyControll(uint8_t type, FM_CH *CH)
1703 {
1704 /* all key on then off (only for operators which were OFF!) */
1705 if (!CH->SLOT[SLOT1].key)
1706 {
1707 FM_KEYON(type, CH,SLOT1);
1708 FM_KEYOFF(CH, SLOT1);
1709 }
1710 if (!CH->SLOT[SLOT2].key)
1711 {
1712 FM_KEYON(type, CH,SLOT2);
1713 FM_KEYOFF(CH, SLOT2);
1714 }
1715 if (!CH->SLOT[SLOT3].key)
1716 {
1717 FM_KEYON(type, CH,SLOT3);
1718 FM_KEYOFF(CH, SLOT3);
1719 }
1720 if (!CH->SLOT[SLOT4].key)
1721 {
1722 FM_KEYON(type, CH,SLOT4);
1723 FM_KEYOFF(CH, SLOT4);
1724 }
1725 }
1726
1727 #ifdef MAME_EMU_SAVE_H
1728 /* FM channel save , internal state only */
FMsave_state_channel(device_t * device,FM_CH * CH,int num_ch)1729 static void FMsave_state_channel(device_t *device,FM_CH *CH,int num_ch)
1730 {
1731 int slot , ch;
1732
1733 for(ch=0;ch<num_ch;ch++,CH++)
1734 {
1735 /* channel */
1736 device->save_item(NAME(CH->op1_out), ch);
1737 device->save_item(NAME(CH->fc), ch);
1738 /* slots */
1739 for(slot=0;slot<4;slot++)
1740 {
1741 FM_SLOT *SLOT = &CH->SLOT[slot];
1742 device->save_item(NAME(SLOT->phase), ch * 4 + slot);
1743 device->save_item(NAME(SLOT->state), ch * 4 + slot);
1744 device->save_item(NAME(SLOT->volume), ch * 4 + slot);
1745 }
1746 }
1747 }
1748
FMsave_state_st(device_t * device,FM_ST * ST)1749 static void FMsave_state_st(device_t *device,FM_ST *ST)
1750 {
1751 #if FM_BUSY_FLAG_SUPPORT
1752 device->save_item(NAME(ST->busy_expiry_time) );
1753 #endif
1754 device->save_item(NAME(ST->address) );
1755 device->save_item(NAME(ST->irq) );
1756 device->save_item(NAME(ST->irqmask) );
1757 device->save_item(NAME(ST->status) );
1758 device->save_item(NAME(ST->mode) );
1759 device->save_item(NAME(ST->prescaler_sel) );
1760 device->save_item(NAME(ST->fn_h) );
1761 device->save_item(NAME(ST->TA) );
1762 device->save_item(NAME(ST->TAC) );
1763 device->save_item(NAME(ST->TB) );
1764 device->save_item(NAME(ST->TBC) );
1765 }
1766 #endif /* MAME_EMU_SAVE_H */
1767
1768 #if BUILD_OPN
1769
1770
1771
1772 /* prescaler set (and make time tables) */
OPNSetPres(FM_OPN * OPN,int pres,int timer_prescaler,int SSGpres)1773 static void OPNSetPres(FM_OPN *OPN, int pres, int timer_prescaler, int SSGpres)
1774 {
1775 int i;
1776
1777 /* frequency base */
1778 OPN->ST.freqbase = (OPN->ST.rate) ? ((double)OPN->ST.clock / OPN->ST.rate) / pres : 0;
1779
1780 #if 0
1781 OPN->ST.rate = (double)OPN->ST.clock / pres;
1782 OPN->ST.freqbase = 1.0;
1783 #endif
1784
1785 OPN->eg_timer_add = (uint32_t)((1<<EG_SH) * OPN->ST.freqbase);
1786 OPN->eg_timer_overflow = ( 3 ) * (1<<EG_SH);
1787
1788
1789 /* Timer base time */
1790 OPN->ST.timer_prescaler = timer_prescaler;
1791
1792 /* SSG part prescaler set */
1793 if( SSGpres ) (*OPN->ST.SSG->set_clock)( OPN->ST.device, OPN->ST.clock * 2 / SSGpres );
1794
1795 /* make time tables */
1796 init_timetables( &OPN->ST, dt_tab );
1797
1798 /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
1799 but LFO works with one more bit of a precision so we really need 4096 elements */
1800 /* calculate fnumber -> increment counter table */
1801 for(i = 0; i < 4096; i++)
1802 {
1803 /* freq table for octave 7 */
1804 /* OPN phase increment counter = 20bit */
1805 OPN->fn_table[i] = (uint32_t)( (double)i * 32 * OPN->ST.freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
1806 #if 0
1807 logerror("FM.C: fn_table[%4i] = %08x (dec=%8i)\n",
1808 i, OPN->fn_table[i]>>6,OPN->fn_table[i]>>6 );
1809 #endif
1810 }
1811
1812 /* maximal frequency is required for Phase overflow calculation, register size is 17 bits (Nemesis) */
1813 OPN->fn_max = (uint32_t)( (double)0x20000 * OPN->ST.freqbase * (1<<(FREQ_SH-10)) );
1814
1815 /* LFO freq. table */
1816 for(i = 0; i < 8; i++)
1817 {
1818 /* Amplitude modulation: 64 output levels (triangle waveform); 1 level lasts for one of "lfo_samples_per_step" samples */
1819 /* Phase modulation: one entry from lfo_pm_output lasts for one of 4 * "lfo_samples_per_step" samples */
1820 OPN->lfo_freq[i] = (uint32_t)((1.0 / lfo_samples_per_step[i]) * (1<<LFO_SH) * OPN->ST.freqbase);
1821 #if 0
1822 logerror("FM.C: lfo_freq[%i] = %08x (dec=%8i)\n",
1823 i, OPN->lfo_freq[i],OPN->lfo_freq[i] );
1824 #endif
1825 }
1826 }
1827
1828
1829
1830 /* write a OPN mode register 0x20-0x2f */
OPNWriteMode(FM_OPN * OPN,int r,int v)1831 static void OPNWriteMode(FM_OPN *OPN, int r, int v)
1832 {
1833 uint8_t c;
1834 FM_CH *CH;
1835
1836 switch(r)
1837 {
1838 case 0x21: /* Test */
1839 break;
1840 case 0x22: /* LFO FREQ (YM2608/YM2610/YM2610B/YM2612) */
1841 if( OPN->type & TYPE_LFOPAN )
1842 {
1843 if (v&0x08) /* LFO enabled ? */
1844 {
1845 OPN->lfo_inc = OPN->lfo_freq[v&7];
1846 }
1847 else
1848 {
1849 OPN->lfo_inc = 0;
1850 }
1851 }
1852 break;
1853 case 0x24: /* timer A High 8*/
1854 OPN->ST.TA = (OPN->ST.TA & 0x03)|(((int)v)<<2);
1855 break;
1856 case 0x25: /* timer A Low 2*/
1857 OPN->ST.TA = (OPN->ST.TA & 0x3fc)|(v&3);
1858 break;
1859 case 0x26: /* timer B */
1860 OPN->ST.TB = v;
1861 break;
1862 case 0x27: /* mode, timer control */
1863 set_timers( &(OPN->ST),OPN->ST.device,v );
1864 break;
1865 case 0x28: /* key on / off */
1866 c = v & 0x03;
1867 if( c == 3 ) break;
1868 if( (v&0x04) && (OPN->type & TYPE_6CH) ) c+=3;
1869 CH = OPN->P_CH;
1870 CH = &CH[c];
1871 if(v&0x10) FM_KEYON(OPN->type,CH,SLOT1); else FM_KEYOFF(CH,SLOT1);
1872 if(v&0x20) FM_KEYON(OPN->type,CH,SLOT2); else FM_KEYOFF(CH,SLOT2);
1873 if(v&0x40) FM_KEYON(OPN->type,CH,SLOT3); else FM_KEYOFF(CH,SLOT3);
1874 if(v&0x80) FM_KEYON(OPN->type,CH,SLOT4); else FM_KEYOFF(CH,SLOT4);
1875 break;
1876 }
1877 }
1878
1879 /* write a OPN register (0x30-0xff) */
OPNWriteReg(FM_OPN * OPN,int r,int v)1880 static void OPNWriteReg(FM_OPN *OPN, int r, int v)
1881 {
1882 FM_CH *CH;
1883 FM_SLOT *SLOT;
1884
1885 uint8_t c = OPN_CHAN(r);
1886
1887 if (c == 3) return; /* 0xX3,0xX7,0xXB,0xXF */
1888
1889 if (r >= 0x100) c+=3;
1890
1891 CH = OPN->P_CH;
1892 CH = &CH[c];
1893
1894 SLOT = &(CH->SLOT[OPN_SLOT(r)]);
1895
1896 switch( r & 0xf0 )
1897 {
1898 case 0x30: /* DET , MUL */
1899 set_det_mul(&OPN->ST,CH,SLOT,v);
1900 break;
1901
1902 case 0x40: /* TL */
1903 set_tl(CH,SLOT,v);
1904 break;
1905
1906 case 0x50: /* KS, AR */
1907 set_ar_ksr(OPN->type,CH,SLOT,v);
1908 break;
1909
1910 case 0x60: /* bit7 = AM ENABLE, DR */
1911 set_dr(OPN->type, SLOT,v);
1912
1913 if(OPN->type & TYPE_LFOPAN) /* YM2608/2610/2610B/2612 */
1914 {
1915 SLOT->AMmask = (v&0x80) ? ~0 : 0;
1916 }
1917 break;
1918
1919 case 0x70: /* SR */
1920 set_sr(OPN->type,SLOT,v);
1921 break;
1922
1923 case 0x80: /* SL, RR */
1924 set_sl_rr(OPN->type,SLOT,v);
1925 break;
1926
1927 case 0x90: /* SSG-EG */
1928 SLOT->ssg = v&0x0f;
1929 SLOT->ssgn = (v&0x04)>>1; /* bit 1 in ssgn = attack */
1930
1931 /* SSG-EG envelope shapes :
1932
1933 E AtAlH
1934 1 0 0 0 \\\\
1935
1936 1 0 0 1 \___
1937
1938 1 0 1 0 \/\/
1939 ___
1940 1 0 1 1 \
1941
1942 1 1 0 0 ////
1943 ___
1944 1 1 0 1 /
1945
1946 1 1 1 0 /\/\
1947
1948 1 1 1 1 /___
1949
1950
1951 E = SSG-EG enable
1952
1953
1954 The shapes are generated using Attack, Decay and Sustain phases.
1955
1956 Each single character in the diagrams above represents this whole
1957 sequence:
1958
1959 - when KEY-ON = 1, normal Attack phase is generated (*without* any
1960 difference when compared to normal mode),
1961
1962 - later, when envelope level reaches minimum level (max volume),
1963 the EG switches to Decay phase (which works with bigger steps
1964 when compared to normal mode - see below),
1965
1966 - later when envelope level passes the SL level,
1967 the EG swithes to Sustain phase (which works with bigger steps
1968 when compared to normal mode - see below),
1969
1970 - finally when envelope level reaches maximum level (min volume),
1971 the EG switches to Attack phase again (depends on actual waveform).
1972
1973 Important is that when switch to Attack phase occurs, the phase counter
1974 of that operator will be zeroed-out (as in normal KEY-ON) but not always.
1975 (I havent found the rule for that - perhaps only when the output level is low)
1976
1977 The difference (when compared to normal Envelope Generator mode) is
1978 that the resolution in Decay and Sustain phases is 4 times lower;
1979 this results in only 256 steps instead of normal 1024.
1980 In other words:
1981 when SSG-EG is disabled, the step inside of the EG is one,
1982 when SSG-EG is enabled, the step is four (in Decay and Sustain phases).
1983
1984 Times between the level changes are the same in both modes.
1985
1986
1987 Important:
1988 Decay 1 Level (so called SL) is compared to actual SSG-EG output, so
1989 it is the same in both SSG and no-SSG modes, with this exception:
1990
1991 when the SSG-EG is enabled and is generating raising levels
1992 (when the EG output is inverted) the SL will be found at wrong level !!!
1993 For example, when SL=02:
1994 0 -6 = -6dB in non-inverted EG output
1995 96-6 = -90dB in inverted EG output
1996 Which means that EG compares its level to SL as usual, and that the
1997 output is simply inverted afterall.
1998
1999
2000 The Yamaha's manuals say that AR should be set to 0x1f (max speed).
2001 That is not necessary, but then EG will be generating Attack phase.
2002
2003 */
2004
2005
2006 break;
2007
2008 case 0xa0:
2009 switch( OPN_SLOT(r) )
2010 {
2011 case 0: /* 0xa0-0xa2 : FNUM1 */
2012 {
2013 uint32_t fn = (((uint32_t)( (OPN->ST.fn_h)&7))<<8) + v;
2014 uint8_t blk = OPN->ST.fn_h>>3;
2015 /* keyscale code */
2016 CH->kcode = (blk<<2) | opn_fktable[fn >> 7];
2017 /* phase increment counter */
2018 CH->fc = OPN->fn_table[fn*2]>>(7-blk);
2019
2020 /* store fnum in clear form for LFO PM calculations */
2021 CH->block_fnum = (blk<<11) | fn;
2022
2023 CH->SLOT[SLOT1].Incr=-1;
2024 }
2025 break;
2026 case 1: /* 0xa4-0xa6 : FNUM2,BLK */
2027 OPN->ST.fn_h = v&0x3f;
2028 break;
2029 case 2: /* 0xa8-0xaa : 3CH FNUM1 */
2030 if(r < 0x100)
2031 {
2032 uint32_t fn = (((uint32_t)(OPN->SL3.fn_h&7))<<8) + v;
2033 uint8_t blk = OPN->SL3.fn_h>>3;
2034 /* keyscale code */
2035 OPN->SL3.kcode[c]= (blk<<2) | opn_fktable[fn >> 7];
2036 /* phase increment counter */
2037 OPN->SL3.fc[c] = OPN->fn_table[fn*2]>>(7-blk);
2038 OPN->SL3.block_fnum[c] = (blk<<11) | fn;
2039 (OPN->P_CH)[2].SLOT[SLOT1].Incr=-1;
2040 }
2041 break;
2042 case 3: /* 0xac-0xae : 3CH FNUM2,BLK */
2043 if(r < 0x100)
2044 OPN->SL3.fn_h = v&0x3f;
2045 break;
2046 }
2047 break;
2048
2049 case 0xb0:
2050 switch( OPN_SLOT(r) )
2051 {
2052 case 0: /* 0xb0-0xb2 : FB,ALGO */
2053 {
2054 int feedback = (v>>3)&7;
2055 CH->ALGO = v&7;
2056 CH->FB = feedback ? feedback+6 : 0;
2057 setup_connection( OPN, CH, c );
2058 }
2059 break;
2060 case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (YM2612/YM2610B/YM2610/YM2608) */
2061 if( OPN->type & TYPE_LFOPAN)
2062 {
2063 /* b0-2 PMS */
2064 CH->pms = (v & 7) * 32; /* CH->pms = PM depth * 32 (index in lfo_pm_table) */
2065
2066 /* b4-5 AMS */
2067 CH->ams = lfo_ams_depth_shift[(v>>4) & 0x03];
2068
2069 /* PAN : b7 = L, b6 = R */
2070 OPN->pan[ c*2 ] = (v & 0x80) ? ~0 : 0;
2071 OPN->pan[ c*2+1 ] = (v & 0x40) ? ~0 : 0;
2072
2073 }
2074 break;
2075 }
2076 break;
2077 }
2078 }
2079
2080 #endif /* BUILD_OPN */
2081
2082 #if BUILD_OPN_PRESCALER
2083 /*
2084 prescaler circuit (best guess to verified chip behaviour)
2085
2086 +--------------+ +-sel2-+
2087 | +--|in20 |
2088 +---+ | +-sel1-+ | |
2089 M-CLK -+-|1/2|-+--|in10 | +---+ | out|--INT_CLOCK
2090 | +---+ | out|-|1/3|-|in21 |
2091 +----------|in11 | +---+ +------+
2092 +------+
2093
2094 reg.2d : sel2 = in21 (select sel2)
2095 reg.2e : sel1 = in11 (select sel1)
2096 reg.2f : sel1 = in10 , sel2 = in20 (clear selector)
2097 reset : sel1 = in11 , sel2 = in21 (clear both)
2098
2099 */
OPNPrescaler_w(FM_OPN * OPN,int addr,int pre_divider)2100 static void OPNPrescaler_w(FM_OPN *OPN , int addr, int pre_divider)
2101 {
2102 static const int opn_pres[4] = { 2*12 , 2*12 , 6*12 , 3*12 };
2103 static const int ssg_pres[4] = { 1 , 1 , 4 , 2 };
2104 int sel;
2105
2106 switch(addr)
2107 {
2108 case 0: /* when reset */
2109 OPN->ST.prescaler_sel = 2;
2110 break;
2111 case 1: /* when postload */
2112 break;
2113 case 0x2d: /* divider sel : select 1/1 for 1/3line */
2114 OPN->ST.prescaler_sel |= 0x02;
2115 break;
2116 case 0x2e: /* divider sel , select 1/3line for output */
2117 OPN->ST.prescaler_sel |= 0x01;
2118 break;
2119 case 0x2f: /* divider sel , clear both selector to 1/2,1/2 */
2120 OPN->ST.prescaler_sel = 0;
2121 break;
2122 }
2123 sel = OPN->ST.prescaler_sel & 3;
2124 /* update prescaler */
2125 OPNSetPres( OPN, opn_pres[sel]*pre_divider,
2126 opn_pres[sel]*pre_divider,
2127 ssg_pres[sel]*pre_divider );
2128 }
2129 #endif /* BUILD_OPN_PRESCALER */
2130
2131 #if BUILD_YM2203
2132 /*****************************************************************************/
2133 /* YM2203 local section */
2134 /*****************************************************************************/
2135
2136 /* here's the virtual YM2203(OPN) */
2137 namespace {
2138 struct ym2203_state
2139 {
2140 uint8_t REGS[256]; /* registers */
2141 FM_OPN OPN; /* OPN state */
2142 FM_CH CH[3]; /* channel state */
2143 };
2144 } // anonymous namespace
2145
2146 /* Generate samples for one of the YM2203s */
ym2203_update_one(void * chip,FMSAMPLE * buffer,int length)2147 void ym2203_update_one(void *chip, FMSAMPLE *buffer, int length)
2148 {
2149 ym2203_state *F2203 = (ym2203_state *)chip;
2150 FM_OPN *OPN = &F2203->OPN;
2151 int i;
2152 FMSAMPLE *buf = buffer;
2153 FM_CH *cch[3];
2154
2155 cch[0] = &F2203->CH[0];
2156 cch[1] = &F2203->CH[1];
2157 cch[2] = &F2203->CH[2];
2158
2159
2160 /* refresh PG and EG */
2161 refresh_fc_eg_chan( OPN, cch[0] );
2162 refresh_fc_eg_chan( OPN, cch[1] );
2163 if( (F2203->OPN.ST.mode & 0xc0) )
2164 {
2165 /* 3SLOT MODE */
2166 if( cch[2]->SLOT[SLOT1].Incr==-1)
2167 {
2168 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT1] , OPN->SL3.fc[1] , OPN->SL3.kcode[1] );
2169 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT2] , OPN->SL3.fc[2] , OPN->SL3.kcode[2] );
2170 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT3] , OPN->SL3.fc[0] , OPN->SL3.kcode[0] );
2171 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT4] , cch[2]->fc , cch[2]->kcode );
2172 }
2173 }
2174 else
2175 refresh_fc_eg_chan( OPN, cch[2] );
2176
2177
2178 /* YM2203 doesn't have LFO so we must keep these globals at 0 level */
2179 OPN->LFO_AM = 0;
2180 OPN->LFO_PM = 0;
2181
2182 /* buffering */
2183 for (i=0; i < length ; i++)
2184 {
2185 /* clear outputs */
2186 OPN->out_fm[0] = 0;
2187 OPN->out_fm[1] = 0;
2188 OPN->out_fm[2] = 0;
2189
2190 /* advance envelope generator */
2191 OPN->eg_timer += OPN->eg_timer_add;
2192 while (OPN->eg_timer >= OPN->eg_timer_overflow)
2193 {
2194 OPN->eg_timer -= OPN->eg_timer_overflow;
2195 OPN->eg_cnt++;
2196
2197 advance_eg_channel(OPN, &cch[0]->SLOT[SLOT1]);
2198 advance_eg_channel(OPN, &cch[1]->SLOT[SLOT1]);
2199 advance_eg_channel(OPN, &cch[2]->SLOT[SLOT1]);
2200 }
2201
2202 /* calculate FM */
2203 chan_calc(OPN, cch[0], 0 );
2204 chan_calc(OPN, cch[1], 1 );
2205 chan_calc(OPN, cch[2], 2 );
2206
2207 /* buffering */
2208 {
2209 int lt;
2210
2211 lt = OPN->out_fm[0] + OPN->out_fm[1] + OPN->out_fm[2];
2212
2213 lt >>= FINAL_SH;
2214
2215 Limit( lt , MAXOUT, MINOUT );
2216
2217 #ifdef SAVE_SAMPLE
2218 SAVE_ALL_CHANNELS
2219 #endif
2220
2221 /* buffering */
2222 buf[i] = lt;
2223 }
2224
2225 /* timer A control */
2226 INTERNAL_TIMER_A( &F2203->OPN.ST , cch[2] )
2227 }
2228 INTERNAL_TIMER_B(&F2203->OPN.ST,length)
2229 }
2230
2231 /* ---------- reset one of chip ---------- */
ym2203_reset_chip(void * chip)2232 void ym2203_reset_chip(void *chip)
2233 {
2234 int i;
2235 ym2203_state *F2203 = (ym2203_state *)chip;
2236 FM_OPN *OPN = &F2203->OPN;
2237
2238 /* Reset Prescaler */
2239 OPNPrescaler_w(OPN, 0 , 1 );
2240 /* reset SSG section */
2241 (*OPN->ST.SSG->reset)(OPN->ST.device);
2242 /* status clear */
2243 FM_IRQMASK_SET(&OPN->ST,0x03);
2244 FM_BUSY_CLEAR(&OPN->ST);
2245 OPNWriteMode(OPN,0x27,0x30); /* mode 0 , timer reset */
2246
2247 OPN->eg_timer = 0;
2248 OPN->eg_cnt = 0;
2249
2250 FM_STATUS_RESET(&OPN->ST, 0xff);
2251
2252 reset_channels( &OPN->ST , F2203->CH , 3 );
2253 /* reset OPerator paramater */
2254 for(i = 0xb2 ; i >= 0x30 ; i-- ) OPNWriteReg(OPN,i,0);
2255 for(i = 0x26 ; i >= 0x20 ; i-- ) OPNWriteReg(OPN,i,0);
2256 }
2257
2258 #ifdef MAME_EMU_SAVE_H
ym2203_postload(void * chip)2259 void ym2203_postload(void *chip)
2260 {
2261 if (chip)
2262 {
2263 ym2203_state *F2203 = (ym2203_state *)chip;
2264 int r;
2265
2266 /* prescaler */
2267 OPNPrescaler_w(&F2203->OPN,1,1);
2268
2269 /* SSG registers */
2270 for(r=0;r<16;r++)
2271 {
2272 (*F2203->OPN.ST.SSG->write)(F2203->OPN.ST.device,0,r);
2273 (*F2203->OPN.ST.SSG->write)(F2203->OPN.ST.device,1,F2203->REGS[r]);
2274 }
2275
2276 /* OPN registers */
2277 /* DT / MULTI , TL , KS / AR , AMON / DR , SR , SL / RR , SSG-EG */
2278 for(r=0x30;r<0x9e;r++)
2279 if((r&3) != 3)
2280 OPNWriteReg(&F2203->OPN,r,F2203->REGS[r]);
2281 /* FB / CONNECT , L / R / AMS / PMS */
2282 for(r=0xb0;r<0xb6;r++)
2283 if((r&3) != 3)
2284 OPNWriteReg(&F2203->OPN,r,F2203->REGS[r]);
2285
2286 /* channels */
2287 /*FM_channel_postload(F2203->CH,3);*/
2288 }
2289 }
2290
YM2203_save_state(ym2203_state * F2203,device_t * device)2291 static void YM2203_save_state(ym2203_state *F2203, device_t *device)
2292 {
2293 device->save_item(NAME(F2203->REGS));
2294 FMsave_state_st(device,&F2203->OPN.ST);
2295 FMsave_state_channel(device,F2203->CH,3);
2296 /* 3slots */
2297 device->save_item (NAME(F2203->OPN.SL3.fc));
2298 device->save_item (NAME(F2203->OPN.SL3.fn_h));
2299 device->save_item (NAME(F2203->OPN.SL3.kcode));
2300 }
2301 #endif /* MAME_EMU_SAVE_H */
2302
2303 /* ---------- Initialize YM2203 emulator(s) ----------
2304 'num' is the number of virtual YM2203s to allocate
2305 'clock' is the chip clock in Hz
2306 'rate' is sampling rate
2307 */
ym2203_init(device_t * device,int clock,int rate,FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler,const ssg_callbacks * ssg)2308 void * ym2203_init(device_t *device, int clock, int rate, FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler, const ssg_callbacks *ssg)
2309 {
2310 ym2203_state *F2203;
2311
2312 /* allocate ym2203 state space */
2313 F2203 = new ym2203_state;
2314 memset(F2203, 0, sizeof(*F2203));
2315
2316 if( !init_tables() )
2317 {
2318 delete F2203;
2319 return nullptr;
2320 }
2321
2322 F2203->OPN.type = TYPE_YM2203;
2323 F2203->OPN.P_CH = F2203->CH;
2324 F2203->OPN.ST.device = device;
2325 F2203->OPN.ST.clock = clock;
2326 F2203->OPN.ST.rate = rate;
2327
2328 F2203->OPN.ST.timer_handler = timer_handler;
2329 F2203->OPN.ST.IRQ_Handler = IRQHandler;
2330 F2203->OPN.ST.SSG = ssg;
2331
2332 for (unsigned i = 0; i < 3; i++)
2333 {
2334 F2203->CH[i].pan_volume_l = 46340;
2335 F2203->CH[i].pan_volume_r = 46340;
2336 }
2337
2338 #ifdef MAME_EMU_SAVE_H
2339 YM2203_save_state(F2203, device);
2340 #endif
2341 return F2203;
2342 }
2343
ym2203_clock_changed(void * chip,int clock,int rate)2344 void ym2203_clock_changed(void *chip, int clock, int rate)
2345 {
2346 ym2203_state *FM2203 = (ym2203_state *)chip;
2347
2348 FM2203->OPN.ST.clock = clock;
2349 FM2203->OPN.ST.rate = rate;
2350 }
2351
2352 /* shut down emulator */
ym2203_shutdown(void * chip)2353 void ym2203_shutdown(void *chip)
2354 {
2355 ym2203_state *FM2203 = (ym2203_state *)chip;
2356
2357 FMCloseTable();
2358 delete FM2203;
2359 }
2360
2361 /* YM2203 I/O interface */
ym2203_write(void * chip,int a,uint8_t v)2362 int ym2203_write(void *chip,int a,uint8_t v)
2363 {
2364 ym2203_state *F2203 = (ym2203_state *)chip;
2365 FM_OPN *OPN = &F2203->OPN;
2366
2367 if( !(a&1) )
2368 { /* address port */
2369 OPN->ST.address = (v &= 0xff);
2370
2371 /* Write register to SSG emulator */
2372 if( v < 16 ) (*OPN->ST.SSG->write)(OPN->ST.device,0,v);
2373
2374 /* prescaler select : 2d,2e,2f */
2375 if( v >= 0x2d && v <= 0x2f )
2376 OPNPrescaler_w(OPN , v , 1);
2377 }
2378 else
2379 { /* data port */
2380 int addr = OPN->ST.address;
2381 F2203->REGS[addr] = v;
2382 switch( addr & 0xf0 )
2383 {
2384 case 0x00: /* 0x00-0x0f : SSG section */
2385 /* Write data to SSG emulator */
2386 (*OPN->ST.SSG->write)(OPN->ST.device,a,v);
2387 break;
2388 case 0x20: /* 0x20-0x2f : Mode section */
2389 ym2203_device::update_request(OPN->ST.device);
2390 /* write register */
2391 OPNWriteMode(OPN,addr,v);
2392 break;
2393 default: /* 0x30-0xff : OPN section */
2394 ym2203_device::update_request(OPN->ST.device);
2395 /* write register */
2396 OPNWriteReg(OPN,addr,v);
2397 }
2398 FM_BUSY_SET(&OPN->ST,1);
2399 }
2400 return OPN->ST.irq;
2401 }
2402
ym2203_read(void * chip,int a)2403 uint8_t ym2203_read(void *chip,int a)
2404 {
2405 ym2203_state *F2203 = (ym2203_state *)chip;
2406 int addr = F2203->OPN.ST.address;
2407 uint8_t ret = 0;
2408
2409 if( !(a&1) )
2410 { /* status port */
2411 ret = FM_STATUS_FLAG(&F2203->OPN.ST);
2412 }
2413 else
2414 { /* data port (only SSG) */
2415 if( addr < 16 ) ret = (*F2203->OPN.ST.SSG->read)(F2203->OPN.ST.device);
2416 }
2417 return ret;
2418 }
2419
ym2203_timer_over(void * chip,int c)2420 int ym2203_timer_over(void *chip,int c)
2421 {
2422 ym2203_state *F2203 = (ym2203_state *)chip;
2423
2424 if( c )
2425 { /* Timer B */
2426 TimerBOver( &(F2203->OPN.ST) );
2427 }
2428 else
2429 { /* Timer A */
2430 ym2203_device::update_request(F2203->OPN.ST.device);
2431 /* timer update */
2432 TimerAOver( &(F2203->OPN.ST) );
2433 /* CSM mode key,TL control */
2434 if( F2203->OPN.ST.mode & 0x80 )
2435 { /* CSM mode auto key on */
2436 CSMKeyControll( F2203->OPN.type, &(F2203->CH[2]) );
2437 }
2438 }
2439 return F2203->OPN.ST.irq;
2440 }
2441 #endif /* BUILD_YM2203 */
2442
2443
2444
2445 #if (BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B)
2446
2447 namespace {
2448 /**** YM2610 ADPCM defines ****/
2449 CONSTEXPR unsigned ADPCM_SHIFT = 16; /* frequency step rate */
2450 CONSTEXPR unsigned ADPCMA_ADDRESS_SHIFT = 8; /* adpcm A address shift */
2451
2452 /* speedup purposes only */
2453 static int jedi_table[ 49*16 ];
2454
2455 /* ADPCM type A channel struct */
2456 struct ADPCM_CH
2457 {
2458 uint8_t flag; /* port state */
2459 uint8_t flagMask; /* arrived flag mask */
2460 uint8_t now_data; /* current ROM data */
2461 uint32_t now_addr; /* current ROM address */
2462 uint32_t now_step;
2463 uint32_t step;
2464 uint32_t start; /* sample data start address*/
2465 uint32_t end; /* sample data end address */
2466 uint8_t IL; /* Instrument Level */
2467 int32_t adpcm_acc; /* accumulator */
2468 int32_t adpcm_step; /* step */
2469 int32_t adpcm_out; /* (speedup) hiro-shi!! */
2470 int8_t vol_mul; /* volume in "0.75dB" steps */
2471 uint8_t vol_shift; /* volume in "-6dB" steps */
2472 int32_t *pan; /* &out_adpcm[OPN_xxxx] */
2473 };
2474
2475 /* here's the virtual YM2610 */
2476 struct ym2610_state
2477 {
2478 uint8_t REGS[512]; /* registers */
2479 FM_OPN OPN; /* OPN state */
2480 FM_CH CH[6]; /* channel state */
2481 uint8_t addr_A1; /* address line A1 */
2482
2483 /* ADPCM-A unit */
2484 FM_READBYTE read_byte;
2485 uint8_t adpcmTL; /* adpcmA total level */
2486 ADPCM_CH adpcm[6]; /* adpcm channels */
2487 uint32_t adpcmreg[0x30]; /* registers */
2488 uint8_t adpcm_arrivedEndAddress;
2489 YM_DELTAT deltaT; /* Delta-T ADPCM unit */
2490
2491 uint8_t flagmask; /* YM2608 only */
2492 uint8_t irqmask; /* YM2608 only */
2493
2494 device_t *device;
2495
2496 /* different from the usual ADPCM table */
2497 //static CONSTEXPR int step_inc[8] = { -1*16, -1*16, -1*16, -1*16, 2*16, 5*16, 7*16, 9*16 };
2498 static int step_inc[8];
2499
2500 /* ADPCM A (Non control type) : calculate one channel output */
ADPCMA_calc_chan__anon5147f1670211::ym2610_state2501 inline void ADPCMA_calc_chan( ADPCM_CH *ch )
2502 {
2503 uint32_t step;
2504 uint8_t data;
2505
2506
2507 ch->now_step += ch->step;
2508 if ( ch->now_step >= uint32_t(1<<ADPCM_SHIFT) )
2509 {
2510 step = ch->now_step >> ADPCM_SHIFT;
2511 ch->now_step &= (1<<ADPCM_SHIFT)-1;
2512 do{
2513 /* end check */
2514 /* 11-06-2001 JB: corrected comparison. Was > instead of == */
2515 /* YM2610 checks lower 20 bits only, the 4 MSB bits are sample bank */
2516 /* Here we use 1<<21 to compensate for nibble calculations */
2517
2518 if ( (ch->now_addr & ((1<<21)-1)) == ((ch->end<<1) & ((1<<21)-1)) )
2519 {
2520 ch->flag = 0;
2521 adpcm_arrivedEndAddress |= ch->flagMask;
2522 return;
2523 }
2524 #if 0
2525 if ( ch->now_addr > (pcmsizeA<<1) )
2526 {
2527 LOG(LOG_WAR,("YM2610: Attempting to play past adpcm rom size!\n" ));
2528 return;
2529 }
2530 #endif
2531 if ( ch->now_addr&1 )
2532 data = ch->now_data & 0x0f;
2533 else
2534 {
2535 ch->now_data = read_byte(device, ch->now_addr>>1);
2536 data = (ch->now_data >> 4) & 0x0f;
2537 }
2538
2539 ch->now_addr++;
2540
2541 ch->adpcm_acc += jedi_table[ch->adpcm_step + data];
2542
2543 /* extend 12-bit signed int */
2544 if (ch->adpcm_acc & ~0x7ff)
2545 ch->adpcm_acc |= ~0xfff;
2546 else
2547 ch->adpcm_acc &= 0xfff;
2548
2549 ch->adpcm_step += step_inc[data & 7];
2550 Limit( ch->adpcm_step, 48*16, 0*16 );
2551
2552 }while(--step);
2553
2554 /* calc pcm * volume data */
2555 ch->adpcm_out = ((ch->adpcm_acc * ch->vol_mul) >> ch->vol_shift) & ~3; /* multiply, shift and mask out 2 LSB bits */
2556 }
2557
2558 /* output for work of output channels (out_adpcm[OPNxxxx])*/
2559 *(ch->pan) += ch->adpcm_out;
2560 }
2561
2562 /* ADPCM type A Write */
FM_ADPCMAWrite__anon5147f1670211::ym2610_state2563 void FM_ADPCMAWrite(int r,int v)
2564 {
2565 uint8_t c = r&0x07;
2566
2567 adpcmreg[r] = v&0xff; /* stock data */
2568 switch( r )
2569 {
2570 case 0x00: /* DM,--,C5,C4,C3,C2,C1,C0 */
2571 if( !(v&0x80) )
2572 {
2573 /* KEY ON */
2574 for( c = 0; c < 6; c++ )
2575 {
2576 if( (v>>c)&1 )
2577 {
2578 /**** start adpcm ****/
2579 adpcm[c].step = (uint32_t)((float)(1<<ADPCM_SHIFT)*((float)OPN.ST.freqbase)/3.0f);
2580 adpcm[c].now_addr = adpcm[c].start<<1;
2581 adpcm[c].now_step = 0;
2582 adpcm[c].adpcm_acc = 0;
2583 adpcm[c].adpcm_step= 0;
2584 adpcm[c].adpcm_out = 0;
2585 adpcm[c].flag = 1;
2586 }
2587 }
2588 }
2589 else
2590 {
2591 /* KEY OFF */
2592 for( c = 0; c < 6; c++ )
2593 if( (v>>c)&1 )
2594 adpcm[c].flag = 0;
2595 }
2596 break;
2597 case 0x01: /* B0-5 = TL */
2598 adpcmTL = (v & 0x3f) ^ 0x3f;
2599 for( c = 0; c < 6; c++ )
2600 {
2601 int volume = adpcmTL + adpcm[c].IL;
2602
2603 if ( volume >= 63 ) /* This is correct, 63 = quiet */
2604 {
2605 adpcm[c].vol_mul = 0;
2606 adpcm[c].vol_shift = 0;
2607 }
2608 else
2609 {
2610 adpcm[c].vol_mul = 15 - (volume & 7); /* so called 0.75 dB */
2611 adpcm[c].vol_shift = 1 + (volume >> 3); /* Yamaha engineers used the approximation: each -6 dB is close to divide by two (shift right) */
2612 }
2613
2614 /* calc pcm * volume data */
2615 adpcm[c].adpcm_out = ((adpcm[c].adpcm_acc * adpcm[c].vol_mul) >> adpcm[c].vol_shift) & ~3; /* multiply, shift and mask out low 2 bits */
2616 }
2617 break;
2618 default:
2619 c = r&0x07;
2620 if( c >= 0x06 ) return;
2621 switch( r&0x38 )
2622 {
2623 case 0x08: /* B7=L,B6=R, B4-0=IL */
2624 {
2625 int volume;
2626
2627 adpcm[c].IL = (v & 0x1f) ^ 0x1f;
2628
2629 volume = adpcmTL + adpcm[c].IL;
2630
2631 if ( volume >= 63 ) /* This is correct, 63 = quiet */
2632 {
2633 adpcm[c].vol_mul = 0;
2634 adpcm[c].vol_shift = 0;
2635 }
2636 else
2637 {
2638 adpcm[c].vol_mul = 15 - (volume & 7); /* so called 0.75 dB */
2639 adpcm[c].vol_shift = 1 + (volume >> 3); /* Yamaha engineers used the approximation: each -6 dB is close to divide by two (shift right) */
2640 }
2641
2642 adpcm[c].pan = &OPN.out_adpcm[(v>>6)&0x03];
2643
2644 /* calc pcm * volume data */
2645 adpcm[c].adpcm_out = ((adpcm[c].adpcm_acc * adpcm[c].vol_mul) >> adpcm[c].vol_shift) & ~3; /* multiply, shift and mask out low 2 bits */
2646 }
2647 break;
2648 case 0x10:
2649 case 0x18:
2650 adpcm[c].start = ( (adpcmreg[0x18 + c]*0x0100 | adpcmreg[0x10 + c]) << ADPCMA_ADDRESS_SHIFT);
2651 break;
2652 case 0x20:
2653 case 0x28:
2654 adpcm[c].end = ( (adpcmreg[0x28 + c]*0x0100 | adpcmreg[0x20 + c]) << ADPCMA_ADDRESS_SHIFT);
2655 adpcm[c].end += (1<<ADPCMA_ADDRESS_SHIFT) - 1;
2656 break;
2657 }
2658 }
2659 }
2660
2661 };
2662
2663 int ym2610_state::step_inc[8] = { -1*16, -1*16, -1*16, -1*16, 2*16, 5*16, 7*16, 9*16 };
2664
2665 /* here is the virtual YM2608 */
2666 typedef ym2610_state ym2608_state;
2667
2668
2669 /* Algorithm and tables verified on real YM2608 and YM2610 */
2670
2671 /* usual ADPCM table (16 * 1.1^N) */
2672 CONSTEXPR int steps[49] =
2673 {
2674 16, 17, 19, 21, 23, 25, 28,
2675 31, 34, 37, 41, 45, 50, 55,
2676 60, 66, 73, 80, 88, 97, 107,
2677 118, 130, 143, 157, 173, 190, 209,
2678 230, 253, 279, 307, 337, 371, 408,
2679 449, 494, 544, 598, 658, 724, 796,
2680 876, 963, 1060, 1166, 1282, 1411, 1552
2681 };
2682
2683
Init_ADPCMATable()2684 void Init_ADPCMATable()
2685 {
2686 int step, nib;
2687
2688 for (step = 0; step < 49; step++)
2689 {
2690 /* loop over all nibbles and compute the difference */
2691 for (nib = 0; nib < 16; nib++)
2692 {
2693 int value = (2*(nib & 0x07) + 1) * steps[step] / 8;
2694 jedi_table[step*16 + nib] = (nib&0x08) ? -value : value;
2695 }
2696 }
2697 }
2698
2699 #ifdef MAME_EMU_SAVE_H
2700 /* FM channel save , internal state only */
FMsave_state_adpcma(device_t * device,ADPCM_CH * adpcm)2701 void FMsave_state_adpcma(device_t *device,ADPCM_CH *adpcm)
2702 {
2703 int ch;
2704
2705 for(ch=0;ch<6;ch++,adpcm++)
2706 {
2707 device->save_item(NAME(adpcm->flag), ch);
2708 device->save_item(NAME(adpcm->now_data), ch);
2709 device->save_item(NAME(adpcm->now_addr), ch);
2710 device->save_item(NAME(adpcm->now_step), ch);
2711 device->save_item(NAME(adpcm->adpcm_acc), ch);
2712 device->save_item(NAME(adpcm->adpcm_step), ch);
2713 device->save_item(NAME(adpcm->adpcm_out), ch);
2714 }
2715 }
2716 #endif /* MAME_EMU_SAVE_H */
2717 } // anonymous namespace
2718
2719 #endif /* (BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B) */
2720
2721
2722 #if BUILD_YM2608
2723 /*****************************************************************************/
2724 /* YM2608 local section */
2725 /*****************************************************************************/
2726
2727
2728
2729 static const unsigned int YM2608_ADPCM_ROM_addr[2*6] = {
2730 0x0000, 0x01bf, /* bass drum */
2731 0x01c0, 0x043f, /* snare drum */
2732 0x0440, 0x1b7f, /* top cymbal */
2733 0x1b80, 0x1cff, /* high hat */
2734 0x1d00, 0x1f7f, /* tom tom */
2735 0x1f80, 0x1fff /* rim shot */
2736 };
2737
2738
2739 /* flag enable control 0x110 */
YM2608IRQFlagWrite(FM_OPN * OPN,ym2608_state * F2608,int v)2740 static inline void YM2608IRQFlagWrite(FM_OPN *OPN, ym2608_state *F2608, int v)
2741 {
2742 if( v & 0x80 )
2743 { /* Reset IRQ flag */
2744 FM_STATUS_RESET(&OPN->ST, 0xf7); /* don't touch BUFRDY flag otherwise we'd have to call ymdeltat module to set the flag back */
2745 }
2746 else
2747 { /* Set status flag mask */
2748 F2608->flagmask = (~(v&0x1f));
2749 FM_IRQMASK_SET(&OPN->ST, (F2608->irqmask & F2608->flagmask) );
2750 }
2751 }
2752
2753 /* compatible mode & IRQ enable control 0x29 */
YM2608IRQMaskWrite(FM_OPN * OPN,ym2608_state * F2608,int v)2754 static inline void YM2608IRQMaskWrite(FM_OPN *OPN, ym2608_state *F2608, int v)
2755 {
2756 /* SCH,xx,xxx,EN_ZERO,EN_BRDY,EN_EOS,EN_TB,EN_TA */
2757
2758 /* extend 3ch. enable/disable */
2759 if(v&0x80)
2760 OPN->type |= TYPE_6CH; /* OPNA mode - 6 FM channels */
2761 else
2762 OPN->type &= ~TYPE_6CH; /* OPN mode - 3 FM channels */
2763
2764 /* IRQ MASK store and set */
2765 F2608->irqmask = v&0x1f;
2766 FM_IRQMASK_SET(&OPN->ST, (F2608->irqmask & F2608->flagmask) );
2767 }
2768
2769 /* Generate samples for one of the YM2608s */
ym2608_update_one(void * chip,FMSAMPLE ** buffer,int length)2770 void ym2608_update_one(void *chip, FMSAMPLE **buffer, int length)
2771 {
2772 ym2608_state *F2608 = (ym2608_state *)chip;
2773 FM_OPN *OPN = &F2608->OPN;
2774 YM_DELTAT *DELTAT = &F2608->deltaT;
2775 int i,j;
2776 FMSAMPLE *bufL,*bufR;
2777 FM_CH *cch[6];
2778 int32_t *out_fm = OPN->out_fm;
2779
2780 /* set bufer */
2781 bufL = buffer[0];
2782 bufR = buffer[1];
2783
2784 cch[0] = &F2608->CH[0];
2785 cch[1] = &F2608->CH[1];
2786 cch[2] = &F2608->CH[2];
2787 cch[3] = &F2608->CH[3];
2788 cch[4] = &F2608->CH[4];
2789 cch[5] = &F2608->CH[5];
2790
2791 /* refresh PG and EG */
2792 refresh_fc_eg_chan( OPN, cch[0] );
2793 refresh_fc_eg_chan( OPN, cch[1] );
2794 if( (OPN->ST.mode & 0xc0) )
2795 {
2796 /* 3SLOT MODE */
2797 if( cch[2]->SLOT[SLOT1].Incr==-1)
2798 {
2799 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT1] , OPN->SL3.fc[1] , OPN->SL3.kcode[1] );
2800 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT2] , OPN->SL3.fc[2] , OPN->SL3.kcode[2] );
2801 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT3] , OPN->SL3.fc[0] , OPN->SL3.kcode[0] );
2802 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT4] , cch[2]->fc , cch[2]->kcode );
2803 }
2804 }
2805 else
2806 refresh_fc_eg_chan( OPN, cch[2] );
2807 refresh_fc_eg_chan( OPN, cch[3] );
2808 refresh_fc_eg_chan( OPN, cch[4] );
2809 refresh_fc_eg_chan( OPN, cch[5] );
2810
2811
2812 /* buffering */
2813 for(i=0; i < length ; i++)
2814 {
2815 advance_lfo(OPN);
2816
2817 /* clear output acc. */
2818 OPN->out_adpcm[OUTD_LEFT] = OPN->out_adpcm[OUTD_RIGHT] = OPN->out_adpcm[OUTD_CENTER] = 0;
2819 OPN->out_delta[OUTD_LEFT] = OPN->out_delta[OUTD_RIGHT] = OPN->out_delta[OUTD_CENTER] = 0;
2820 /* clear outputs */
2821 out_fm[0] = 0;
2822 out_fm[1] = 0;
2823 out_fm[2] = 0;
2824 out_fm[3] = 0;
2825 out_fm[4] = 0;
2826 out_fm[5] = 0;
2827
2828 /* calculate FM */
2829 chan_calc(OPN, cch[0], 0 );
2830 chan_calc(OPN, cch[1], 1 );
2831 chan_calc(OPN, cch[2], 2 );
2832 chan_calc(OPN, cch[3], 3 );
2833 chan_calc(OPN, cch[4], 4 );
2834 chan_calc(OPN, cch[5], 5 );
2835
2836 /* deltaT ADPCM */
2837 if( DELTAT->portstate&0x80 )
2838 DELTAT->ADPCM_CALC();
2839
2840 /* ADPCMA */
2841 for( j = 0; j < 6; j++ )
2842 {
2843 if( F2608->adpcm[j].flag )
2844 F2608->ADPCMA_calc_chan( &F2608->adpcm[j]);
2845 }
2846
2847 /* advance envelope generator */
2848 OPN->eg_timer += OPN->eg_timer_add;
2849 while (OPN->eg_timer >= OPN->eg_timer_overflow)
2850 {
2851 OPN->eg_timer -= OPN->eg_timer_overflow;
2852 OPN->eg_cnt++;
2853
2854 advance_eg_channel(OPN, &cch[0]->SLOT[SLOT1]);
2855 advance_eg_channel(OPN, &cch[1]->SLOT[SLOT1]);
2856 advance_eg_channel(OPN, &cch[2]->SLOT[SLOT1]);
2857 advance_eg_channel(OPN, &cch[3]->SLOT[SLOT1]);
2858 advance_eg_channel(OPN, &cch[4]->SLOT[SLOT1]);
2859 advance_eg_channel(OPN, &cch[5]->SLOT[SLOT1]);
2860 }
2861
2862 /* buffering */
2863 {
2864 int lt,rt;
2865
2866 lt = OPN->out_adpcm[OUTD_LEFT] + OPN->out_adpcm[OUTD_CENTER];
2867 rt = OPN->out_adpcm[OUTD_RIGHT] + OPN->out_adpcm[OUTD_CENTER];
2868 lt += (OPN->out_delta[OUTD_LEFT] + OPN->out_delta[OUTD_CENTER])>>9;
2869 rt += (OPN->out_delta[OUTD_RIGHT] + OPN->out_delta[OUTD_CENTER])>>9;
2870
2871 /* libOPNMIDI: 6-channels mixing */
2872 #define PANLAW_L(ch, chpan) (((out_fm[ch]>>1) * cch[ch]->pan_volume_l / 65535) & OPN->pan[chpan]);
2873 #define PANLAW_R(ch, chpan) (((out_fm[ch]>>1) * cch[ch]->pan_volume_r / 65535) & OPN->pan[chpan]);
2874 lt = PANLAW_L(0, 0);
2875 rt = PANLAW_R(0, 1);
2876 lt += PANLAW_L(1, 2);
2877 rt += PANLAW_R(1, 3);
2878 lt += PANLAW_L(2, 4);
2879 rt += PANLAW_R(2, 5);
2880 lt += PANLAW_L(3, 6);
2881 rt += PANLAW_R(3, 7);
2882 lt += PANLAW_L(4, 8);
2883 rt += PANLAW_R(4, 9);
2884 lt += PANLAW_L(5, 10);
2885 rt += PANLAW_R(5, 11);
2886 #undef PANLAW_L
2887 #undef PANLAW_R
2888
2889 lt >>= FINAL_SH;
2890 rt >>= FINAL_SH;
2891
2892 Limit( lt, MAXOUT, MINOUT );
2893 Limit( rt, MAXOUT, MINOUT );
2894 /* buffering */
2895 bufL[i] = lt;
2896 bufR[i] = rt;
2897
2898 #ifdef SAVE_SAMPLE
2899 SAVE_ALL_CHANNELS
2900 #endif
2901
2902 }
2903
2904 /* timer A control */
2905 INTERNAL_TIMER_A( &OPN->ST , cch[2] )
2906 }
2907 INTERNAL_TIMER_B(&OPN->ST,length)
2908
2909
2910 /* check IRQ for DELTA-T EOS */
2911 FM_STATUS_SET(&OPN->ST, 0);
2912
2913 }
2914 #ifdef MAME_EMU_SAVE_H
ym2608_postload(void * chip)2915 void ym2608_postload(void *chip)
2916 {
2917 if (chip)
2918 {
2919 ym2608_state *F2608 = (ym2608_state *)chip;
2920 int r;
2921
2922 /* prescaler */
2923 OPNPrescaler_w(&F2608->OPN,1,2);
2924 F2608->deltaT.freqbase = F2608->OPN.ST.freqbase;
2925 /* IRQ mask / mode */
2926 YM2608IRQMaskWrite(&F2608->OPN, F2608, F2608->REGS[0x29]);
2927 /* SSG registers */
2928 for(r=0;r<16;r++)
2929 {
2930 (*F2608->OPN.ST.SSG->write)(F2608->OPN.ST.device,0,r);
2931 (*F2608->OPN.ST.SSG->write)(F2608->OPN.ST.device,1,F2608->REGS[r]);
2932 }
2933
2934 /* OPN registers */
2935 /* DT / MULTI , TL , KS / AR , AMON / DR , SR , SL / RR , SSG-EG */
2936 for(r=0x30;r<0x9e;r++)
2937 if((r&3) != 3)
2938 {
2939 OPNWriteReg(&F2608->OPN,r,F2608->REGS[r]);
2940 OPNWriteReg(&F2608->OPN,r|0x100,F2608->REGS[r|0x100]);
2941 }
2942 /* FB / CONNECT , L / R / AMS / PMS */
2943 for(r=0xb0;r<0xb6;r++)
2944 if((r&3) != 3)
2945 {
2946 OPNWriteReg(&F2608->OPN,r,F2608->REGS[r]);
2947 OPNWriteReg(&F2608->OPN,r|0x100,F2608->REGS[r|0x100]);
2948 }
2949 /* FM channels */
2950 /*FM_channel_postload(F2608->CH,6);*/
2951 /* rhythm(ADPCMA) */
2952 F2608->FM_ADPCMAWrite(1,F2608->REGS[0x111]);
2953 for( r=0x08 ; r<0x0c ; r++)
2954 F2608->FM_ADPCMAWrite(r,F2608->REGS[r+0x110]);
2955 /* Delta-T ADPCM unit */
2956 F2608->deltaT.postload( &F2608->REGS[0x100] );
2957 }
2958 }
2959
YM2608_save_state(ym2608_state * F2608,device_t * device)2960 static void YM2608_save_state(ym2608_state *F2608, device_t *device)
2961 {
2962 device->save_item(NAME(F2608->REGS));
2963 FMsave_state_st(device,&F2608->OPN.ST);
2964 FMsave_state_channel(device,F2608->CH,6);
2965 /* 3slots */
2966 device->save_item(NAME(F2608->OPN.SL3.fc));
2967 device->save_item(NAME(F2608->OPN.SL3.fn_h));
2968 device->save_item(NAME(F2608->OPN.SL3.kcode));
2969 /* address register1 */
2970 device->save_item(NAME(F2608->addr_A1));
2971 /* rhythm(ADPCMA) */
2972 FMsave_state_adpcma(device,F2608->adpcm);
2973 /* Delta-T ADPCM unit */
2974 F2608->deltaT.savestate(device);
2975 }
2976 #endif /* MAME_EMU_SAVE_H */
2977
YM2608_deltat_status_set(void * chip,uint8_t changebits)2978 static void YM2608_deltat_status_set(void *chip, uint8_t changebits)
2979 {
2980 ym2608_state *F2608 = (ym2608_state *)chip;
2981 FM_STATUS_SET(&(F2608->OPN.ST), changebits);
2982 }
YM2608_deltat_status_reset(void * chip,uint8_t changebits)2983 static void YM2608_deltat_status_reset(void *chip, uint8_t changebits)
2984 {
2985 ym2608_state *F2608 = (ym2608_state *)chip;
2986 FM_STATUS_RESET(&(F2608->OPN.ST), changebits);
2987 }
2988 /* YM2608(OPNA) */
ym2608_init(device_t * device,int clock,int rate,FM_READBYTE InternalReadByte,FM_READBYTE ExternalReadByte,FM_WRITEBYTE ExternalWriteByte,FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler,const ssg_callbacks * ssg)2989 void * ym2608_init(device_t *device, int clock, int rate,
2990 FM_READBYTE InternalReadByte,
2991 FM_READBYTE ExternalReadByte, FM_WRITEBYTE ExternalWriteByte,
2992 FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler, const ssg_callbacks *ssg)
2993 {
2994 ym2608_state *F2608;
2995
2996 /* allocate extend state space */
2997 F2608 = new ym2608_state;
2998 memset(F2608, 0, sizeof(*F2608));
2999 /* allocate total level table (128kb space) */
3000 if( !init_tables() )
3001 {
3002 delete F2608;
3003 return NULLPTR;
3004 }
3005
3006 F2608->device = device;
3007 F2608->OPN.type = TYPE_YM2608;
3008 F2608->OPN.P_CH = F2608->CH;
3009 F2608->OPN.ST.device = device;
3010 F2608->OPN.ST.clock = clock;
3011 F2608->OPN.ST.rate = rate;
3012
3013 /* External handlers */
3014 F2608->OPN.ST.timer_handler = timer_handler;
3015 F2608->OPN.ST.IRQ_Handler = IRQHandler;
3016 F2608->OPN.ST.SSG = ssg;
3017
3018 /* DELTA-T */
3019 F2608->deltaT.read_byte = ExternalReadByte;
3020 F2608->deltaT.write_byte = ExternalWriteByte;
3021
3022 /*F2608->deltaT.write_time = 20.0 / clock;*/ /* a single byte write takes 20 cycles of main clock */
3023 /*F2608->deltaT.read_time = 18.0 / clock;*/ /* a single byte read takes 18 cycles of main clock */
3024
3025 F2608->deltaT.status_set_handler = YM2608_deltat_status_set;
3026 F2608->deltaT.status_reset_handler = YM2608_deltat_status_reset;
3027 F2608->deltaT.status_change_which_chip = F2608;
3028 F2608->deltaT.status_change_EOS_bit = 0x04; /* status flag: set bit2 on End Of Sample */
3029 F2608->deltaT.status_change_BRDY_bit = 0x08; /* status flag: set bit3 on BRDY */
3030 F2608->deltaT.status_change_ZERO_bit = 0x10; /* status flag: set bit4 if silence continues for more than 290 milliseconds while recording the ADPCM */
3031
3032 /* ADPCM Rhythm */
3033 F2608->read_byte = InternalReadByte;
3034
3035 Init_ADPCMATable();
3036
3037 for (unsigned i = 0; i < 6; i++)
3038 {
3039 F2608->CH[i].pan_volume_l = 46340;
3040 F2608->CH[i].pan_volume_r = 46340;
3041 }
3042
3043 #ifdef MAME_EMU_SAVE_H
3044 YM2608_save_state(F2608, device);
3045 #endif
3046 return F2608;
3047 }
3048
ym2608_clock_changed(void * chip,int clock,int rate)3049 void ym2608_clock_changed(void *chip, int clock, int rate)
3050 {
3051 ym2608_state *F2608 = (ym2608_state *)chip;
3052
3053 F2608->OPN.ST.clock = clock;
3054 F2608->OPN.ST.rate = rate;
3055 }
3056
3057 /* shut down emulator */
ym2608_shutdown(void * chip)3058 void ym2608_shutdown(void *chip)
3059 {
3060 ym2608_state *F2608 = (ym2608_state *)chip;
3061
3062 FMCloseTable();
3063 delete F2608;
3064 }
3065
3066 /* reset one of chips */
ym2608_reset_chip(void * chip)3067 void ym2608_reset_chip(void *chip)
3068 {
3069 int i;
3070 ym2608_state *F2608 = (ym2608_state *)chip;
3071 FM_OPN *OPN = &F2608->OPN;
3072 YM_DELTAT *DELTAT = &F2608->deltaT;
3073
3074 /* Reset Prescaler */
3075 OPNPrescaler_w(OPN , 0 , 2);
3076 F2608->deltaT.freqbase = OPN->ST.freqbase;
3077 /* reset SSG section */
3078 (*OPN->ST.SSG->reset)(OPN->ST.device);
3079
3080 /* status clear */
3081 FM_BUSY_CLEAR(&OPN->ST);
3082
3083 /* register 0x29 - default value after reset is:
3084 enable only 3 FM channels and enable all the status flags */
3085 YM2608IRQMaskWrite(OPN, F2608, 0x1f ); /* default value for D4-D0 is 1 */
3086
3087 /* register 0x10, A1=1 - default value is 1 for D4, D3, D2, 0 for the rest */
3088 YM2608IRQFlagWrite(OPN, F2608, 0x1c ); /* default: enable timer A and B, disable EOS, BRDY and ZERO */
3089
3090 OPNWriteMode(OPN,0x27,0x30); /* mode 0 , timer reset */
3091
3092 OPN->eg_timer = 0;
3093 OPN->eg_cnt = 0;
3094
3095 FM_STATUS_RESET(&OPN->ST, 0xff);
3096
3097 reset_channels( &OPN->ST , F2608->CH , 6 );
3098 /* reset OPerator paramater */
3099 for(i = 0xb6 ; i >= 0xb4 ; i-- )
3100 {
3101 OPNWriteReg(OPN,i ,0xc0);
3102 OPNWriteReg(OPN,i|0x100,0xc0);
3103 }
3104 for(i = 0xb2 ; i >= 0x30 ; i-- )
3105 {
3106 OPNWriteReg(OPN,i ,0);
3107 OPNWriteReg(OPN,i|0x100,0);
3108 }
3109 for(i = 0x26 ; i >= 0x20 ; i-- ) OPNWriteReg(OPN,i,0);
3110
3111 /* ADPCM - percussion sounds */
3112 for( i = 0; i < 6; i++ )
3113 {
3114 if (i<=3) /* channels 0,1,2,3 */
3115 F2608->adpcm[i].step = (uint32_t)((float)(1<<ADPCM_SHIFT)*((float)F2608->OPN.ST.freqbase)/3.0f);
3116 else /* channels 4 and 5 work with slower clock */
3117 F2608->adpcm[i].step = (uint32_t)((float)(1<<ADPCM_SHIFT)*((float)F2608->OPN.ST.freqbase)/6.0f);
3118
3119 F2608->adpcm[i].start = YM2608_ADPCM_ROM_addr[i*2];
3120 F2608->adpcm[i].end = YM2608_ADPCM_ROM_addr[i*2+1];
3121
3122 F2608->adpcm[i].now_addr = 0;
3123 F2608->adpcm[i].now_step = 0;
3124 /* F2608->adpcm[i].delta = 21866; */
3125 F2608->adpcm[i].vol_mul = 0;
3126 F2608->adpcm[i].pan = &OPN->out_adpcm[OUTD_CENTER]; /* default center */
3127 F2608->adpcm[i].flagMask = 0;
3128 F2608->adpcm[i].flag = 0;
3129 F2608->adpcm[i].adpcm_acc = 0;
3130 F2608->adpcm[i].adpcm_step= 0;
3131 F2608->adpcm[i].adpcm_out = 0;
3132 }
3133 F2608->adpcmTL = 0x3f;
3134
3135 F2608->adpcm_arrivedEndAddress = 0; /* not used */
3136
3137 /* DELTA-T unit */
3138 DELTAT->freqbase = OPN->ST.freqbase;
3139 DELTAT->output_pointer = OPN->out_delta;
3140 DELTAT->portshift = 5; /* always 5bits shift */ /* ASG */
3141 DELTAT->output_range = 1<<23;
3142 DELTAT->ADPCM_Reset(OUTD_CENTER,YM_DELTAT::EMULATION_MODE_NORMAL,F2608->device);
3143 }
3144
3145 /* YM2608 write */
3146 /* n = number */
3147 /* a = address */
3148 /* v = value */
ym2608_write(void * chip,int a,uint8_t v)3149 int ym2608_write(void *chip, int a,uint8_t v)
3150 {
3151 ym2608_state *F2608 = (ym2608_state *)chip;
3152 FM_OPN *OPN = &F2608->OPN;
3153 int addr;
3154
3155 v &= 0xff; /*adjust to 8 bit bus */
3156
3157
3158 switch(a&3)
3159 {
3160 case 0: /* address port 0 */
3161 OPN->ST.address = v;
3162 F2608->addr_A1 = 0;
3163
3164 /* Write register to SSG emulator */
3165 if( v < 16 ) (*OPN->ST.SSG->write)(OPN->ST.device,0,v);
3166 /* prescaler selecter : 2d,2e,2f */
3167 if( v >= 0x2d && v <= 0x2f )
3168 {
3169 OPNPrescaler_w(OPN , v , 2);
3170 F2608->deltaT.freqbase = OPN->ST.freqbase;
3171 }
3172 break;
3173
3174 case 1: /* data port 0 */
3175 if (F2608->addr_A1 != 0)
3176 break; /* verified on real YM2608 */
3177
3178 addr = OPN->ST.address;
3179 F2608->REGS[addr] = v;
3180 switch(addr & 0xf0)
3181 {
3182 case 0x00: /* SSG section */
3183 /* Write data to SSG emulator */
3184 (*OPN->ST.SSG->write)(OPN->ST.device,a,v);
3185 break;
3186 case 0x10: /* 0x10-0x1f : Rhythm section */
3187 ym2608_device::update_request(OPN->ST.device);
3188 F2608->FM_ADPCMAWrite(addr-0x10,v);
3189 break;
3190 case 0x20: /* Mode Register */
3191 switch(addr)
3192 {
3193 case 0x29: /* SCH,xx,xxx,EN_ZERO,EN_BRDY,EN_EOS,EN_TB,EN_TA */
3194 YM2608IRQMaskWrite(OPN, F2608, v);
3195 break;
3196 default:
3197 ym2608_device::update_request(OPN->ST.device);
3198 OPNWriteMode(OPN,addr,v);
3199 }
3200 break;
3201 default: /* OPN section */
3202 ym2608_device::update_request(OPN->ST.device);
3203 OPNWriteReg(OPN,addr,v);
3204 }
3205 break;
3206
3207 case 2: /* address port 1 */
3208 OPN->ST.address = v;
3209 F2608->addr_A1 = 1;
3210 break;
3211
3212 case 3: /* data port 1 */
3213 if (F2608->addr_A1 != 1)
3214 break; /* verified on real YM2608 */
3215
3216 addr = OPN->ST.address;
3217 F2608->REGS[addr | 0x100] = v;
3218 ym2608_device::update_request(OPN->ST.device);
3219 switch( addr & 0xf0 )
3220 {
3221 case 0x00: /* DELTAT PORT */
3222 switch( addr )
3223 {
3224 case 0x0e: /* DAC data */
3225 F2608->device->logerror("YM2608: write to DAC data (unimplemented) value=%02x\n",v);
3226 break;
3227 default:
3228 /* 0x00-0x0d */
3229 F2608->deltaT.ADPCM_Write(addr,v);
3230 }
3231 break;
3232 case 0x10: /* IRQ Flag control */
3233 if( addr == 0x10 )
3234 {
3235 YM2608IRQFlagWrite(OPN, F2608, v);
3236 }
3237 break;
3238 default:
3239 OPNWriteReg(OPN,addr | 0x100,v);
3240 }
3241 }
3242 return OPN->ST.irq;
3243 }
3244
3245 // libOPNMIDI: soft panning
ym2608_write_pan(void * chip,int c,unsigned char v)3246 void ym2608_write_pan(void *chip, int c, unsigned char v)
3247 {
3248 ym2608_state *F2608 = (ym2608_state *)chip;
3249 assert((c >= 0) && (c < 6));
3250 F2608->CH[c].pan_volume_l = panlawtable[v & 0x7F];
3251 F2608->CH[c].pan_volume_r = panlawtable[0x7F - (v & 0x7F)];
3252 }
3253
ym2608_read(void * chip,int a)3254 uint8_t ym2608_read(void *chip,int a)
3255 {
3256 ym2608_state *F2608 = (ym2608_state *)chip;
3257 int addr = F2608->OPN.ST.address;
3258 uint8_t ret = 0;
3259
3260 switch( a&3 )
3261 {
3262 case 0: /* status 0 : YM2203 compatible */
3263 /* BUSY:x:x:x:x:x:FLAGB:FLAGA */
3264 ret = FM_STATUS_FLAG(&F2608->OPN.ST) & 0x83;
3265 break;
3266
3267 case 1: /* status 0, ID */
3268 if( addr < 16 ) ret = (*F2608->OPN.ST.SSG->read)(F2608->OPN.ST.device);
3269 else if(addr == 0xff) ret = 0x01; /* ID code */
3270 break;
3271
3272 case 2: /* status 1 : status 0 + ADPCM status */
3273 /* BUSY : x : PCMBUSY : ZERO : BRDY : EOS : FLAGB : FLAGA */
3274 ret = (FM_STATUS_FLAG(&F2608->OPN.ST) & (F2608->flagmask|0x80)) | ((F2608->deltaT.PCM_BSY & 1)<<5) ;
3275 break;
3276
3277 case 3:
3278 if(addr == 0x08)
3279 {
3280 ret = F2608->deltaT.ADPCM_Read();
3281 }
3282 else
3283 {
3284 if(addr == 0x0f)
3285 {
3286 F2608->device->logerror("YM2608 A/D conversion is accessed but not implemented !\n");
3287 ret = 0x80; /* 2's complement PCM data - result from A/D conversion */
3288 }
3289 }
3290 break;
3291 }
3292 return ret;
3293 }
3294
ym2608_timer_over(void * chip,int c)3295 int ym2608_timer_over(void *chip,int c)
3296 {
3297 ym2608_state *F2608 = (ym2608_state *)chip;
3298
3299 switch(c)
3300 {
3301 #if 0
3302 case 2:
3303 { /* BUFRDY flag */
3304 F2608->deltaT.BRDY_callback();
3305 }
3306 break;
3307 #endif
3308 case 1:
3309 { /* Timer B */
3310 TimerBOver( &(F2608->OPN.ST) );
3311 }
3312 break;
3313 case 0:
3314 { /* Timer A */
3315 ym2608_device::update_request(F2608->OPN.ST.device);
3316 /* timer update */
3317 TimerAOver( &(F2608->OPN.ST) );
3318 /* CSM mode key,TL controll */
3319 if( F2608->OPN.ST.mode & 0x80 )
3320 { /* CSM mode total level latch and auto key on */
3321 CSMKeyControll( F2608->OPN.type, &(F2608->CH[2]) );
3322 }
3323 }
3324 break;
3325 default:
3326 break;
3327 }
3328
3329 return F2608->OPN.ST.irq;
3330 }
3331
3332 #endif /* BUILD_YM2608 */
3333
3334
3335
3336 #if (BUILD_YM2610||BUILD_YM2610B)
3337 /* YM2610(OPNB) */
3338
3339 /* Generate samples for one of the YM2610s */
ym2610_update_one(void * chip,FMSAMPLE ** buffer,int length)3340 void ym2610_update_one(void *chip, FMSAMPLE **buffer, int length)
3341 {
3342 ym2610_state *F2610 = (ym2610_state *)chip;
3343 FM_OPN *OPN = &F2610->OPN;
3344 YM_DELTAT *DELTAT = &F2610->deltaT;
3345 int i,j;
3346 FMSAMPLE *bufL,*bufR;
3347 FM_CH *cch[4];
3348 int32_t *out_fm = OPN->out_fm;
3349
3350 /* buffer setup */
3351 bufL = buffer[0];
3352 bufR = buffer[1];
3353
3354 cch[0] = &F2610->CH[1];
3355 cch[1] = &F2610->CH[2];
3356 cch[2] = &F2610->CH[4];
3357 cch[3] = &F2610->CH[5];
3358
3359 #ifdef YM2610B_WARNING
3360 #define FM_KEY_IS(SLOT) ((SLOT)->key)
3361 #define FM_MSG_YM2610B "YM2610-%p.CH%d is playing,Check whether the type of the chip is YM2610B\n"
3362 /* Check YM2610B warning message */
3363 if( FM_KEY_IS(&F2610->CH[0].SLOT[3]) )
3364 LOG(F2610->device,LOG_WAR,(FM_MSG_YM2610B,F2610->OPN.ST.device,0));
3365 if( FM_KEY_IS(&F2610->CH[3].SLOT[3]) )
3366 LOG(F2610->device,LOG_WAR,(FM_MSG_YM2610B,F2610->OPN.ST.device,3));
3367 #endif
3368
3369 /* refresh PG and EG */
3370 refresh_fc_eg_chan( OPN, cch[0] );
3371 if( (OPN->ST.mode & 0xc0) )
3372 {
3373 /* 3SLOT MODE */
3374 if( cch[1]->SLOT[SLOT1].Incr==-1)
3375 {
3376 refresh_fc_eg_slot(OPN, &cch[1]->SLOT[SLOT1] , OPN->SL3.fc[1] , OPN->SL3.kcode[1] );
3377 refresh_fc_eg_slot(OPN, &cch[1]->SLOT[SLOT2] , OPN->SL3.fc[2] , OPN->SL3.kcode[2] );
3378 refresh_fc_eg_slot(OPN, &cch[1]->SLOT[SLOT3] , OPN->SL3.fc[0] , OPN->SL3.kcode[0] );
3379 refresh_fc_eg_slot(OPN, &cch[1]->SLOT[SLOT4] , cch[1]->fc , cch[1]->kcode );
3380 }
3381 }
3382 else
3383 refresh_fc_eg_chan( OPN, cch[1] );
3384 refresh_fc_eg_chan( OPN, cch[2] );
3385 refresh_fc_eg_chan( OPN, cch[3] );
3386
3387 /* buffering */
3388 for(i=0; i < length ; i++)
3389 {
3390 advance_lfo(OPN);
3391
3392 /* clear output acc. */
3393 OPN->out_adpcm[OUTD_LEFT] = OPN->out_adpcm[OUTD_RIGHT] = OPN->out_adpcm[OUTD_CENTER] = 0;
3394 OPN->out_delta[OUTD_LEFT] = OPN->out_delta[OUTD_RIGHT] = OPN->out_delta[OUTD_CENTER] = 0;
3395 /* clear outputs */
3396 out_fm[1] = 0;
3397 out_fm[2] = 0;
3398 out_fm[4] = 0;
3399 out_fm[5] = 0;
3400
3401 /* advance envelope generator */
3402 OPN->eg_timer += OPN->eg_timer_add;
3403 while (OPN->eg_timer >= OPN->eg_timer_overflow)
3404 {
3405 OPN->eg_timer -= OPN->eg_timer_overflow;
3406 OPN->eg_cnt++;
3407
3408 advance_eg_channel(OPN, &cch[0]->SLOT[SLOT1]);
3409 advance_eg_channel(OPN, &cch[1]->SLOT[SLOT1]);
3410 advance_eg_channel(OPN, &cch[2]->SLOT[SLOT1]);
3411 advance_eg_channel(OPN, &cch[3]->SLOT[SLOT1]);
3412 }
3413
3414 /* calculate FM */
3415 chan_calc(OPN, cch[0], 1 ); /*remapped to 1*/
3416 chan_calc(OPN, cch[1], 2 ); /*remapped to 2*/
3417 chan_calc(OPN, cch[2], 4 ); /*remapped to 4*/
3418 chan_calc(OPN, cch[3], 5 ); /*remapped to 5*/
3419
3420 /* deltaT ADPCM */
3421 if( DELTAT->portstate&0x80 )
3422 DELTAT->ADPCM_CALC();
3423
3424 /* ADPCMA */
3425 for( j = 0; j < 6; j++ )
3426 {
3427 if( F2610->adpcm[j].flag )
3428 F2610->ADPCMA_calc_chan(&F2610->adpcm[j]);
3429 }
3430
3431 /* buffering */
3432 {
3433 int lt,rt;
3434
3435 lt = OPN->out_adpcm[OUTD_LEFT] + OPN->out_adpcm[OUTD_CENTER];
3436 rt = OPN->out_adpcm[OUTD_RIGHT] + OPN->out_adpcm[OUTD_CENTER];
3437 lt += (OPN->out_delta[OUTD_LEFT] + OPN->out_delta[OUTD_CENTER])>>9;
3438 rt += (OPN->out_delta[OUTD_RIGHT] + OPN->out_delta[OUTD_CENTER])>>9;
3439
3440
3441 lt += ((out_fm[1]>>1) & OPN->pan[2]); /* the shift right was verified on real chip */
3442 rt += ((out_fm[1]>>1) & OPN->pan[3]);
3443 lt += ((out_fm[2]>>1) & OPN->pan[4]);
3444 rt += ((out_fm[2]>>1) & OPN->pan[5]);
3445
3446 lt += ((out_fm[4]>>1) & OPN->pan[8]);
3447 rt += ((out_fm[4]>>1) & OPN->pan[9]);
3448 lt += ((out_fm[5]>>1) & OPN->pan[10]);
3449 rt += ((out_fm[5]>>1) & OPN->pan[11]);
3450
3451
3452 lt >>= FINAL_SH;
3453 rt >>= FINAL_SH;
3454
3455 Limit( lt, MAXOUT, MINOUT );
3456 Limit( rt, MAXOUT, MINOUT );
3457
3458 #ifdef SAVE_SAMPLE
3459 SAVE_ALL_CHANNELS
3460 #endif
3461
3462 /* buffering */
3463 bufL[i] = lt;
3464 bufR[i] = rt;
3465 }
3466
3467 /* timer A control */
3468 INTERNAL_TIMER_A( &OPN->ST , cch[1] )
3469 }
3470 INTERNAL_TIMER_B(&OPN->ST,length)
3471
3472 }
3473
3474 #if BUILD_YM2610B
3475 /* Generate samples for one of the YM2610Bs */
ym2610b_update_one(void * chip,FMSAMPLE ** buffer,int length)3476 void ym2610b_update_one(void *chip, FMSAMPLE **buffer, int length)
3477 {
3478 ym2610_state *F2610 = (ym2610_state *)chip;
3479 FM_OPN *OPN = &F2610->OPN;
3480 YM_DELTAT *DELTAT = &F2610->deltaT;
3481 int i,j;
3482 FMSAMPLE *bufL,*bufR;
3483 FM_CH *cch[6];
3484 int32_t *out_fm = OPN->out_fm;
3485
3486 /* buffer setup */
3487 bufL = buffer[0];
3488 bufR = buffer[1];
3489
3490 cch[0] = &F2610->CH[0];
3491 cch[1] = &F2610->CH[1];
3492 cch[2] = &F2610->CH[2];
3493 cch[3] = &F2610->CH[3];
3494 cch[4] = &F2610->CH[4];
3495 cch[5] = &F2610->CH[5];
3496
3497 /* refresh PG and EG */
3498 refresh_fc_eg_chan( OPN, cch[0] );
3499 refresh_fc_eg_chan( OPN, cch[1] );
3500 if( (OPN->ST.mode & 0xc0) )
3501 {
3502 /* 3SLOT MODE */
3503 if( cch[2]->SLOT[SLOT1].Incr==-1)
3504 {
3505 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT1] , OPN->SL3.fc[1] , OPN->SL3.kcode[1] );
3506 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT2] , OPN->SL3.fc[2] , OPN->SL3.kcode[2] );
3507 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT3] , OPN->SL3.fc[0] , OPN->SL3.kcode[0] );
3508 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT4] , cch[2]->fc , cch[2]->kcode );
3509 }
3510 }
3511 else
3512 refresh_fc_eg_chan( OPN, cch[2] );
3513 refresh_fc_eg_chan( OPN, cch[3] );
3514 refresh_fc_eg_chan( OPN, cch[4] );
3515 refresh_fc_eg_chan( OPN, cch[5] );
3516
3517 /* buffering */
3518 for(i=0; i < length ; i++)
3519 {
3520 advance_lfo(OPN);
3521
3522 /* clear output acc. */
3523 OPN->out_adpcm[OUTD_LEFT] = OPN->out_adpcm[OUTD_RIGHT] = OPN->out_adpcm[OUTD_CENTER] = 0;
3524 OPN->out_delta[OUTD_LEFT] = OPN->out_delta[OUTD_RIGHT] = OPN->out_delta[OUTD_CENTER] = 0;
3525 /* clear outputs */
3526 out_fm[0] = 0;
3527 out_fm[1] = 0;
3528 out_fm[2] = 0;
3529 out_fm[3] = 0;
3530 out_fm[4] = 0;
3531 out_fm[5] = 0;
3532
3533 /* advance envelope generator */
3534 OPN->eg_timer += OPN->eg_timer_add;
3535 while (OPN->eg_timer >= OPN->eg_timer_overflow)
3536 {
3537 OPN->eg_timer -= OPN->eg_timer_overflow;
3538 OPN->eg_cnt++;
3539
3540 advance_eg_channel(OPN, &cch[0]->SLOT[SLOT1]);
3541 advance_eg_channel(OPN, &cch[1]->SLOT[SLOT1]);
3542 advance_eg_channel(OPN, &cch[2]->SLOT[SLOT1]);
3543 advance_eg_channel(OPN, &cch[3]->SLOT[SLOT1]);
3544 advance_eg_channel(OPN, &cch[4]->SLOT[SLOT1]);
3545 advance_eg_channel(OPN, &cch[5]->SLOT[SLOT1]);
3546 }
3547
3548 /* calculate FM */
3549 chan_calc(OPN, cch[0], 0 );
3550 chan_calc(OPN, cch[1], 1 );
3551 chan_calc(OPN, cch[2], 2 );
3552 chan_calc(OPN, cch[3], 3 );
3553 chan_calc(OPN, cch[4], 4 );
3554 chan_calc(OPN, cch[5], 5 );
3555
3556 /* deltaT ADPCM */
3557 if( DELTAT->portstate&0x80 )
3558 DELTAT->ADPCM_CALC();
3559
3560 /* ADPCMA */
3561 for( j = 0; j < 6; j++ )
3562 {
3563 if( F2610->adpcm[j].flag )
3564 F2610->ADPCMA_calc_chan(&F2610->adpcm[j]);
3565 }
3566
3567 /* buffering */
3568 {
3569 int lt,rt;
3570
3571 lt = OPN->out_adpcm[OUTD_LEFT] + OPN->out_adpcm[OUTD_CENTER];
3572 rt = OPN->out_adpcm[OUTD_RIGHT] + OPN->out_adpcm[OUTD_CENTER];
3573 lt += (OPN->out_delta[OUTD_LEFT] + OPN->out_delta[OUTD_CENTER])>>9;
3574 rt += (OPN->out_delta[OUTD_RIGHT] + OPN->out_delta[OUTD_CENTER])>>9;
3575
3576 lt += ((out_fm[0]>>1) & OPN->pan[0]); /* the shift right is verified on YM2610 */
3577 rt += ((out_fm[0]>>1) & OPN->pan[1]);
3578 lt += ((out_fm[1]>>1) & OPN->pan[2]);
3579 rt += ((out_fm[1]>>1) & OPN->pan[3]);
3580 lt += ((out_fm[2]>>1) & OPN->pan[4]);
3581 rt += ((out_fm[2]>>1) & OPN->pan[5]);
3582 lt += ((out_fm[3]>>1) & OPN->pan[6]);
3583 rt += ((out_fm[3]>>1) & OPN->pan[7]);
3584 lt += ((out_fm[4]>>1) & OPN->pan[8]);
3585 rt += ((out_fm[4]>>1) & OPN->pan[9]);
3586 lt += ((out_fm[5]>>1) & OPN->pan[10]);
3587 rt += ((out_fm[5]>>1) & OPN->pan[11]);
3588
3589
3590 lt >>= FINAL_SH;
3591 rt >>= FINAL_SH;
3592
3593 Limit( lt, MAXOUT, MINOUT );
3594 Limit( rt, MAXOUT, MINOUT );
3595
3596 #ifdef SAVE_SAMPLE
3597 SAVE_ALL_CHANNELS
3598 #endif
3599
3600 /* buffering */
3601 bufL[i] = lt;
3602 bufR[i] = rt;
3603 }
3604
3605 /* timer A control */
3606 INTERNAL_TIMER_A( &OPN->ST , cch[2] )
3607 }
3608 INTERNAL_TIMER_B(&OPN->ST,length)
3609
3610 }
3611 #endif /* BUILD_YM2610B */
3612
3613
3614 #ifdef MAME_EMU_SAVE_H
ym2610_postload(void * chip)3615 void ym2610_postload(void *chip)
3616 {
3617 if (chip)
3618 {
3619 ym2610_state *F2610 = (ym2610_state *)chip;
3620 int r;
3621
3622 /* SSG registers */
3623 for(r=0;r<16;r++)
3624 {
3625 (*F2610->OPN.ST.SSG->write)(F2610->OPN.ST.device,0,r);
3626 (*F2610->OPN.ST.SSG->write)(F2610->OPN.ST.device,1,F2610->REGS[r]);
3627 }
3628
3629 /* OPN registers */
3630 /* DT / MULTI , TL , KS / AR , AMON / DR , SR , SL / RR , SSG-EG */
3631 for(r=0x30;r<0x9e;r++)
3632 if((r&3) != 3)
3633 {
3634 OPNWriteReg(&F2610->OPN,r,F2610->REGS[r]);
3635 OPNWriteReg(&F2610->OPN,r|0x100,F2610->REGS[r|0x100]);
3636 }
3637 /* FB / CONNECT , L / R / AMS / PMS */
3638 for(r=0xb0;r<0xb6;r++)
3639 if((r&3) != 3)
3640 {
3641 OPNWriteReg(&F2610->OPN,r,F2610->REGS[r]);
3642 OPNWriteReg(&F2610->OPN,r|0x100,F2610->REGS[r|0x100]);
3643 }
3644 /* FM channels */
3645 /*FM_channel_postload(F2610->CH,6);*/
3646
3647 /* rhythm(ADPCMA) */
3648 F2610->FM_ADPCMAWrite(1,F2610->REGS[0x101]);
3649 for( r=0 ; r<6 ; r++)
3650 {
3651 F2610->FM_ADPCMAWrite(r+0x08,F2610->REGS[r+0x108]);
3652 F2610->FM_ADPCMAWrite(r+0x10,F2610->REGS[r+0x110]);
3653 F2610->FM_ADPCMAWrite(r+0x18,F2610->REGS[r+0x118]);
3654 F2610->FM_ADPCMAWrite(r+0x20,F2610->REGS[r+0x120]);
3655 F2610->FM_ADPCMAWrite(r+0x28,F2610->REGS[r+0x128]);
3656 }
3657 /* Delta-T ADPCM unit */
3658 F2610->deltaT.postload( &F2610->REGS[0x010] );
3659 }
3660 }
3661
YM2610_save_state(ym2610_state * F2610,device_t * device)3662 static void YM2610_save_state(ym2610_state *F2610, device_t *device)
3663 {
3664 device->save_item(NAME(F2610->REGS));
3665 FMsave_state_st(device,&F2610->OPN.ST);
3666 FMsave_state_channel(device,F2610->CH,6);
3667 /* 3slots */
3668 device->save_item(NAME(F2610->OPN.SL3.fc));
3669 device->save_item(NAME(F2610->OPN.SL3.fn_h));
3670 device->save_item(NAME(F2610->OPN.SL3.kcode));
3671 /* address register1 */
3672 device->save_item(NAME(F2610->addr_A1));
3673
3674 device->save_item(NAME(F2610->adpcm_arrivedEndAddress));
3675 /* rhythm(ADPCMA) */
3676 FMsave_state_adpcma(device,F2610->adpcm);
3677 /* Delta-T ADPCM unit */
3678 F2610->deltaT.savestate(device);
3679 }
3680 #endif /* MAME_EMU_SAVE_H */
3681
YM2610_deltat_status_set(void * chip,uint8_t changebits)3682 static void YM2610_deltat_status_set(void *chip, uint8_t changebits)
3683 {
3684 ym2610_state *F2610 = (ym2610_state *)chip;
3685 F2610->adpcm_arrivedEndAddress |= changebits;
3686 }
YM2610_deltat_status_reset(void * chip,uint8_t changebits)3687 static void YM2610_deltat_status_reset(void *chip, uint8_t changebits)
3688 {
3689 ym2610_state *F2610 = (ym2610_state *)chip;
3690 F2610->adpcm_arrivedEndAddress &= (~changebits);
3691 }
3692
ym2610_init(device_t * device,int clock,int rate,FM_READBYTE adpcm_a_read_byte,FM_READBYTE adpcm_b_read_byte,FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler,const ssg_callbacks * ssg)3693 void *ym2610_init(device_t *device, int clock, int rate,
3694 FM_READBYTE adpcm_a_read_byte, FM_READBYTE adpcm_b_read_byte,
3695 FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler, const ssg_callbacks *ssg)
3696 {
3697 ym2610_state *F2610;
3698
3699 /* allocate extend state space */
3700 F2610 = new ym2610_state;
3701 memset(F2610, 0, sizeof(*F2610));
3702 /* allocate total level table (128kb space) */
3703 if( !init_tables() )
3704 {
3705 delete F2610;
3706 return nullptr;
3707 }
3708
3709 F2610->device = device;
3710 /* FM */
3711 F2610->OPN.type = TYPE_YM2610;
3712 F2610->OPN.P_CH = F2610->CH;
3713 F2610->OPN.ST.device = device;
3714 F2610->OPN.ST.clock = clock;
3715 F2610->OPN.ST.rate = rate;
3716 /* Extend handler */
3717 F2610->OPN.ST.timer_handler = timer_handler;
3718 F2610->OPN.ST.IRQ_Handler = IRQHandler;
3719 F2610->OPN.ST.SSG = ssg;
3720 /* ADPCM */
3721 F2610->read_byte = adpcm_a_read_byte;
3722 /* DELTA-T */
3723 F2610->deltaT.read_byte = adpcm_b_read_byte;
3724 F2610->deltaT.write_byte = nullptr;
3725
3726 F2610->deltaT.status_set_handler = YM2610_deltat_status_set;
3727 F2610->deltaT.status_reset_handler = YM2610_deltat_status_reset;
3728 F2610->deltaT.status_change_which_chip = F2610;
3729 F2610->deltaT.status_change_EOS_bit = 0x80; /* status flag: set bit7 on End Of Sample */
3730
3731 Init_ADPCMATable();
3732
3733 for (unsigned i = 0; i < 6; i++)
3734 {
3735 F2610->CH[i].pan_volume_l = 46340;
3736 F2610->CH[i].pan_volume_r = 46340;
3737 }
3738
3739 #ifdef MAME_EMU_SAVE_H
3740 YM2610_save_state(F2610, device);
3741 #endif
3742 return F2610;
3743 }
3744
ym2610_clock_changed(void * chip,int clock,int rate)3745 void ym2610_clock_changed(void *chip, int clock, int rate)
3746 {
3747 ym2610_state *F2610 = (ym2610_state *)chip;
3748
3749 F2610->OPN.ST.clock = clock;
3750 F2610->OPN.ST.rate = rate;
3751 }
3752
3753 /* shut down emulator */
ym2610_shutdown(void * chip)3754 void ym2610_shutdown(void *chip)
3755 {
3756 ym2610_state *F2610 = (ym2610_state *)chip;
3757
3758 FMCloseTable();
3759 delete F2610;
3760 }
3761
3762 /* reset one of chip */
ym2610_reset_chip(void * chip)3763 void ym2610_reset_chip(void *chip)
3764 {
3765 int i;
3766 ym2610_state *F2610 = (ym2610_state *)chip;
3767 FM_OPN *OPN = &F2610->OPN;
3768 YM_DELTAT *DELTAT = &F2610->deltaT;
3769
3770 device_t* dev = F2610->OPN.ST.device;
3771 std::string name(dev->tag());
3772
3773 /* Reset Prescaler */
3774 OPNSetPres( OPN, 6*24, 6*24, 4*2); /* OPN 1/6 , SSG 1/4 */
3775 /* reset SSG section */
3776 (*OPN->ST.SSG->reset)(OPN->ST.device);
3777 /* status clear */
3778 FM_IRQMASK_SET(&OPN->ST,0x03);
3779 FM_BUSY_CLEAR(&OPN->ST);
3780 OPNWriteMode(OPN,0x27,0x30); /* mode 0 , timer reset */
3781
3782 OPN->eg_timer = 0;
3783 OPN->eg_cnt = 0;
3784
3785 FM_STATUS_RESET(&OPN->ST, 0xff);
3786
3787 reset_channels( &OPN->ST , F2610->CH , 6 );
3788 /* reset OPerator paramater */
3789 for(i = 0xb6 ; i >= 0xb4 ; i-- )
3790 {
3791 OPNWriteReg(OPN,i ,0xc0);
3792 OPNWriteReg(OPN,i|0x100,0xc0);
3793 }
3794 for(i = 0xb2 ; i >= 0x30 ; i-- )
3795 {
3796 OPNWriteReg(OPN,i ,0);
3797 OPNWriteReg(OPN,i|0x100,0);
3798 }
3799 for(i = 0x26 ; i >= 0x20 ; i-- ) OPNWriteReg(OPN,i,0);
3800 /**** ADPCM work initial ****/
3801 for( i = 0; i < 6 ; i++ )
3802 {
3803 F2610->adpcm[i].step = (uint32_t)((float)(1<<ADPCM_SHIFT)*((float)F2610->OPN.ST.freqbase)/3.0f);
3804 F2610->adpcm[i].now_addr = 0;
3805 F2610->adpcm[i].now_step = 0;
3806 F2610->adpcm[i].start = 0;
3807 F2610->adpcm[i].end = 0;
3808 /* F2610->adpcm[i].delta = 21866; */
3809 F2610->adpcm[i].vol_mul = 0;
3810 F2610->adpcm[i].pan = &OPN->out_adpcm[OUTD_CENTER]; /* default center */
3811 F2610->adpcm[i].flagMask = 1<<i;
3812 F2610->adpcm[i].flag = 0;
3813 F2610->adpcm[i].adpcm_acc = 0;
3814 F2610->adpcm[i].adpcm_step= 0;
3815 F2610->adpcm[i].adpcm_out = 0;
3816 }
3817 F2610->adpcmTL = 0x3f;
3818
3819 F2610->adpcm_arrivedEndAddress = 0;
3820
3821 /* DELTA-T unit */
3822 DELTAT->freqbase = OPN->ST.freqbase;
3823 DELTAT->output_pointer = OPN->out_delta;
3824 DELTAT->portshift = 8; /* allways 8bits shift */
3825 DELTAT->output_range = 1<<23;
3826 DELTAT->ADPCM_Reset(OUTD_CENTER,YM_DELTAT::EMULATION_MODE_YM2610,F2610->device);
3827 }
3828
3829 /* YM2610 write */
3830 /* n = number */
3831 /* a = address */
3832 /* v = value */
ym2610_write(void * chip,int a,uint8_t v)3833 int ym2610_write(void *chip, int a, uint8_t v)
3834 {
3835 ym2610_state *F2610 = (ym2610_state *)chip;
3836 FM_OPN *OPN = &F2610->OPN;
3837 int addr;
3838 int ch;
3839
3840 v &= 0xff; /* adjust to 8 bit bus */
3841
3842 switch( a&3 )
3843 {
3844 case 0: /* address port 0 */
3845 OPN->ST.address = v;
3846 F2610->addr_A1 = 0;
3847
3848 /* Write register to SSG emulator */
3849 if( v < 16 ) (*OPN->ST.SSG->write)(OPN->ST.device,0,v);
3850 break;
3851
3852 case 1: /* data port 0 */
3853 if (F2610->addr_A1 != 0)
3854 break; /* verified on real YM2608 */
3855
3856 addr = OPN->ST.address;
3857 F2610->REGS[addr] = v;
3858 switch(addr & 0xf0)
3859 {
3860 case 0x00: /* SSG section */
3861 /* Write data to SSG emulator */
3862 (*OPN->ST.SSG->write)(OPN->ST.device,a,v);
3863 break;
3864 case 0x10: /* DeltaT ADPCM */
3865 ym2610_device::update_request(OPN->ST.device);
3866
3867 switch(addr)
3868 {
3869 case 0x10: /* control 1 */
3870 case 0x11: /* control 2 */
3871 case 0x12: /* start address L */
3872 case 0x13: /* start address H */
3873 case 0x14: /* stop address L */
3874 case 0x15: /* stop address H */
3875
3876 case 0x19: /* delta-n L */
3877 case 0x1a: /* delta-n H */
3878 case 0x1b: /* volume */
3879 {
3880 F2610->deltaT.ADPCM_Write(addr-0x10,v);
3881 }
3882 break;
3883
3884 case 0x1c: /* FLAG CONTROL : Extend Status Clear/Mask */
3885 {
3886 uint8_t statusmask = ~v;
3887 /* set arrived flag mask */
3888 for(ch=0;ch<6;ch++)
3889 F2610->adpcm[ch].flagMask = statusmask&(1<<ch);
3890
3891 F2610->deltaT.status_change_EOS_bit = statusmask & 0x80; /* status flag: set bit7 on End Of Sample */
3892
3893 /* clear arrived flag */
3894 F2610->adpcm_arrivedEndAddress &= statusmask;
3895 }
3896 break;
3897
3898 default:
3899 F2610->device->logerror("YM2610: write to unknown deltat register %02x val=%02x\n",addr,v);
3900 break;
3901 }
3902
3903 break;
3904 case 0x20: /* Mode Register */
3905 ym2610_device::update_request(OPN->ST.device);
3906 OPNWriteMode(OPN,addr,v);
3907 break;
3908 default: /* OPN section */
3909 ym2610_device::update_request(OPN->ST.device);
3910 /* write register */
3911 OPNWriteReg(OPN,addr,v);
3912 }
3913 break;
3914
3915 case 2: /* address port 1 */
3916 OPN->ST.address = v;
3917 F2610->addr_A1 = 1;
3918 break;
3919
3920 case 3: /* data port 1 */
3921 if (F2610->addr_A1 != 1)
3922 break; /* verified on real YM2608 */
3923
3924 ym2610_device::update_request(OPN->ST.device);
3925 addr = OPN->ST.address;
3926 F2610->REGS[addr | 0x100] = v;
3927 if( addr < 0x30 )
3928 /* 100-12f : ADPCM A section */
3929 F2610->FM_ADPCMAWrite(addr,v);
3930 else
3931 OPNWriteReg(OPN,addr | 0x100,v);
3932 }
3933 return OPN->ST.irq;
3934 }
3935
ym2610_read(void * chip,int a)3936 uint8_t ym2610_read(void *chip,int a)
3937 {
3938 ym2610_state *F2610 = (ym2610_state *)chip;
3939 int addr = F2610->OPN.ST.address;
3940 uint8_t ret = 0;
3941
3942 switch( a&3)
3943 {
3944 case 0: /* status 0 : YM2203 compatible */
3945 ret = FM_STATUS_FLAG(&F2610->OPN.ST) & 0x83;
3946 break;
3947 case 1: /* data 0 */
3948 if( addr < 16 ) ret = (*F2610->OPN.ST.SSG->read)(F2610->OPN.ST.device);
3949 if( addr == 0xff ) ret = 0x01;
3950 break;
3951 case 2: /* status 1 : ADPCM status */
3952 /* ADPCM STATUS (arrived End Address) */
3953 /* B,--,A5,A4,A3,A2,A1,A0 */
3954 /* B = ADPCM-B(DELTA-T) arrived end address */
3955 /* A0-A5 = ADPCM-A arrived end address */
3956 ret = F2610->adpcm_arrivedEndAddress;
3957 break;
3958 case 3:
3959 ret = 0;
3960 break;
3961 }
3962 return ret;
3963 }
3964
ym2610_timer_over(void * chip,int c)3965 int ym2610_timer_over(void *chip,int c)
3966 {
3967 ym2610_state *F2610 = (ym2610_state *)chip;
3968
3969 if( c )
3970 { /* Timer B */
3971 TimerBOver( &(F2610->OPN.ST) );
3972 }
3973 else
3974 { /* Timer A */
3975 ym2610_device::update_request(F2610->OPN.ST.device);
3976 /* timer update */
3977 TimerAOver( &(F2610->OPN.ST) );
3978 /* CSM mode key,TL controll */
3979 if( F2610->OPN.ST.mode & 0x80 )
3980 { /* CSM mode total level latch and auto key on */
3981 CSMKeyControll( F2610->OPN.type, &(F2610->CH[2]) );
3982 }
3983 }
3984 return F2610->OPN.ST.irq;
3985 }
3986
3987 #endif /* (BUILD_YM2610||BUILD_YM2610B) */
3988