1 /*
2 ** MIPS instruction emitter.
3 ** Copyright (C) 2005-2017 Mike Pall. See Copyright Notice in luajit.h
4 */
5
6 #if LJ_64
get_k64val(IRIns * ir)7 static intptr_t get_k64val(IRIns *ir)
8 {
9 if (ir->o == IR_KINT64) {
10 return (intptr_t)ir_kint64(ir)->u64;
11 } else if (ir->o == IR_KGC) {
12 return (intptr_t)ir_kgc(ir);
13 } else if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
14 return (intptr_t)ir_kptr(ir);
15 } else {
16 lua_assert(ir->o == IR_KINT || ir->o == IR_KNULL);
17 return ir->i; /* Sign-extended. */
18 }
19 }
20 #endif
21
22 #if LJ_64
23 #define get_kval(ir) get_k64val(ir)
24 #else
25 #define get_kval(ir) ((ir)->i)
26 #endif
27
28 /* -- Emit basic instructions --------------------------------------------- */
29
emit_dst(ASMState * as,MIPSIns mi,Reg rd,Reg rs,Reg rt)30 static void emit_dst(ASMState *as, MIPSIns mi, Reg rd, Reg rs, Reg rt)
31 {
32 *--as->mcp = mi | MIPSF_D(rd) | MIPSF_S(rs) | MIPSF_T(rt);
33 }
34
emit_dta(ASMState * as,MIPSIns mi,Reg rd,Reg rt,uint32_t a)35 static void emit_dta(ASMState *as, MIPSIns mi, Reg rd, Reg rt, uint32_t a)
36 {
37 *--as->mcp = mi | MIPSF_D(rd) | MIPSF_T(rt) | MIPSF_A(a);
38 }
39
40 #define emit_ds(as, mi, rd, rs) emit_dst(as, (mi), (rd), (rs), 0)
41 #define emit_tg(as, mi, rt, rg) emit_dst(as, (mi), (rg)&31, 0, (rt))
42
emit_tsi(ASMState * as,MIPSIns mi,Reg rt,Reg rs,int32_t i)43 static void emit_tsi(ASMState *as, MIPSIns mi, Reg rt, Reg rs, int32_t i)
44 {
45 *--as->mcp = mi | MIPSF_T(rt) | MIPSF_S(rs) | (i & 0xffff);
46 }
47
48 #define emit_ti(as, mi, rt, i) emit_tsi(as, (mi), (rt), 0, (i))
49 #define emit_hsi(as, mi, rh, rs, i) emit_tsi(as, (mi), (rh) & 31, (rs), (i))
50
emit_fgh(ASMState * as,MIPSIns mi,Reg rf,Reg rg,Reg rh)51 static void emit_fgh(ASMState *as, MIPSIns mi, Reg rf, Reg rg, Reg rh)
52 {
53 *--as->mcp = mi | MIPSF_F(rf&31) | MIPSF_G(rg&31) | MIPSF_H(rh&31);
54 }
55
56 #define emit_fg(as, mi, rf, rg) emit_fgh(as, (mi), (rf), (rg), 0)
57
emit_rotr(ASMState * as,Reg dest,Reg src,Reg tmp,uint32_t shift)58 static void emit_rotr(ASMState *as, Reg dest, Reg src, Reg tmp, uint32_t shift)
59 {
60 if (LJ_64 || (as->flags & JIT_F_MIPSXXR2)) {
61 emit_dta(as, MIPSI_ROTR, dest, src, shift);
62 } else {
63 emit_dst(as, MIPSI_OR, dest, dest, tmp);
64 emit_dta(as, MIPSI_SLL, dest, src, (-shift)&31);
65 emit_dta(as, MIPSI_SRL, tmp, src, shift);
66 }
67 }
68
69 #if LJ_64
emit_tsml(ASMState * as,MIPSIns mi,Reg rt,Reg rs,uint32_t msb,uint32_t lsb)70 static void emit_tsml(ASMState *as, MIPSIns mi, Reg rt, Reg rs, uint32_t msb,
71 uint32_t lsb)
72 {
73 *--as->mcp = mi | MIPSF_T(rt) | MIPSF_S(rs) | MIPSF_M(msb) | MIPSF_L(lsb);
74 }
75 #endif
76
77 /* -- Emit loads/stores --------------------------------------------------- */
78
79 /* Prefer rematerialization of BASE/L from global_State over spills. */
80 #define emit_canremat(ref) ((ref) <= REF_BASE)
81
82 /* Try to find a one step delta relative to another constant. */
emit_kdelta1(ASMState * as,Reg t,intptr_t i)83 static int emit_kdelta1(ASMState *as, Reg t, intptr_t i)
84 {
85 RegSet work = ~as->freeset & RSET_GPR;
86 while (work) {
87 Reg r = rset_picktop(work);
88 IRRef ref = regcost_ref(as->cost[r]);
89 lua_assert(r != t);
90 if (ref < ASMREF_L) {
91 intptr_t delta = (intptr_t)((uintptr_t)i -
92 (uintptr_t)(ra_iskref(ref) ? ra_krefk(as, ref) : get_kval(IR(ref))));
93 if (checki16(delta)) {
94 emit_tsi(as, MIPSI_AADDIU, t, r, delta);
95 return 1;
96 }
97 }
98 rset_clear(work, r);
99 }
100 return 0; /* Failed. */
101 }
102
103 /* Load a 32 bit constant into a GPR. */
emit_loadi(ASMState * as,Reg r,int32_t i)104 static void emit_loadi(ASMState *as, Reg r, int32_t i)
105 {
106 if (checki16(i)) {
107 emit_ti(as, MIPSI_LI, r, i);
108 } else {
109 if ((i & 0xffff)) {
110 intptr_t jgl = (intptr_t)(void *)J2G(as->J);
111 if ((uintptr_t)(i-jgl) < 65536) {
112 emit_tsi(as, MIPSI_ADDIU, r, RID_JGL, i-jgl-32768);
113 return;
114 } else if (emit_kdelta1(as, r, i)) {
115 return;
116 } else if ((i >> 16) == 0) {
117 emit_tsi(as, MIPSI_ORI, r, RID_ZERO, i);
118 return;
119 }
120 emit_tsi(as, MIPSI_ORI, r, r, i);
121 }
122 emit_ti(as, MIPSI_LUI, r, (i >> 16));
123 }
124 }
125
126 #if LJ_64
127 /* Load a 64 bit constant into a GPR. */
emit_loadu64(ASMState * as,Reg r,uint64_t u64)128 static void emit_loadu64(ASMState *as, Reg r, uint64_t u64)
129 {
130 if (checki32((int64_t)u64)) {
131 emit_loadi(as, r, (int32_t)u64);
132 } else {
133 uint64_t delta = u64 - (uint64_t)(void *)J2G(as->J);
134 if (delta < 65536) {
135 emit_tsi(as, MIPSI_DADDIU, r, RID_JGL, (int32_t)(delta-32768));
136 } else if (emit_kdelta1(as, r, (intptr_t)u64)) {
137 return;
138 } else {
139 if ((u64 & 0xffff)) {
140 emit_tsi(as, MIPSI_ORI, r, r, u64 & 0xffff);
141 }
142 if (((u64 >> 16) & 0xffff)) {
143 emit_dta(as, MIPSI_DSLL, r, r, 16);
144 emit_tsi(as, MIPSI_ORI, r, r, (u64 >> 16) & 0xffff);
145 emit_dta(as, MIPSI_DSLL, r, r, 16);
146 } else {
147 emit_dta(as, MIPSI_DSLL32, r, r, 0);
148 }
149 emit_loadi(as, r, (int32_t)(u64 >> 32));
150 }
151 /* TODO: There are probably more optimization opportunities. */
152 }
153 }
154
155 #define emit_loada(as, r, addr) emit_loadu64(as, (r), u64ptr((addr)))
156 #else
157 #define emit_loada(as, r, addr) emit_loadi(as, (r), i32ptr((addr)))
158 #endif
159
160 static Reg ra_allock(ASMState *as, intptr_t k, RegSet allow);
161 static void ra_allockreg(ASMState *as, intptr_t k, Reg r);
162
163 /* Get/set from constant pointer. */
emit_lsptr(ASMState * as,MIPSIns mi,Reg r,void * p,RegSet allow)164 static void emit_lsptr(ASMState *as, MIPSIns mi, Reg r, void *p, RegSet allow)
165 {
166 intptr_t jgl = (intptr_t)(J2G(as->J));
167 intptr_t i = (intptr_t)(p);
168 Reg base;
169 if ((uint32_t)(i-jgl) < 65536) {
170 i = i-jgl-32768;
171 base = RID_JGL;
172 } else {
173 base = ra_allock(as, i-(int16_t)i, allow);
174 }
175 emit_tsi(as, mi, r, base, i);
176 }
177
178 #if LJ_64
emit_loadk64(ASMState * as,Reg r,IRIns * ir)179 static void emit_loadk64(ASMState *as, Reg r, IRIns *ir)
180 {
181 const uint64_t *k = &ir_k64(ir)->u64;
182 Reg r64 = r;
183 if (rset_test(RSET_FPR, r)) {
184 r64 = RID_TMP;
185 emit_tg(as, MIPSI_DMTC1, r64, r);
186 }
187 if ((uint32_t)((intptr_t)k-(intptr_t)J2G(as->J)) < 65536)
188 emit_lsptr(as, MIPSI_LD, r64, (void *)k, 0);
189 else
190 emit_loadu64(as, r64, *k);
191 }
192 #else
193 #define emit_loadk64(as, r, ir) \
194 emit_lsptr(as, MIPSI_LDC1, ((r) & 31), (void *)&ir_knum((ir))->u64, RSET_GPR)
195 #endif
196
197 /* Get/set global_State fields. */
emit_lsglptr(ASMState * as,MIPSIns mi,Reg r,int32_t ofs)198 static void emit_lsglptr(ASMState *as, MIPSIns mi, Reg r, int32_t ofs)
199 {
200 emit_tsi(as, mi, r, RID_JGL, ofs-32768);
201 }
202
203 #define emit_getgl(as, r, field) \
204 emit_lsglptr(as, MIPSI_AL, (r), (int32_t)offsetof(global_State, field))
205 #define emit_setgl(as, r, field) \
206 emit_lsglptr(as, MIPSI_AS, (r), (int32_t)offsetof(global_State, field))
207
208 /* Trace number is determined from per-trace exit stubs. */
209 #define emit_setvmstate(as, i) UNUSED(i)
210
211 /* -- Emit control-flow instructions -------------------------------------- */
212
213 /* Label for internal jumps. */
214 typedef MCode *MCLabel;
215
216 /* Return label pointing to current PC. */
217 #define emit_label(as) ((as)->mcp)
218
emit_branch(ASMState * as,MIPSIns mi,Reg rs,Reg rt,MCode * target)219 static void emit_branch(ASMState *as, MIPSIns mi, Reg rs, Reg rt, MCode *target)
220 {
221 MCode *p = as->mcp;
222 ptrdiff_t delta = target - p;
223 lua_assert(((delta + 0x8000) >> 16) == 0);
224 *--p = mi | MIPSF_S(rs) | MIPSF_T(rt) | ((uint32_t)delta & 0xffffu);
225 as->mcp = p;
226 }
227
emit_jmp(ASMState * as,MCode * target)228 static void emit_jmp(ASMState *as, MCode *target)
229 {
230 *--as->mcp = MIPSI_NOP;
231 emit_branch(as, MIPSI_B, RID_ZERO, RID_ZERO, (target));
232 }
233
emit_call(ASMState * as,void * target,int needcfa)234 static void emit_call(ASMState *as, void *target, int needcfa)
235 {
236 MCode *p = as->mcp;
237 *--p = MIPSI_NOP;
238 if ((((uintptr_t)target ^ (uintptr_t)p) >> 28) == 0) {
239 *--p = (((uintptr_t)target & 1) ? MIPSI_JALX : MIPSI_JAL) |
240 (((uintptr_t)target >>2) & 0x03ffffffu);
241 } else { /* Target out of range: need indirect call. */
242 *--p = MIPSI_JALR | MIPSF_S(RID_CFUNCADDR);
243 needcfa = 1;
244 }
245 as->mcp = p;
246 if (needcfa) ra_allockreg(as, (intptr_t)target, RID_CFUNCADDR);
247 }
248
249 /* -- Emit generic operations --------------------------------------------- */
250
251 #define emit_move(as, dst, src) \
252 emit_ds(as, MIPSI_MOVE, (dst), (src))
253
254 /* Generic move between two regs. */
emit_movrr(ASMState * as,IRIns * ir,Reg dst,Reg src)255 static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
256 {
257 if (dst < RID_MAX_GPR)
258 emit_move(as, dst, src);
259 else
260 emit_fg(as, irt_isnum(ir->t) ? MIPSI_MOV_D : MIPSI_MOV_S, dst, src);
261 }
262
263 /* Generic load of register with base and (small) offset address. */
emit_loadofs(ASMState * as,IRIns * ir,Reg r,Reg base,int32_t ofs)264 static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
265 {
266 if (r < RID_MAX_GPR)
267 emit_tsi(as, irt_is64(ir->t) ? MIPSI_LD : MIPSI_LW, r, base, ofs);
268 else
269 emit_tsi(as, irt_isnum(ir->t) ? MIPSI_LDC1 : MIPSI_LWC1,
270 (r & 31), base, ofs);
271 }
272
273 /* Generic store of register with base and (small) offset address. */
emit_storeofs(ASMState * as,IRIns * ir,Reg r,Reg base,int32_t ofs)274 static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
275 {
276 if (r < RID_MAX_GPR)
277 emit_tsi(as, irt_is64(ir->t) ? MIPSI_SD : MIPSI_SW, r, base, ofs);
278 else
279 emit_tsi(as, irt_isnum(ir->t) ? MIPSI_SDC1 : MIPSI_SWC1,
280 (r&31), base, ofs);
281 }
282
283 /* Add offset to pointer. */
emit_addptr(ASMState * as,Reg r,int32_t ofs)284 static void emit_addptr(ASMState *as, Reg r, int32_t ofs)
285 {
286 if (ofs) {
287 lua_assert(checki16(ofs));
288 emit_tsi(as, MIPSI_AADDIU, r, r, ofs);
289 }
290 }
291
292 #define emit_spsub(as, ofs) emit_addptr(as, RID_SP, -(ofs))
293
294