1 2---------------------------------------------------------------- 3-- 4-- Created by the Synopsys Library Compiler 1999.10 5-- FILENAME : sxlib_UDSM.vhd 6-- FILE CONTENTS: Entity, Structural Architecture(UDSM), 7-- and Configuration 8-- DATE CREATED : Mon May 7 10:19:50 2001 9-- 10-- LIBRARY : sxlib 11-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 12-- REVISION : 1.200000 13-- TECHNOLOGY : cmos 14-- TIME SCALE : 1 ns 15-- LOGIC SYSTEM : IEEE-1164 16-- NOTES : UDSM 17-- HISTORY : 18-- 19---------------------------------------------------------------- 20 21----- CELL a2_x2 ----- 22library IEEE; 23use IEEE.STD_LOGIC_1164.all; 24library SYNOPSYS; 25use SYNOPSYS.attributes.REAL_NAME; 26 27-- entity declaration -- 28entity a2_x2 is 29 generic( 30 Timing_mesg: Boolean := True; 31 Timing_xgen: Boolean := False; 32 tpdi0_q_R : Time := 0.261 ns; 33 tpdi0_q_F : Time := 0.388 ns; 34 tpdi1_q_R : Time := 0.203 ns; 35 tpdi1_q_F : Time := 0.434 ns; 36 twdi0_R : Time := 0.000 ns; 37 twdi0_F : Time := 0.000 ns; 38 twdi1_R : Time := 0.000 ns; 39 twdi1_F : Time := 0.000 ns); 40 41 port( 42 i0 : in STD_LOGIC; 43 i1 : in STD_LOGIC; 44 q : out STD_LOGIC); 45end a2_x2; 46 47-- architecture body -- 48library IEEE_ASIC; 49use IEEE.STD_LOGIC_MISC.all; 50use SYNOPSYS.attributes.backplane; 51use SYNOPSYS.attributes.PRIVATE; 52use SYNOPSYS.attributes.ASIC_CELL; 53 54architecture UDSM of a2_x2 is 55 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 56 attribute PRIVATE of UDSM : architecture is TRUE; 57 attribute ASIC_CELL of UDSM : architecture is TRUE; 58 59 component AND2MAC 60 generic( 61 tpdY_R : Time := 0 ns; 62 tpdY_F : Time := 0 ns; 63 strn : STRENGTH := strn_X01); 64 port( 65 I0 : in STD_LOGIC; 66 I1 : in STD_LOGIC; 67 Y : out STD_LOGIC); 68 end component; 69 70begin 71 72 -- Netlist 73 U1 : AND2MAC 74 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 75 port map( I0 => i0, I1 => i1, Y => q); 76 77 78end UDSM; 79 80configuration CFG_a2_x2_UDSM of a2_x2 is 81 for UDSM 82 end for; 83end CFG_a2_x2_UDSM; 84 85 86----- CELL a2_x4 ----- 87library IEEE; 88use IEEE.STD_LOGIC_1164.all; 89library SYNOPSYS; 90use SYNOPSYS.attributes.REAL_NAME; 91 92-- entity declaration -- 93entity a2_x4 is 94 generic( 95 Timing_mesg: Boolean := True; 96 Timing_xgen: Boolean := False; 97 tpdi0_q_R : Time := 0.338 ns; 98 tpdi0_q_F : Time := 0.476 ns; 99 tpdi1_q_R : Time := 0.269 ns; 100 tpdi1_q_F : Time := 0.518 ns; 101 twdi0_R : Time := 0.000 ns; 102 twdi0_F : Time := 0.000 ns; 103 twdi1_R : Time := 0.000 ns; 104 twdi1_F : Time := 0.000 ns); 105 106 port( 107 i0 : in STD_LOGIC; 108 i1 : in STD_LOGIC; 109 q : out STD_LOGIC); 110end a2_x4; 111 112-- architecture body -- 113library IEEE_ASIC; 114use IEEE.STD_LOGIC_MISC.all; 115use SYNOPSYS.attributes.backplane; 116use SYNOPSYS.attributes.PRIVATE; 117use SYNOPSYS.attributes.ASIC_CELL; 118 119architecture UDSM of a2_x4 is 120 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 121 attribute PRIVATE of UDSM : architecture is TRUE; 122 attribute ASIC_CELL of UDSM : architecture is TRUE; 123 124 component AND2MAC 125 generic( 126 tpdY_R : Time := 0 ns; 127 tpdY_F : Time := 0 ns; 128 strn : STRENGTH := strn_X01); 129 port( 130 I0 : in STD_LOGIC; 131 I1 : in STD_LOGIC; 132 Y : out STD_LOGIC); 133 end component; 134 135begin 136 137 -- Netlist 138 U1 : AND2MAC 139 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 140 port map( I0 => i0, I1 => i1, Y => q); 141 142 143end UDSM; 144 145configuration CFG_a2_x4_UDSM of a2_x4 is 146 for UDSM 147 end for; 148end CFG_a2_x4_UDSM; 149 150 151----- CELL a3_x2 ----- 152library IEEE; 153use IEEE.STD_LOGIC_1164.all; 154library SYNOPSYS; 155use SYNOPSYS.attributes.REAL_NAME; 156 157-- entity declaration -- 158entity a3_x2 is 159 generic( 160 Timing_mesg: Boolean := True; 161 Timing_xgen: Boolean := False; 162 tpdi0_q_R : Time := 0.395 ns; 163 tpdi0_q_F : Time := 0.435 ns; 164 tpdi1_q_R : Time := 0.353 ns; 165 tpdi1_q_F : Time := 0.479 ns; 166 tpdi2_q_R : Time := 0.290 ns; 167 tpdi2_q_F : Time := 0.521 ns; 168 twdi0_R : Time := 0.000 ns; 169 twdi0_F : Time := 0.000 ns; 170 twdi1_R : Time := 0.000 ns; 171 twdi1_F : Time := 0.000 ns; 172 twdi2_R : Time := 0.000 ns; 173 twdi2_F : Time := 0.000 ns); 174 175 port( 176 i0 : in STD_LOGIC; 177 i1 : in STD_LOGIC; 178 i2 : in STD_LOGIC; 179 q : out STD_LOGIC); 180end a3_x2; 181 182-- architecture body -- 183library IEEE_ASIC; 184use IEEE.STD_LOGIC_MISC.all; 185use SYNOPSYS.attributes.backplane; 186use SYNOPSYS.attributes.PRIVATE; 187use SYNOPSYS.attributes.ASIC_CELL; 188 189architecture UDSM of a3_x2 is 190 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 191 attribute PRIVATE of UDSM : architecture is TRUE; 192 attribute ASIC_CELL of UDSM : architecture is TRUE; 193 194 component AND3MAC 195 generic( 196 tpdY_R : Time := 0 ns; 197 tpdY_F : Time := 0 ns; 198 strn : STRENGTH := strn_X01); 199 port( 200 I0 : in STD_LOGIC; 201 I1 : in STD_LOGIC; 202 I2 : in STD_LOGIC; 203 Y : out STD_LOGIC); 204 end component; 205 206begin 207 208 -- Netlist 209 U1 : AND3MAC 210 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 211 port map( I0 => i1, I1 => i2, I2 => i0, Y => q); 212 213 214end UDSM; 215 216configuration CFG_a3_x2_UDSM of a3_x2 is 217 for UDSM 218 end for; 219end CFG_a3_x2_UDSM; 220 221 222----- CELL a3_x4 ----- 223library IEEE; 224use IEEE.STD_LOGIC_1164.all; 225library SYNOPSYS; 226use SYNOPSYS.attributes.REAL_NAME; 227 228-- entity declaration -- 229entity a3_x4 is 230 generic( 231 Timing_mesg: Boolean := True; 232 Timing_xgen: Boolean := False; 233 tpdi0_q_R : Time := 0.478 ns; 234 tpdi0_q_F : Time := 0.514 ns; 235 tpdi1_q_R : Time := 0.428 ns; 236 tpdi1_q_F : Time := 0.554 ns; 237 tpdi2_q_R : Time := 0.356 ns; 238 tpdi2_q_F : Time := 0.592 ns; 239 twdi0_R : Time := 0.000 ns; 240 twdi0_F : Time := 0.000 ns; 241 twdi1_R : Time := 0.000 ns; 242 twdi1_F : Time := 0.000 ns; 243 twdi2_R : Time := 0.000 ns; 244 twdi2_F : Time := 0.000 ns); 245 246 port( 247 i0 : in STD_LOGIC; 248 i1 : in STD_LOGIC; 249 i2 : in STD_LOGIC; 250 q : out STD_LOGIC); 251end a3_x4; 252 253-- architecture body -- 254library IEEE_ASIC; 255use IEEE.STD_LOGIC_MISC.all; 256use SYNOPSYS.attributes.backplane; 257use SYNOPSYS.attributes.PRIVATE; 258use SYNOPSYS.attributes.ASIC_CELL; 259 260architecture UDSM of a3_x4 is 261 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 262 attribute PRIVATE of UDSM : architecture is TRUE; 263 attribute ASIC_CELL of UDSM : architecture is TRUE; 264 265 component AND3MAC 266 generic( 267 tpdY_R : Time := 0 ns; 268 tpdY_F : Time := 0 ns; 269 strn : STRENGTH := strn_X01); 270 port( 271 I0 : in STD_LOGIC; 272 I1 : in STD_LOGIC; 273 I2 : in STD_LOGIC; 274 Y : out STD_LOGIC); 275 end component; 276 277begin 278 279 -- Netlist 280 U1 : AND3MAC 281 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 282 port map( I0 => i1, I1 => i2, I2 => i0, Y => q); 283 284 285end UDSM; 286 287configuration CFG_a3_x4_UDSM of a3_x4 is 288 for UDSM 289 end for; 290end CFG_a3_x4_UDSM; 291 292 293----- CELL a4_x2 ----- 294library IEEE; 295use IEEE.STD_LOGIC_1164.all; 296library SYNOPSYS; 297use SYNOPSYS.attributes.REAL_NAME; 298 299-- entity declaration -- 300entity a4_x2 is 301 generic( 302 Timing_mesg: Boolean := True; 303 Timing_xgen: Boolean := False; 304 tpdi0_q_R : Time := 0.374 ns; 305 tpdi0_q_F : Time := 0.578 ns; 306 tpdi1_q_R : Time := 0.441 ns; 307 tpdi1_q_F : Time := 0.539 ns; 308 tpdi2_q_R : Time := 0.482 ns; 309 tpdi2_q_F : Time := 0.498 ns; 310 tpdi3_q_R : Time := 0.506 ns; 311 tpdi3_q_F : Time := 0.455 ns; 312 twdi0_R : Time := 0.000 ns; 313 twdi0_F : Time := 0.000 ns; 314 twdi1_R : Time := 0.000 ns; 315 twdi1_F : Time := 0.000 ns; 316 twdi2_R : Time := 0.000 ns; 317 twdi2_F : Time := 0.000 ns; 318 twdi3_R : Time := 0.000 ns; 319 twdi3_F : Time := 0.000 ns); 320 321 port( 322 i0 : in STD_LOGIC; 323 i1 : in STD_LOGIC; 324 i2 : in STD_LOGIC; 325 i3 : in STD_LOGIC; 326 q : out STD_LOGIC); 327end a4_x2; 328 329-- architecture body -- 330library IEEE_ASIC; 331use IEEE.STD_LOGIC_MISC.all; 332use SYNOPSYS.attributes.backplane; 333use SYNOPSYS.attributes.PRIVATE; 334use SYNOPSYS.attributes.ASIC_CELL; 335 336architecture UDSM of a4_x2 is 337 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 338 attribute PRIVATE of UDSM : architecture is TRUE; 339 attribute ASIC_CELL of UDSM : architecture is TRUE; 340 341 component AND4MAC 342 generic( 343 tpdY_R : Time := 0 ns; 344 tpdY_F : Time := 0 ns; 345 strn : STRENGTH := strn_X01); 346 port( 347 I0 : in STD_LOGIC; 348 I1 : in STD_LOGIC; 349 I2 : in STD_LOGIC; 350 I3 : in STD_LOGIC; 351 Y : out STD_LOGIC); 352 end component; 353 354begin 355 356 -- Netlist 357 U1 : AND4MAC 358 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 359 port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q); 360 361 362end UDSM; 363 364configuration CFG_a4_x2_UDSM of a4_x2 is 365 for UDSM 366 end for; 367end CFG_a4_x2_UDSM; 368 369 370----- CELL a4_x4 ----- 371library IEEE; 372use IEEE.STD_LOGIC_1164.all; 373library SYNOPSYS; 374use SYNOPSYS.attributes.REAL_NAME; 375 376-- entity declaration -- 377entity a4_x4 is 378 generic( 379 Timing_mesg: Boolean := True; 380 Timing_xgen: Boolean := False; 381 tpdi0_q_R : Time := 0.505 ns; 382 tpdi0_q_F : Time := 0.650 ns; 383 tpdi1_q_R : Time := 0.578 ns; 384 tpdi1_q_F : Time := 0.614 ns; 385 tpdi2_q_R : Time := 0.627 ns; 386 tpdi2_q_F : Time := 0.576 ns; 387 tpdi3_q_R : Time := 0.661 ns; 388 tpdi3_q_F : Time := 0.538 ns; 389 twdi0_R : Time := 0.000 ns; 390 twdi0_F : Time := 0.000 ns; 391 twdi1_R : Time := 0.000 ns; 392 twdi1_F : Time := 0.000 ns; 393 twdi2_R : Time := 0.000 ns; 394 twdi2_F : Time := 0.000 ns; 395 twdi3_R : Time := 0.000 ns; 396 twdi3_F : Time := 0.000 ns); 397 398 port( 399 i0 : in STD_LOGIC; 400 i1 : in STD_LOGIC; 401 i2 : in STD_LOGIC; 402 i3 : in STD_LOGIC; 403 q : out STD_LOGIC); 404end a4_x4; 405 406-- architecture body -- 407library IEEE_ASIC; 408use IEEE.STD_LOGIC_MISC.all; 409use SYNOPSYS.attributes.backplane; 410use SYNOPSYS.attributes.PRIVATE; 411use SYNOPSYS.attributes.ASIC_CELL; 412 413architecture UDSM of a4_x4 is 414 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 415 attribute PRIVATE of UDSM : architecture is TRUE; 416 attribute ASIC_CELL of UDSM : architecture is TRUE; 417 418 component AND4MAC 419 generic( 420 tpdY_R : Time := 0 ns; 421 tpdY_F : Time := 0 ns; 422 strn : STRENGTH := strn_X01); 423 port( 424 I0 : in STD_LOGIC; 425 I1 : in STD_LOGIC; 426 I2 : in STD_LOGIC; 427 I3 : in STD_LOGIC; 428 Y : out STD_LOGIC); 429 end component; 430 431begin 432 433 -- Netlist 434 U1 : AND4MAC 435 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 436 port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q); 437 438 439end UDSM; 440 441configuration CFG_a4_x4_UDSM of a4_x4 is 442 for UDSM 443 end for; 444end CFG_a4_x4_UDSM; 445 446 447----- CELL an12_x1 ----- 448library IEEE; 449use IEEE.STD_LOGIC_1164.all; 450library SYNOPSYS; 451use SYNOPSYS.attributes.REAL_NAME; 452 453-- entity declaration -- 454entity an12_x1 is 455 generic( 456 Timing_mesg: Boolean := True; 457 Timing_xgen: Boolean := False; 458 tpdi0_q_R : Time := 0.200 ns; 459 tpdi0_q_F : Time := 0.168 ns; 460 tpdi1_q_R : Time := 0.285 ns; 461 tpdi1_q_F : Time := 0.405 ns; 462 twdi0_R : Time := 0.000 ns; 463 twdi0_F : Time := 0.000 ns; 464 twdi1_R : Time := 0.000 ns; 465 twdi1_F : Time := 0.000 ns); 466 467 port( 468 i0 : in STD_LOGIC; 469 i1 : in STD_LOGIC; 470 q : out STD_LOGIC); 471end an12_x1; 472 473-- architecture body -- 474library IEEE_ASIC; 475use IEEE.STD_LOGIC_MISC.all; 476use SYNOPSYS.attributes.backplane; 477use SYNOPSYS.attributes.PRIVATE; 478use SYNOPSYS.attributes.ASIC_CELL; 479 480architecture UDSM of an12_x1 is 481 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 482 attribute PRIVATE of UDSM : architecture is TRUE; 483 attribute ASIC_CELL of UDSM : architecture is TRUE; 484 485 signal n1 : STD_LOGIC; 486 487 component AND2MAC 488 generic( 489 tpdY_R : Time := 0 ns; 490 tpdY_F : Time := 0 ns; 491 strn : STRENGTH := strn_X01); 492 port( 493 I0 : in STD_LOGIC; 494 I1 : in STD_LOGIC; 495 Y : out STD_LOGIC); 496 end component; 497 498 component INVMAC 499 generic( 500 tpdY_R : Time := 0 ns; 501 tpdY_F : Time := 0 ns; 502 strn : STRENGTH := strn_X01); 503 port( 504 I0 : in STD_LOGIC; 505 Y : out STD_LOGIC); 506 end component; 507 508begin 509 510 -- Netlist 511 U1 : AND2MAC 512 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 513 port map( I0 => i1, I1 => n1, Y => q); 514 515 U2 : INVMAC 516 port map( I0 => i0, Y => n1); 517 518 519end UDSM; 520 521configuration CFG_an12_x1_UDSM of an12_x1 is 522 for UDSM 523 end for; 524end CFG_an12_x1_UDSM; 525 526 527----- CELL an12_x4 ----- 528library IEEE; 529use IEEE.STD_LOGIC_1164.all; 530library SYNOPSYS; 531use SYNOPSYS.attributes.REAL_NAME; 532 533-- entity declaration -- 534entity an12_x4 is 535 generic( 536 Timing_mesg: Boolean := True; 537 Timing_xgen: Boolean := False; 538 tpdi0_q_R : Time := 0.461 ns; 539 tpdi0_q_F : Time := 0.471 ns; 540 tpdi1_q_R : Time := 0.269 ns; 541 tpdi1_q_F : Time := 0.518 ns; 542 twdi0_R : Time := 0.000 ns; 543 twdi0_F : Time := 0.000 ns; 544 twdi1_R : Time := 0.000 ns; 545 twdi1_F : Time := 0.000 ns); 546 547 port( 548 i0 : in STD_LOGIC; 549 i1 : in STD_LOGIC; 550 q : out STD_LOGIC); 551end an12_x4; 552 553-- architecture body -- 554library IEEE_ASIC; 555use IEEE.STD_LOGIC_MISC.all; 556use SYNOPSYS.attributes.backplane; 557use SYNOPSYS.attributes.PRIVATE; 558use SYNOPSYS.attributes.ASIC_CELL; 559 560architecture UDSM of an12_x4 is 561 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 562 attribute PRIVATE of UDSM : architecture is TRUE; 563 attribute ASIC_CELL of UDSM : architecture is TRUE; 564 565 signal n1 : STD_LOGIC; 566 567 component AND2MAC 568 generic( 569 tpdY_R : Time := 0 ns; 570 tpdY_F : Time := 0 ns; 571 strn : STRENGTH := strn_X01); 572 port( 573 I0 : in STD_LOGIC; 574 I1 : in STD_LOGIC; 575 Y : out STD_LOGIC); 576 end component; 577 578 component INVMAC 579 generic( 580 tpdY_R : Time := 0 ns; 581 tpdY_F : Time := 0 ns; 582 strn : STRENGTH := strn_X01); 583 port( 584 I0 : in STD_LOGIC; 585 Y : out STD_LOGIC); 586 end component; 587 588begin 589 590 -- Netlist 591 U1 : AND2MAC 592 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 593 port map( I0 => i1, I1 => n1, Y => q); 594 595 U2 : INVMAC 596 port map( I0 => i0, Y => n1); 597 598 599end UDSM; 600 601configuration CFG_an12_x4_UDSM of an12_x4 is 602 for UDSM 603 end for; 604end CFG_an12_x4_UDSM; 605 606 607----- CELL ao2o22_x2 ----- 608library IEEE; 609use IEEE.STD_LOGIC_1164.all; 610library SYNOPSYS; 611use SYNOPSYS.attributes.REAL_NAME; 612 613-- entity declaration -- 614entity ao2o22_x2 is 615 generic( 616 Timing_mesg: Boolean := True; 617 Timing_xgen: Boolean := False; 618 tpdi0_q_R : Time := 0.572 ns; 619 tpdi0_q_F : Time := 0.451 ns; 620 tpdi1_q_R : Time := 0.508 ns; 621 tpdi1_q_F : Time := 0.542 ns; 622 tpdi2_q_R : Time := 0.432 ns; 623 tpdi2_q_F : Time := 0.627 ns; 624 tpdi3_q_R : Time := 0.488 ns; 625 tpdi3_q_F : Time := 0.526 ns; 626 twdi0_R : Time := 0.000 ns; 627 twdi0_F : Time := 0.000 ns; 628 twdi1_R : Time := 0.000 ns; 629 twdi1_F : Time := 0.000 ns; 630 twdi2_R : Time := 0.000 ns; 631 twdi2_F : Time := 0.000 ns; 632 twdi3_R : Time := 0.000 ns; 633 twdi3_F : Time := 0.000 ns); 634 635 port( 636 i0 : in STD_LOGIC; 637 i1 : in STD_LOGIC; 638 i2 : in STD_LOGIC; 639 i3 : in STD_LOGIC; 640 q : out STD_LOGIC); 641end ao2o22_x2; 642 643-- architecture body -- 644library IEEE_ASIC; 645use IEEE.STD_LOGIC_MISC.all; 646use SYNOPSYS.attributes.backplane; 647use SYNOPSYS.attributes.PRIVATE; 648use SYNOPSYS.attributes.ASIC_CELL; 649 650architecture UDSM of ao2o22_x2 is 651 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 652 attribute PRIVATE of UDSM : architecture is TRUE; 653 attribute ASIC_CELL of UDSM : architecture is TRUE; 654 655 signal n1, n2 : STD_LOGIC; 656 657 component AND2MAC 658 generic( 659 tpdY_R : Time := 0 ns; 660 tpdY_F : Time := 0 ns; 661 strn : STRENGTH := strn_X01); 662 port( 663 I0 : in STD_LOGIC; 664 I1 : in STD_LOGIC; 665 Y : out STD_LOGIC); 666 end component; 667 668 component OR2MAC 669 generic( 670 tpdY_R : Time := 0 ns; 671 tpdY_F : Time := 0 ns; 672 strn : STRENGTH := strn_X01); 673 port( 674 I0 : in STD_LOGIC; 675 I1 : in STD_LOGIC; 676 Y : out STD_LOGIC); 677 end component; 678 679begin 680 681 -- Netlist 682 U1 : AND2MAC 683 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 684 port map( I0 => n1, I1 => n2, Y => q); 685 686 U2 : OR2MAC 687 port map( I0 => i3, I1 => i2, Y => n2); 688 689 U3 : OR2MAC 690 port map( I0 => i1, I1 => i0, Y => n1); 691 692 693end UDSM; 694 695configuration CFG_ao2o22_x2_UDSM of ao2o22_x2 is 696 for UDSM 697 end for; 698end CFG_ao2o22_x2_UDSM; 699 700 701----- CELL ao2o22_x4 ----- 702library IEEE; 703use IEEE.STD_LOGIC_1164.all; 704library SYNOPSYS; 705use SYNOPSYS.attributes.REAL_NAME; 706 707-- entity declaration -- 708entity ao2o22_x4 is 709 generic( 710 Timing_mesg: Boolean := True; 711 Timing_xgen: Boolean := False; 712 tpdi0_q_R : Time := 0.696 ns; 713 tpdi0_q_F : Time := 0.569 ns; 714 tpdi1_q_R : Time := 0.637 ns; 715 tpdi1_q_F : Time := 0.666 ns; 716 tpdi2_q_R : Time := 0.554 ns; 717 tpdi2_q_F : Time := 0.744 ns; 718 tpdi3_q_R : Time := 0.606 ns; 719 tpdi3_q_F : Time := 0.639 ns; 720 twdi0_R : Time := 0.000 ns; 721 twdi0_F : Time := 0.000 ns; 722 twdi1_R : Time := 0.000 ns; 723 twdi1_F : Time := 0.000 ns; 724 twdi2_R : Time := 0.000 ns; 725 twdi2_F : Time := 0.000 ns; 726 twdi3_R : Time := 0.000 ns; 727 twdi3_F : Time := 0.000 ns); 728 729 port( 730 i0 : in STD_LOGIC; 731 i1 : in STD_LOGIC; 732 i2 : in STD_LOGIC; 733 i3 : in STD_LOGIC; 734 q : out STD_LOGIC); 735end ao2o22_x4; 736 737-- architecture body -- 738library IEEE_ASIC; 739use IEEE.STD_LOGIC_MISC.all; 740use SYNOPSYS.attributes.backplane; 741use SYNOPSYS.attributes.PRIVATE; 742use SYNOPSYS.attributes.ASIC_CELL; 743 744architecture UDSM of ao2o22_x4 is 745 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 746 attribute PRIVATE of UDSM : architecture is TRUE; 747 attribute ASIC_CELL of UDSM : architecture is TRUE; 748 749 signal n1, n2 : STD_LOGIC; 750 751 component AND2MAC 752 generic( 753 tpdY_R : Time := 0 ns; 754 tpdY_F : Time := 0 ns; 755 strn : STRENGTH := strn_X01); 756 port( 757 I0 : in STD_LOGIC; 758 I1 : in STD_LOGIC; 759 Y : out STD_LOGIC); 760 end component; 761 762 component OR2MAC 763 generic( 764 tpdY_R : Time := 0 ns; 765 tpdY_F : Time := 0 ns; 766 strn : STRENGTH := strn_X01); 767 port( 768 I0 : in STD_LOGIC; 769 I1 : in STD_LOGIC; 770 Y : out STD_LOGIC); 771 end component; 772 773begin 774 775 -- Netlist 776 U1 : AND2MAC 777 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 778 port map( I0 => n1, I1 => n2, Y => q); 779 780 U2 : OR2MAC 781 port map( I0 => i3, I1 => i2, Y => n2); 782 783 U3 : OR2MAC 784 port map( I0 => i1, I1 => i0, Y => n1); 785 786 787end UDSM; 788 789configuration CFG_ao2o22_x4_UDSM of ao2o22_x4 is 790 for UDSM 791 end for; 792end CFG_ao2o22_x4_UDSM; 793 794 795----- CELL ao22_x2 ----- 796library IEEE; 797use IEEE.STD_LOGIC_1164.all; 798library SYNOPSYS; 799use SYNOPSYS.attributes.REAL_NAME; 800 801-- entity declaration -- 802entity ao22_x2 is 803 generic( 804 Timing_mesg: Boolean := True; 805 Timing_xgen: Boolean := False; 806 tpdi0_q_R : Time := 0.558 ns; 807 tpdi0_q_F : Time := 0.447 ns; 808 tpdi1_q_R : Time := 0.493 ns; 809 tpdi1_q_F : Time := 0.526 ns; 810 tpdi2_q_R : Time := 0.420 ns; 811 tpdi2_q_F : Time := 0.425 ns; 812 twdi0_R : Time := 0.000 ns; 813 twdi0_F : Time := 0.000 ns; 814 twdi1_R : Time := 0.000 ns; 815 twdi1_F : Time := 0.000 ns; 816 twdi2_R : Time := 0.000 ns; 817 twdi2_F : Time := 0.000 ns); 818 819 port( 820 i0 : in STD_LOGIC; 821 i1 : in STD_LOGIC; 822 i2 : in STD_LOGIC; 823 q : out STD_LOGIC); 824end ao22_x2; 825 826-- architecture body -- 827library IEEE_ASIC; 828use IEEE.STD_LOGIC_MISC.all; 829use SYNOPSYS.attributes.backplane; 830use SYNOPSYS.attributes.PRIVATE; 831use SYNOPSYS.attributes.ASIC_CELL; 832 833architecture UDSM of ao22_x2 is 834 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 835 attribute PRIVATE of UDSM : architecture is TRUE; 836 attribute ASIC_CELL of UDSM : architecture is TRUE; 837 838 signal n1 : STD_LOGIC; 839 840 component AND2MAC 841 generic( 842 tpdY_R : Time := 0 ns; 843 tpdY_F : Time := 0 ns; 844 strn : STRENGTH := strn_X01); 845 port( 846 I0 : in STD_LOGIC; 847 I1 : in STD_LOGIC; 848 Y : out STD_LOGIC); 849 end component; 850 851 component OR2MAC 852 generic( 853 tpdY_R : Time := 0 ns; 854 tpdY_F : Time := 0 ns; 855 strn : STRENGTH := strn_X01); 856 port( 857 I0 : in STD_LOGIC; 858 I1 : in STD_LOGIC; 859 Y : out STD_LOGIC); 860 end component; 861 862begin 863 864 -- Netlist 865 U1 : AND2MAC 866 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 867 port map( I0 => i2, I1 => n1, Y => q); 868 869 U2 : OR2MAC 870 port map( I0 => i1, I1 => i0, Y => n1); 871 872 873end UDSM; 874 875configuration CFG_ao22_x2_UDSM of ao22_x2 is 876 for UDSM 877 end for; 878end CFG_ao22_x2_UDSM; 879 880 881----- CELL ao22_x4 ----- 882library IEEE; 883use IEEE.STD_LOGIC_1164.all; 884library SYNOPSYS; 885use SYNOPSYS.attributes.REAL_NAME; 886 887-- entity declaration -- 888entity ao22_x4 is 889 generic( 890 Timing_mesg: Boolean := True; 891 Timing_xgen: Boolean := False; 892 tpdi0_q_R : Time := 0.674 ns; 893 tpdi0_q_F : Time := 0.552 ns; 894 tpdi1_q_R : Time := 0.615 ns; 895 tpdi1_q_F : Time := 0.647 ns; 896 tpdi2_q_R : Time := 0.526 ns; 897 tpdi2_q_F : Time := 0.505 ns; 898 twdi0_R : Time := 0.000 ns; 899 twdi0_F : Time := 0.000 ns; 900 twdi1_R : Time := 0.000 ns; 901 twdi1_F : Time := 0.000 ns; 902 twdi2_R : Time := 0.000 ns; 903 twdi2_F : Time := 0.000 ns); 904 905 port( 906 i0 : in STD_LOGIC; 907 i1 : in STD_LOGIC; 908 i2 : in STD_LOGIC; 909 q : out STD_LOGIC); 910end ao22_x4; 911 912-- architecture body -- 913library IEEE_ASIC; 914use IEEE.STD_LOGIC_MISC.all; 915use SYNOPSYS.attributes.backplane; 916use SYNOPSYS.attributes.PRIVATE; 917use SYNOPSYS.attributes.ASIC_CELL; 918 919architecture UDSM of ao22_x4 is 920 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 921 attribute PRIVATE of UDSM : architecture is TRUE; 922 attribute ASIC_CELL of UDSM : architecture is TRUE; 923 924 signal n1 : STD_LOGIC; 925 926 component AND2MAC 927 generic( 928 tpdY_R : Time := 0 ns; 929 tpdY_F : Time := 0 ns; 930 strn : STRENGTH := strn_X01); 931 port( 932 I0 : in STD_LOGIC; 933 I1 : in STD_LOGIC; 934 Y : out STD_LOGIC); 935 end component; 936 937 component OR2MAC 938 generic( 939 tpdY_R : Time := 0 ns; 940 tpdY_F : Time := 0 ns; 941 strn : STRENGTH := strn_X01); 942 port( 943 I0 : in STD_LOGIC; 944 I1 : in STD_LOGIC; 945 Y : out STD_LOGIC); 946 end component; 947 948begin 949 950 -- Netlist 951 U1 : AND2MAC 952 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 953 port map( I0 => i2, I1 => n1, Y => q); 954 955 U2 : OR2MAC 956 port map( I0 => i1, I1 => i0, Y => n1); 957 958 959end UDSM; 960 961configuration CFG_ao22_x4_UDSM of ao22_x4 is 962 for UDSM 963 end for; 964end CFG_ao22_x4_UDSM; 965 966 967----- CELL buf_x2 ----- 968library IEEE; 969use IEEE.STD_LOGIC_1164.all; 970library SYNOPSYS; 971use SYNOPSYS.attributes.REAL_NAME; 972 973-- entity declaration -- 974entity buf_x2 is 975 generic( 976 Timing_mesg: Boolean := True; 977 Timing_xgen: Boolean := False; 978 tpdi_q_R : Time := 0.409 ns; 979 tpdi_q_F : Time := 0.391 ns; 980 twdi_R : Time := 0.000 ns; 981 twdi_F : Time := 0.000 ns); 982 983 port( 984 i : in STD_LOGIC; 985 q : out STD_LOGIC); 986end buf_x2; 987 988-- architecture body -- 989library IEEE_ASIC; 990use IEEE.STD_LOGIC_MISC.all; 991use SYNOPSYS.attributes.backplane; 992use SYNOPSYS.attributes.PRIVATE; 993use SYNOPSYS.attributes.ASIC_CELL; 994 995architecture UDSM of buf_x2 is 996 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 997 attribute PRIVATE of UDSM : architecture is TRUE; 998 attribute ASIC_CELL of UDSM : architecture is TRUE; 999 1000begin 1001 1002 -- Concurrent assignments 1003 U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1004 generic map( tLH => 1 ns, tHL => 1 ns) 1005 port map( Input => i, Output => q); 1006 1007 1008end UDSM; 1009 1010configuration CFG_buf_x2_UDSM of buf_x2 is 1011 for UDSM 1012 end for; 1013end CFG_buf_x2_UDSM; 1014 1015 1016----- CELL buf_x4 ----- 1017library IEEE; 1018use IEEE.STD_LOGIC_1164.all; 1019library SYNOPSYS; 1020use SYNOPSYS.attributes.REAL_NAME; 1021 1022-- entity declaration -- 1023entity buf_x4 is 1024 generic( 1025 Timing_mesg: Boolean := True; 1026 Timing_xgen: Boolean := False; 1027 tpdi_q_R : Time := 0.379 ns; 1028 tpdi_q_F : Time := 0.409 ns; 1029 twdi_R : Time := 0.000 ns; 1030 twdi_F : Time := 0.000 ns); 1031 1032 port( 1033 i : in STD_LOGIC; 1034 q : out STD_LOGIC); 1035end buf_x4; 1036 1037-- architecture body -- 1038library IEEE_ASIC; 1039use IEEE.STD_LOGIC_MISC.all; 1040use SYNOPSYS.attributes.backplane; 1041use SYNOPSYS.attributes.PRIVATE; 1042use SYNOPSYS.attributes.ASIC_CELL; 1043 1044architecture UDSM of buf_x4 is 1045 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1046 attribute PRIVATE of UDSM : architecture is TRUE; 1047 attribute ASIC_CELL of UDSM : architecture is TRUE; 1048 1049begin 1050 1051 -- Concurrent assignments 1052 U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1053 generic map( tLH => 1 ns, tHL => 1 ns) 1054 port map( Input => i, Output => q); 1055 1056 1057end UDSM; 1058 1059configuration CFG_buf_x4_UDSM of buf_x4 is 1060 for UDSM 1061 end for; 1062end CFG_buf_x4_UDSM; 1063 1064 1065----- CELL buf_x8 ----- 1066library IEEE; 1067use IEEE.STD_LOGIC_1164.all; 1068library SYNOPSYS; 1069use SYNOPSYS.attributes.REAL_NAME; 1070 1071-- entity declaration -- 1072entity buf_x8 is 1073 generic( 1074 Timing_mesg: Boolean := True; 1075 Timing_xgen: Boolean := False; 1076 tpdi_q_R : Time := 0.343 ns; 1077 tpdi_q_F : Time := 0.396 ns; 1078 twdi_R : Time := 0.000 ns; 1079 twdi_F : Time := 0.000 ns); 1080 1081 port( 1082 i : in STD_LOGIC; 1083 q : out STD_LOGIC); 1084end buf_x8; 1085 1086-- architecture body -- 1087library IEEE_ASIC; 1088use IEEE.STD_LOGIC_MISC.all; 1089use SYNOPSYS.attributes.backplane; 1090use SYNOPSYS.attributes.PRIVATE; 1091use SYNOPSYS.attributes.ASIC_CELL; 1092 1093architecture UDSM of buf_x8 is 1094 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1095 attribute PRIVATE of UDSM : architecture is TRUE; 1096 attribute ASIC_CELL of UDSM : architecture is TRUE; 1097 1098begin 1099 1100 -- Concurrent assignments 1101 U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1102 generic map( tLH => 1 ns, tHL => 1 ns) 1103 port map( Input => i, Output => q); 1104 1105 1106end UDSM; 1107 1108configuration CFG_buf_x8_UDSM of buf_x8 is 1109 for UDSM 1110 end for; 1111end CFG_buf_x8_UDSM; 1112 1113 1114----- CELL inv_x1 ----- 1115library IEEE; 1116use IEEE.STD_LOGIC_1164.all; 1117library SYNOPSYS; 1118use SYNOPSYS.attributes.REAL_NAME; 1119 1120-- entity declaration -- 1121entity inv_x1 is 1122 generic( 1123 Timing_mesg: Boolean := True; 1124 Timing_xgen: Boolean := False; 1125 tpdi_nq_R : Time := 0.101 ns; 1126 tpdi_nq_F : Time := 0.139 ns; 1127 twdi_R : Time := 0.000 ns; 1128 twdi_F : Time := 0.000 ns); 1129 1130 port( 1131 i : in STD_LOGIC; 1132 nq : out STD_LOGIC); 1133end inv_x1; 1134 1135-- architecture body -- 1136library IEEE_ASIC; 1137use IEEE.STD_LOGIC_MISC.all; 1138use SYNOPSYS.attributes.backplane; 1139use SYNOPSYS.attributes.PRIVATE; 1140use SYNOPSYS.attributes.ASIC_CELL; 1141 1142architecture UDSM of inv_x1 is 1143 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1144 attribute PRIVATE of UDSM : architecture is TRUE; 1145 attribute ASIC_CELL of UDSM : architecture is TRUE; 1146 1147 component INVMAC 1148 generic( 1149 tpdY_R : Time := 0 ns; 1150 tpdY_F : Time := 0 ns; 1151 strn : STRENGTH := strn_X01); 1152 port( 1153 I0 : in STD_LOGIC; 1154 Y : out STD_LOGIC); 1155 end component; 1156 1157begin 1158 1159 -- Netlist 1160 U1 : INVMAC 1161 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1162 port map( I0 => i, Y => nq); 1163 1164 1165end UDSM; 1166 1167configuration CFG_inv_x1_UDSM of inv_x1 is 1168 for UDSM 1169 end for; 1170end CFG_inv_x1_UDSM; 1171 1172 1173----- CELL inv_x2 ----- 1174library IEEE; 1175use IEEE.STD_LOGIC_1164.all; 1176library SYNOPSYS; 1177use SYNOPSYS.attributes.REAL_NAME; 1178 1179-- entity declaration -- 1180entity inv_x2 is 1181 generic( 1182 Timing_mesg: Boolean := True; 1183 Timing_xgen: Boolean := False; 1184 tpdi_nq_R : Time := 0.069 ns; 1185 tpdi_nq_F : Time := 0.163 ns; 1186 twdi_R : Time := 0.000 ns; 1187 twdi_F : Time := 0.000 ns); 1188 1189 port( 1190 i : in STD_LOGIC; 1191 nq : out STD_LOGIC); 1192end inv_x2; 1193 1194-- architecture body -- 1195library IEEE_ASIC; 1196use IEEE.STD_LOGIC_MISC.all; 1197use SYNOPSYS.attributes.backplane; 1198use SYNOPSYS.attributes.PRIVATE; 1199use SYNOPSYS.attributes.ASIC_CELL; 1200 1201architecture UDSM of inv_x2 is 1202 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1203 attribute PRIVATE of UDSM : architecture is TRUE; 1204 attribute ASIC_CELL of UDSM : architecture is TRUE; 1205 1206 component INVMAC 1207 generic( 1208 tpdY_R : Time := 0 ns; 1209 tpdY_F : Time := 0 ns; 1210 strn : STRENGTH := strn_X01); 1211 port( 1212 I0 : in STD_LOGIC; 1213 Y : out STD_LOGIC); 1214 end component; 1215 1216begin 1217 1218 -- Netlist 1219 U1 : INVMAC 1220 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1221 port map( I0 => i, Y => nq); 1222 1223 1224end UDSM; 1225 1226configuration CFG_inv_x2_UDSM of inv_x2 is 1227 for UDSM 1228 end for; 1229end CFG_inv_x2_UDSM; 1230 1231 1232----- CELL inv_x4 ----- 1233library IEEE; 1234use IEEE.STD_LOGIC_1164.all; 1235library SYNOPSYS; 1236use SYNOPSYS.attributes.REAL_NAME; 1237 1238-- entity declaration -- 1239entity inv_x4 is 1240 generic( 1241 Timing_mesg: Boolean := True; 1242 Timing_xgen: Boolean := False; 1243 tpdi_nq_R : Time := 0.071 ns; 1244 tpdi_nq_F : Time := 0.143 ns; 1245 twdi_R : Time := 0.000 ns; 1246 twdi_F : Time := 0.000 ns); 1247 1248 port( 1249 i : in STD_LOGIC; 1250 nq : out STD_LOGIC); 1251end inv_x4; 1252 1253-- architecture body -- 1254library IEEE_ASIC; 1255use IEEE.STD_LOGIC_MISC.all; 1256use SYNOPSYS.attributes.backplane; 1257use SYNOPSYS.attributes.PRIVATE; 1258use SYNOPSYS.attributes.ASIC_CELL; 1259 1260architecture UDSM of inv_x4 is 1261 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1262 attribute PRIVATE of UDSM : architecture is TRUE; 1263 attribute ASIC_CELL of UDSM : architecture is TRUE; 1264 1265 component INVMAC 1266 generic( 1267 tpdY_R : Time := 0 ns; 1268 tpdY_F : Time := 0 ns; 1269 strn : STRENGTH := strn_X01); 1270 port( 1271 I0 : in STD_LOGIC; 1272 Y : out STD_LOGIC); 1273 end component; 1274 1275begin 1276 1277 -- Netlist 1278 U1 : INVMAC 1279 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1280 port map( I0 => i, Y => nq); 1281 1282 1283end UDSM; 1284 1285configuration CFG_inv_x4_UDSM of inv_x4 is 1286 for UDSM 1287 end for; 1288end CFG_inv_x4_UDSM; 1289 1290 1291----- CELL inv_x8 ----- 1292library IEEE; 1293use IEEE.STD_LOGIC_1164.all; 1294library SYNOPSYS; 1295use SYNOPSYS.attributes.REAL_NAME; 1296 1297-- entity declaration -- 1298entity inv_x8 is 1299 generic( 1300 Timing_mesg: Boolean := True; 1301 Timing_xgen: Boolean := False; 1302 tpdi_nq_R : Time := 0.086 ns; 1303 tpdi_nq_F : Time := 0.133 ns; 1304 twdi_R : Time := 0.000 ns; 1305 twdi_F : Time := 0.000 ns); 1306 1307 port( 1308 i : in STD_LOGIC; 1309 nq : out STD_LOGIC); 1310end inv_x8; 1311 1312-- architecture body -- 1313library IEEE_ASIC; 1314use IEEE.STD_LOGIC_MISC.all; 1315use SYNOPSYS.attributes.backplane; 1316use SYNOPSYS.attributes.PRIVATE; 1317use SYNOPSYS.attributes.ASIC_CELL; 1318 1319architecture UDSM of inv_x8 is 1320 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1321 attribute PRIVATE of UDSM : architecture is TRUE; 1322 attribute ASIC_CELL of UDSM : architecture is TRUE; 1323 1324 component INVMAC 1325 generic( 1326 tpdY_R : Time := 0 ns; 1327 tpdY_F : Time := 0 ns; 1328 strn : STRENGTH := strn_X01); 1329 port( 1330 I0 : in STD_LOGIC; 1331 Y : out STD_LOGIC); 1332 end component; 1333 1334begin 1335 1336 -- Netlist 1337 U1 : INVMAC 1338 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1339 port map( I0 => i, Y => nq); 1340 1341 1342end UDSM; 1343 1344configuration CFG_inv_x8_UDSM of inv_x8 is 1345 for UDSM 1346 end for; 1347end CFG_inv_x8_UDSM; 1348 1349 1350----- CELL mx2_x2 ----- 1351library IEEE; 1352use IEEE.STD_LOGIC_1164.all; 1353library SYNOPSYS; 1354use SYNOPSYS.attributes.REAL_NAME; 1355 1356-- entity declaration -- 1357entity mx2_x2 is 1358 generic( 1359 Timing_mesg: Boolean := True; 1360 Timing_xgen: Boolean := False; 1361 tpdcmd_q_R : Time := 0.484 ns; 1362 tpdcmd_q_F : Time := 0.522 ns; 1363 tpdi0_q_R : Time := 0.451 ns; 1364 tpdi0_q_F : Time := 0.469 ns; 1365 tpdi1_q_R : Time := 0.451 ns; 1366 tpdi1_q_F : Time := 0.469 ns; 1367 twdcmd_R : Time := 0.000 ns; 1368 twdcmd_F : Time := 0.000 ns; 1369 twdi0_R : Time := 0.000 ns; 1370 twdi0_F : Time := 0.000 ns; 1371 twdi1_R : Time := 0.000 ns; 1372 twdi1_F : Time := 0.000 ns); 1373 1374 port( 1375 cmd : in STD_LOGIC; 1376 i0 : in STD_LOGIC; 1377 i1 : in STD_LOGIC; 1378 q : out STD_LOGIC); 1379end mx2_x2; 1380 1381-- architecture body -- 1382library IEEE_ASIC; 1383use IEEE.STD_LOGIC_MISC.all; 1384use SYNOPSYS.attributes.backplane; 1385use SYNOPSYS.attributes.PRIVATE; 1386use SYNOPSYS.attributes.ASIC_CELL; 1387 1388architecture UDSM of mx2_x2 is 1389 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1390 attribute PRIVATE of UDSM : architecture is TRUE; 1391 attribute ASIC_CELL of UDSM : architecture is TRUE; 1392 1393 component MUX2MAC 1394 generic( 1395 tpdY_R : Time := 0 ns; 1396 tpdY_F : Time := 0 ns; 1397 strn : STRENGTH := strn_X01); 1398 port( 1399 I0 : in STD_LOGIC; 1400 I1 : in STD_LOGIC; 1401 S0 : in STD_LOGIC; 1402 Y : out STD_LOGIC); 1403 end component; 1404 1405begin 1406 1407 -- Netlist 1408 U1 : MUX2MAC 1409 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1410 port map( I0 => i0, I1 => i1, S0 => cmd, Y => q); 1411 1412 1413end UDSM; 1414 1415configuration CFG_mx2_x2_UDSM of mx2_x2 is 1416 for UDSM 1417 end for; 1418end CFG_mx2_x2_UDSM; 1419 1420 1421----- CELL mx2_x4 ----- 1422library IEEE; 1423use IEEE.STD_LOGIC_1164.all; 1424library SYNOPSYS; 1425use SYNOPSYS.attributes.REAL_NAME; 1426 1427-- entity declaration -- 1428entity mx2_x4 is 1429 generic( 1430 Timing_mesg: Boolean := True; 1431 Timing_xgen: Boolean := False; 1432 tpdcmd_q_R : Time := 0.615 ns; 1433 tpdcmd_q_F : Time := 0.647 ns; 1434 tpdi0_q_R : Time := 0.564 ns; 1435 tpdi0_q_F : Time := 0.576 ns; 1436 tpdi1_q_R : Time := 0.564 ns; 1437 tpdi1_q_F : Time := 0.576 ns; 1438 twdcmd_R : Time := 0.000 ns; 1439 twdcmd_F : Time := 0.000 ns; 1440 twdi0_R : Time := 0.000 ns; 1441 twdi0_F : Time := 0.000 ns; 1442 twdi1_R : Time := 0.000 ns; 1443 twdi1_F : Time := 0.000 ns); 1444 1445 port( 1446 cmd : in STD_LOGIC; 1447 i0 : in STD_LOGIC; 1448 i1 : in STD_LOGIC; 1449 q : out STD_LOGIC); 1450end mx2_x4; 1451 1452-- architecture body -- 1453library IEEE_ASIC; 1454use IEEE.STD_LOGIC_MISC.all; 1455use SYNOPSYS.attributes.backplane; 1456use SYNOPSYS.attributes.PRIVATE; 1457use SYNOPSYS.attributes.ASIC_CELL; 1458 1459architecture UDSM of mx2_x4 is 1460 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1461 attribute PRIVATE of UDSM : architecture is TRUE; 1462 attribute ASIC_CELL of UDSM : architecture is TRUE; 1463 1464 component MUX2MAC 1465 generic( 1466 tpdY_R : Time := 0 ns; 1467 tpdY_F : Time := 0 ns; 1468 strn : STRENGTH := strn_X01); 1469 port( 1470 I0 : in STD_LOGIC; 1471 I1 : in STD_LOGIC; 1472 S0 : in STD_LOGIC; 1473 Y : out STD_LOGIC); 1474 end component; 1475 1476begin 1477 1478 -- Netlist 1479 U1 : MUX2MAC 1480 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1481 port map( I0 => i0, I1 => i1, S0 => cmd, Y => q); 1482 1483 1484end UDSM; 1485 1486configuration CFG_mx2_x4_UDSM of mx2_x4 is 1487 for UDSM 1488 end for; 1489end CFG_mx2_x4_UDSM; 1490 1491 1492----- CELL mx3_x2 ----- 1493library IEEE; 1494use IEEE.STD_LOGIC_1164.all; 1495library SYNOPSYS; 1496use SYNOPSYS.attributes.REAL_NAME; 1497 1498-- entity declaration -- 1499entity mx3_x2 is 1500 generic( 1501 Timing_mesg: Boolean := True; 1502 Timing_xgen: Boolean := False; 1503 tpdcmd0_q_R : Time := 0.573 ns; 1504 tpdcmd0_q_F : Time := 0.680 ns; 1505 tpdcmd1_q_R : Time := 0.664 ns; 1506 tpdcmd1_q_F : Time := 0.817 ns; 1507 tpdi0_q_R : Time := 0.538 ns; 1508 tpdi0_q_F : Time := 0.658 ns; 1509 tpdi1_q_R : Time := 0.654 ns; 1510 tpdi1_q_F : Time := 0.808 ns; 1511 tpdi2_q_R : Time := 0.654 ns; 1512 tpdi2_q_F : Time := 0.808 ns; 1513 twdcmd0_R : Time := 0.000 ns; 1514 twdcmd0_F : Time := 0.000 ns; 1515 twdcmd1_R : Time := 0.000 ns; 1516 twdcmd1_F : Time := 0.000 ns; 1517 twdi0_R : Time := 0.000 ns; 1518 twdi0_F : Time := 0.000 ns; 1519 twdi1_R : Time := 0.000 ns; 1520 twdi1_F : Time := 0.000 ns; 1521 twdi2_R : Time := 0.000 ns; 1522 twdi2_F : Time := 0.000 ns); 1523 1524 port( 1525 cmd0 : in STD_LOGIC; 1526 cmd1 : in STD_LOGIC; 1527 i0 : in STD_LOGIC; 1528 i1 : in STD_LOGIC; 1529 i2 : in STD_LOGIC; 1530 q : out STD_LOGIC); 1531end mx3_x2; 1532 1533-- architecture body -- 1534library IEEE_ASIC; 1535use IEEE.STD_LOGIC_MISC.all; 1536use SYNOPSYS.attributes.backplane; 1537use SYNOPSYS.attributes.PRIVATE; 1538use SYNOPSYS.attributes.ASIC_CELL; 1539 1540architecture UDSM of mx3_x2 is 1541 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1542 attribute PRIVATE of UDSM : architecture is TRUE; 1543 attribute ASIC_CELL of UDSM : architecture is TRUE; 1544 1545 signal n1 : STD_LOGIC; 1546 1547 component MUX2MAC 1548 generic( 1549 tpdY_R : Time := 0 ns; 1550 tpdY_F : Time := 0 ns; 1551 strn : STRENGTH := strn_X01); 1552 port( 1553 I0 : in STD_LOGIC; 1554 I1 : in STD_LOGIC; 1555 S0 : in STD_LOGIC; 1556 Y : out STD_LOGIC); 1557 end component; 1558 1559begin 1560 1561 -- Netlist 1562 U1 : MUX2MAC 1563 port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); 1564 1565 U2 : MUX2MAC 1566 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1567 port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q); 1568 1569 1570end UDSM; 1571 1572configuration CFG_mx3_x2_UDSM of mx3_x2 is 1573 for UDSM 1574 end for; 1575end CFG_mx3_x2_UDSM; 1576 1577 1578----- CELL mx3_x4 ----- 1579library IEEE; 1580use IEEE.STD_LOGIC_1164.all; 1581library SYNOPSYS; 1582use SYNOPSYS.attributes.REAL_NAME; 1583 1584-- entity declaration -- 1585entity mx3_x4 is 1586 generic( 1587 Timing_mesg: Boolean := True; 1588 Timing_xgen: Boolean := False; 1589 tpdcmd0_q_R : Time := 0.683 ns; 1590 tpdcmd0_q_F : Time := 0.779 ns; 1591 tpdcmd1_q_R : Time := 0.792 ns; 1592 tpdcmd1_q_F : Time := 0.967 ns; 1593 tpdi0_q_R : Time := 0.640 ns; 1594 tpdi0_q_F : Time := 0.774 ns; 1595 tpdi1_q_R : Time := 0.770 ns; 1596 tpdi1_q_F : Time := 0.948 ns; 1597 tpdi2_q_R : Time := 0.770 ns; 1598 tpdi2_q_F : Time := 0.948 ns; 1599 twdcmd0_R : Time := 0.000 ns; 1600 twdcmd0_F : Time := 0.000 ns; 1601 twdcmd1_R : Time := 0.000 ns; 1602 twdcmd1_F : Time := 0.000 ns; 1603 twdi0_R : Time := 0.000 ns; 1604 twdi0_F : Time := 0.000 ns; 1605 twdi1_R : Time := 0.000 ns; 1606 twdi1_F : Time := 0.000 ns; 1607 twdi2_R : Time := 0.000 ns; 1608 twdi2_F : Time := 0.000 ns); 1609 1610 port( 1611 cmd0 : in STD_LOGIC; 1612 cmd1 : in STD_LOGIC; 1613 i0 : in STD_LOGIC; 1614 i1 : in STD_LOGIC; 1615 i2 : in STD_LOGIC; 1616 q : out STD_LOGIC); 1617end mx3_x4; 1618 1619-- architecture body -- 1620library IEEE_ASIC; 1621use IEEE.STD_LOGIC_MISC.all; 1622use SYNOPSYS.attributes.backplane; 1623use SYNOPSYS.attributes.PRIVATE; 1624use SYNOPSYS.attributes.ASIC_CELL; 1625 1626architecture UDSM of mx3_x4 is 1627 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1628 attribute PRIVATE of UDSM : architecture is TRUE; 1629 attribute ASIC_CELL of UDSM : architecture is TRUE; 1630 1631 signal n1 : STD_LOGIC; 1632 1633 component MUX2MAC 1634 generic( 1635 tpdY_R : Time := 0 ns; 1636 tpdY_F : Time := 0 ns; 1637 strn : STRENGTH := strn_X01); 1638 port( 1639 I0 : in STD_LOGIC; 1640 I1 : in STD_LOGIC; 1641 S0 : in STD_LOGIC; 1642 Y : out STD_LOGIC); 1643 end component; 1644 1645begin 1646 1647 -- Netlist 1648 U1 : MUX2MAC 1649 port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); 1650 1651 U2 : MUX2MAC 1652 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1653 port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q); 1654 1655 1656end UDSM; 1657 1658configuration CFG_mx3_x4_UDSM of mx3_x4 is 1659 for UDSM 1660 end for; 1661end CFG_mx3_x4_UDSM; 1662 1663 1664----- CELL na2_x1 ----- 1665library IEEE; 1666use IEEE.STD_LOGIC_1164.all; 1667library SYNOPSYS; 1668use SYNOPSYS.attributes.REAL_NAME; 1669 1670-- entity declaration -- 1671entity na2_x1 is 1672 generic( 1673 Timing_mesg: Boolean := True; 1674 Timing_xgen: Boolean := False; 1675 tpdi0_nq_R : Time := 0.059 ns; 1676 tpdi0_nq_F : Time := 0.288 ns; 1677 tpdi1_nq_R : Time := 0.111 ns; 1678 tpdi1_nq_F : Time := 0.234 ns; 1679 twdi0_R : Time := 0.000 ns; 1680 twdi0_F : Time := 0.000 ns; 1681 twdi1_R : Time := 0.000 ns; 1682 twdi1_F : Time := 0.000 ns); 1683 1684 port( 1685 i0 : in STD_LOGIC; 1686 i1 : in STD_LOGIC; 1687 nq : out STD_LOGIC); 1688end na2_x1; 1689 1690-- architecture body -- 1691library IEEE_ASIC; 1692use IEEE.STD_LOGIC_MISC.all; 1693use SYNOPSYS.attributes.backplane; 1694use SYNOPSYS.attributes.PRIVATE; 1695use SYNOPSYS.attributes.ASIC_CELL; 1696 1697architecture UDSM of na2_x1 is 1698 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1699 attribute PRIVATE of UDSM : architecture is TRUE; 1700 attribute ASIC_CELL of UDSM : architecture is TRUE; 1701 1702 component NAND2MAC 1703 generic( 1704 tpdY_R : Time := 0 ns; 1705 tpdY_F : Time := 0 ns; 1706 strn : STRENGTH := strn_X01); 1707 port( 1708 I0 : in STD_LOGIC; 1709 I1 : in STD_LOGIC; 1710 Y : out STD_LOGIC); 1711 end component; 1712 1713begin 1714 1715 -- Netlist 1716 U1 : NAND2MAC 1717 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1718 port map( I0 => i0, I1 => i1, Y => nq); 1719 1720 1721end UDSM; 1722 1723configuration CFG_na2_x1_UDSM of na2_x1 is 1724 for UDSM 1725 end for; 1726end CFG_na2_x1_UDSM; 1727 1728 1729----- CELL na2_x4 ----- 1730library IEEE; 1731use IEEE.STD_LOGIC_1164.all; 1732library SYNOPSYS; 1733use SYNOPSYS.attributes.REAL_NAME; 1734 1735-- entity declaration -- 1736entity na2_x4 is 1737 generic( 1738 Timing_mesg: Boolean := True; 1739 Timing_xgen: Boolean := False; 1740 tpdi0_nq_R : Time := 0.412 ns; 1741 tpdi0_nq_F : Time := 0.552 ns; 1742 tpdi1_nq_R : Time := 0.353 ns; 1743 tpdi1_nq_F : Time := 0.601 ns; 1744 twdi0_R : Time := 0.000 ns; 1745 twdi0_F : Time := 0.000 ns; 1746 twdi1_R : Time := 0.000 ns; 1747 twdi1_F : Time := 0.000 ns); 1748 1749 port( 1750 i0 : in STD_LOGIC; 1751 i1 : in STD_LOGIC; 1752 nq : out STD_LOGIC); 1753end na2_x4; 1754 1755-- architecture body -- 1756library IEEE_ASIC; 1757use IEEE.STD_LOGIC_MISC.all; 1758use SYNOPSYS.attributes.backplane; 1759use SYNOPSYS.attributes.PRIVATE; 1760use SYNOPSYS.attributes.ASIC_CELL; 1761 1762architecture UDSM of na2_x4 is 1763 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1764 attribute PRIVATE of UDSM : architecture is TRUE; 1765 attribute ASIC_CELL of UDSM : architecture is TRUE; 1766 1767 component NAND2MAC 1768 generic( 1769 tpdY_R : Time := 0 ns; 1770 tpdY_F : Time := 0 ns; 1771 strn : STRENGTH := strn_X01); 1772 port( 1773 I0 : in STD_LOGIC; 1774 I1 : in STD_LOGIC; 1775 Y : out STD_LOGIC); 1776 end component; 1777 1778begin 1779 1780 -- Netlist 1781 U1 : NAND2MAC 1782 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1783 port map( I0 => i0, I1 => i1, Y => nq); 1784 1785 1786end UDSM; 1787 1788configuration CFG_na2_x4_UDSM of na2_x4 is 1789 for UDSM 1790 end for; 1791end CFG_na2_x4_UDSM; 1792 1793 1794----- CELL na3_x1 ----- 1795library IEEE; 1796use IEEE.STD_LOGIC_1164.all; 1797library SYNOPSYS; 1798use SYNOPSYS.attributes.REAL_NAME; 1799 1800-- entity declaration -- 1801entity na3_x1 is 1802 generic( 1803 Timing_mesg: Boolean := True; 1804 Timing_xgen: Boolean := False; 1805 tpdi0_nq_R : Time := 0.119 ns; 1806 tpdi0_nq_F : Time := 0.363 ns; 1807 tpdi1_nq_R : Time := 0.171 ns; 1808 tpdi1_nq_F : Time := 0.316 ns; 1809 tpdi2_nq_R : Time := 0.193 ns; 1810 tpdi2_nq_F : Time := 0.265 ns; 1811 twdi0_R : Time := 0.000 ns; 1812 twdi0_F : Time := 0.000 ns; 1813 twdi1_R : Time := 0.000 ns; 1814 twdi1_F : Time := 0.000 ns; 1815 twdi2_R : Time := 0.000 ns; 1816 twdi2_F : Time := 0.000 ns); 1817 1818 port( 1819 i0 : in STD_LOGIC; 1820 i1 : in STD_LOGIC; 1821 i2 : in STD_LOGIC; 1822 nq : out STD_LOGIC); 1823end na3_x1; 1824 1825-- architecture body -- 1826library IEEE_ASIC; 1827use IEEE.STD_LOGIC_MISC.all; 1828use SYNOPSYS.attributes.backplane; 1829use SYNOPSYS.attributes.PRIVATE; 1830use SYNOPSYS.attributes.ASIC_CELL; 1831 1832architecture UDSM of na3_x1 is 1833 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1834 attribute PRIVATE of UDSM : architecture is TRUE; 1835 attribute ASIC_CELL of UDSM : architecture is TRUE; 1836 1837 component NAND3MAC 1838 generic( 1839 tpdY_R : Time := 0 ns; 1840 tpdY_F : Time := 0 ns; 1841 strn : STRENGTH := strn_X01); 1842 port( 1843 I0 : in STD_LOGIC; 1844 I1 : in STD_LOGIC; 1845 I2 : in STD_LOGIC; 1846 Y : out STD_LOGIC); 1847 end component; 1848 1849begin 1850 1851 -- Netlist 1852 U1 : NAND3MAC 1853 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1854 port map( I0 => i1, I1 => i2, I2 => i0, Y => nq); 1855 1856 1857end UDSM; 1858 1859configuration CFG_na3_x1_UDSM of na3_x1 is 1860 for UDSM 1861 end for; 1862end CFG_na3_x1_UDSM; 1863 1864 1865----- CELL na3_x4 ----- 1866library IEEE; 1867use IEEE.STD_LOGIC_1164.all; 1868library SYNOPSYS; 1869use SYNOPSYS.attributes.REAL_NAME; 1870 1871-- entity declaration -- 1872entity na3_x4 is 1873 generic( 1874 Timing_mesg: Boolean := True; 1875 Timing_xgen: Boolean := False; 1876 tpdi0_nq_R : Time := 0.556 ns; 1877 tpdi0_nq_F : Time := 0.601 ns; 1878 tpdi1_nq_R : Time := 0.460 ns; 1879 tpdi1_nq_F : Time := 0.691 ns; 1880 tpdi2_nq_R : Time := 0.519 ns; 1881 tpdi2_nq_F : Time := 0.647 ns; 1882 twdi0_R : Time := 0.000 ns; 1883 twdi0_F : Time := 0.000 ns; 1884 twdi1_R : Time := 0.000 ns; 1885 twdi1_F : Time := 0.000 ns; 1886 twdi2_R : Time := 0.000 ns; 1887 twdi2_F : Time := 0.000 ns); 1888 1889 port( 1890 i0 : in STD_LOGIC; 1891 i1 : in STD_LOGIC; 1892 i2 : in STD_LOGIC; 1893 nq : out STD_LOGIC); 1894end na3_x4; 1895 1896-- architecture body -- 1897library IEEE_ASIC; 1898use IEEE.STD_LOGIC_MISC.all; 1899use SYNOPSYS.attributes.backplane; 1900use SYNOPSYS.attributes.PRIVATE; 1901use SYNOPSYS.attributes.ASIC_CELL; 1902 1903architecture UDSM of na3_x4 is 1904 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1905 attribute PRIVATE of UDSM : architecture is TRUE; 1906 attribute ASIC_CELL of UDSM : architecture is TRUE; 1907 1908 component NAND3MAC 1909 generic( 1910 tpdY_R : Time := 0 ns; 1911 tpdY_F : Time := 0 ns; 1912 strn : STRENGTH := strn_X01); 1913 port( 1914 I0 : in STD_LOGIC; 1915 I1 : in STD_LOGIC; 1916 I2 : in STD_LOGIC; 1917 Y : out STD_LOGIC); 1918 end component; 1919 1920begin 1921 1922 -- Netlist 1923 U1 : NAND3MAC 1924 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 1925 port map( I0 => i1, I1 => i2, I2 => i0, Y => nq); 1926 1927 1928end UDSM; 1929 1930configuration CFG_na3_x4_UDSM of na3_x4 is 1931 for UDSM 1932 end for; 1933end CFG_na3_x4_UDSM; 1934 1935 1936----- CELL na4_x1 ----- 1937library IEEE; 1938use IEEE.STD_LOGIC_1164.all; 1939library SYNOPSYS; 1940use SYNOPSYS.attributes.REAL_NAME; 1941 1942-- entity declaration -- 1943entity na4_x1 is 1944 generic( 1945 Timing_mesg: Boolean := True; 1946 Timing_xgen: Boolean := False; 1947 tpdi0_nq_R : Time := 0.179 ns; 1948 tpdi0_nq_F : Time := 0.438 ns; 1949 tpdi1_nq_R : Time := 0.237 ns; 1950 tpdi1_nq_F : Time := 0.395 ns; 1951 tpdi2_nq_R : Time := 0.269 ns; 1952 tpdi2_nq_F : Time := 0.350 ns; 1953 tpdi3_nq_R : Time := 0.282 ns; 1954 tpdi3_nq_F : Time := 0.302 ns; 1955 twdi0_R : Time := 0.000 ns; 1956 twdi0_F : Time := 0.000 ns; 1957 twdi1_R : Time := 0.000 ns; 1958 twdi1_F : Time := 0.000 ns; 1959 twdi2_R : Time := 0.000 ns; 1960 twdi2_F : Time := 0.000 ns; 1961 twdi3_R : Time := 0.000 ns; 1962 twdi3_F : Time := 0.000 ns); 1963 1964 port( 1965 i0 : in STD_LOGIC; 1966 i1 : in STD_LOGIC; 1967 i2 : in STD_LOGIC; 1968 i3 : in STD_LOGIC; 1969 nq : out STD_LOGIC); 1970end na4_x1; 1971 1972-- architecture body -- 1973library IEEE_ASIC; 1974use IEEE.STD_LOGIC_MISC.all; 1975use SYNOPSYS.attributes.backplane; 1976use SYNOPSYS.attributes.PRIVATE; 1977use SYNOPSYS.attributes.ASIC_CELL; 1978 1979architecture UDSM of na4_x1 is 1980 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 1981 attribute PRIVATE of UDSM : architecture is TRUE; 1982 attribute ASIC_CELL of UDSM : architecture is TRUE; 1983 1984 component NAND4MAC 1985 generic( 1986 tpdY_R : Time := 0 ns; 1987 tpdY_F : Time := 0 ns; 1988 strn : STRENGTH := strn_X01); 1989 port( 1990 I0 : in STD_LOGIC; 1991 I1 : in STD_LOGIC; 1992 I2 : in STD_LOGIC; 1993 I3 : in STD_LOGIC; 1994 Y : out STD_LOGIC); 1995 end component; 1996 1997begin 1998 1999 -- Netlist 2000 U1 : NAND4MAC 2001 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2002 port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); 2003 2004 2005end UDSM; 2006 2007configuration CFG_na4_x1_UDSM of na4_x1 is 2008 for UDSM 2009 end for; 2010end CFG_na4_x1_UDSM; 2011 2012 2013----- CELL na4_x4 ----- 2014library IEEE; 2015use IEEE.STD_LOGIC_1164.all; 2016library SYNOPSYS; 2017use SYNOPSYS.attributes.REAL_NAME; 2018 2019-- entity declaration -- 2020entity na4_x4 is 2021 generic( 2022 Timing_mesg: Boolean := True; 2023 Timing_xgen: Boolean := False; 2024 tpdi0_nq_R : Time := 0.578 ns; 2025 tpdi0_nq_F : Time := 0.771 ns; 2026 tpdi1_nq_R : Time := 0.643 ns; 2027 tpdi1_nq_F : Time := 0.731 ns; 2028 tpdi2_nq_R : Time := 0.681 ns; 2029 tpdi2_nq_F : Time := 0.689 ns; 2030 tpdi3_nq_R : Time := 0.703 ns; 2031 tpdi3_nq_F : Time := 0.644 ns; 2032 twdi0_R : Time := 0.000 ns; 2033 twdi0_F : Time := 0.000 ns; 2034 twdi1_R : Time := 0.000 ns; 2035 twdi1_F : Time := 0.000 ns; 2036 twdi2_R : Time := 0.000 ns; 2037 twdi2_F : Time := 0.000 ns; 2038 twdi3_R : Time := 0.000 ns; 2039 twdi3_F : Time := 0.000 ns); 2040 2041 port( 2042 i0 : in STD_LOGIC; 2043 i1 : in STD_LOGIC; 2044 i2 : in STD_LOGIC; 2045 i3 : in STD_LOGIC; 2046 nq : out STD_LOGIC); 2047end na4_x4; 2048 2049-- architecture body -- 2050library IEEE_ASIC; 2051use IEEE.STD_LOGIC_MISC.all; 2052use SYNOPSYS.attributes.backplane; 2053use SYNOPSYS.attributes.PRIVATE; 2054use SYNOPSYS.attributes.ASIC_CELL; 2055 2056architecture UDSM of na4_x4 is 2057 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2058 attribute PRIVATE of UDSM : architecture is TRUE; 2059 attribute ASIC_CELL of UDSM : architecture is TRUE; 2060 2061 component NAND4MAC 2062 generic( 2063 tpdY_R : Time := 0 ns; 2064 tpdY_F : Time := 0 ns; 2065 strn : STRENGTH := strn_X01); 2066 port( 2067 I0 : in STD_LOGIC; 2068 I1 : in STD_LOGIC; 2069 I2 : in STD_LOGIC; 2070 I3 : in STD_LOGIC; 2071 Y : out STD_LOGIC); 2072 end component; 2073 2074begin 2075 2076 -- Netlist 2077 U1 : NAND4MAC 2078 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2079 port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); 2080 2081 2082end UDSM; 2083 2084configuration CFG_na4_x4_UDSM of na4_x4 is 2085 for UDSM 2086 end for; 2087end CFG_na4_x4_UDSM; 2088 2089 2090----- CELL nao2o22_x1 ----- 2091library IEEE; 2092use IEEE.STD_LOGIC_1164.all; 2093library SYNOPSYS; 2094use SYNOPSYS.attributes.REAL_NAME; 2095 2096-- entity declaration -- 2097entity nao2o22_x1 is 2098 generic( 2099 Timing_mesg: Boolean := True; 2100 Timing_xgen: Boolean := False; 2101 tpdi0_nq_R : Time := 0.294 ns; 2102 tpdi0_nq_F : Time := 0.226 ns; 2103 tpdi1_nq_R : Time := 0.218 ns; 2104 tpdi1_nq_F : Time := 0.287 ns; 2105 tpdi2_nq_R : Time := 0.237 ns; 2106 tpdi2_nq_F : Time := 0.307 ns; 2107 tpdi3_nq_R : Time := 0.174 ns; 2108 tpdi3_nq_F : Time := 0.382 ns; 2109 twdi0_R : Time := 0.000 ns; 2110 twdi0_F : Time := 0.000 ns; 2111 twdi1_R : Time := 0.000 ns; 2112 twdi1_F : Time := 0.000 ns; 2113 twdi2_R : Time := 0.000 ns; 2114 twdi2_F : Time := 0.000 ns; 2115 twdi3_R : Time := 0.000 ns; 2116 twdi3_F : Time := 0.000 ns); 2117 2118 port( 2119 i0 : in STD_LOGIC; 2120 i1 : in STD_LOGIC; 2121 i2 : in STD_LOGIC; 2122 i3 : in STD_LOGIC; 2123 nq : out STD_LOGIC); 2124end nao2o22_x1; 2125 2126-- architecture body -- 2127library IEEE_ASIC; 2128use IEEE.STD_LOGIC_MISC.all; 2129use SYNOPSYS.attributes.backplane; 2130use SYNOPSYS.attributes.PRIVATE; 2131use SYNOPSYS.attributes.ASIC_CELL; 2132 2133architecture UDSM of nao2o22_x1 is 2134 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2135 attribute PRIVATE of UDSM : architecture is TRUE; 2136 attribute ASIC_CELL of UDSM : architecture is TRUE; 2137 2138 signal n1, n2 : STD_LOGIC; 2139 2140 component NAND2MAC 2141 generic( 2142 tpdY_R : Time := 0 ns; 2143 tpdY_F : Time := 0 ns; 2144 strn : STRENGTH := strn_X01); 2145 port( 2146 I0 : in STD_LOGIC; 2147 I1 : in STD_LOGIC; 2148 Y : out STD_LOGIC); 2149 end component; 2150 2151 component OR2MAC 2152 generic( 2153 tpdY_R : Time := 0 ns; 2154 tpdY_F : Time := 0 ns; 2155 strn : STRENGTH := strn_X01); 2156 port( 2157 I0 : in STD_LOGIC; 2158 I1 : in STD_LOGIC; 2159 Y : out STD_LOGIC); 2160 end component; 2161 2162begin 2163 2164 -- Netlist 2165 U1 : NAND2MAC 2166 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2167 port map( I0 => n1, I1 => n2, Y => nq); 2168 2169 U2 : OR2MAC 2170 port map( I0 => i2, I1 => i3, Y => n2); 2171 2172 U3 : OR2MAC 2173 port map( I0 => i0, I1 => i1, Y => n1); 2174 2175 2176end UDSM; 2177 2178configuration CFG_nao2o22_x1_UDSM of nao2o22_x1 is 2179 for UDSM 2180 end for; 2181end CFG_nao2o22_x1_UDSM; 2182 2183 2184----- CELL nao2o22_x4 ----- 2185library IEEE; 2186use IEEE.STD_LOGIC_1164.all; 2187library SYNOPSYS; 2188use SYNOPSYS.attributes.REAL_NAME; 2189 2190-- entity declaration -- 2191entity nao2o22_x4 is 2192 generic( 2193 Timing_mesg: Boolean := True; 2194 Timing_xgen: Boolean := False; 2195 tpdi0_nq_R : Time := 0.734 ns; 2196 tpdi0_nq_F : Time := 0.644 ns; 2197 tpdi1_nq_R : Time := 0.666 ns; 2198 tpdi1_nq_F : Time := 0.717 ns; 2199 tpdi2_nq_R : Time := 0.664 ns; 2200 tpdi2_nq_F : Time := 0.721 ns; 2201 tpdi3_nq_R : Time := 0.607 ns; 2202 tpdi3_nq_F : Time := 0.807 ns; 2203 twdi0_R : Time := 0.000 ns; 2204 twdi0_F : Time := 0.000 ns; 2205 twdi1_R : Time := 0.000 ns; 2206 twdi1_F : Time := 0.000 ns; 2207 twdi2_R : Time := 0.000 ns; 2208 twdi2_F : Time := 0.000 ns; 2209 twdi3_R : Time := 0.000 ns; 2210 twdi3_F : Time := 0.000 ns); 2211 2212 port( 2213 i0 : in STD_LOGIC; 2214 i1 : in STD_LOGIC; 2215 i2 : in STD_LOGIC; 2216 i3 : in STD_LOGIC; 2217 nq : out STD_LOGIC); 2218end nao2o22_x4; 2219 2220-- architecture body -- 2221library IEEE_ASIC; 2222use IEEE.STD_LOGIC_MISC.all; 2223use SYNOPSYS.attributes.backplane; 2224use SYNOPSYS.attributes.PRIVATE; 2225use SYNOPSYS.attributes.ASIC_CELL; 2226 2227architecture UDSM of nao2o22_x4 is 2228 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2229 attribute PRIVATE of UDSM : architecture is TRUE; 2230 attribute ASIC_CELL of UDSM : architecture is TRUE; 2231 2232 signal n1, n2 : STD_LOGIC; 2233 2234 component NAND2MAC 2235 generic( 2236 tpdY_R : Time := 0 ns; 2237 tpdY_F : Time := 0 ns; 2238 strn : STRENGTH := strn_X01); 2239 port( 2240 I0 : in STD_LOGIC; 2241 I1 : in STD_LOGIC; 2242 Y : out STD_LOGIC); 2243 end component; 2244 2245 component OR2MAC 2246 generic( 2247 tpdY_R : Time := 0 ns; 2248 tpdY_F : Time := 0 ns; 2249 strn : STRENGTH := strn_X01); 2250 port( 2251 I0 : in STD_LOGIC; 2252 I1 : in STD_LOGIC; 2253 Y : out STD_LOGIC); 2254 end component; 2255 2256begin 2257 2258 -- Netlist 2259 U1 : NAND2MAC 2260 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2261 port map( I0 => n1, I1 => n2, Y => nq); 2262 2263 U2 : OR2MAC 2264 port map( I0 => i2, I1 => i3, Y => n2); 2265 2266 U3 : OR2MAC 2267 port map( I0 => i0, I1 => i1, Y => n1); 2268 2269 2270end UDSM; 2271 2272configuration CFG_nao2o22_x4_UDSM of nao2o22_x4 is 2273 for UDSM 2274 end for; 2275end CFG_nao2o22_x4_UDSM; 2276 2277 2278----- CELL nao22_x1 ----- 2279library IEEE; 2280use IEEE.STD_LOGIC_1164.all; 2281library SYNOPSYS; 2282use SYNOPSYS.attributes.REAL_NAME; 2283 2284-- entity declaration -- 2285entity nao22_x1 is 2286 generic( 2287 Timing_mesg: Boolean := True; 2288 Timing_xgen: Boolean := False; 2289 tpdi0_nq_R : Time := 0.294 ns; 2290 tpdi0_nq_F : Time := 0.226 ns; 2291 tpdi1_nq_R : Time := 0.218 ns; 2292 tpdi1_nq_F : Time := 0.287 ns; 2293 tpdi2_nq_R : Time := 0.165 ns; 2294 tpdi2_nq_F : Time := 0.238 ns; 2295 twdi0_R : Time := 0.000 ns; 2296 twdi0_F : Time := 0.000 ns; 2297 twdi1_R : Time := 0.000 ns; 2298 twdi1_F : Time := 0.000 ns; 2299 twdi2_R : Time := 0.000 ns; 2300 twdi2_F : Time := 0.000 ns); 2301 2302 port( 2303 i0 : in STD_LOGIC; 2304 i1 : in STD_LOGIC; 2305 i2 : in STD_LOGIC; 2306 nq : out STD_LOGIC); 2307end nao22_x1; 2308 2309-- architecture body -- 2310library IEEE_ASIC; 2311use IEEE.STD_LOGIC_MISC.all; 2312use SYNOPSYS.attributes.backplane; 2313use SYNOPSYS.attributes.PRIVATE; 2314use SYNOPSYS.attributes.ASIC_CELL; 2315 2316architecture UDSM of nao22_x1 is 2317 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2318 attribute PRIVATE of UDSM : architecture is TRUE; 2319 attribute ASIC_CELL of UDSM : architecture is TRUE; 2320 2321 signal n1 : STD_LOGIC; 2322 2323 component NAND2MAC 2324 generic( 2325 tpdY_R : Time := 0 ns; 2326 tpdY_F : Time := 0 ns; 2327 strn : STRENGTH := strn_X01); 2328 port( 2329 I0 : in STD_LOGIC; 2330 I1 : in STD_LOGIC; 2331 Y : out STD_LOGIC); 2332 end component; 2333 2334 component OR2MAC 2335 generic( 2336 tpdY_R : Time := 0 ns; 2337 tpdY_F : Time := 0 ns; 2338 strn : STRENGTH := strn_X01); 2339 port( 2340 I0 : in STD_LOGIC; 2341 I1 : in STD_LOGIC; 2342 Y : out STD_LOGIC); 2343 end component; 2344 2345begin 2346 2347 -- Netlist 2348 U1 : NAND2MAC 2349 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2350 port map( I0 => i2, I1 => n1, Y => nq); 2351 2352 U2 : OR2MAC 2353 port map( I0 => i0, I1 => i1, Y => n1); 2354 2355 2356end UDSM; 2357 2358configuration CFG_nao22_x1_UDSM of nao22_x1 is 2359 for UDSM 2360 end for; 2361end CFG_nao22_x1_UDSM; 2362 2363 2364----- CELL nao22_x4 ----- 2365library IEEE; 2366use IEEE.STD_LOGIC_1164.all; 2367library SYNOPSYS; 2368use SYNOPSYS.attributes.REAL_NAME; 2369 2370-- entity declaration -- 2371entity nao22_x4 is 2372 generic( 2373 Timing_mesg: Boolean := True; 2374 Timing_xgen: Boolean := False; 2375 tpdi0_nq_R : Time := 0.732 ns; 2376 tpdi0_nq_F : Time := 0.650 ns; 2377 tpdi1_nq_R : Time := 0.664 ns; 2378 tpdi1_nq_F : Time := 0.723 ns; 2379 tpdi2_nq_R : Time := 0.596 ns; 2380 tpdi2_nq_F : Time := 0.636 ns; 2381 twdi0_R : Time := 0.000 ns; 2382 twdi0_F : Time := 0.000 ns; 2383 twdi1_R : Time := 0.000 ns; 2384 twdi1_F : Time := 0.000 ns; 2385 twdi2_R : Time := 0.000 ns; 2386 twdi2_F : Time := 0.000 ns); 2387 2388 port( 2389 i0 : in STD_LOGIC; 2390 i1 : in STD_LOGIC; 2391 i2 : in STD_LOGIC; 2392 nq : out STD_LOGIC); 2393end nao22_x4; 2394 2395-- architecture body -- 2396library IEEE_ASIC; 2397use IEEE.STD_LOGIC_MISC.all; 2398use SYNOPSYS.attributes.backplane; 2399use SYNOPSYS.attributes.PRIVATE; 2400use SYNOPSYS.attributes.ASIC_CELL; 2401 2402architecture UDSM of nao22_x4 is 2403 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2404 attribute PRIVATE of UDSM : architecture is TRUE; 2405 attribute ASIC_CELL of UDSM : architecture is TRUE; 2406 2407 signal n1 : STD_LOGIC; 2408 2409 component NAND2MAC 2410 generic( 2411 tpdY_R : Time := 0 ns; 2412 tpdY_F : Time := 0 ns; 2413 strn : STRENGTH := strn_X01); 2414 port( 2415 I0 : in STD_LOGIC; 2416 I1 : in STD_LOGIC; 2417 Y : out STD_LOGIC); 2418 end component; 2419 2420 component OR2MAC 2421 generic( 2422 tpdY_R : Time := 0 ns; 2423 tpdY_F : Time := 0 ns; 2424 strn : STRENGTH := strn_X01); 2425 port( 2426 I0 : in STD_LOGIC; 2427 I1 : in STD_LOGIC; 2428 Y : out STD_LOGIC); 2429 end component; 2430 2431begin 2432 2433 -- Netlist 2434 U1 : NAND2MAC 2435 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2436 port map( I0 => i2, I1 => n1, Y => nq); 2437 2438 U2 : OR2MAC 2439 port map( I0 => i0, I1 => i1, Y => n1); 2440 2441 2442end UDSM; 2443 2444configuration CFG_nao22_x4_UDSM of nao22_x4 is 2445 for UDSM 2446 end for; 2447end CFG_nao22_x4_UDSM; 2448 2449 2450----- CELL nmx2_x1 ----- 2451library IEEE; 2452use IEEE.STD_LOGIC_1164.all; 2453library SYNOPSYS; 2454use SYNOPSYS.attributes.REAL_NAME; 2455 2456-- entity declaration -- 2457entity nmx2_x1 is 2458 generic( 2459 Timing_mesg: Boolean := True; 2460 Timing_xgen: Boolean := False; 2461 tpdcmd_nq_R : Time := 0.218 ns; 2462 tpdcmd_nq_F : Time := 0.287 ns; 2463 tpdi0_nq_R : Time := 0.217 ns; 2464 tpdi0_nq_F : Time := 0.256 ns; 2465 tpdi1_nq_R : Time := 0.217 ns; 2466 tpdi1_nq_F : Time := 0.256 ns; 2467 twdcmd_R : Time := 0.000 ns; 2468 twdcmd_F : Time := 0.000 ns; 2469 twdi0_R : Time := 0.000 ns; 2470 twdi0_F : Time := 0.000 ns; 2471 twdi1_R : Time := 0.000 ns; 2472 twdi1_F : Time := 0.000 ns); 2473 2474 port( 2475 cmd : in STD_LOGIC; 2476 i0 : in STD_LOGIC; 2477 i1 : in STD_LOGIC; 2478 nq : out STD_LOGIC); 2479end nmx2_x1; 2480 2481-- architecture body -- 2482library IEEE_ASIC; 2483use IEEE.STD_LOGIC_MISC.all; 2484use SYNOPSYS.attributes.backplane; 2485use SYNOPSYS.attributes.PRIVATE; 2486use SYNOPSYS.attributes.ASIC_CELL; 2487 2488architecture UDSM of nmx2_x1 is 2489 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2490 attribute PRIVATE of UDSM : architecture is TRUE; 2491 attribute ASIC_CELL of UDSM : architecture is TRUE; 2492 2493 signal n1 : STD_LOGIC; 2494 2495 component MUX2MAC 2496 generic( 2497 tpdY_R : Time := 0 ns; 2498 tpdY_F : Time := 0 ns; 2499 strn : STRENGTH := strn_X01); 2500 port( 2501 I0 : in STD_LOGIC; 2502 I1 : in STD_LOGIC; 2503 S0 : in STD_LOGIC; 2504 Y : out STD_LOGIC); 2505 end component; 2506 2507 component INVMAC 2508 generic( 2509 tpdY_R : Time := 0 ns; 2510 tpdY_F : Time := 0 ns; 2511 strn : STRENGTH := strn_X01); 2512 port( 2513 I0 : in STD_LOGIC; 2514 Y : out STD_LOGIC); 2515 end component; 2516 2517begin 2518 2519 -- Netlist 2520 U1 : MUX2MAC 2521 port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); 2522 2523 U2 : INVMAC 2524 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2525 port map( I0 => n1, Y => nq); 2526 2527 2528end UDSM; 2529 2530configuration CFG_nmx2_x1_UDSM of nmx2_x1 is 2531 for UDSM 2532 end for; 2533end CFG_nmx2_x1_UDSM; 2534 2535 2536----- CELL nmx2_x4 ----- 2537library IEEE; 2538use IEEE.STD_LOGIC_1164.all; 2539library SYNOPSYS; 2540use SYNOPSYS.attributes.REAL_NAME; 2541 2542-- entity declaration -- 2543entity nmx2_x4 is 2544 generic( 2545 Timing_mesg: Boolean := True; 2546 Timing_xgen: Boolean := False; 2547 tpdcmd_nq_R : Time := 0.632 ns; 2548 tpdcmd_nq_F : Time := 0.708 ns; 2549 tpdi0_nq_R : Time := 0.610 ns; 2550 tpdi0_nq_F : Time := 0.653 ns; 2551 tpdi1_nq_R : Time := 0.610 ns; 2552 tpdi1_nq_F : Time := 0.653 ns; 2553 twdcmd_R : Time := 0.000 ns; 2554 twdcmd_F : Time := 0.000 ns; 2555 twdi0_R : Time := 0.000 ns; 2556 twdi0_F : Time := 0.000 ns; 2557 twdi1_R : Time := 0.000 ns; 2558 twdi1_F : Time := 0.000 ns); 2559 2560 port( 2561 cmd : in STD_LOGIC; 2562 i0 : in STD_LOGIC; 2563 i1 : in STD_LOGIC; 2564 nq : out STD_LOGIC); 2565end nmx2_x4; 2566 2567-- architecture body -- 2568library IEEE_ASIC; 2569use IEEE.STD_LOGIC_MISC.all; 2570use SYNOPSYS.attributes.backplane; 2571use SYNOPSYS.attributes.PRIVATE; 2572use SYNOPSYS.attributes.ASIC_CELL; 2573 2574architecture UDSM of nmx2_x4 is 2575 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2576 attribute PRIVATE of UDSM : architecture is TRUE; 2577 attribute ASIC_CELL of UDSM : architecture is TRUE; 2578 2579 signal n1 : STD_LOGIC; 2580 2581 component MUX2MAC 2582 generic( 2583 tpdY_R : Time := 0 ns; 2584 tpdY_F : Time := 0 ns; 2585 strn : STRENGTH := strn_X01); 2586 port( 2587 I0 : in STD_LOGIC; 2588 I1 : in STD_LOGIC; 2589 S0 : in STD_LOGIC; 2590 Y : out STD_LOGIC); 2591 end component; 2592 2593 component INVMAC 2594 generic( 2595 tpdY_R : Time := 0 ns; 2596 tpdY_F : Time := 0 ns; 2597 strn : STRENGTH := strn_X01); 2598 port( 2599 I0 : in STD_LOGIC; 2600 Y : out STD_LOGIC); 2601 end component; 2602 2603begin 2604 2605 -- Netlist 2606 U1 : MUX2MAC 2607 port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); 2608 2609 U2 : INVMAC 2610 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2611 port map( I0 => n1, Y => nq); 2612 2613 2614end UDSM; 2615 2616configuration CFG_nmx2_x4_UDSM of nmx2_x4 is 2617 for UDSM 2618 end for; 2619end CFG_nmx2_x4_UDSM; 2620 2621 2622----- CELL nmx3_x1 ----- 2623library IEEE; 2624use IEEE.STD_LOGIC_1164.all; 2625library SYNOPSYS; 2626use SYNOPSYS.attributes.REAL_NAME; 2627 2628-- entity declaration -- 2629entity nmx3_x1 is 2630 generic( 2631 Timing_mesg: Boolean := True; 2632 Timing_xgen: Boolean := False; 2633 tpdcmd0_nq_R : Time := 0.356 ns; 2634 tpdcmd0_nq_F : Time := 0.495 ns; 2635 tpdcmd1_nq_R : Time := 0.414 ns; 2636 tpdcmd1_nq_F : Time := 0.566 ns; 2637 tpdi0_nq_R : Time := 0.315 ns; 2638 tpdi0_nq_F : Time := 0.441 ns; 2639 tpdi1_nq_R : Time := 0.429 ns; 2640 tpdi1_nq_F : Time := 0.582 ns; 2641 tpdi2_nq_R : Time := 0.429 ns; 2642 tpdi2_nq_F : Time := 0.582 ns; 2643 twdcmd0_R : Time := 0.000 ns; 2644 twdcmd0_F : Time := 0.000 ns; 2645 twdcmd1_R : Time := 0.000 ns; 2646 twdcmd1_F : Time := 0.000 ns; 2647 twdi0_R : Time := 0.000 ns; 2648 twdi0_F : Time := 0.000 ns; 2649 twdi1_R : Time := 0.000 ns; 2650 twdi1_F : Time := 0.000 ns; 2651 twdi2_R : Time := 0.000 ns; 2652 twdi2_F : Time := 0.000 ns); 2653 2654 port( 2655 cmd0 : in STD_LOGIC; 2656 cmd1 : in STD_LOGIC; 2657 i0 : in STD_LOGIC; 2658 i1 : in STD_LOGIC; 2659 i2 : in STD_LOGIC; 2660 nq : out STD_LOGIC); 2661end nmx3_x1; 2662 2663-- architecture body -- 2664library IEEE_ASIC; 2665use IEEE.STD_LOGIC_MISC.all; 2666use SYNOPSYS.attributes.backplane; 2667use SYNOPSYS.attributes.PRIVATE; 2668use SYNOPSYS.attributes.ASIC_CELL; 2669 2670architecture UDSM of nmx3_x1 is 2671 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2672 attribute PRIVATE of UDSM : architecture is TRUE; 2673 attribute ASIC_CELL of UDSM : architecture is TRUE; 2674 2675 signal n1, n2 : STD_LOGIC; 2676 2677 component MUX2MAC 2678 generic( 2679 tpdY_R : Time := 0 ns; 2680 tpdY_F : Time := 0 ns; 2681 strn : STRENGTH := strn_X01); 2682 port( 2683 I0 : in STD_LOGIC; 2684 I1 : in STD_LOGIC; 2685 S0 : in STD_LOGIC; 2686 Y : out STD_LOGIC); 2687 end component; 2688 2689 component INVMAC 2690 generic( 2691 tpdY_R : Time := 0 ns; 2692 tpdY_F : Time := 0 ns; 2693 strn : STRENGTH := strn_X01); 2694 port( 2695 I0 : in STD_LOGIC; 2696 Y : out STD_LOGIC); 2697 end component; 2698 2699begin 2700 2701 -- Netlist 2702 U1 : MUX2MAC 2703 port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); 2704 2705 U2 : MUX2MAC 2706 port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2); 2707 2708 U3 : INVMAC 2709 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2710 port map( I0 => n2, Y => nq); 2711 2712 2713end UDSM; 2714 2715configuration CFG_nmx3_x1_UDSM of nmx3_x1 is 2716 for UDSM 2717 end for; 2718end CFG_nmx3_x1_UDSM; 2719 2720 2721----- CELL nmx3_x4 ----- 2722library IEEE; 2723use IEEE.STD_LOGIC_1164.all; 2724library SYNOPSYS; 2725use SYNOPSYS.attributes.REAL_NAME; 2726 2727-- entity declaration -- 2728entity nmx3_x4 is 2729 generic( 2730 Timing_mesg: Boolean := True; 2731 Timing_xgen: Boolean := False; 2732 tpdcmd0_nq_R : Time := 0.790 ns; 2733 tpdcmd0_nq_F : Time := 0.936 ns; 2734 tpdcmd1_nq_R : Time := 0.866 ns; 2735 tpdcmd1_nq_F : Time := 1.048 ns; 2736 tpdi0_nq_R : Time := 0.748 ns; 2737 tpdi0_nq_F : Time := 0.900 ns; 2738 tpdi1_nq_R : Time := 0.869 ns; 2739 tpdi1_nq_F : Time := 1.053 ns; 2740 tpdi2_nq_R : Time := 0.869 ns; 2741 tpdi2_nq_F : Time := 1.053 ns; 2742 twdcmd0_R : Time := 0.000 ns; 2743 twdcmd0_F : Time := 0.000 ns; 2744 twdcmd1_R : Time := 0.000 ns; 2745 twdcmd1_F : Time := 0.000 ns; 2746 twdi0_R : Time := 0.000 ns; 2747 twdi0_F : Time := 0.000 ns; 2748 twdi1_R : Time := 0.000 ns; 2749 twdi1_F : Time := 0.000 ns; 2750 twdi2_R : Time := 0.000 ns; 2751 twdi2_F : Time := 0.000 ns); 2752 2753 port( 2754 cmd0 : in STD_LOGIC; 2755 cmd1 : in STD_LOGIC; 2756 i0 : in STD_LOGIC; 2757 i1 : in STD_LOGIC; 2758 i2 : in STD_LOGIC; 2759 nq : out STD_LOGIC); 2760end nmx3_x4; 2761 2762-- architecture body -- 2763library IEEE_ASIC; 2764use IEEE.STD_LOGIC_MISC.all; 2765use SYNOPSYS.attributes.backplane; 2766use SYNOPSYS.attributes.PRIVATE; 2767use SYNOPSYS.attributes.ASIC_CELL; 2768 2769architecture UDSM of nmx3_x4 is 2770 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2771 attribute PRIVATE of UDSM : architecture is TRUE; 2772 attribute ASIC_CELL of UDSM : architecture is TRUE; 2773 2774 signal n1, n2 : STD_LOGIC; 2775 2776 component MUX2MAC 2777 generic( 2778 tpdY_R : Time := 0 ns; 2779 tpdY_F : Time := 0 ns; 2780 strn : STRENGTH := strn_X01); 2781 port( 2782 I0 : in STD_LOGIC; 2783 I1 : in STD_LOGIC; 2784 S0 : in STD_LOGIC; 2785 Y : out STD_LOGIC); 2786 end component; 2787 2788 component INVMAC 2789 generic( 2790 tpdY_R : Time := 0 ns; 2791 tpdY_F : Time := 0 ns; 2792 strn : STRENGTH := strn_X01); 2793 port( 2794 I0 : in STD_LOGIC; 2795 Y : out STD_LOGIC); 2796 end component; 2797 2798begin 2799 2800 -- Netlist 2801 U1 : MUX2MAC 2802 port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); 2803 2804 U2 : MUX2MAC 2805 port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2); 2806 2807 U3 : INVMAC 2808 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2809 port map( I0 => n2, Y => nq); 2810 2811 2812end UDSM; 2813 2814configuration CFG_nmx3_x4_UDSM of nmx3_x4 is 2815 for UDSM 2816 end for; 2817end CFG_nmx3_x4_UDSM; 2818 2819 2820----- CELL no2_x1 ----- 2821library IEEE; 2822use IEEE.STD_LOGIC_1164.all; 2823library SYNOPSYS; 2824use SYNOPSYS.attributes.REAL_NAME; 2825 2826-- entity declaration -- 2827entity no2_x1 is 2828 generic( 2829 Timing_mesg: Boolean := True; 2830 Timing_xgen: Boolean := False; 2831 tpdi0_nq_R : Time := 0.298 ns; 2832 tpdi0_nq_F : Time := 0.121 ns; 2833 tpdi1_nq_R : Time := 0.193 ns; 2834 tpdi1_nq_F : Time := 0.161 ns; 2835 twdi0_R : Time := 0.000 ns; 2836 twdi0_F : Time := 0.000 ns; 2837 twdi1_R : Time := 0.000 ns; 2838 twdi1_F : Time := 0.000 ns); 2839 2840 port( 2841 i0 : in STD_LOGIC; 2842 i1 : in STD_LOGIC; 2843 nq : out STD_LOGIC); 2844end no2_x1; 2845 2846-- architecture body -- 2847library IEEE_ASIC; 2848use IEEE.STD_LOGIC_MISC.all; 2849use SYNOPSYS.attributes.backplane; 2850use SYNOPSYS.attributes.PRIVATE; 2851use SYNOPSYS.attributes.ASIC_CELL; 2852 2853architecture UDSM of no2_x1 is 2854 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2855 attribute PRIVATE of UDSM : architecture is TRUE; 2856 attribute ASIC_CELL of UDSM : architecture is TRUE; 2857 2858 component NOR2MAC 2859 generic( 2860 tpdY_R : Time := 0 ns; 2861 tpdY_F : Time := 0 ns; 2862 strn : STRENGTH := strn_X01); 2863 port( 2864 I0 : in STD_LOGIC; 2865 I1 : in STD_LOGIC; 2866 Y : out STD_LOGIC); 2867 end component; 2868 2869begin 2870 2871 -- Netlist 2872 U1 : NOR2MAC 2873 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2874 port map( I0 => i0, I1 => i1, Y => nq); 2875 2876 2877end UDSM; 2878 2879configuration CFG_no2_x1_UDSM of no2_x1 is 2880 for UDSM 2881 end for; 2882end CFG_no2_x1_UDSM; 2883 2884 2885----- CELL no2_x4 ----- 2886library IEEE; 2887use IEEE.STD_LOGIC_1164.all; 2888library SYNOPSYS; 2889use SYNOPSYS.attributes.REAL_NAME; 2890 2891-- entity declaration -- 2892entity no2_x4 is 2893 generic( 2894 Timing_mesg: Boolean := True; 2895 Timing_xgen: Boolean := False; 2896 tpdi0_nq_R : Time := 0.618 ns; 2897 tpdi0_nq_F : Time := 0.447 ns; 2898 tpdi1_nq_R : Time := 0.522 ns; 2899 tpdi1_nq_F : Time := 0.504 ns; 2900 twdi0_R : Time := 0.000 ns; 2901 twdi0_F : Time := 0.000 ns; 2902 twdi1_R : Time := 0.000 ns; 2903 twdi1_F : Time := 0.000 ns); 2904 2905 port( 2906 i0 : in STD_LOGIC; 2907 i1 : in STD_LOGIC; 2908 nq : out STD_LOGIC); 2909end no2_x4; 2910 2911-- architecture body -- 2912library IEEE_ASIC; 2913use IEEE.STD_LOGIC_MISC.all; 2914use SYNOPSYS.attributes.backplane; 2915use SYNOPSYS.attributes.PRIVATE; 2916use SYNOPSYS.attributes.ASIC_CELL; 2917 2918architecture UDSM of no2_x4 is 2919 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2920 attribute PRIVATE of UDSM : architecture is TRUE; 2921 attribute ASIC_CELL of UDSM : architecture is TRUE; 2922 2923 component NOR2MAC 2924 generic( 2925 tpdY_R : Time := 0 ns; 2926 tpdY_F : Time := 0 ns; 2927 strn : STRENGTH := strn_X01); 2928 port( 2929 I0 : in STD_LOGIC; 2930 I1 : in STD_LOGIC; 2931 Y : out STD_LOGIC); 2932 end component; 2933 2934begin 2935 2936 -- Netlist 2937 U1 : NOR2MAC 2938 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 2939 port map( I0 => i0, I1 => i1, Y => nq); 2940 2941 2942end UDSM; 2943 2944configuration CFG_no2_x4_UDSM of no2_x4 is 2945 for UDSM 2946 end for; 2947end CFG_no2_x4_UDSM; 2948 2949 2950----- CELL no3_x1 ----- 2951library IEEE; 2952use IEEE.STD_LOGIC_1164.all; 2953library SYNOPSYS; 2954use SYNOPSYS.attributes.REAL_NAME; 2955 2956-- entity declaration -- 2957entity no3_x1 is 2958 generic( 2959 Timing_mesg: Boolean := True; 2960 Timing_xgen: Boolean := False; 2961 tpdi0_nq_R : Time := 0.318 ns; 2962 tpdi0_nq_F : Time := 0.246 ns; 2963 tpdi1_nq_R : Time := 0.215 ns; 2964 tpdi1_nq_F : Time := 0.243 ns; 2965 tpdi2_nq_R : Time := 0.407 ns; 2966 tpdi2_nq_F : Time := 0.192 ns; 2967 twdi0_R : Time := 0.000 ns; 2968 twdi0_F : Time := 0.000 ns; 2969 twdi1_R : Time := 0.000 ns; 2970 twdi1_F : Time := 0.000 ns; 2971 twdi2_R : Time := 0.000 ns; 2972 twdi2_F : Time := 0.000 ns); 2973 2974 port( 2975 i0 : in STD_LOGIC; 2976 i1 : in STD_LOGIC; 2977 i2 : in STD_LOGIC; 2978 nq : out STD_LOGIC); 2979end no3_x1; 2980 2981-- architecture body -- 2982library IEEE_ASIC; 2983use IEEE.STD_LOGIC_MISC.all; 2984use SYNOPSYS.attributes.backplane; 2985use SYNOPSYS.attributes.PRIVATE; 2986use SYNOPSYS.attributes.ASIC_CELL; 2987 2988architecture UDSM of no3_x1 is 2989 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 2990 attribute PRIVATE of UDSM : architecture is TRUE; 2991 attribute ASIC_CELL of UDSM : architecture is TRUE; 2992 2993 component NOR3MAC 2994 generic( 2995 tpdY_R : Time := 0 ns; 2996 tpdY_F : Time := 0 ns; 2997 strn : STRENGTH := strn_X01); 2998 port( 2999 I0 : in STD_LOGIC; 3000 I1 : in STD_LOGIC; 3001 I2 : in STD_LOGIC; 3002 Y : out STD_LOGIC); 3003 end component; 3004 3005begin 3006 3007 -- Netlist 3008 U1 : NOR3MAC 3009 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3010 port map( I0 => i2, I1 => i0, I2 => i1, Y => nq); 3011 3012 3013end UDSM; 3014 3015configuration CFG_no3_x1_UDSM of no3_x1 is 3016 for UDSM 3017 end for; 3018end CFG_no3_x1_UDSM; 3019 3020 3021----- CELL no3_x4 ----- 3022library IEEE; 3023use IEEE.STD_LOGIC_1164.all; 3024library SYNOPSYS; 3025use SYNOPSYS.attributes.REAL_NAME; 3026 3027-- entity declaration -- 3028entity no3_x4 is 3029 generic( 3030 Timing_mesg: Boolean := True; 3031 Timing_xgen: Boolean := False; 3032 tpdi0_nq_R : Time := 0.722 ns; 3033 tpdi0_nq_F : Time := 0.561 ns; 3034 tpdi1_nq_R : Time := 0.638 ns; 3035 tpdi1_nq_F : Time := 0.623 ns; 3036 tpdi2_nq_R : Time := 0.545 ns; 3037 tpdi2_nq_F : Time := 0.640 ns; 3038 twdi0_R : Time := 0.000 ns; 3039 twdi0_F : Time := 0.000 ns; 3040 twdi1_R : Time := 0.000 ns; 3041 twdi1_F : Time := 0.000 ns; 3042 twdi2_R : Time := 0.000 ns; 3043 twdi2_F : Time := 0.000 ns); 3044 3045 port( 3046 i0 : in STD_LOGIC; 3047 i1 : in STD_LOGIC; 3048 i2 : in STD_LOGIC; 3049 nq : out STD_LOGIC); 3050end no3_x4; 3051 3052-- architecture body -- 3053library IEEE_ASIC; 3054use IEEE.STD_LOGIC_MISC.all; 3055use SYNOPSYS.attributes.backplane; 3056use SYNOPSYS.attributes.PRIVATE; 3057use SYNOPSYS.attributes.ASIC_CELL; 3058 3059architecture UDSM of no3_x4 is 3060 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3061 attribute PRIVATE of UDSM : architecture is TRUE; 3062 attribute ASIC_CELL of UDSM : architecture is TRUE; 3063 3064 component NOR3MAC 3065 generic( 3066 tpdY_R : Time := 0 ns; 3067 tpdY_F : Time := 0 ns; 3068 strn : STRENGTH := strn_X01); 3069 port( 3070 I0 : in STD_LOGIC; 3071 I1 : in STD_LOGIC; 3072 I2 : in STD_LOGIC; 3073 Y : out STD_LOGIC); 3074 end component; 3075 3076begin 3077 3078 -- Netlist 3079 U1 : NOR3MAC 3080 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3081 port map( I0 => i2, I1 => i0, I2 => i1, Y => nq); 3082 3083 3084end UDSM; 3085 3086configuration CFG_no3_x4_UDSM of no3_x4 is 3087 for UDSM 3088 end for; 3089end CFG_no3_x4_UDSM; 3090 3091 3092----- CELL no4_x1 ----- 3093library IEEE; 3094use IEEE.STD_LOGIC_1164.all; 3095library SYNOPSYS; 3096use SYNOPSYS.attributes.REAL_NAME; 3097 3098-- entity declaration -- 3099entity no4_x1 is 3100 generic( 3101 Timing_mesg: Boolean := True; 3102 Timing_xgen: Boolean := False; 3103 tpdi0_nq_R : Time := 0.330 ns; 3104 tpdi0_nq_F : Time := 0.340 ns; 3105 tpdi1_nq_R : Time := 0.230 ns; 3106 tpdi1_nq_F : Time := 0.320 ns; 3107 tpdi2_nq_R : Time := 0.419 ns; 3108 tpdi2_nq_F : Time := 0.333 ns; 3109 tpdi3_nq_R : Time := 0.499 ns; 3110 tpdi3_nq_F : Time := 0.271 ns; 3111 twdi0_R : Time := 0.000 ns; 3112 twdi0_F : Time := 0.000 ns; 3113 twdi1_R : Time := 0.000 ns; 3114 twdi1_F : Time := 0.000 ns; 3115 twdi2_R : Time := 0.000 ns; 3116 twdi2_F : Time := 0.000 ns; 3117 twdi3_R : Time := 0.000 ns; 3118 twdi3_F : Time := 0.000 ns); 3119 3120 port( 3121 i0 : in STD_LOGIC; 3122 i1 : in STD_LOGIC; 3123 i2 : in STD_LOGIC; 3124 i3 : in STD_LOGIC; 3125 nq : out STD_LOGIC); 3126end no4_x1; 3127 3128-- architecture body -- 3129library IEEE_ASIC; 3130use IEEE.STD_LOGIC_MISC.all; 3131use SYNOPSYS.attributes.backplane; 3132use SYNOPSYS.attributes.PRIVATE; 3133use SYNOPSYS.attributes.ASIC_CELL; 3134 3135architecture UDSM of no4_x1 is 3136 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3137 attribute PRIVATE of UDSM : architecture is TRUE; 3138 attribute ASIC_CELL of UDSM : architecture is TRUE; 3139 3140 component NOR4MAC 3141 generic( 3142 tpdY_R : Time := 0 ns; 3143 tpdY_F : Time := 0 ns; 3144 strn : STRENGTH := strn_X01); 3145 port( 3146 I0 : in STD_LOGIC; 3147 I1 : in STD_LOGIC; 3148 I2 : in STD_LOGIC; 3149 I3 : in STD_LOGIC; 3150 Y : out STD_LOGIC); 3151 end component; 3152 3153begin 3154 3155 -- Netlist 3156 U1 : NOR4MAC 3157 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3158 port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); 3159 3160 3161end UDSM; 3162 3163configuration CFG_no4_x1_UDSM of no4_x1 is 3164 for UDSM 3165 end for; 3166end CFG_no4_x1_UDSM; 3167 3168 3169----- CELL no4_x4 ----- 3170library IEEE; 3171use IEEE.STD_LOGIC_1164.all; 3172library SYNOPSYS; 3173use SYNOPSYS.attributes.REAL_NAME; 3174 3175-- entity declaration -- 3176entity no4_x4 is 3177 generic( 3178 Timing_mesg: Boolean := True; 3179 Timing_xgen: Boolean := False; 3180 tpdi0_nq_R : Time := 0.656 ns; 3181 tpdi0_nq_F : Time := 0.777 ns; 3182 tpdi1_nq_R : Time := 0.564 ns; 3183 tpdi1_nq_F : Time := 0.768 ns; 3184 tpdi2_nq_R : Time := 0.739 ns; 3185 tpdi2_nq_F : Time := 0.761 ns; 3186 tpdi3_nq_R : Time := 0.816 ns; 3187 tpdi3_nq_F : Time := 0.693 ns; 3188 twdi0_R : Time := 0.000 ns; 3189 twdi0_F : Time := 0.000 ns; 3190 twdi1_R : Time := 0.000 ns; 3191 twdi1_F : Time := 0.000 ns; 3192 twdi2_R : Time := 0.000 ns; 3193 twdi2_F : Time := 0.000 ns; 3194 twdi3_R : Time := 0.000 ns; 3195 twdi3_F : Time := 0.000 ns); 3196 3197 port( 3198 i0 : in STD_LOGIC; 3199 i1 : in STD_LOGIC; 3200 i2 : in STD_LOGIC; 3201 i3 : in STD_LOGIC; 3202 nq : out STD_LOGIC); 3203end no4_x4; 3204 3205-- architecture body -- 3206library IEEE_ASIC; 3207use IEEE.STD_LOGIC_MISC.all; 3208use SYNOPSYS.attributes.backplane; 3209use SYNOPSYS.attributes.PRIVATE; 3210use SYNOPSYS.attributes.ASIC_CELL; 3211 3212architecture UDSM of no4_x4 is 3213 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3214 attribute PRIVATE of UDSM : architecture is TRUE; 3215 attribute ASIC_CELL of UDSM : architecture is TRUE; 3216 3217 component NOR4MAC 3218 generic( 3219 tpdY_R : Time := 0 ns; 3220 tpdY_F : Time := 0 ns; 3221 strn : STRENGTH := strn_X01); 3222 port( 3223 I0 : in STD_LOGIC; 3224 I1 : in STD_LOGIC; 3225 I2 : in STD_LOGIC; 3226 I3 : in STD_LOGIC; 3227 Y : out STD_LOGIC); 3228 end component; 3229 3230begin 3231 3232 -- Netlist 3233 U1 : NOR4MAC 3234 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3235 port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); 3236 3237 3238end UDSM; 3239 3240configuration CFG_no4_x4_UDSM of no4_x4 is 3241 for UDSM 3242 end for; 3243end CFG_no4_x4_UDSM; 3244 3245 3246----- CELL noa2a2a2a24_x1 ----- 3247library IEEE; 3248use IEEE.STD_LOGIC_1164.all; 3249library SYNOPSYS; 3250use SYNOPSYS.attributes.REAL_NAME; 3251 3252-- entity declaration -- 3253entity noa2a2a2a24_x1 is 3254 generic( 3255 Timing_mesg: Boolean := True; 3256 Timing_xgen: Boolean := False; 3257 tpdi0_nq_R : Time := 0.649 ns; 3258 tpdi0_nq_F : Time := 0.606 ns; 3259 tpdi1_nq_R : Time := 0.775 ns; 3260 tpdi1_nq_F : Time := 0.562 ns; 3261 tpdi2_nq_R : Time := 0.550 ns; 3262 tpdi2_nq_F : Time := 0.662 ns; 3263 tpdi3_nq_R : Time := 0.667 ns; 3264 tpdi3_nq_F : Time := 0.616 ns; 3265 tpdi4_nq_R : Time := 0.419 ns; 3266 tpdi4_nq_F : Time := 0.613 ns; 3267 tpdi5_nq_R : Time := 0.329 ns; 3268 tpdi5_nq_F : Time := 0.662 ns; 3269 tpdi6_nq_R : Time := 0.270 ns; 3270 tpdi6_nq_F : Time := 0.535 ns; 3271 tpdi7_nq_R : Time := 0.200 ns; 3272 tpdi7_nq_F : Time := 0.591 ns; 3273 twdi0_R : Time := 0.000 ns; 3274 twdi0_F : Time := 0.000 ns; 3275 twdi1_R : Time := 0.000 ns; 3276 twdi1_F : Time := 0.000 ns; 3277 twdi2_R : Time := 0.000 ns; 3278 twdi2_F : Time := 0.000 ns; 3279 twdi3_R : Time := 0.000 ns; 3280 twdi3_F : Time := 0.000 ns; 3281 twdi4_R : Time := 0.000 ns; 3282 twdi4_F : Time := 0.000 ns; 3283 twdi5_R : Time := 0.000 ns; 3284 twdi5_F : Time := 0.000 ns; 3285 twdi6_R : Time := 0.000 ns; 3286 twdi6_F : Time := 0.000 ns; 3287 twdi7_R : Time := 0.000 ns; 3288 twdi7_F : Time := 0.000 ns); 3289 3290 port( 3291 i0 : in STD_LOGIC; 3292 i1 : in STD_LOGIC; 3293 i2 : in STD_LOGIC; 3294 i3 : in STD_LOGIC; 3295 i4 : in STD_LOGIC; 3296 i5 : in STD_LOGIC; 3297 i6 : in STD_LOGIC; 3298 i7 : in STD_LOGIC; 3299 nq : out STD_LOGIC); 3300end noa2a2a2a24_x1; 3301 3302-- architecture body -- 3303library IEEE_ASIC; 3304use IEEE.STD_LOGIC_MISC.all; 3305use SYNOPSYS.attributes.backplane; 3306use SYNOPSYS.attributes.PRIVATE; 3307use SYNOPSYS.attributes.ASIC_CELL; 3308 3309architecture UDSM of noa2a2a2a24_x1 is 3310 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3311 attribute PRIVATE of UDSM : architecture is TRUE; 3312 attribute ASIC_CELL of UDSM : architecture is TRUE; 3313 3314 signal n1, n2, n3, n4 : STD_LOGIC; 3315 3316 component AND4MAC 3317 generic( 3318 tpdY_R : Time := 0 ns; 3319 tpdY_F : Time := 0 ns; 3320 strn : STRENGTH := strn_X01); 3321 port( 3322 I0 : in STD_LOGIC; 3323 I1 : in STD_LOGIC; 3324 I2 : in STD_LOGIC; 3325 I3 : in STD_LOGIC; 3326 Y : out STD_LOGIC); 3327 end component; 3328 3329 component NAND2MAC 3330 generic( 3331 tpdY_R : Time := 0 ns; 3332 tpdY_F : Time := 0 ns; 3333 strn : STRENGTH := strn_X01); 3334 port( 3335 I0 : in STD_LOGIC; 3336 I1 : in STD_LOGIC; 3337 Y : out STD_LOGIC); 3338 end component; 3339 3340begin 3341 3342 -- Netlist 3343 U1 : AND4MAC 3344 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3345 port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); 3346 3347 U2 : NAND2MAC 3348 port map( I0 => i0, I1 => i1, Y => n4); 3349 3350 U3 : NAND2MAC 3351 port map( I0 => i2, I1 => i3, Y => n3); 3352 3353 U4 : NAND2MAC 3354 port map( I0 => i4, I1 => i5, Y => n2); 3355 3356 U5 : NAND2MAC 3357 port map( I0 => i6, I1 => i7, Y => n1); 3358 3359 3360end UDSM; 3361 3362configuration CFG_noa2a2a2a24_x1_UDSM of noa2a2a2a24_x1 is 3363 for UDSM 3364 end for; 3365end CFG_noa2a2a2a24_x1_UDSM; 3366 3367 3368----- CELL noa2a2a2a24_x4 ----- 3369library IEEE; 3370use IEEE.STD_LOGIC_1164.all; 3371library SYNOPSYS; 3372use SYNOPSYS.attributes.REAL_NAME; 3373 3374-- entity declaration -- 3375entity noa2a2a2a24_x4 is 3376 generic( 3377 Timing_mesg: Boolean := True; 3378 Timing_xgen: Boolean := False; 3379 tpdi0_nq_R : Time := 0.966 ns; 3380 tpdi0_nq_F : Time := 1.049 ns; 3381 tpdi1_nq_R : Time := 1.097 ns; 3382 tpdi1_nq_F : Time := 1.005 ns; 3383 tpdi2_nq_R : Time := 0.867 ns; 3384 tpdi2_nq_F : Time := 1.106 ns; 3385 tpdi3_nq_R : Time := 0.990 ns; 3386 tpdi3_nq_F : Time := 1.061 ns; 3387 tpdi4_nq_R : Time := 0.748 ns; 3388 tpdi4_nq_F : Time := 1.061 ns; 3389 tpdi5_nq_R : Time := 0.649 ns; 3390 tpdi5_nq_F : Time := 1.109 ns; 3391 tpdi6_nq_R : Time := 0.606 ns; 3392 tpdi6_nq_F : Time := 0.999 ns; 3393 tpdi7_nq_R : Time := 0.525 ns; 3394 tpdi7_nq_F : Time := 1.052 ns; 3395 twdi0_R : Time := 0.000 ns; 3396 twdi0_F : Time := 0.000 ns; 3397 twdi1_R : Time := 0.000 ns; 3398 twdi1_F : Time := 0.000 ns; 3399 twdi2_R : Time := 0.000 ns; 3400 twdi2_F : Time := 0.000 ns; 3401 twdi3_R : Time := 0.000 ns; 3402 twdi3_F : Time := 0.000 ns; 3403 twdi4_R : Time := 0.000 ns; 3404 twdi4_F : Time := 0.000 ns; 3405 twdi5_R : Time := 0.000 ns; 3406 twdi5_F : Time := 0.000 ns; 3407 twdi6_R : Time := 0.000 ns; 3408 twdi6_F : Time := 0.000 ns; 3409 twdi7_R : Time := 0.000 ns; 3410 twdi7_F : Time := 0.000 ns); 3411 3412 port( 3413 i0 : in STD_LOGIC; 3414 i1 : in STD_LOGIC; 3415 i2 : in STD_LOGIC; 3416 i3 : in STD_LOGIC; 3417 i4 : in STD_LOGIC; 3418 i5 : in STD_LOGIC; 3419 i6 : in STD_LOGIC; 3420 i7 : in STD_LOGIC; 3421 nq : out STD_LOGIC); 3422end noa2a2a2a24_x4; 3423 3424-- architecture body -- 3425library IEEE_ASIC; 3426use IEEE.STD_LOGIC_MISC.all; 3427use SYNOPSYS.attributes.backplane; 3428use SYNOPSYS.attributes.PRIVATE; 3429use SYNOPSYS.attributes.ASIC_CELL; 3430 3431architecture UDSM of noa2a2a2a24_x4 is 3432 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3433 attribute PRIVATE of UDSM : architecture is TRUE; 3434 attribute ASIC_CELL of UDSM : architecture is TRUE; 3435 3436 signal n1, n2, n3, n4 : STD_LOGIC; 3437 3438 component AND4MAC 3439 generic( 3440 tpdY_R : Time := 0 ns; 3441 tpdY_F : Time := 0 ns; 3442 strn : STRENGTH := strn_X01); 3443 port( 3444 I0 : in STD_LOGIC; 3445 I1 : in STD_LOGIC; 3446 I2 : in STD_LOGIC; 3447 I3 : in STD_LOGIC; 3448 Y : out STD_LOGIC); 3449 end component; 3450 3451 component NAND2MAC 3452 generic( 3453 tpdY_R : Time := 0 ns; 3454 tpdY_F : Time := 0 ns; 3455 strn : STRENGTH := strn_X01); 3456 port( 3457 I0 : in STD_LOGIC; 3458 I1 : in STD_LOGIC; 3459 Y : out STD_LOGIC); 3460 end component; 3461 3462begin 3463 3464 -- Netlist 3465 U1 : AND4MAC 3466 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3467 port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); 3468 3469 U2 : NAND2MAC 3470 port map( I0 => i0, I1 => i1, Y => n4); 3471 3472 U3 : NAND2MAC 3473 port map( I0 => i2, I1 => i3, Y => n3); 3474 3475 U4 : NAND2MAC 3476 port map( I0 => i4, I1 => i5, Y => n2); 3477 3478 U5 : NAND2MAC 3479 port map( I0 => i6, I1 => i7, Y => n1); 3480 3481 3482end UDSM; 3483 3484configuration CFG_noa2a2a2a24_x4_UDSM of noa2a2a2a24_x4 is 3485 for UDSM 3486 end for; 3487end CFG_noa2a2a2a24_x4_UDSM; 3488 3489 3490----- CELL noa2a2a23_x1 ----- 3491library IEEE; 3492use IEEE.STD_LOGIC_1164.all; 3493library SYNOPSYS; 3494use SYNOPSYS.attributes.REAL_NAME; 3495 3496-- entity declaration -- 3497entity noa2a2a23_x1 is 3498 generic( 3499 Timing_mesg: Boolean := True; 3500 Timing_xgen: Boolean := False; 3501 tpdi0_nq_R : Time := 0.525 ns; 3502 tpdi0_nq_F : Time := 0.425 ns; 3503 tpdi1_nq_R : Time := 0.643 ns; 3504 tpdi1_nq_F : Time := 0.388 ns; 3505 tpdi2_nq_R : Time := 0.307 ns; 3506 tpdi2_nq_F : Time := 0.479 ns; 3507 tpdi3_nq_R : Time := 0.398 ns; 3508 tpdi3_nq_F : Time := 0.438 ns; 3509 tpdi4_nq_R : Time := 0.250 ns; 3510 tpdi4_nq_F : Time := 0.416 ns; 3511 tpdi5_nq_R : Time := 0.178 ns; 3512 tpdi5_nq_F : Time := 0.464 ns; 3513 twdi0_R : Time := 0.000 ns; 3514 twdi0_F : Time := 0.000 ns; 3515 twdi1_R : Time := 0.000 ns; 3516 twdi1_F : Time := 0.000 ns; 3517 twdi2_R : Time := 0.000 ns; 3518 twdi2_F : Time := 0.000 ns; 3519 twdi3_R : Time := 0.000 ns; 3520 twdi3_F : Time := 0.000 ns; 3521 twdi4_R : Time := 0.000 ns; 3522 twdi4_F : Time := 0.000 ns; 3523 twdi5_R : Time := 0.000 ns; 3524 twdi5_F : Time := 0.000 ns); 3525 3526 port( 3527 i0 : in STD_LOGIC; 3528 i1 : in STD_LOGIC; 3529 i2 : in STD_LOGIC; 3530 i3 : in STD_LOGIC; 3531 i4 : in STD_LOGIC; 3532 i5 : in STD_LOGIC; 3533 nq : out STD_LOGIC); 3534end noa2a2a23_x1; 3535 3536-- architecture body -- 3537library IEEE_ASIC; 3538use IEEE.STD_LOGIC_MISC.all; 3539use SYNOPSYS.attributes.backplane; 3540use SYNOPSYS.attributes.PRIVATE; 3541use SYNOPSYS.attributes.ASIC_CELL; 3542 3543architecture UDSM of noa2a2a23_x1 is 3544 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3545 attribute PRIVATE of UDSM : architecture is TRUE; 3546 attribute ASIC_CELL of UDSM : architecture is TRUE; 3547 3548 signal n1, n2, n3 : STD_LOGIC; 3549 3550 component AND3MAC 3551 generic( 3552 tpdY_R : Time := 0 ns; 3553 tpdY_F : Time := 0 ns; 3554 strn : STRENGTH := strn_X01); 3555 port( 3556 I0 : in STD_LOGIC; 3557 I1 : in STD_LOGIC; 3558 I2 : in STD_LOGIC; 3559 Y : out STD_LOGIC); 3560 end component; 3561 3562 component NAND2MAC 3563 generic( 3564 tpdY_R : Time := 0 ns; 3565 tpdY_F : Time := 0 ns; 3566 strn : STRENGTH := strn_X01); 3567 port( 3568 I0 : in STD_LOGIC; 3569 I1 : in STD_LOGIC; 3570 Y : out STD_LOGIC); 3571 end component; 3572 3573begin 3574 3575 -- Netlist 3576 U1 : AND3MAC 3577 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3578 port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); 3579 3580 U2 : NAND2MAC 3581 port map( I0 => i2, I1 => i3, Y => n2); 3582 3583 U3 : NAND2MAC 3584 port map( I0 => i0, I1 => i1, Y => n1); 3585 3586 U4 : NAND2MAC 3587 port map( I0 => i4, I1 => i5, Y => n3); 3588 3589 3590end UDSM; 3591 3592configuration CFG_noa2a2a23_x1_UDSM of noa2a2a23_x1 is 3593 for UDSM 3594 end for; 3595end CFG_noa2a2a23_x1_UDSM; 3596 3597 3598----- CELL noa2a2a23_x4 ----- 3599library IEEE; 3600use IEEE.STD_LOGIC_1164.all; 3601library SYNOPSYS; 3602use SYNOPSYS.attributes.REAL_NAME; 3603 3604-- entity declaration -- 3605entity noa2a2a23_x4 is 3606 generic( 3607 Timing_mesg: Boolean := True; 3608 Timing_xgen: Boolean := False; 3609 tpdi0_nq_R : Time := 0.834 ns; 3610 tpdi0_nq_F : Time := 0.814 ns; 3611 tpdi1_nq_R : Time := 0.955 ns; 3612 tpdi1_nq_F : Time := 0.778 ns; 3613 tpdi2_nq_R : Time := 0.620 ns; 3614 tpdi2_nq_F : Time := 0.873 ns; 3615 tpdi3_nq_R : Time := 0.716 ns; 3616 tpdi3_nq_F : Time := 0.833 ns; 3617 tpdi4_nq_R : Time := 0.574 ns; 3618 tpdi4_nq_F : Time := 0.819 ns; 3619 tpdi5_nq_R : Time := 0.496 ns; 3620 tpdi5_nq_F : Time := 0.865 ns; 3621 twdi0_R : Time := 0.000 ns; 3622 twdi0_F : Time := 0.000 ns; 3623 twdi1_R : Time := 0.000 ns; 3624 twdi1_F : Time := 0.000 ns; 3625 twdi2_R : Time := 0.000 ns; 3626 twdi2_F : Time := 0.000 ns; 3627 twdi3_R : Time := 0.000 ns; 3628 twdi3_F : Time := 0.000 ns; 3629 twdi4_R : Time := 0.000 ns; 3630 twdi4_F : Time := 0.000 ns; 3631 twdi5_R : Time := 0.000 ns; 3632 twdi5_F : Time := 0.000 ns); 3633 3634 port( 3635 i0 : in STD_LOGIC; 3636 i1 : in STD_LOGIC; 3637 i2 : in STD_LOGIC; 3638 i3 : in STD_LOGIC; 3639 i4 : in STD_LOGIC; 3640 i5 : in STD_LOGIC; 3641 nq : out STD_LOGIC); 3642end noa2a2a23_x4; 3643 3644-- architecture body -- 3645library IEEE_ASIC; 3646use IEEE.STD_LOGIC_MISC.all; 3647use SYNOPSYS.attributes.backplane; 3648use SYNOPSYS.attributes.PRIVATE; 3649use SYNOPSYS.attributes.ASIC_CELL; 3650 3651architecture UDSM of noa2a2a23_x4 is 3652 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3653 attribute PRIVATE of UDSM : architecture is TRUE; 3654 attribute ASIC_CELL of UDSM : architecture is TRUE; 3655 3656 signal n1, n2, n3 : STD_LOGIC; 3657 3658 component AND3MAC 3659 generic( 3660 tpdY_R : Time := 0 ns; 3661 tpdY_F : Time := 0 ns; 3662 strn : STRENGTH := strn_X01); 3663 port( 3664 I0 : in STD_LOGIC; 3665 I1 : in STD_LOGIC; 3666 I2 : in STD_LOGIC; 3667 Y : out STD_LOGIC); 3668 end component; 3669 3670 component NAND2MAC 3671 generic( 3672 tpdY_R : Time := 0 ns; 3673 tpdY_F : Time := 0 ns; 3674 strn : STRENGTH := strn_X01); 3675 port( 3676 I0 : in STD_LOGIC; 3677 I1 : in STD_LOGIC; 3678 Y : out STD_LOGIC); 3679 end component; 3680 3681begin 3682 3683 -- Netlist 3684 U1 : AND3MAC 3685 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3686 port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); 3687 3688 U2 : NAND2MAC 3689 port map( I0 => i2, I1 => i3, Y => n2); 3690 3691 U3 : NAND2MAC 3692 port map( I0 => i0, I1 => i1, Y => n1); 3693 3694 U4 : NAND2MAC 3695 port map( I0 => i4, I1 => i5, Y => n3); 3696 3697 3698end UDSM; 3699 3700configuration CFG_noa2a2a23_x4_UDSM of noa2a2a23_x4 is 3701 for UDSM 3702 end for; 3703end CFG_noa2a2a23_x4_UDSM; 3704 3705 3706----- CELL noa2a22_x1 ----- 3707library IEEE; 3708use IEEE.STD_LOGIC_1164.all; 3709library SYNOPSYS; 3710use SYNOPSYS.attributes.REAL_NAME; 3711 3712-- entity declaration -- 3713entity noa2a22_x1 is 3714 generic( 3715 Timing_mesg: Boolean := True; 3716 Timing_xgen: Boolean := False; 3717 tpdi0_nq_R : Time := 0.151 ns; 3718 tpdi0_nq_F : Time := 0.327 ns; 3719 tpdi1_nq_R : Time := 0.218 ns; 3720 tpdi1_nq_F : Time := 0.287 ns; 3721 tpdi2_nq_R : Time := 0.284 ns; 3722 tpdi2_nq_F : Time := 0.289 ns; 3723 tpdi3_nq_R : Time := 0.372 ns; 3724 tpdi3_nq_F : Time := 0.256 ns; 3725 twdi0_R : Time := 0.000 ns; 3726 twdi0_F : Time := 0.000 ns; 3727 twdi1_R : Time := 0.000 ns; 3728 twdi1_F : Time := 0.000 ns; 3729 twdi2_R : Time := 0.000 ns; 3730 twdi2_F : Time := 0.000 ns; 3731 twdi3_R : Time := 0.000 ns; 3732 twdi3_F : Time := 0.000 ns); 3733 3734 port( 3735 i0 : in STD_LOGIC; 3736 i1 : in STD_LOGIC; 3737 i2 : in STD_LOGIC; 3738 i3 : in STD_LOGIC; 3739 nq : out STD_LOGIC); 3740end noa2a22_x1; 3741 3742-- architecture body -- 3743library IEEE_ASIC; 3744use IEEE.STD_LOGIC_MISC.all; 3745use SYNOPSYS.attributes.backplane; 3746use SYNOPSYS.attributes.PRIVATE; 3747use SYNOPSYS.attributes.ASIC_CELL; 3748 3749architecture UDSM of noa2a22_x1 is 3750 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3751 attribute PRIVATE of UDSM : architecture is TRUE; 3752 attribute ASIC_CELL of UDSM : architecture is TRUE; 3753 3754 signal n1, n2 : STD_LOGIC; 3755 3756 component AND2MAC 3757 generic( 3758 tpdY_R : Time := 0 ns; 3759 tpdY_F : Time := 0 ns; 3760 strn : STRENGTH := strn_X01); 3761 port( 3762 I0 : in STD_LOGIC; 3763 I1 : in STD_LOGIC; 3764 Y : out STD_LOGIC); 3765 end component; 3766 3767 component NAND2MAC 3768 generic( 3769 tpdY_R : Time := 0 ns; 3770 tpdY_F : Time := 0 ns; 3771 strn : STRENGTH := strn_X01); 3772 port( 3773 I0 : in STD_LOGIC; 3774 I1 : in STD_LOGIC; 3775 Y : out STD_LOGIC); 3776 end component; 3777 3778begin 3779 3780 -- Netlist 3781 U1 : AND2MAC 3782 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3783 port map( I0 => n1, I1 => n2, Y => nq); 3784 3785 U2 : NAND2MAC 3786 port map( I0 => i2, I1 => i3, Y => n2); 3787 3788 U3 : NAND2MAC 3789 port map( I0 => i0, I1 => i1, Y => n1); 3790 3791 3792end UDSM; 3793 3794configuration CFG_noa2a22_x1_UDSM of noa2a22_x1 is 3795 for UDSM 3796 end for; 3797end CFG_noa2a22_x1_UDSM; 3798 3799 3800----- CELL noa2a22_x4 ----- 3801library IEEE; 3802use IEEE.STD_LOGIC_1164.all; 3803library SYNOPSYS; 3804use SYNOPSYS.attributes.REAL_NAME; 3805 3806-- entity declaration -- 3807entity noa2a22_x4 is 3808 generic( 3809 Timing_mesg: Boolean := True; 3810 Timing_xgen: Boolean := False; 3811 tpdi0_nq_R : Time := 0.562 ns; 3812 tpdi0_nq_F : Time := 0.745 ns; 3813 tpdi1_nq_R : Time := 0.646 ns; 3814 tpdi1_nq_F : Time := 0.714 ns; 3815 tpdi2_nq_R : Time := 0.701 ns; 3816 tpdi2_nq_F : Time := 0.703 ns; 3817 tpdi3_nq_R : Time := 0.805 ns; 3818 tpdi3_nq_F : Time := 0.677 ns; 3819 twdi0_R : Time := 0.000 ns; 3820 twdi0_F : Time := 0.000 ns; 3821 twdi1_R : Time := 0.000 ns; 3822 twdi1_F : Time := 0.000 ns; 3823 twdi2_R : Time := 0.000 ns; 3824 twdi2_F : Time := 0.000 ns; 3825 twdi3_R : Time := 0.000 ns; 3826 twdi3_F : Time := 0.000 ns); 3827 3828 port( 3829 i0 : in STD_LOGIC; 3830 i1 : in STD_LOGIC; 3831 i2 : in STD_LOGIC; 3832 i3 : in STD_LOGIC; 3833 nq : out STD_LOGIC); 3834end noa2a22_x4; 3835 3836-- architecture body -- 3837library IEEE_ASIC; 3838use IEEE.STD_LOGIC_MISC.all; 3839use SYNOPSYS.attributes.backplane; 3840use SYNOPSYS.attributes.PRIVATE; 3841use SYNOPSYS.attributes.ASIC_CELL; 3842 3843architecture UDSM of noa2a22_x4 is 3844 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3845 attribute PRIVATE of UDSM : architecture is TRUE; 3846 attribute ASIC_CELL of UDSM : architecture is TRUE; 3847 3848 signal n1, n2 : STD_LOGIC; 3849 3850 component AND2MAC 3851 generic( 3852 tpdY_R : Time := 0 ns; 3853 tpdY_F : Time := 0 ns; 3854 strn : STRENGTH := strn_X01); 3855 port( 3856 I0 : in STD_LOGIC; 3857 I1 : in STD_LOGIC; 3858 Y : out STD_LOGIC); 3859 end component; 3860 3861 component NAND2MAC 3862 generic( 3863 tpdY_R : Time := 0 ns; 3864 tpdY_F : Time := 0 ns; 3865 strn : STRENGTH := strn_X01); 3866 port( 3867 I0 : in STD_LOGIC; 3868 I1 : in STD_LOGIC; 3869 Y : out STD_LOGIC); 3870 end component; 3871 3872begin 3873 3874 -- Netlist 3875 U1 : AND2MAC 3876 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3877 port map( I0 => n1, I1 => n2, Y => nq); 3878 3879 U2 : NAND2MAC 3880 port map( I0 => i2, I1 => i3, Y => n2); 3881 3882 U3 : NAND2MAC 3883 port map( I0 => i0, I1 => i1, Y => n1); 3884 3885 3886end UDSM; 3887 3888configuration CFG_noa2a22_x4_UDSM of noa2a22_x4 is 3889 for UDSM 3890 end for; 3891end CFG_noa2a22_x4_UDSM; 3892 3893 3894----- CELL noa2ao222_x1 ----- 3895library IEEE; 3896use IEEE.STD_LOGIC_1164.all; 3897library SYNOPSYS; 3898use SYNOPSYS.attributes.REAL_NAME; 3899 3900-- entity declaration -- 3901entity noa2ao222_x1 is 3902 generic( 3903 Timing_mesg: Boolean := True; 3904 Timing_xgen: Boolean := False; 3905 tpdi0_nq_R : Time := 0.348 ns; 3906 tpdi0_nq_F : Time := 0.422 ns; 3907 tpdi1_nq_R : Time := 0.440 ns; 3908 tpdi1_nq_F : Time := 0.378 ns; 3909 tpdi2_nq_R : Time := 0.186 ns; 3910 tpdi2_nq_F : Time := 0.473 ns; 3911 tpdi3_nq_R : Time := 0.256 ns; 3912 tpdi3_nq_F : Time := 0.459 ns; 3913 tpdi4_nq_R : Time := 0.240 ns; 3914 tpdi4_nq_F : Time := 0.309 ns; 3915 twdi0_R : Time := 0.000 ns; 3916 twdi0_F : Time := 0.000 ns; 3917 twdi1_R : Time := 0.000 ns; 3918 twdi1_F : Time := 0.000 ns; 3919 twdi2_R : Time := 0.000 ns; 3920 twdi2_F : Time := 0.000 ns; 3921 twdi3_R : Time := 0.000 ns; 3922 twdi3_F : Time := 0.000 ns; 3923 twdi4_R : Time := 0.000 ns; 3924 twdi4_F : Time := 0.000 ns); 3925 3926 port( 3927 i0 : in STD_LOGIC; 3928 i1 : in STD_LOGIC; 3929 i2 : in STD_LOGIC; 3930 i3 : in STD_LOGIC; 3931 i4 : in STD_LOGIC; 3932 nq : out STD_LOGIC); 3933end noa2ao222_x1; 3934 3935-- architecture body -- 3936library IEEE_ASIC; 3937use IEEE.STD_LOGIC_MISC.all; 3938use SYNOPSYS.attributes.backplane; 3939use SYNOPSYS.attributes.PRIVATE; 3940use SYNOPSYS.attributes.ASIC_CELL; 3941 3942architecture UDSM of noa2ao222_x1 is 3943 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 3944 attribute PRIVATE of UDSM : architecture is TRUE; 3945 attribute ASIC_CELL of UDSM : architecture is TRUE; 3946 3947 signal n1, n2, n3 : STD_LOGIC; 3948 3949 component AND2MAC 3950 generic( 3951 tpdY_R : Time := 0 ns; 3952 tpdY_F : Time := 0 ns; 3953 strn : STRENGTH := strn_X01); 3954 port( 3955 I0 : in STD_LOGIC; 3956 I1 : in STD_LOGIC; 3957 Y : out STD_LOGIC); 3958 end component; 3959 3960 component OR2MAC 3961 generic( 3962 tpdY_R : Time := 0 ns; 3963 tpdY_F : Time := 0 ns; 3964 strn : STRENGTH := strn_X01); 3965 port( 3966 I0 : in STD_LOGIC; 3967 I1 : in STD_LOGIC; 3968 Y : out STD_LOGIC); 3969 end component; 3970 3971 component NAND2MAC 3972 generic( 3973 tpdY_R : Time := 0 ns; 3974 tpdY_F : Time := 0 ns; 3975 strn : STRENGTH := strn_X01); 3976 port( 3977 I0 : in STD_LOGIC; 3978 I1 : in STD_LOGIC; 3979 Y : out STD_LOGIC); 3980 end component; 3981 3982begin 3983 3984 -- Netlist 3985 U1 : AND2MAC 3986 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 3987 port map( I0 => n1, I1 => n2, Y => nq); 3988 3989 U2 : OR2MAC 3990 port map( I0 => i2, I1 => i3, Y => n3); 3991 3992 U3 : NAND2MAC 3993 port map( I0 => i4, I1 => n3, Y => n2); 3994 3995 U4 : NAND2MAC 3996 port map( I0 => i0, I1 => i1, Y => n1); 3997 3998 3999end UDSM; 4000 4001configuration CFG_noa2ao222_x1_UDSM of noa2ao222_x1 is 4002 for UDSM 4003 end for; 4004end CFG_noa2ao222_x1_UDSM; 4005 4006 4007----- CELL noa2ao222_x4 ----- 4008library IEEE; 4009use IEEE.STD_LOGIC_1164.all; 4010library SYNOPSYS; 4011use SYNOPSYS.attributes.REAL_NAME; 4012 4013-- entity declaration -- 4014entity noa2ao222_x4 is 4015 generic( 4016 Timing_mesg: Boolean := True; 4017 Timing_xgen: Boolean := False; 4018 tpdi0_nq_R : Time := 0.684 ns; 4019 tpdi0_nq_F : Time := 0.801 ns; 4020 tpdi1_nq_R : Time := 0.780 ns; 4021 tpdi1_nq_F : Time := 0.758 ns; 4022 tpdi2_nq_R : Time := 0.638 ns; 4023 tpdi2_nq_F : Time := 0.809 ns; 4024 tpdi3_nq_R : Time := 0.732 ns; 4025 tpdi3_nq_F : Time := 0.795 ns; 4026 tpdi4_nq_R : Time := 0.718 ns; 4027 tpdi4_nq_F : Time := 0.664 ns; 4028 twdi0_R : Time := 0.000 ns; 4029 twdi0_F : Time := 0.000 ns; 4030 twdi1_R : Time := 0.000 ns; 4031 twdi1_F : Time := 0.000 ns; 4032 twdi2_R : Time := 0.000 ns; 4033 twdi2_F : Time := 0.000 ns; 4034 twdi3_R : Time := 0.000 ns; 4035 twdi3_F : Time := 0.000 ns; 4036 twdi4_R : Time := 0.000 ns; 4037 twdi4_F : Time := 0.000 ns); 4038 4039 port( 4040 i0 : in STD_LOGIC; 4041 i1 : in STD_LOGIC; 4042 i2 : in STD_LOGIC; 4043 i3 : in STD_LOGIC; 4044 i4 : in STD_LOGIC; 4045 nq : out STD_LOGIC); 4046end noa2ao222_x4; 4047 4048-- architecture body -- 4049library IEEE_ASIC; 4050use IEEE.STD_LOGIC_MISC.all; 4051use SYNOPSYS.attributes.backplane; 4052use SYNOPSYS.attributes.PRIVATE; 4053use SYNOPSYS.attributes.ASIC_CELL; 4054 4055architecture UDSM of noa2ao222_x4 is 4056 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4057 attribute PRIVATE of UDSM : architecture is TRUE; 4058 attribute ASIC_CELL of UDSM : architecture is TRUE; 4059 4060 signal n1, n2, n3 : STD_LOGIC; 4061 4062 component AND2MAC 4063 generic( 4064 tpdY_R : Time := 0 ns; 4065 tpdY_F : Time := 0 ns; 4066 strn : STRENGTH := strn_X01); 4067 port( 4068 I0 : in STD_LOGIC; 4069 I1 : in STD_LOGIC; 4070 Y : out STD_LOGIC); 4071 end component; 4072 4073 component OR2MAC 4074 generic( 4075 tpdY_R : Time := 0 ns; 4076 tpdY_F : Time := 0 ns; 4077 strn : STRENGTH := strn_X01); 4078 port( 4079 I0 : in STD_LOGIC; 4080 I1 : in STD_LOGIC; 4081 Y : out STD_LOGIC); 4082 end component; 4083 4084 component NAND2MAC 4085 generic( 4086 tpdY_R : Time := 0 ns; 4087 tpdY_F : Time := 0 ns; 4088 strn : STRENGTH := strn_X01); 4089 port( 4090 I0 : in STD_LOGIC; 4091 I1 : in STD_LOGIC; 4092 Y : out STD_LOGIC); 4093 end component; 4094 4095begin 4096 4097 -- Netlist 4098 U1 : AND2MAC 4099 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4100 port map( I0 => n1, I1 => n2, Y => nq); 4101 4102 U2 : OR2MAC 4103 port map( I0 => i2, I1 => i3, Y => n3); 4104 4105 U3 : NAND2MAC 4106 port map( I0 => i4, I1 => n3, Y => n2); 4107 4108 U4 : NAND2MAC 4109 port map( I0 => i0, I1 => i1, Y => n1); 4110 4111 4112end UDSM; 4113 4114configuration CFG_noa2ao222_x4_UDSM of noa2ao222_x4 is 4115 for UDSM 4116 end for; 4117end CFG_noa2ao222_x4_UDSM; 4118 4119 4120----- CELL noa3ao322_x1 ----- 4121library IEEE; 4122use IEEE.STD_LOGIC_1164.all; 4123library SYNOPSYS; 4124use SYNOPSYS.attributes.REAL_NAME; 4125 4126-- entity declaration -- 4127entity noa3ao322_x1 is 4128 generic( 4129 Timing_mesg: Boolean := True; 4130 Timing_xgen: Boolean := False; 4131 tpdi0_nq_R : Time := 0.396 ns; 4132 tpdi0_nq_F : Time := 0.616 ns; 4133 tpdi1_nq_R : Time := 0.486 ns; 4134 tpdi1_nq_F : Time := 0.552 ns; 4135 tpdi2_nq_R : Time := 0.546 ns; 4136 tpdi2_nq_F : Time := 0.488 ns; 4137 tpdi3_nq_R : Time := 0.196 ns; 4138 tpdi3_nq_F : Time := 0.599 ns; 4139 tpdi4_nq_R : Time := 0.264 ns; 4140 tpdi4_nq_F : Time := 0.608 ns; 4141 tpdi5_nq_R : Time := 0.328 ns; 4142 tpdi5_nq_F : Time := 0.581 ns; 4143 tpdi6_nq_R : Time := 0.246 ns; 4144 tpdi6_nq_F : Time := 0.311 ns; 4145 twdi0_R : Time := 0.000 ns; 4146 twdi0_F : Time := 0.000 ns; 4147 twdi1_R : Time := 0.000 ns; 4148 twdi1_F : Time := 0.000 ns; 4149 twdi2_R : Time := 0.000 ns; 4150 twdi2_F : Time := 0.000 ns; 4151 twdi3_R : Time := 0.000 ns; 4152 twdi3_F : Time := 0.000 ns; 4153 twdi4_R : Time := 0.000 ns; 4154 twdi4_F : Time := 0.000 ns; 4155 twdi5_R : Time := 0.000 ns; 4156 twdi5_F : Time := 0.000 ns; 4157 twdi6_R : Time := 0.000 ns; 4158 twdi6_F : Time := 0.000 ns); 4159 4160 port( 4161 i0 : in STD_LOGIC; 4162 i1 : in STD_LOGIC; 4163 i2 : in STD_LOGIC; 4164 i3 : in STD_LOGIC; 4165 i4 : in STD_LOGIC; 4166 i5 : in STD_LOGIC; 4167 i6 : in STD_LOGIC; 4168 nq : out STD_LOGIC); 4169end noa3ao322_x1; 4170 4171-- architecture body -- 4172library IEEE_ASIC; 4173use IEEE.STD_LOGIC_MISC.all; 4174use SYNOPSYS.attributes.backplane; 4175use SYNOPSYS.attributes.PRIVATE; 4176use SYNOPSYS.attributes.ASIC_CELL; 4177 4178architecture UDSM of noa3ao322_x1 is 4179 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4180 attribute PRIVATE of UDSM : architecture is TRUE; 4181 attribute ASIC_CELL of UDSM : architecture is TRUE; 4182 4183 signal n1, n2, n3 : STD_LOGIC; 4184 4185 component AND2MAC 4186 generic( 4187 tpdY_R : Time := 0 ns; 4188 tpdY_F : Time := 0 ns; 4189 strn : STRENGTH := strn_X01); 4190 port( 4191 I0 : in STD_LOGIC; 4192 I1 : in STD_LOGIC; 4193 Y : out STD_LOGIC); 4194 end component; 4195 4196 component NAND3MAC 4197 generic( 4198 tpdY_R : Time := 0 ns; 4199 tpdY_F : Time := 0 ns; 4200 strn : STRENGTH := strn_X01); 4201 port( 4202 I0 : in STD_LOGIC; 4203 I1 : in STD_LOGIC; 4204 I2 : in STD_LOGIC; 4205 Y : out STD_LOGIC); 4206 end component; 4207 4208 component OR3MAC 4209 generic( 4210 tpdY_R : Time := 0 ns; 4211 tpdY_F : Time := 0 ns; 4212 strn : STRENGTH := strn_X01); 4213 port( 4214 I0 : in STD_LOGIC; 4215 I1 : in STD_LOGIC; 4216 I2 : in STD_LOGIC; 4217 Y : out STD_LOGIC); 4218 end component; 4219 4220 component NAND2MAC 4221 generic( 4222 tpdY_R : Time := 0 ns; 4223 tpdY_F : Time := 0 ns; 4224 strn : STRENGTH := strn_X01); 4225 port( 4226 I0 : in STD_LOGIC; 4227 I1 : in STD_LOGIC; 4228 Y : out STD_LOGIC); 4229 end component; 4230 4231begin 4232 4233 -- Netlist 4234 U1 : AND2MAC 4235 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4236 port map( I0 => n1, I1 => n2, Y => nq); 4237 4238 U2 : NAND3MAC 4239 port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); 4240 4241 U3 : OR3MAC 4242 port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); 4243 4244 U4 : NAND2MAC 4245 port map( I0 => i6, I1 => n3, Y => n1); 4246 4247 4248end UDSM; 4249 4250configuration CFG_noa3ao322_x1_UDSM of noa3ao322_x1 is 4251 for UDSM 4252 end for; 4253end CFG_noa3ao322_x1_UDSM; 4254 4255 4256----- CELL noa3ao322_x4 ----- 4257library IEEE; 4258use IEEE.STD_LOGIC_1164.all; 4259library SYNOPSYS; 4260use SYNOPSYS.attributes.REAL_NAME; 4261 4262-- entity declaration -- 4263entity noa3ao322_x4 is 4264 generic( 4265 Timing_mesg: Boolean := True; 4266 Timing_xgen: Boolean := False; 4267 tpdi0_nq_R : Time := 0.819 ns; 4268 tpdi0_nq_F : Time := 0.987 ns; 4269 tpdi1_nq_R : Time := 0.914 ns; 4270 tpdi1_nq_F : Time := 0.931 ns; 4271 tpdi2_nq_R : Time := 0.990 ns; 4272 tpdi2_nq_F : Time := 0.874 ns; 4273 tpdi3_nq_R : Time := 0.729 ns; 4274 tpdi3_nq_F : Time := 0.926 ns; 4275 tpdi4_nq_R : Time := 0.821 ns; 4276 tpdi4_nq_F : Time := 0.924 ns; 4277 tpdi5_nq_R : Time := 0.907 ns; 4278 tpdi5_nq_F : Time := 0.900 ns; 4279 tpdi6_nq_R : Time := 0.738 ns; 4280 tpdi6_nq_F : Time := 0.718 ns; 4281 twdi0_R : Time := 0.000 ns; 4282 twdi0_F : Time := 0.000 ns; 4283 twdi1_R : Time := 0.000 ns; 4284 twdi1_F : Time := 0.000 ns; 4285 twdi2_R : Time := 0.000 ns; 4286 twdi2_F : Time := 0.000 ns; 4287 twdi3_R : Time := 0.000 ns; 4288 twdi3_F : Time := 0.000 ns; 4289 twdi4_R : Time := 0.000 ns; 4290 twdi4_F : Time := 0.000 ns; 4291 twdi5_R : Time := 0.000 ns; 4292 twdi5_F : Time := 0.000 ns; 4293 twdi6_R : Time := 0.000 ns; 4294 twdi6_F : Time := 0.000 ns); 4295 4296 port( 4297 i0 : in STD_LOGIC; 4298 i1 : in STD_LOGIC; 4299 i2 : in STD_LOGIC; 4300 i3 : in STD_LOGIC; 4301 i4 : in STD_LOGIC; 4302 i5 : in STD_LOGIC; 4303 i6 : in STD_LOGIC; 4304 nq : out STD_LOGIC); 4305end noa3ao322_x4; 4306 4307-- architecture body -- 4308library IEEE_ASIC; 4309use IEEE.STD_LOGIC_MISC.all; 4310use SYNOPSYS.attributes.backplane; 4311use SYNOPSYS.attributes.PRIVATE; 4312use SYNOPSYS.attributes.ASIC_CELL; 4313 4314architecture UDSM of noa3ao322_x4 is 4315 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4316 attribute PRIVATE of UDSM : architecture is TRUE; 4317 attribute ASIC_CELL of UDSM : architecture is TRUE; 4318 4319 signal n1, n2, n3 : STD_LOGIC; 4320 4321 component AND2MAC 4322 generic( 4323 tpdY_R : Time := 0 ns; 4324 tpdY_F : Time := 0 ns; 4325 strn : STRENGTH := strn_X01); 4326 port( 4327 I0 : in STD_LOGIC; 4328 I1 : in STD_LOGIC; 4329 Y : out STD_LOGIC); 4330 end component; 4331 4332 component NAND3MAC 4333 generic( 4334 tpdY_R : Time := 0 ns; 4335 tpdY_F : Time := 0 ns; 4336 strn : STRENGTH := strn_X01); 4337 port( 4338 I0 : in STD_LOGIC; 4339 I1 : in STD_LOGIC; 4340 I2 : in STD_LOGIC; 4341 Y : out STD_LOGIC); 4342 end component; 4343 4344 component OR3MAC 4345 generic( 4346 tpdY_R : Time := 0 ns; 4347 tpdY_F : Time := 0 ns; 4348 strn : STRENGTH := strn_X01); 4349 port( 4350 I0 : in STD_LOGIC; 4351 I1 : in STD_LOGIC; 4352 I2 : in STD_LOGIC; 4353 Y : out STD_LOGIC); 4354 end component; 4355 4356 component NAND2MAC 4357 generic( 4358 tpdY_R : Time := 0 ns; 4359 tpdY_F : Time := 0 ns; 4360 strn : STRENGTH := strn_X01); 4361 port( 4362 I0 : in STD_LOGIC; 4363 I1 : in STD_LOGIC; 4364 Y : out STD_LOGIC); 4365 end component; 4366 4367begin 4368 4369 -- Netlist 4370 U1 : AND2MAC 4371 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4372 port map( I0 => n1, I1 => n2, Y => nq); 4373 4374 U2 : NAND3MAC 4375 port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); 4376 4377 U3 : OR3MAC 4378 port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); 4379 4380 U4 : NAND2MAC 4381 port map( I0 => i6, I1 => n3, Y => n1); 4382 4383 4384end UDSM; 4385 4386configuration CFG_noa3ao322_x4_UDSM of noa3ao322_x4 is 4387 for UDSM 4388 end for; 4389end CFG_noa3ao322_x4_UDSM; 4390 4391 4392----- CELL noa22_x1 ----- 4393library IEEE; 4394use IEEE.STD_LOGIC_1164.all; 4395library SYNOPSYS; 4396use SYNOPSYS.attributes.REAL_NAME; 4397 4398-- entity declaration -- 4399entity noa22_x1 is 4400 generic( 4401 Timing_mesg: Boolean := True; 4402 Timing_xgen: Boolean := False; 4403 tpdi0_nq_R : Time := 0.151 ns; 4404 tpdi0_nq_F : Time := 0.327 ns; 4405 tpdi1_nq_R : Time := 0.218 ns; 4406 tpdi1_nq_F : Time := 0.287 ns; 4407 tpdi2_nq_R : Time := 0.218 ns; 4408 tpdi2_nq_F : Time := 0.241 ns; 4409 twdi0_R : Time := 0.000 ns; 4410 twdi0_F : Time := 0.000 ns; 4411 twdi1_R : Time := 0.000 ns; 4412 twdi1_F : Time := 0.000 ns; 4413 twdi2_R : Time := 0.000 ns; 4414 twdi2_F : Time := 0.000 ns); 4415 4416 port( 4417 i0 : in STD_LOGIC; 4418 i1 : in STD_LOGIC; 4419 i2 : in STD_LOGIC; 4420 nq : out STD_LOGIC); 4421end noa22_x1; 4422 4423-- architecture body -- 4424library IEEE_ASIC; 4425use IEEE.STD_LOGIC_MISC.all; 4426use SYNOPSYS.attributes.backplane; 4427use SYNOPSYS.attributes.PRIVATE; 4428use SYNOPSYS.attributes.ASIC_CELL; 4429 4430architecture UDSM of noa22_x1 is 4431 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4432 attribute PRIVATE of UDSM : architecture is TRUE; 4433 attribute ASIC_CELL of UDSM : architecture is TRUE; 4434 4435 signal n1 : STD_LOGIC; 4436 4437 component NOR2MAC 4438 generic( 4439 tpdY_R : Time := 0 ns; 4440 tpdY_F : Time := 0 ns; 4441 strn : STRENGTH := strn_X01); 4442 port( 4443 I0 : in STD_LOGIC; 4444 I1 : in STD_LOGIC; 4445 Y : out STD_LOGIC); 4446 end component; 4447 4448 component AND2MAC 4449 generic( 4450 tpdY_R : Time := 0 ns; 4451 tpdY_F : Time := 0 ns; 4452 strn : STRENGTH := strn_X01); 4453 port( 4454 I0 : in STD_LOGIC; 4455 I1 : in STD_LOGIC; 4456 Y : out STD_LOGIC); 4457 end component; 4458 4459begin 4460 4461 -- Netlist 4462 U1 : NOR2MAC 4463 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4464 port map( I0 => i2, I1 => n1, Y => nq); 4465 4466 U2 : AND2MAC 4467 port map( I0 => i0, I1 => i1, Y => n1); 4468 4469 4470end UDSM; 4471 4472configuration CFG_noa22_x1_UDSM of noa22_x1 is 4473 for UDSM 4474 end for; 4475end CFG_noa22_x1_UDSM; 4476 4477 4478----- CELL noa22_x4 ----- 4479library IEEE; 4480use IEEE.STD_LOGIC_1164.all; 4481library SYNOPSYS; 4482use SYNOPSYS.attributes.REAL_NAME; 4483 4484-- entity declaration -- 4485entity noa22_x4 is 4486 generic( 4487 Timing_mesg: Boolean := True; 4488 Timing_xgen: Boolean := False; 4489 tpdi0_nq_R : Time := 0.550 ns; 4490 tpdi0_nq_F : Time := 0.740 ns; 4491 tpdi1_nq_R : Time := 0.643 ns; 4492 tpdi1_nq_F : Time := 0.709 ns; 4493 tpdi2_nq_R : Time := 0.610 ns; 4494 tpdi2_nq_F : Time := 0.646 ns; 4495 twdi0_R : Time := 0.000 ns; 4496 twdi0_F : Time := 0.000 ns; 4497 twdi1_R : Time := 0.000 ns; 4498 twdi1_F : Time := 0.000 ns; 4499 twdi2_R : Time := 0.000 ns; 4500 twdi2_F : Time := 0.000 ns); 4501 4502 port( 4503 i0 : in STD_LOGIC; 4504 i1 : in STD_LOGIC; 4505 i2 : in STD_LOGIC; 4506 nq : out STD_LOGIC); 4507end noa22_x4; 4508 4509-- architecture body -- 4510library IEEE_ASIC; 4511use IEEE.STD_LOGIC_MISC.all; 4512use SYNOPSYS.attributes.backplane; 4513use SYNOPSYS.attributes.PRIVATE; 4514use SYNOPSYS.attributes.ASIC_CELL; 4515 4516architecture UDSM of noa22_x4 is 4517 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4518 attribute PRIVATE of UDSM : architecture is TRUE; 4519 attribute ASIC_CELL of UDSM : architecture is TRUE; 4520 4521 signal n1 : STD_LOGIC; 4522 4523 component NOR2MAC 4524 generic( 4525 tpdY_R : Time := 0 ns; 4526 tpdY_F : Time := 0 ns; 4527 strn : STRENGTH := strn_X01); 4528 port( 4529 I0 : in STD_LOGIC; 4530 I1 : in STD_LOGIC; 4531 Y : out STD_LOGIC); 4532 end component; 4533 4534 component AND2MAC 4535 generic( 4536 tpdY_R : Time := 0 ns; 4537 tpdY_F : Time := 0 ns; 4538 strn : STRENGTH := strn_X01); 4539 port( 4540 I0 : in STD_LOGIC; 4541 I1 : in STD_LOGIC; 4542 Y : out STD_LOGIC); 4543 end component; 4544 4545begin 4546 4547 -- Netlist 4548 U1 : NOR2MAC 4549 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4550 port map( I0 => i2, I1 => n1, Y => nq); 4551 4552 U2 : AND2MAC 4553 port map( I0 => i0, I1 => i1, Y => n1); 4554 4555 4556end UDSM; 4557 4558configuration CFG_noa22_x4_UDSM of noa22_x4 is 4559 for UDSM 4560 end for; 4561end CFG_noa22_x4_UDSM; 4562 4563 4564----- CELL nts_x1 ----- 4565library IEEE; 4566use IEEE.STD_LOGIC_1164.all; 4567library SYNOPSYS; 4568use SYNOPSYS.attributes.REAL_NAME; 4569 4570-- entity declaration -- 4571entity nts_x1 is 4572 generic( 4573 Timing_mesg: Boolean := True; 4574 Timing_xgen: Boolean := False; 4575 tpdcmd_nq_R : Time := 0.249 ns; 4576 tpdcmd_nq_F : Time := 0.041 ns; 4577 tpdcmd_nq_LZ : Time := 0.249 ns; 4578 tpdcmd_nq_HZ : Time := 0.041 ns; 4579 tpdi_nq_R : Time := 0.169 ns; 4580 tpdi_nq_F : Time := 0.201 ns; 4581 twdi_R : Time := 0.000 ns; 4582 twdi_F : Time := 0.000 ns; 4583 twdcmd_R : Time := 0.000 ns; 4584 twdcmd_F : Time := 0.000 ns); 4585 4586 port( 4587 i : in STD_LOGIC; 4588 cmd : in STD_LOGIC; 4589 nq : out STD_LOGIC); 4590end nts_x1; 4591 4592-- architecture body -- 4593library IEEE_ASIC; 4594use IEEE.STD_LOGIC_MISC.all; 4595use SYNOPSYS.attributes.backplane; 4596use SYNOPSYS.attributes.PRIVATE; 4597use SYNOPSYS.attributes.ASIC_CELL; 4598 4599architecture UDSM of nts_x1 is 4600 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4601 attribute PRIVATE of UDSM : architecture is TRUE; 4602 attribute ASIC_CELL of UDSM : architecture is TRUE; 4603 4604 component INV3SHEMAC 4605 generic( 4606 tpdY_R : Time := 0 ns; 4607 tpdY_F : Time := 0 ns; 4608 strn : STRENGTH := strn_X01); 4609 port( 4610 I0 : in STD_LOGIC; 4611 OE : in STD_LOGIC; 4612 Y : out STD_LOGIC); 4613 end component; 4614 4615begin 4616 4617 -- Netlist 4618 U1 : INV3SHEMAC 4619 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4620 port map( I0 => i, OE => cmd, Y => nq); 4621 4622 4623end UDSM; 4624 4625configuration CFG_nts_x1_UDSM of nts_x1 is 4626 for UDSM 4627 end for; 4628end CFG_nts_x1_UDSM; 4629 4630 4631----- CELL nts_x2 ----- 4632library IEEE; 4633use IEEE.STD_LOGIC_1164.all; 4634library SYNOPSYS; 4635use SYNOPSYS.attributes.REAL_NAME; 4636 4637-- entity declaration -- 4638entity nts_x2 is 4639 generic( 4640 Timing_mesg: Boolean := True; 4641 Timing_xgen: Boolean := False; 4642 tpdcmd_nq_R : Time := 0.330 ns; 4643 tpdcmd_nq_F : Time := 0.033 ns; 4644 tpdcmd_nq_LZ : Time := 0.330 ns; 4645 tpdcmd_nq_HZ : Time := 0.033 ns; 4646 tpdi_nq_R : Time := 0.167 ns; 4647 tpdi_nq_F : Time := 0.201 ns; 4648 twdi_R : Time := 0.000 ns; 4649 twdi_F : Time := 0.000 ns; 4650 twdcmd_R : Time := 0.000 ns; 4651 twdcmd_F : Time := 0.000 ns); 4652 4653 port( 4654 i : in STD_LOGIC; 4655 cmd : in STD_LOGIC; 4656 nq : out STD_LOGIC); 4657end nts_x2; 4658 4659-- architecture body -- 4660library IEEE_ASIC; 4661use IEEE.STD_LOGIC_MISC.all; 4662use SYNOPSYS.attributes.backplane; 4663use SYNOPSYS.attributes.PRIVATE; 4664use SYNOPSYS.attributes.ASIC_CELL; 4665 4666architecture UDSM of nts_x2 is 4667 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4668 attribute PRIVATE of UDSM : architecture is TRUE; 4669 attribute ASIC_CELL of UDSM : architecture is TRUE; 4670 4671 component INV3SHEMAC 4672 generic( 4673 tpdY_R : Time := 0 ns; 4674 tpdY_F : Time := 0 ns; 4675 strn : STRENGTH := strn_X01); 4676 port( 4677 I0 : in STD_LOGIC; 4678 OE : in STD_LOGIC; 4679 Y : out STD_LOGIC); 4680 end component; 4681 4682begin 4683 4684 -- Netlist 4685 U1 : INV3SHEMAC 4686 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4687 port map( I0 => i, OE => cmd, Y => nq); 4688 4689 4690end UDSM; 4691 4692configuration CFG_nts_x2_UDSM of nts_x2 is 4693 for UDSM 4694 end for; 4695end CFG_nts_x2_UDSM; 4696 4697 4698----- CELL nxr2_x1 ----- 4699library IEEE; 4700use IEEE.STD_LOGIC_1164.all; 4701library SYNOPSYS; 4702use SYNOPSYS.attributes.REAL_NAME; 4703 4704-- entity declaration -- 4705entity nxr2_x1 is 4706 generic( 4707 Timing_mesg: Boolean := True; 4708 Timing_xgen: Boolean := False; 4709 tpdi0_nq_R : Time := 0.288 ns; 4710 tpdi0_nq_F : Time := 0.293 ns; 4711 tpdi1_nq_R : Time := 0.156 ns; 4712 tpdi1_nq_F : Time := 0.327 ns; 4713 twdi0_R : Time := 0.000 ns; 4714 twdi0_F : Time := 0.000 ns; 4715 twdi1_R : Time := 0.000 ns; 4716 twdi1_F : Time := 0.000 ns); 4717 4718 port( 4719 i0 : in STD_LOGIC; 4720 i1 : in STD_LOGIC; 4721 nq : out STD_LOGIC); 4722end nxr2_x1; 4723 4724-- architecture body -- 4725library IEEE_ASIC; 4726use IEEE.STD_LOGIC_MISC.all; 4727use SYNOPSYS.attributes.backplane; 4728use SYNOPSYS.attributes.PRIVATE; 4729use SYNOPSYS.attributes.ASIC_CELL; 4730 4731architecture UDSM of nxr2_x1 is 4732 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4733 attribute PRIVATE of UDSM : architecture is TRUE; 4734 attribute ASIC_CELL of UDSM : architecture is TRUE; 4735 4736 component NXOR2MAC 4737 generic( 4738 tpdY_R : Time := 0 ns; 4739 tpdY_F : Time := 0 ns; 4740 strn : STRENGTH := strn_X01); 4741 port( 4742 I0 : in STD_LOGIC; 4743 I1 : in STD_LOGIC; 4744 Y : out STD_LOGIC); 4745 end component; 4746 4747begin 4748 4749 -- Netlist 4750 U1 : NXOR2MAC 4751 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4752 port map( I0 => i1, I1 => i0, Y => nq); 4753 4754 4755end UDSM; 4756 4757configuration CFG_nxr2_x1_UDSM of nxr2_x1 is 4758 for UDSM 4759 end for; 4760end CFG_nxr2_x1_UDSM; 4761 4762 4763----- CELL nxr2_x4 ----- 4764library IEEE; 4765use IEEE.STD_LOGIC_1164.all; 4766library SYNOPSYS; 4767use SYNOPSYS.attributes.REAL_NAME; 4768 4769-- entity declaration -- 4770entity nxr2_x4 is 4771 generic( 4772 Timing_mesg: Boolean := True; 4773 Timing_xgen: Boolean := False; 4774 tpdi0_nq_R : Time := 0.522 ns; 4775 tpdi0_nq_F : Time := 0.553 ns; 4776 tpdi1_nq_R : Time := 0.553 ns; 4777 tpdi1_nq_F : Time := 0.542 ns; 4778 twdi0_R : Time := 0.000 ns; 4779 twdi0_F : Time := 0.000 ns; 4780 twdi1_R : Time := 0.000 ns; 4781 twdi1_F : Time := 0.000 ns); 4782 4783 port( 4784 i0 : in STD_LOGIC; 4785 i1 : in STD_LOGIC; 4786 nq : out STD_LOGIC); 4787end nxr2_x4; 4788 4789-- architecture body -- 4790library IEEE_ASIC; 4791use IEEE.STD_LOGIC_MISC.all; 4792use SYNOPSYS.attributes.backplane; 4793use SYNOPSYS.attributes.PRIVATE; 4794use SYNOPSYS.attributes.ASIC_CELL; 4795 4796architecture UDSM of nxr2_x4 is 4797 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4798 attribute PRIVATE of UDSM : architecture is TRUE; 4799 attribute ASIC_CELL of UDSM : architecture is TRUE; 4800 4801 component NXOR2MAC 4802 generic( 4803 tpdY_R : Time := 0 ns; 4804 tpdY_F : Time := 0 ns; 4805 strn : STRENGTH := strn_X01); 4806 port( 4807 I0 : in STD_LOGIC; 4808 I1 : in STD_LOGIC; 4809 Y : out STD_LOGIC); 4810 end component; 4811 4812begin 4813 4814 -- Netlist 4815 U1 : NXOR2MAC 4816 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4817 port map( I0 => i1, I1 => i0, Y => nq); 4818 4819 4820end UDSM; 4821 4822configuration CFG_nxr2_x4_UDSM of nxr2_x4 is 4823 for UDSM 4824 end for; 4825end CFG_nxr2_x4_UDSM; 4826 4827 4828----- CELL o2_x2 ----- 4829library IEEE; 4830use IEEE.STD_LOGIC_1164.all; 4831library SYNOPSYS; 4832use SYNOPSYS.attributes.REAL_NAME; 4833 4834-- entity declaration -- 4835entity o2_x2 is 4836 generic( 4837 Timing_mesg: Boolean := True; 4838 Timing_xgen: Boolean := False; 4839 tpdi0_q_R : Time := 0.406 ns; 4840 tpdi0_q_F : Time := 0.310 ns; 4841 tpdi1_q_R : Time := 0.335 ns; 4842 tpdi1_q_F : Time := 0.364 ns; 4843 twdi0_R : Time := 0.000 ns; 4844 twdi0_F : Time := 0.000 ns; 4845 twdi1_R : Time := 0.000 ns; 4846 twdi1_F : Time := 0.000 ns); 4847 4848 port( 4849 i0 : in STD_LOGIC; 4850 i1 : in STD_LOGIC; 4851 q : out STD_LOGIC); 4852end o2_x2; 4853 4854-- architecture body -- 4855library IEEE_ASIC; 4856use IEEE.STD_LOGIC_MISC.all; 4857use SYNOPSYS.attributes.backplane; 4858use SYNOPSYS.attributes.PRIVATE; 4859use SYNOPSYS.attributes.ASIC_CELL; 4860 4861architecture UDSM of o2_x2 is 4862 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4863 attribute PRIVATE of UDSM : architecture is TRUE; 4864 attribute ASIC_CELL of UDSM : architecture is TRUE; 4865 4866 component OR2MAC 4867 generic( 4868 tpdY_R : Time := 0 ns; 4869 tpdY_F : Time := 0 ns; 4870 strn : STRENGTH := strn_X01); 4871 port( 4872 I0 : in STD_LOGIC; 4873 I1 : in STD_LOGIC; 4874 Y : out STD_LOGIC); 4875 end component; 4876 4877begin 4878 4879 -- Netlist 4880 U1 : OR2MAC 4881 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4882 port map( I0 => i1, I1 => i0, Y => q); 4883 4884 4885end UDSM; 4886 4887configuration CFG_o2_x2_UDSM of o2_x2 is 4888 for UDSM 4889 end for; 4890end CFG_o2_x2_UDSM; 4891 4892 4893----- CELL o2_x4 ----- 4894library IEEE; 4895use IEEE.STD_LOGIC_1164.all; 4896library SYNOPSYS; 4897use SYNOPSYS.attributes.REAL_NAME; 4898 4899-- entity declaration -- 4900entity o2_x4 is 4901 generic( 4902 Timing_mesg: Boolean := True; 4903 Timing_xgen: Boolean := False; 4904 tpdi0_q_R : Time := 0.491 ns; 4905 tpdi0_q_F : Time := 0.394 ns; 4906 tpdi1_q_R : Time := 0.427 ns; 4907 tpdi1_q_F : Time := 0.464 ns; 4908 twdi0_R : Time := 0.000 ns; 4909 twdi0_F : Time := 0.000 ns; 4910 twdi1_R : Time := 0.000 ns; 4911 twdi1_F : Time := 0.000 ns); 4912 4913 port( 4914 i0 : in STD_LOGIC; 4915 i1 : in STD_LOGIC; 4916 q : out STD_LOGIC); 4917end o2_x4; 4918 4919-- architecture body -- 4920library IEEE_ASIC; 4921use IEEE.STD_LOGIC_MISC.all; 4922use SYNOPSYS.attributes.backplane; 4923use SYNOPSYS.attributes.PRIVATE; 4924use SYNOPSYS.attributes.ASIC_CELL; 4925 4926architecture UDSM of o2_x4 is 4927 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4928 attribute PRIVATE of UDSM : architecture is TRUE; 4929 attribute ASIC_CELL of UDSM : architecture is TRUE; 4930 4931 component OR2MAC 4932 generic( 4933 tpdY_R : Time := 0 ns; 4934 tpdY_F : Time := 0 ns; 4935 strn : STRENGTH := strn_X01); 4936 port( 4937 I0 : in STD_LOGIC; 4938 I1 : in STD_LOGIC; 4939 Y : out STD_LOGIC); 4940 end component; 4941 4942begin 4943 4944 -- Netlist 4945 U1 : OR2MAC 4946 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 4947 port map( I0 => i1, I1 => i0, Y => q); 4948 4949 4950end UDSM; 4951 4952configuration CFG_o2_x4_UDSM of o2_x4 is 4953 for UDSM 4954 end for; 4955end CFG_o2_x4_UDSM; 4956 4957 4958----- CELL o3_x2 ----- 4959library IEEE; 4960use IEEE.STD_LOGIC_1164.all; 4961library SYNOPSYS; 4962use SYNOPSYS.attributes.REAL_NAME; 4963 4964-- entity declaration -- 4965entity o3_x2 is 4966 generic( 4967 Timing_mesg: Boolean := True; 4968 Timing_xgen: Boolean := False; 4969 tpdi0_q_R : Time := 0.494 ns; 4970 tpdi0_q_F : Time := 0.407 ns; 4971 tpdi1_q_R : Time := 0.430 ns; 4972 tpdi1_q_F : Time := 0.482 ns; 4973 tpdi2_q_R : Time := 0.360 ns; 4974 tpdi2_q_F : Time := 0.506 ns; 4975 twdi0_R : Time := 0.000 ns; 4976 twdi0_F : Time := 0.000 ns; 4977 twdi1_R : Time := 0.000 ns; 4978 twdi1_F : Time := 0.000 ns; 4979 twdi2_R : Time := 0.000 ns; 4980 twdi2_F : Time := 0.000 ns); 4981 4982 port( 4983 i0 : in STD_LOGIC; 4984 i1 : in STD_LOGIC; 4985 i2 : in STD_LOGIC; 4986 q : out STD_LOGIC); 4987end o3_x2; 4988 4989-- architecture body -- 4990library IEEE_ASIC; 4991use IEEE.STD_LOGIC_MISC.all; 4992use SYNOPSYS.attributes.backplane; 4993use SYNOPSYS.attributes.PRIVATE; 4994use SYNOPSYS.attributes.ASIC_CELL; 4995 4996architecture UDSM of o3_x2 is 4997 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 4998 attribute PRIVATE of UDSM : architecture is TRUE; 4999 attribute ASIC_CELL of UDSM : architecture is TRUE; 5000 5001 component OR3MAC 5002 generic( 5003 tpdY_R : Time := 0 ns; 5004 tpdY_F : Time := 0 ns; 5005 strn : STRENGTH := strn_X01); 5006 port( 5007 I0 : in STD_LOGIC; 5008 I1 : in STD_LOGIC; 5009 I2 : in STD_LOGIC; 5010 Y : out STD_LOGIC); 5011 end component; 5012 5013begin 5014 5015 -- Netlist 5016 U1 : OR3MAC 5017 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5018 port map( I0 => i0, I1 => i1, I2 => i2, Y => q); 5019 5020 5021end UDSM; 5022 5023configuration CFG_o3_x2_UDSM of o3_x2 is 5024 for UDSM 5025 end for; 5026end CFG_o3_x2_UDSM; 5027 5028 5029----- CELL o3_x4 ----- 5030library IEEE; 5031use IEEE.STD_LOGIC_1164.all; 5032library SYNOPSYS; 5033use SYNOPSYS.attributes.REAL_NAME; 5034 5035-- entity declaration -- 5036entity o3_x4 is 5037 generic( 5038 Timing_mesg: Boolean := True; 5039 Timing_xgen: Boolean := False; 5040 tpdi0_q_R : Time := 0.569 ns; 5041 tpdi0_q_F : Time := 0.501 ns; 5042 tpdi1_q_R : Time := 0.510 ns; 5043 tpdi1_q_F : Time := 0.585 ns; 5044 tpdi2_q_R : Time := 0.447 ns; 5045 tpdi2_q_F : Time := 0.622 ns; 5046 twdi0_R : Time := 0.000 ns; 5047 twdi0_F : Time := 0.000 ns; 5048 twdi1_R : Time := 0.000 ns; 5049 twdi1_F : Time := 0.000 ns; 5050 twdi2_R : Time := 0.000 ns; 5051 twdi2_F : Time := 0.000 ns); 5052 5053 port( 5054 i0 : in STD_LOGIC; 5055 i1 : in STD_LOGIC; 5056 i2 : in STD_LOGIC; 5057 q : out STD_LOGIC); 5058end o3_x4; 5059 5060-- architecture body -- 5061library IEEE_ASIC; 5062use IEEE.STD_LOGIC_MISC.all; 5063use SYNOPSYS.attributes.backplane; 5064use SYNOPSYS.attributes.PRIVATE; 5065use SYNOPSYS.attributes.ASIC_CELL; 5066 5067architecture UDSM of o3_x4 is 5068 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5069 attribute PRIVATE of UDSM : architecture is TRUE; 5070 attribute ASIC_CELL of UDSM : architecture is TRUE; 5071 5072 component OR3MAC 5073 generic( 5074 tpdY_R : Time := 0 ns; 5075 tpdY_F : Time := 0 ns; 5076 strn : STRENGTH := strn_X01); 5077 port( 5078 I0 : in STD_LOGIC; 5079 I1 : in STD_LOGIC; 5080 I2 : in STD_LOGIC; 5081 Y : out STD_LOGIC); 5082 end component; 5083 5084begin 5085 5086 -- Netlist 5087 U1 : OR3MAC 5088 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5089 port map( I0 => i0, I1 => i1, I2 => i2, Y => q); 5090 5091 5092end UDSM; 5093 5094configuration CFG_o3_x4_UDSM of o3_x4 is 5095 for UDSM 5096 end for; 5097end CFG_o3_x4_UDSM; 5098 5099 5100----- CELL o4_x2 ----- 5101library IEEE; 5102use IEEE.STD_LOGIC_1164.all; 5103library SYNOPSYS; 5104use SYNOPSYS.attributes.REAL_NAME; 5105 5106-- entity declaration -- 5107entity o4_x2 is 5108 generic( 5109 Timing_mesg: Boolean := True; 5110 Timing_xgen: Boolean := False; 5111 tpdi0_q_R : Time := 0.508 ns; 5112 tpdi0_q_F : Time := 0.601 ns; 5113 tpdi1_q_R : Time := 0.446 ns; 5114 tpdi1_q_F : Time := 0.631 ns; 5115 tpdi2_q_R : Time := 0.567 ns; 5116 tpdi2_q_F : Time := 0.531 ns; 5117 tpdi3_q_R : Time := 0.378 ns; 5118 tpdi3_q_F : Time := 0.626 ns; 5119 twdi0_R : Time := 0.000 ns; 5120 twdi0_F : Time := 0.000 ns; 5121 twdi1_R : Time := 0.000 ns; 5122 twdi1_F : Time := 0.000 ns; 5123 twdi2_R : Time := 0.000 ns; 5124 twdi2_F : Time := 0.000 ns; 5125 twdi3_R : Time := 0.000 ns; 5126 twdi3_F : Time := 0.000 ns); 5127 5128 port( 5129 i0 : in STD_LOGIC; 5130 i1 : in STD_LOGIC; 5131 i2 : in STD_LOGIC; 5132 i3 : in STD_LOGIC; 5133 q : out STD_LOGIC); 5134end o4_x2; 5135 5136-- architecture body -- 5137library IEEE_ASIC; 5138use IEEE.STD_LOGIC_MISC.all; 5139use SYNOPSYS.attributes.backplane; 5140use SYNOPSYS.attributes.PRIVATE; 5141use SYNOPSYS.attributes.ASIC_CELL; 5142 5143architecture UDSM of o4_x2 is 5144 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5145 attribute PRIVATE of UDSM : architecture is TRUE; 5146 attribute ASIC_CELL of UDSM : architecture is TRUE; 5147 5148 component OR4MAC 5149 generic( 5150 tpdY_R : Time := 0 ns; 5151 tpdY_F : Time := 0 ns; 5152 strn : STRENGTH := strn_X01); 5153 port( 5154 I0 : in STD_LOGIC; 5155 I1 : in STD_LOGIC; 5156 I2 : in STD_LOGIC; 5157 I3 : in STD_LOGIC; 5158 Y : out STD_LOGIC); 5159 end component; 5160 5161begin 5162 5163 -- Netlist 5164 U1 : OR4MAC 5165 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5166 port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q); 5167 5168 5169end UDSM; 5170 5171configuration CFG_o4_x2_UDSM of o4_x2 is 5172 for UDSM 5173 end for; 5174end CFG_o4_x2_UDSM; 5175 5176 5177----- CELL o4_x4 ----- 5178library IEEE; 5179use IEEE.STD_LOGIC_1164.all; 5180library SYNOPSYS; 5181use SYNOPSYS.attributes.REAL_NAME; 5182 5183-- entity declaration -- 5184entity o4_x4 is 5185 generic( 5186 Timing_mesg: Boolean := True; 5187 Timing_xgen: Boolean := False; 5188 tpdi0_q_R : Time := 0.574 ns; 5189 tpdi0_q_F : Time := 0.638 ns; 5190 tpdi1_q_R : Time := 0.492 ns; 5191 tpdi1_q_F : Time := 0.650 ns; 5192 tpdi2_q_R : Time := 0.649 ns; 5193 tpdi2_q_F : Time := 0.611 ns; 5194 tpdi3_q_R : Time := 0.721 ns; 5195 tpdi3_q_F : Time := 0.536 ns; 5196 twdi0_R : Time := 0.000 ns; 5197 twdi0_F : Time := 0.000 ns; 5198 twdi1_R : Time := 0.000 ns; 5199 twdi1_F : Time := 0.000 ns; 5200 twdi2_R : Time := 0.000 ns; 5201 twdi2_F : Time := 0.000 ns; 5202 twdi3_R : Time := 0.000 ns; 5203 twdi3_F : Time := 0.000 ns); 5204 5205 port( 5206 i0 : in STD_LOGIC; 5207 i1 : in STD_LOGIC; 5208 i2 : in STD_LOGIC; 5209 i3 : in STD_LOGIC; 5210 q : out STD_LOGIC); 5211end o4_x4; 5212 5213-- architecture body -- 5214library IEEE_ASIC; 5215use IEEE.STD_LOGIC_MISC.all; 5216use SYNOPSYS.attributes.backplane; 5217use SYNOPSYS.attributes.PRIVATE; 5218use SYNOPSYS.attributes.ASIC_CELL; 5219 5220architecture UDSM of o4_x4 is 5221 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5222 attribute PRIVATE of UDSM : architecture is TRUE; 5223 attribute ASIC_CELL of UDSM : architecture is TRUE; 5224 5225 component OR4MAC 5226 generic( 5227 tpdY_R : Time := 0 ns; 5228 tpdY_F : Time := 0 ns; 5229 strn : STRENGTH := strn_X01); 5230 port( 5231 I0 : in STD_LOGIC; 5232 I1 : in STD_LOGIC; 5233 I2 : in STD_LOGIC; 5234 I3 : in STD_LOGIC; 5235 Y : out STD_LOGIC); 5236 end component; 5237 5238begin 5239 5240 -- Netlist 5241 U1 : OR4MAC 5242 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5243 port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q); 5244 5245 5246end UDSM; 5247 5248configuration CFG_o4_x4_UDSM of o4_x4 is 5249 for UDSM 5250 end for; 5251end CFG_o4_x4_UDSM; 5252 5253 5254----- CELL oa2a2a2a24_x2 ----- 5255library IEEE; 5256use IEEE.STD_LOGIC_1164.all; 5257library SYNOPSYS; 5258use SYNOPSYS.attributes.REAL_NAME; 5259 5260-- entity declaration -- 5261entity oa2a2a2a24_x2 is 5262 generic( 5263 Timing_mesg: Boolean := True; 5264 Timing_xgen: Boolean := False; 5265 tpdi0_q_R : Time := 0.780 ns; 5266 tpdi0_q_F : Time := 0.797 ns; 5267 tpdi1_q_R : Time := 0.909 ns; 5268 tpdi1_q_F : Time := 0.753 ns; 5269 tpdi2_q_R : Time := 0.682 ns; 5270 tpdi2_q_F : Time := 0.856 ns; 5271 tpdi3_q_R : Time := 0.803 ns; 5272 tpdi3_q_F : Time := 0.810 ns; 5273 tpdi4_q_R : Time := 0.565 ns; 5274 tpdi4_q_F : Time := 0.813 ns; 5275 tpdi5_q_R : Time := 0.467 ns; 5276 tpdi5_q_F : Time := 0.861 ns; 5277 tpdi6_q_R : Time := 0.426 ns; 5278 tpdi6_q_F : Time := 0.748 ns; 5279 tpdi7_q_R : Time := 0.346 ns; 5280 tpdi7_q_F : Time := 0.800 ns; 5281 twdi0_R : Time := 0.000 ns; 5282 twdi0_F : Time := 0.000 ns; 5283 twdi1_R : Time := 0.000 ns; 5284 twdi1_F : Time := 0.000 ns; 5285 twdi2_R : Time := 0.000 ns; 5286 twdi2_F : Time := 0.000 ns; 5287 twdi3_R : Time := 0.000 ns; 5288 twdi3_F : Time := 0.000 ns; 5289 twdi4_R : Time := 0.000 ns; 5290 twdi4_F : Time := 0.000 ns; 5291 twdi5_R : Time := 0.000 ns; 5292 twdi5_F : Time := 0.000 ns; 5293 twdi6_R : Time := 0.000 ns; 5294 twdi6_F : Time := 0.000 ns; 5295 twdi7_R : Time := 0.000 ns; 5296 twdi7_F : Time := 0.000 ns); 5297 5298 port( 5299 i0 : in STD_LOGIC; 5300 i1 : in STD_LOGIC; 5301 i2 : in STD_LOGIC; 5302 i3 : in STD_LOGIC; 5303 i4 : in STD_LOGIC; 5304 i5 : in STD_LOGIC; 5305 i6 : in STD_LOGIC; 5306 i7 : in STD_LOGIC; 5307 q : out STD_LOGIC); 5308end oa2a2a2a24_x2; 5309 5310-- architecture body -- 5311library IEEE_ASIC; 5312use IEEE.STD_LOGIC_MISC.all; 5313use SYNOPSYS.attributes.backplane; 5314use SYNOPSYS.attributes.PRIVATE; 5315use SYNOPSYS.attributes.ASIC_CELL; 5316 5317architecture UDSM of oa2a2a2a24_x2 is 5318 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5319 attribute PRIVATE of UDSM : architecture is TRUE; 5320 attribute ASIC_CELL of UDSM : architecture is TRUE; 5321 5322 signal n1, n2, n3, n4 : STD_LOGIC; 5323 5324 component NAND4MAC 5325 generic( 5326 tpdY_R : Time := 0 ns; 5327 tpdY_F : Time := 0 ns; 5328 strn : STRENGTH := strn_X01); 5329 port( 5330 I0 : in STD_LOGIC; 5331 I1 : in STD_LOGIC; 5332 I2 : in STD_LOGIC; 5333 I3 : in STD_LOGIC; 5334 Y : out STD_LOGIC); 5335 end component; 5336 5337 component NAND2MAC 5338 generic( 5339 tpdY_R : Time := 0 ns; 5340 tpdY_F : Time := 0 ns; 5341 strn : STRENGTH := strn_X01); 5342 port( 5343 I0 : in STD_LOGIC; 5344 I1 : in STD_LOGIC; 5345 Y : out STD_LOGIC); 5346 end component; 5347 5348begin 5349 5350 -- Netlist 5351 U1 : NAND4MAC 5352 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5353 port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); 5354 5355 U2 : NAND2MAC 5356 port map( I0 => i6, I1 => i7, Y => n4); 5357 5358 U3 : NAND2MAC 5359 port map( I0 => i4, I1 => i5, Y => n3); 5360 5361 U4 : NAND2MAC 5362 port map( I0 => i2, I1 => i3, Y => n2); 5363 5364 U5 : NAND2MAC 5365 port map( I0 => i0, I1 => i1, Y => n1); 5366 5367 5368end UDSM; 5369 5370configuration CFG_oa2a2a2a24_x2_UDSM of oa2a2a2a24_x2 is 5371 for UDSM 5372 end for; 5373end CFG_oa2a2a2a24_x2_UDSM; 5374 5375 5376----- CELL oa2a2a2a24_x4 ----- 5377library IEEE; 5378use IEEE.STD_LOGIC_1164.all; 5379library SYNOPSYS; 5380use SYNOPSYS.attributes.REAL_NAME; 5381 5382-- entity declaration -- 5383entity oa2a2a2a24_x4 is 5384 generic( 5385 Timing_mesg: Boolean := True; 5386 Timing_xgen: Boolean := False; 5387 tpdi0_q_R : Time := 0.823 ns; 5388 tpdi0_q_F : Time := 0.879 ns; 5389 tpdi1_q_R : Time := 0.955 ns; 5390 tpdi1_q_F : Time := 0.835 ns; 5391 tpdi2_q_R : Time := 0.726 ns; 5392 tpdi2_q_F : Time := 0.940 ns; 5393 tpdi3_q_R : Time := 0.851 ns; 5394 tpdi3_q_F : Time := 0.895 ns; 5395 tpdi4_q_R : Time := 0.619 ns; 5396 tpdi4_q_F : Time := 0.902 ns; 5397 tpdi5_q_R : Time := 0.515 ns; 5398 tpdi5_q_F : Time := 0.949 ns; 5399 tpdi6_q_R : Time := 0.487 ns; 5400 tpdi6_q_F : Time := 0.845 ns; 5401 tpdi7_q_R : Time := 0.399 ns; 5402 tpdi7_q_F : Time := 0.895 ns; 5403 twdi0_R : Time := 0.000 ns; 5404 twdi0_F : Time := 0.000 ns; 5405 twdi1_R : Time := 0.000 ns; 5406 twdi1_F : Time := 0.000 ns; 5407 twdi2_R : Time := 0.000 ns; 5408 twdi2_F : Time := 0.000 ns; 5409 twdi3_R : Time := 0.000 ns; 5410 twdi3_F : Time := 0.000 ns; 5411 twdi4_R : Time := 0.000 ns; 5412 twdi4_F : Time := 0.000 ns; 5413 twdi5_R : Time := 0.000 ns; 5414 twdi5_F : Time := 0.000 ns; 5415 twdi6_R : Time := 0.000 ns; 5416 twdi6_F : Time := 0.000 ns; 5417 twdi7_R : Time := 0.000 ns; 5418 twdi7_F : Time := 0.000 ns); 5419 5420 port( 5421 i0 : in STD_LOGIC; 5422 i1 : in STD_LOGIC; 5423 i2 : in STD_LOGIC; 5424 i3 : in STD_LOGIC; 5425 i4 : in STD_LOGIC; 5426 i5 : in STD_LOGIC; 5427 i6 : in STD_LOGIC; 5428 i7 : in STD_LOGIC; 5429 q : out STD_LOGIC); 5430end oa2a2a2a24_x4; 5431 5432-- architecture body -- 5433library IEEE_ASIC; 5434use IEEE.STD_LOGIC_MISC.all; 5435use SYNOPSYS.attributes.backplane; 5436use SYNOPSYS.attributes.PRIVATE; 5437use SYNOPSYS.attributes.ASIC_CELL; 5438 5439architecture UDSM of oa2a2a2a24_x4 is 5440 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5441 attribute PRIVATE of UDSM : architecture is TRUE; 5442 attribute ASIC_CELL of UDSM : architecture is TRUE; 5443 5444 signal n1, n2, n3, n4 : STD_LOGIC; 5445 5446 component NAND4MAC 5447 generic( 5448 tpdY_R : Time := 0 ns; 5449 tpdY_F : Time := 0 ns; 5450 strn : STRENGTH := strn_X01); 5451 port( 5452 I0 : in STD_LOGIC; 5453 I1 : in STD_LOGIC; 5454 I2 : in STD_LOGIC; 5455 I3 : in STD_LOGIC; 5456 Y : out STD_LOGIC); 5457 end component; 5458 5459 component NAND2MAC 5460 generic( 5461 tpdY_R : Time := 0 ns; 5462 tpdY_F : Time := 0 ns; 5463 strn : STRENGTH := strn_X01); 5464 port( 5465 I0 : in STD_LOGIC; 5466 I1 : in STD_LOGIC; 5467 Y : out STD_LOGIC); 5468 end component; 5469 5470begin 5471 5472 -- Netlist 5473 U1 : NAND4MAC 5474 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5475 port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); 5476 5477 U2 : NAND2MAC 5478 port map( I0 => i6, I1 => i7, Y => n4); 5479 5480 U3 : NAND2MAC 5481 port map( I0 => i4, I1 => i5, Y => n3); 5482 5483 U4 : NAND2MAC 5484 port map( I0 => i2, I1 => i3, Y => n2); 5485 5486 U5 : NAND2MAC 5487 port map( I0 => i0, I1 => i1, Y => n1); 5488 5489 5490end UDSM; 5491 5492configuration CFG_oa2a2a2a24_x4_UDSM of oa2a2a2a24_x4 is 5493 for UDSM 5494 end for; 5495end CFG_oa2a2a2a24_x4_UDSM; 5496 5497 5498----- CELL oa2a2a23_x2 ----- 5499library IEEE; 5500use IEEE.STD_LOGIC_1164.all; 5501library SYNOPSYS; 5502use SYNOPSYS.attributes.REAL_NAME; 5503 5504-- entity declaration -- 5505entity oa2a2a23_x2 is 5506 generic( 5507 Timing_mesg: Boolean := True; 5508 Timing_xgen: Boolean := False; 5509 tpdi0_q_R : Time := 0.653 ns; 5510 tpdi0_q_F : Time := 0.578 ns; 5511 tpdi1_q_R : Time := 0.775 ns; 5512 tpdi1_q_F : Time := 0.542 ns; 5513 tpdi2_q_R : Time := 0.441 ns; 5514 tpdi2_q_F : Time := 0.639 ns; 5515 tpdi3_q_R : Time := 0.540 ns; 5516 tpdi3_q_F : Time := 0.600 ns; 5517 tpdi4_q_R : Time := 0.402 ns; 5518 tpdi4_q_F : Time := 0.591 ns; 5519 tpdi5_q_R : Time := 0.321 ns; 5520 tpdi5_q_F : Time := 0.636 ns; 5521 twdi0_R : Time := 0.000 ns; 5522 twdi0_F : Time := 0.000 ns; 5523 twdi1_R : Time := 0.000 ns; 5524 twdi1_F : Time := 0.000 ns; 5525 twdi2_R : Time := 0.000 ns; 5526 twdi2_F : Time := 0.000 ns; 5527 twdi3_R : Time := 0.000 ns; 5528 twdi3_F : Time := 0.000 ns; 5529 twdi4_R : Time := 0.000 ns; 5530 twdi4_F : Time := 0.000 ns; 5531 twdi5_R : Time := 0.000 ns; 5532 twdi5_F : Time := 0.000 ns); 5533 5534 port( 5535 i0 : in STD_LOGIC; 5536 i1 : in STD_LOGIC; 5537 i2 : in STD_LOGIC; 5538 i3 : in STD_LOGIC; 5539 i4 : in STD_LOGIC; 5540 i5 : in STD_LOGIC; 5541 q : out STD_LOGIC); 5542end oa2a2a23_x2; 5543 5544-- architecture body -- 5545library IEEE_ASIC; 5546use IEEE.STD_LOGIC_MISC.all; 5547use SYNOPSYS.attributes.backplane; 5548use SYNOPSYS.attributes.PRIVATE; 5549use SYNOPSYS.attributes.ASIC_CELL; 5550 5551architecture UDSM of oa2a2a23_x2 is 5552 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5553 attribute PRIVATE of UDSM : architecture is TRUE; 5554 attribute ASIC_CELL of UDSM : architecture is TRUE; 5555 5556 signal n1, n2, n3 : STD_LOGIC; 5557 5558 component NAND3MAC 5559 generic( 5560 tpdY_R : Time := 0 ns; 5561 tpdY_F : Time := 0 ns; 5562 strn : STRENGTH := strn_X01); 5563 port( 5564 I0 : in STD_LOGIC; 5565 I1 : in STD_LOGIC; 5566 I2 : in STD_LOGIC; 5567 Y : out STD_LOGIC); 5568 end component; 5569 5570 component NAND2MAC 5571 generic( 5572 tpdY_R : Time := 0 ns; 5573 tpdY_F : Time := 0 ns; 5574 strn : STRENGTH := strn_X01); 5575 port( 5576 I0 : in STD_LOGIC; 5577 I1 : in STD_LOGIC; 5578 Y : out STD_LOGIC); 5579 end component; 5580 5581begin 5582 5583 -- Netlist 5584 U1 : NAND3MAC 5585 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5586 port map( I0 => n1, I1 => n2, I2 => n3, Y => q); 5587 5588 U2 : NAND2MAC 5589 port map( I0 => i4, I1 => i5, Y => n2); 5590 5591 U3 : NAND2MAC 5592 port map( I0 => i2, I1 => i3, Y => n1); 5593 5594 U4 : NAND2MAC 5595 port map( I0 => i0, I1 => i1, Y => n3); 5596 5597 5598end UDSM; 5599 5600configuration CFG_oa2a2a23_x2_UDSM of oa2a2a23_x2 is 5601 for UDSM 5602 end for; 5603end CFG_oa2a2a23_x2_UDSM; 5604 5605 5606----- CELL oa2a2a23_x4 ----- 5607library IEEE; 5608use IEEE.STD_LOGIC_1164.all; 5609library SYNOPSYS; 5610use SYNOPSYS.attributes.REAL_NAME; 5611 5612-- entity declaration -- 5613entity oa2a2a23_x4 is 5614 generic( 5615 Timing_mesg: Boolean := True; 5616 Timing_xgen: Boolean := False; 5617 tpdi0_q_R : Time := 0.699 ns; 5618 tpdi0_q_F : Time := 0.648 ns; 5619 tpdi1_q_R : Time := 0.822 ns; 5620 tpdi1_q_F : Time := 0.613 ns; 5621 tpdi2_q_R : Time := 0.493 ns; 5622 tpdi2_q_F : Time := 0.715 ns; 5623 tpdi3_q_R : Time := 0.594 ns; 5624 tpdi3_q_F : Time := 0.677 ns; 5625 tpdi4_q_R : Time := 0.464 ns; 5626 tpdi4_q_F : Time := 0.673 ns; 5627 tpdi5_q_R : Time := 0.379 ns; 5628 tpdi5_q_F : Time := 0.714 ns; 5629 twdi0_R : Time := 0.000 ns; 5630 twdi0_F : Time := 0.000 ns; 5631 twdi1_R : Time := 0.000 ns; 5632 twdi1_F : Time := 0.000 ns; 5633 twdi2_R : Time := 0.000 ns; 5634 twdi2_F : Time := 0.000 ns; 5635 twdi3_R : Time := 0.000 ns; 5636 twdi3_F : Time := 0.000 ns; 5637 twdi4_R : Time := 0.000 ns; 5638 twdi4_F : Time := 0.000 ns; 5639 twdi5_R : Time := 0.000 ns; 5640 twdi5_F : Time := 0.000 ns); 5641 5642 port( 5643 i0 : in STD_LOGIC; 5644 i1 : in STD_LOGIC; 5645 i2 : in STD_LOGIC; 5646 i3 : in STD_LOGIC; 5647 i4 : in STD_LOGIC; 5648 i5 : in STD_LOGIC; 5649 q : out STD_LOGIC); 5650end oa2a2a23_x4; 5651 5652-- architecture body -- 5653library IEEE_ASIC; 5654use IEEE.STD_LOGIC_MISC.all; 5655use SYNOPSYS.attributes.backplane; 5656use SYNOPSYS.attributes.PRIVATE; 5657use SYNOPSYS.attributes.ASIC_CELL; 5658 5659architecture UDSM of oa2a2a23_x4 is 5660 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5661 attribute PRIVATE of UDSM : architecture is TRUE; 5662 attribute ASIC_CELL of UDSM : architecture is TRUE; 5663 5664 signal n1, n2, n3 : STD_LOGIC; 5665 5666 component NAND3MAC 5667 generic( 5668 tpdY_R : Time := 0 ns; 5669 tpdY_F : Time := 0 ns; 5670 strn : STRENGTH := strn_X01); 5671 port( 5672 I0 : in STD_LOGIC; 5673 I1 : in STD_LOGIC; 5674 I2 : in STD_LOGIC; 5675 Y : out STD_LOGIC); 5676 end component; 5677 5678 component NAND2MAC 5679 generic( 5680 tpdY_R : Time := 0 ns; 5681 tpdY_F : Time := 0 ns; 5682 strn : STRENGTH := strn_X01); 5683 port( 5684 I0 : in STD_LOGIC; 5685 I1 : in STD_LOGIC; 5686 Y : out STD_LOGIC); 5687 end component; 5688 5689begin 5690 5691 -- Netlist 5692 U1 : NAND3MAC 5693 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5694 port map( I0 => n1, I1 => n2, I2 => n3, Y => q); 5695 5696 U2 : NAND2MAC 5697 port map( I0 => i4, I1 => i5, Y => n2); 5698 5699 U3 : NAND2MAC 5700 port map( I0 => i2, I1 => i3, Y => n1); 5701 5702 U4 : NAND2MAC 5703 port map( I0 => i0, I1 => i1, Y => n3); 5704 5705 5706end UDSM; 5707 5708configuration CFG_oa2a2a23_x4_UDSM of oa2a2a23_x4 is 5709 for UDSM 5710 end for; 5711end CFG_oa2a2a23_x4_UDSM; 5712 5713 5714----- CELL oa2a22_x2 ----- 5715library IEEE; 5716use IEEE.STD_LOGIC_1164.all; 5717library SYNOPSYS; 5718use SYNOPSYS.attributes.REAL_NAME; 5719 5720-- entity declaration -- 5721entity oa2a22_x2 is 5722 generic( 5723 Timing_mesg: Boolean := True; 5724 Timing_xgen: Boolean := False; 5725 tpdi0_q_R : Time := 0.403 ns; 5726 tpdi0_q_F : Time := 0.564 ns; 5727 tpdi1_q_R : Time := 0.495 ns; 5728 tpdi1_q_F : Time := 0.534 ns; 5729 tpdi2_q_R : Time := 0.646 ns; 5730 tpdi2_q_F : Time := 0.487 ns; 5731 tpdi3_q_R : Time := 0.537 ns; 5732 tpdi3_q_F : Time := 0.512 ns; 5733 twdi0_R : Time := 0.000 ns; 5734 twdi0_F : Time := 0.000 ns; 5735 twdi1_R : Time := 0.000 ns; 5736 twdi1_F : Time := 0.000 ns; 5737 twdi2_R : Time := 0.000 ns; 5738 twdi2_F : Time := 0.000 ns; 5739 twdi3_R : Time := 0.000 ns; 5740 twdi3_F : Time := 0.000 ns); 5741 5742 port( 5743 i0 : in STD_LOGIC; 5744 i1 : in STD_LOGIC; 5745 i2 : in STD_LOGIC; 5746 i3 : in STD_LOGIC; 5747 q : out STD_LOGIC); 5748end oa2a22_x2; 5749 5750-- architecture body -- 5751library IEEE_ASIC; 5752use IEEE.STD_LOGIC_MISC.all; 5753use SYNOPSYS.attributes.backplane; 5754use SYNOPSYS.attributes.PRIVATE; 5755use SYNOPSYS.attributes.ASIC_CELL; 5756 5757architecture UDSM of oa2a22_x2 is 5758 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5759 attribute PRIVATE of UDSM : architecture is TRUE; 5760 attribute ASIC_CELL of UDSM : architecture is TRUE; 5761 5762 signal n1, n2 : STD_LOGIC; 5763 5764 component NAND2MAC 5765 generic( 5766 tpdY_R : Time := 0 ns; 5767 tpdY_F : Time := 0 ns; 5768 strn : STRENGTH := strn_X01); 5769 port( 5770 I0 : in STD_LOGIC; 5771 I1 : in STD_LOGIC; 5772 Y : out STD_LOGIC); 5773 end component; 5774 5775begin 5776 5777 -- Netlist 5778 U1 : NAND2MAC 5779 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5780 port map( I0 => n1, I1 => n2, Y => q); 5781 5782 U2 : NAND2MAC 5783 port map( I0 => i2, I1 => i3, Y => n2); 5784 5785 U3 : NAND2MAC 5786 port map( I0 => i0, I1 => i1, Y => n1); 5787 5788 5789end UDSM; 5790 5791configuration CFG_oa2a22_x2_UDSM of oa2a22_x2 is 5792 for UDSM 5793 end for; 5794end CFG_oa2a22_x2_UDSM; 5795 5796 5797----- CELL oa2a22_x4 ----- 5798library IEEE; 5799use IEEE.STD_LOGIC_1164.all; 5800library SYNOPSYS; 5801use SYNOPSYS.attributes.REAL_NAME; 5802 5803-- entity declaration -- 5804entity oa2a22_x4 is 5805 generic( 5806 Timing_mesg: Boolean := True; 5807 Timing_xgen: Boolean := False; 5808 tpdi0_q_R : Time := 0.519 ns; 5809 tpdi0_q_F : Time := 0.696 ns; 5810 tpdi1_q_R : Time := 0.624 ns; 5811 tpdi1_q_F : Time := 0.669 ns; 5812 tpdi2_q_R : Time := 0.763 ns; 5813 tpdi2_q_F : Time := 0.596 ns; 5814 tpdi3_q_R : Time := 0.644 ns; 5815 tpdi3_q_F : Time := 0.619 ns; 5816 twdi0_R : Time := 0.000 ns; 5817 twdi0_F : Time := 0.000 ns; 5818 twdi1_R : Time := 0.000 ns; 5819 twdi1_F : Time := 0.000 ns; 5820 twdi2_R : Time := 0.000 ns; 5821 twdi2_F : Time := 0.000 ns; 5822 twdi3_R : Time := 0.000 ns; 5823 twdi3_F : Time := 0.000 ns); 5824 5825 port( 5826 i0 : in STD_LOGIC; 5827 i1 : in STD_LOGIC; 5828 i2 : in STD_LOGIC; 5829 i3 : in STD_LOGIC; 5830 q : out STD_LOGIC); 5831end oa2a22_x4; 5832 5833-- architecture body -- 5834library IEEE_ASIC; 5835use IEEE.STD_LOGIC_MISC.all; 5836use SYNOPSYS.attributes.backplane; 5837use SYNOPSYS.attributes.PRIVATE; 5838use SYNOPSYS.attributes.ASIC_CELL; 5839 5840architecture UDSM of oa2a22_x4 is 5841 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5842 attribute PRIVATE of UDSM : architecture is TRUE; 5843 attribute ASIC_CELL of UDSM : architecture is TRUE; 5844 5845 signal n1, n2 : STD_LOGIC; 5846 5847 component NAND2MAC 5848 generic( 5849 tpdY_R : Time := 0 ns; 5850 tpdY_F : Time := 0 ns; 5851 strn : STRENGTH := strn_X01); 5852 port( 5853 I0 : in STD_LOGIC; 5854 I1 : in STD_LOGIC; 5855 Y : out STD_LOGIC); 5856 end component; 5857 5858begin 5859 5860 -- Netlist 5861 U1 : NAND2MAC 5862 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5863 port map( I0 => n1, I1 => n2, Y => q); 5864 5865 U2 : NAND2MAC 5866 port map( I0 => i2, I1 => i3, Y => n2); 5867 5868 U3 : NAND2MAC 5869 port map( I0 => i0, I1 => i1, Y => n1); 5870 5871 5872end UDSM; 5873 5874configuration CFG_oa2a22_x4_UDSM of oa2a22_x4 is 5875 for UDSM 5876 end for; 5877end CFG_oa2a22_x4_UDSM; 5878 5879 5880----- CELL oa2ao222_x2 ----- 5881library IEEE; 5882use IEEE.STD_LOGIC_1164.all; 5883library SYNOPSYS; 5884use SYNOPSYS.attributes.REAL_NAME; 5885 5886-- entity declaration -- 5887entity oa2ao222_x2 is 5888 generic( 5889 Timing_mesg: Boolean := True; 5890 Timing_xgen: Boolean := False; 5891 tpdi0_q_R : Time := 0.495 ns; 5892 tpdi0_q_F : Time := 0.581 ns; 5893 tpdi1_q_R : Time := 0.598 ns; 5894 tpdi1_q_F : Time := 0.539 ns; 5895 tpdi2_q_R : Time := 0.464 ns; 5896 tpdi2_q_F : Time := 0.604 ns; 5897 tpdi3_q_R : Time := 0.556 ns; 5898 tpdi3_q_F : Time := 0.578 ns; 5899 tpdi4_q_R : Time := 0.558 ns; 5900 tpdi4_q_F : Time := 0.453 ns; 5901 twdi0_R : Time := 0.000 ns; 5902 twdi0_F : Time := 0.000 ns; 5903 twdi1_R : Time := 0.000 ns; 5904 twdi1_F : Time := 0.000 ns; 5905 twdi2_R : Time := 0.000 ns; 5906 twdi2_F : Time := 0.000 ns; 5907 twdi3_R : Time := 0.000 ns; 5908 twdi3_F : Time := 0.000 ns; 5909 twdi4_R : Time := 0.000 ns; 5910 twdi4_F : Time := 0.000 ns); 5911 5912 port( 5913 i0 : in STD_LOGIC; 5914 i1 : in STD_LOGIC; 5915 i2 : in STD_LOGIC; 5916 i3 : in STD_LOGIC; 5917 i4 : in STD_LOGIC; 5918 q : out STD_LOGIC); 5919end oa2ao222_x2; 5920 5921-- architecture body -- 5922library IEEE_ASIC; 5923use IEEE.STD_LOGIC_MISC.all; 5924use SYNOPSYS.attributes.backplane; 5925use SYNOPSYS.attributes.PRIVATE; 5926use SYNOPSYS.attributes.ASIC_CELL; 5927 5928architecture UDSM of oa2ao222_x2 is 5929 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 5930 attribute PRIVATE of UDSM : architecture is TRUE; 5931 attribute ASIC_CELL of UDSM : architecture is TRUE; 5932 5933 signal n1, n2, n3 : STD_LOGIC; 5934 5935 component NAND2MAC 5936 generic( 5937 tpdY_R : Time := 0 ns; 5938 tpdY_F : Time := 0 ns; 5939 strn : STRENGTH := strn_X01); 5940 port( 5941 I0 : in STD_LOGIC; 5942 I1 : in STD_LOGIC; 5943 Y : out STD_LOGIC); 5944 end component; 5945 5946 component OR2MAC 5947 generic( 5948 tpdY_R : Time := 0 ns; 5949 tpdY_F : Time := 0 ns; 5950 strn : STRENGTH := strn_X01); 5951 port( 5952 I0 : in STD_LOGIC; 5953 I1 : in STD_LOGIC; 5954 Y : out STD_LOGIC); 5955 end component; 5956 5957begin 5958 5959 -- Netlist 5960 U1 : NAND2MAC 5961 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 5962 port map( I0 => n1, I1 => n2, Y => q); 5963 5964 U2 : OR2MAC 5965 port map( I0 => i3, I1 => i2, Y => n3); 5966 5967 U3 : NAND2MAC 5968 port map( I0 => i4, I1 => n3, Y => n2); 5969 5970 U4 : NAND2MAC 5971 port map( I0 => i0, I1 => i1, Y => n1); 5972 5973 5974end UDSM; 5975 5976configuration CFG_oa2ao222_x2_UDSM of oa2ao222_x2 is 5977 for UDSM 5978 end for; 5979end CFG_oa2ao222_x2_UDSM; 5980 5981 5982----- CELL oa2ao222_x4 ----- 5983library IEEE; 5984use IEEE.STD_LOGIC_1164.all; 5985library SYNOPSYS; 5986use SYNOPSYS.attributes.REAL_NAME; 5987 5988-- entity declaration -- 5989entity oa2ao222_x4 is 5990 generic( 5991 Timing_mesg: Boolean := True; 5992 Timing_xgen: Boolean := False; 5993 tpdi0_q_R : Time := 0.553 ns; 5994 tpdi0_q_F : Time := 0.657 ns; 5995 tpdi1_q_R : Time := 0.662 ns; 5996 tpdi1_q_F : Time := 0.616 ns; 5997 tpdi2_q_R : Time := 0.552 ns; 5998 tpdi2_q_F : Time := 0.693 ns; 5999 tpdi3_q_R : Time := 0.640 ns; 6000 tpdi3_q_F : Time := 0.660 ns; 6001 tpdi4_q_R : Time := 0.656 ns; 6002 tpdi4_q_F : Time := 0.529 ns; 6003 twdi0_R : Time := 0.000 ns; 6004 twdi0_F : Time := 0.000 ns; 6005 twdi1_R : Time := 0.000 ns; 6006 twdi1_F : Time := 0.000 ns; 6007 twdi2_R : Time := 0.000 ns; 6008 twdi2_F : Time := 0.000 ns; 6009 twdi3_R : Time := 0.000 ns; 6010 twdi3_F : Time := 0.000 ns; 6011 twdi4_R : Time := 0.000 ns; 6012 twdi4_F : Time := 0.000 ns); 6013 6014 port( 6015 i0 : in STD_LOGIC; 6016 i1 : in STD_LOGIC; 6017 i2 : in STD_LOGIC; 6018 i3 : in STD_LOGIC; 6019 i4 : in STD_LOGIC; 6020 q : out STD_LOGIC); 6021end oa2ao222_x4; 6022 6023-- architecture body -- 6024library IEEE_ASIC; 6025use IEEE.STD_LOGIC_MISC.all; 6026use SYNOPSYS.attributes.backplane; 6027use SYNOPSYS.attributes.PRIVATE; 6028use SYNOPSYS.attributes.ASIC_CELL; 6029 6030architecture UDSM of oa2ao222_x4 is 6031 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6032 attribute PRIVATE of UDSM : architecture is TRUE; 6033 attribute ASIC_CELL of UDSM : architecture is TRUE; 6034 6035 signal n1, n2, n3 : STD_LOGIC; 6036 6037 component NAND2MAC 6038 generic( 6039 tpdY_R : Time := 0 ns; 6040 tpdY_F : Time := 0 ns; 6041 strn : STRENGTH := strn_X01); 6042 port( 6043 I0 : in STD_LOGIC; 6044 I1 : in STD_LOGIC; 6045 Y : out STD_LOGIC); 6046 end component; 6047 6048 component OR2MAC 6049 generic( 6050 tpdY_R : Time := 0 ns; 6051 tpdY_F : Time := 0 ns; 6052 strn : STRENGTH := strn_X01); 6053 port( 6054 I0 : in STD_LOGIC; 6055 I1 : in STD_LOGIC; 6056 Y : out STD_LOGIC); 6057 end component; 6058 6059begin 6060 6061 -- Netlist 6062 U1 : NAND2MAC 6063 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 6064 port map( I0 => n1, I1 => n2, Y => q); 6065 6066 U2 : OR2MAC 6067 port map( I0 => i3, I1 => i2, Y => n3); 6068 6069 U3 : NAND2MAC 6070 port map( I0 => i4, I1 => n3, Y => n2); 6071 6072 U4 : NAND2MAC 6073 port map( I0 => i0, I1 => i1, Y => n1); 6074 6075 6076end UDSM; 6077 6078configuration CFG_oa2ao222_x4_UDSM of oa2ao222_x4 is 6079 for UDSM 6080 end for; 6081end CFG_oa2ao222_x4_UDSM; 6082 6083 6084----- CELL oa3ao322_x2 ----- 6085library IEEE; 6086use IEEE.STD_LOGIC_1164.all; 6087library SYNOPSYS; 6088use SYNOPSYS.attributes.REAL_NAME; 6089 6090-- entity declaration -- 6091entity oa3ao322_x2 is 6092 generic( 6093 Timing_mesg: Boolean := True; 6094 Timing_xgen: Boolean := False; 6095 tpdi0_q_R : Time := 0.638 ns; 6096 tpdi0_q_F : Time := 0.820 ns; 6097 tpdi1_q_R : Time := 0.735 ns; 6098 tpdi1_q_F : Time := 0.764 ns; 6099 tpdi2_q_R : Time := 0.806 ns; 6100 tpdi2_q_F : Time := 0.707 ns; 6101 tpdi3_q_R : Time := 0.560 ns; 6102 tpdi3_q_F : Time := 0.765 ns; 6103 tpdi4_q_R : Time := 0.649 ns; 6104 tpdi4_q_F : Time := 0.760 ns; 6105 tpdi5_q_R : Time := 0.734 ns; 6106 tpdi5_q_F : Time := 0.734 ns; 6107 tpdi6_q_R : Time := 0.563 ns; 6108 tpdi6_q_F : Time := 0.540 ns; 6109 twdi0_R : Time := 0.000 ns; 6110 twdi0_F : Time := 0.000 ns; 6111 twdi1_R : Time := 0.000 ns; 6112 twdi1_F : Time := 0.000 ns; 6113 twdi2_R : Time := 0.000 ns; 6114 twdi2_F : Time := 0.000 ns; 6115 twdi3_R : Time := 0.000 ns; 6116 twdi3_F : Time := 0.000 ns; 6117 twdi4_R : Time := 0.000 ns; 6118 twdi4_F : Time := 0.000 ns; 6119 twdi5_R : Time := 0.000 ns; 6120 twdi5_F : Time := 0.000 ns; 6121 twdi6_R : Time := 0.000 ns; 6122 twdi6_F : Time := 0.000 ns); 6123 6124 port( 6125 i0 : in STD_LOGIC; 6126 i1 : in STD_LOGIC; 6127 i2 : in STD_LOGIC; 6128 i3 : in STD_LOGIC; 6129 i4 : in STD_LOGIC; 6130 i5 : in STD_LOGIC; 6131 i6 : in STD_LOGIC; 6132 q : out STD_LOGIC); 6133end oa3ao322_x2; 6134 6135-- architecture body -- 6136library IEEE_ASIC; 6137use IEEE.STD_LOGIC_MISC.all; 6138use SYNOPSYS.attributes.backplane; 6139use SYNOPSYS.attributes.PRIVATE; 6140use SYNOPSYS.attributes.ASIC_CELL; 6141 6142architecture UDSM of oa3ao322_x2 is 6143 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6144 attribute PRIVATE of UDSM : architecture is TRUE; 6145 attribute ASIC_CELL of UDSM : architecture is TRUE; 6146 6147 signal n1, n2, n3 : STD_LOGIC; 6148 6149 component NAND2MAC 6150 generic( 6151 tpdY_R : Time := 0 ns; 6152 tpdY_F : Time := 0 ns; 6153 strn : STRENGTH := strn_X01); 6154 port( 6155 I0 : in STD_LOGIC; 6156 I1 : in STD_LOGIC; 6157 Y : out STD_LOGIC); 6158 end component; 6159 6160 component OR3MAC 6161 generic( 6162 tpdY_R : Time := 0 ns; 6163 tpdY_F : Time := 0 ns; 6164 strn : STRENGTH := strn_X01); 6165 port( 6166 I0 : in STD_LOGIC; 6167 I1 : in STD_LOGIC; 6168 I2 : in STD_LOGIC; 6169 Y : out STD_LOGIC); 6170 end component; 6171 6172 component NAND3MAC 6173 generic( 6174 tpdY_R : Time := 0 ns; 6175 tpdY_F : Time := 0 ns; 6176 strn : STRENGTH := strn_X01); 6177 port( 6178 I0 : in STD_LOGIC; 6179 I1 : in STD_LOGIC; 6180 I2 : in STD_LOGIC; 6181 Y : out STD_LOGIC); 6182 end component; 6183 6184begin 6185 6186 -- Netlist 6187 U1 : NAND2MAC 6188 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 6189 port map( I0 => n1, I1 => n2, Y => q); 6190 6191 U2 : OR3MAC 6192 port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); 6193 6194 U3 : NAND3MAC 6195 port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); 6196 6197 U4 : NAND2MAC 6198 port map( I0 => i6, I1 => n3, Y => n1); 6199 6200 6201end UDSM; 6202 6203configuration CFG_oa3ao322_x2_UDSM of oa3ao322_x2 is 6204 for UDSM 6205 end for; 6206end CFG_oa3ao322_x2_UDSM; 6207 6208 6209----- CELL oa3ao322_x4 ----- 6210library IEEE; 6211use IEEE.STD_LOGIC_1164.all; 6212library SYNOPSYS; 6213use SYNOPSYS.attributes.REAL_NAME; 6214 6215-- entity declaration -- 6216entity oa3ao322_x4 is 6217 generic( 6218 Timing_mesg: Boolean := True; 6219 Timing_xgen: Boolean := False; 6220 tpdi0_q_R : Time := 0.717 ns; 6221 tpdi0_q_F : Time := 0.946 ns; 6222 tpdi1_q_R : Time := 0.818 ns; 6223 tpdi1_q_F : Time := 0.890 ns; 6224 tpdi2_q_R : Time := 0.894 ns; 6225 tpdi2_q_F : Time := 0.834 ns; 6226 tpdi3_q_R : Time := 0.673 ns; 6227 tpdi3_q_F : Time := 0.898 ns; 6228 tpdi4_q_R : Time := 0.758 ns; 6229 tpdi4_q_F : Time := 0.896 ns; 6230 tpdi5_q_R : Time := 0.839 ns; 6231 tpdi5_q_F : Time := 0.865 ns; 6232 tpdi6_q_R : Time := 0.684 ns; 6233 tpdi6_q_F : Time := 0.651 ns; 6234 twdi0_R : Time := 0.000 ns; 6235 twdi0_F : Time := 0.000 ns; 6236 twdi1_R : Time := 0.000 ns; 6237 twdi1_F : Time := 0.000 ns; 6238 twdi2_R : Time := 0.000 ns; 6239 twdi2_F : Time := 0.000 ns; 6240 twdi3_R : Time := 0.000 ns; 6241 twdi3_F : Time := 0.000 ns; 6242 twdi4_R : Time := 0.000 ns; 6243 twdi4_F : Time := 0.000 ns; 6244 twdi5_R : Time := 0.000 ns; 6245 twdi5_F : Time := 0.000 ns; 6246 twdi6_R : Time := 0.000 ns; 6247 twdi6_F : Time := 0.000 ns); 6248 6249 port( 6250 i0 : in STD_LOGIC; 6251 i1 : in STD_LOGIC; 6252 i2 : in STD_LOGIC; 6253 i3 : in STD_LOGIC; 6254 i4 : in STD_LOGIC; 6255 i5 : in STD_LOGIC; 6256 i6 : in STD_LOGIC; 6257 q : out STD_LOGIC); 6258end oa3ao322_x4; 6259 6260-- architecture body -- 6261library IEEE_ASIC; 6262use IEEE.STD_LOGIC_MISC.all; 6263use SYNOPSYS.attributes.backplane; 6264use SYNOPSYS.attributes.PRIVATE; 6265use SYNOPSYS.attributes.ASIC_CELL; 6266 6267architecture UDSM of oa3ao322_x4 is 6268 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6269 attribute PRIVATE of UDSM : architecture is TRUE; 6270 attribute ASIC_CELL of UDSM : architecture is TRUE; 6271 6272 signal n1, n2, n3 : STD_LOGIC; 6273 6274 component NAND2MAC 6275 generic( 6276 tpdY_R : Time := 0 ns; 6277 tpdY_F : Time := 0 ns; 6278 strn : STRENGTH := strn_X01); 6279 port( 6280 I0 : in STD_LOGIC; 6281 I1 : in STD_LOGIC; 6282 Y : out STD_LOGIC); 6283 end component; 6284 6285 component OR3MAC 6286 generic( 6287 tpdY_R : Time := 0 ns; 6288 tpdY_F : Time := 0 ns; 6289 strn : STRENGTH := strn_X01); 6290 port( 6291 I0 : in STD_LOGIC; 6292 I1 : in STD_LOGIC; 6293 I2 : in STD_LOGIC; 6294 Y : out STD_LOGIC); 6295 end component; 6296 6297 component NAND3MAC 6298 generic( 6299 tpdY_R : Time := 0 ns; 6300 tpdY_F : Time := 0 ns; 6301 strn : STRENGTH := strn_X01); 6302 port( 6303 I0 : in STD_LOGIC; 6304 I1 : in STD_LOGIC; 6305 I2 : in STD_LOGIC; 6306 Y : out STD_LOGIC); 6307 end component; 6308 6309begin 6310 6311 -- Netlist 6312 U1 : NAND2MAC 6313 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 6314 port map( I0 => n1, I1 => n2, Y => q); 6315 6316 U2 : OR3MAC 6317 port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); 6318 6319 U3 : NAND3MAC 6320 port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); 6321 6322 U4 : NAND2MAC 6323 port map( I0 => i6, I1 => n3, Y => n1); 6324 6325 6326end UDSM; 6327 6328configuration CFG_oa3ao322_x4_UDSM of oa3ao322_x4 is 6329 for UDSM 6330 end for; 6331end CFG_oa3ao322_x4_UDSM; 6332 6333 6334----- CELL oa22_x2 ----- 6335library IEEE; 6336use IEEE.STD_LOGIC_1164.all; 6337library SYNOPSYS; 6338use SYNOPSYS.attributes.REAL_NAME; 6339 6340-- entity declaration -- 6341entity oa22_x2 is 6342 generic( 6343 Timing_mesg: Boolean := True; 6344 Timing_xgen: Boolean := False; 6345 tpdi0_q_R : Time := 0.390 ns; 6346 tpdi0_q_F : Time := 0.555 ns; 6347 tpdi1_q_R : Time := 0.488 ns; 6348 tpdi1_q_F : Time := 0.525 ns; 6349 tpdi2_q_R : Time := 0.438 ns; 6350 tpdi2_q_F : Time := 0.454 ns; 6351 twdi0_R : Time := 0.000 ns; 6352 twdi0_F : Time := 0.000 ns; 6353 twdi1_R : Time := 0.000 ns; 6354 twdi1_F : Time := 0.000 ns; 6355 twdi2_R : Time := 0.000 ns; 6356 twdi2_F : Time := 0.000 ns); 6357 6358 port( 6359 i0 : in STD_LOGIC; 6360 i1 : in STD_LOGIC; 6361 i2 : in STD_LOGIC; 6362 q : out STD_LOGIC); 6363end oa22_x2; 6364 6365-- architecture body -- 6366library IEEE_ASIC; 6367use IEEE.STD_LOGIC_MISC.all; 6368use SYNOPSYS.attributes.backplane; 6369use SYNOPSYS.attributes.PRIVATE; 6370use SYNOPSYS.attributes.ASIC_CELL; 6371 6372architecture UDSM of oa22_x2 is 6373 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6374 attribute PRIVATE of UDSM : architecture is TRUE; 6375 attribute ASIC_CELL of UDSM : architecture is TRUE; 6376 6377 signal n1 : STD_LOGIC; 6378 6379 component OR2MAC 6380 generic( 6381 tpdY_R : Time := 0 ns; 6382 tpdY_F : Time := 0 ns; 6383 strn : STRENGTH := strn_X01); 6384 port( 6385 I0 : in STD_LOGIC; 6386 I1 : in STD_LOGIC; 6387 Y : out STD_LOGIC); 6388 end component; 6389 6390 component AND2MAC 6391 generic( 6392 tpdY_R : Time := 0 ns; 6393 tpdY_F : Time := 0 ns; 6394 strn : STRENGTH := strn_X01); 6395 port( 6396 I0 : in STD_LOGIC; 6397 I1 : in STD_LOGIC; 6398 Y : out STD_LOGIC); 6399 end component; 6400 6401begin 6402 6403 -- Netlist 6404 U1 : OR2MAC 6405 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 6406 port map( I0 => n1, I1 => i2, Y => q); 6407 6408 U2 : AND2MAC 6409 port map( I0 => i0, I1 => i1, Y => n1); 6410 6411 6412end UDSM; 6413 6414configuration CFG_oa22_x2_UDSM of oa22_x2 is 6415 for UDSM 6416 end for; 6417end CFG_oa22_x2_UDSM; 6418 6419 6420----- CELL oa22_x4 ----- 6421library IEEE; 6422use IEEE.STD_LOGIC_1164.all; 6423library SYNOPSYS; 6424use SYNOPSYS.attributes.REAL_NAME; 6425 6426-- entity declaration -- 6427entity oa22_x4 is 6428 generic( 6429 Timing_mesg: Boolean := True; 6430 Timing_xgen: Boolean := False; 6431 tpdi0_q_R : Time := 0.511 ns; 6432 tpdi0_q_F : Time := 0.677 ns; 6433 tpdi1_q_R : Time := 0.615 ns; 6434 tpdi1_q_F : Time := 0.650 ns; 6435 tpdi2_q_R : Time := 0.523 ns; 6436 tpdi2_q_F : Time := 0.571 ns; 6437 twdi0_R : Time := 0.000 ns; 6438 twdi0_F : Time := 0.000 ns; 6439 twdi1_R : Time := 0.000 ns; 6440 twdi1_F : Time := 0.000 ns; 6441 twdi2_R : Time := 0.000 ns; 6442 twdi2_F : Time := 0.000 ns); 6443 6444 port( 6445 i0 : in STD_LOGIC; 6446 i1 : in STD_LOGIC; 6447 i2 : in STD_LOGIC; 6448 q : out STD_LOGIC); 6449end oa22_x4; 6450 6451-- architecture body -- 6452library IEEE_ASIC; 6453use IEEE.STD_LOGIC_MISC.all; 6454use SYNOPSYS.attributes.backplane; 6455use SYNOPSYS.attributes.PRIVATE; 6456use SYNOPSYS.attributes.ASIC_CELL; 6457 6458architecture UDSM of oa22_x4 is 6459 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6460 attribute PRIVATE of UDSM : architecture is TRUE; 6461 attribute ASIC_CELL of UDSM : architecture is TRUE; 6462 6463 signal n1 : STD_LOGIC; 6464 6465 component OR2MAC 6466 generic( 6467 tpdY_R : Time := 0 ns; 6468 tpdY_F : Time := 0 ns; 6469 strn : STRENGTH := strn_X01); 6470 port( 6471 I0 : in STD_LOGIC; 6472 I1 : in STD_LOGIC; 6473 Y : out STD_LOGIC); 6474 end component; 6475 6476 component AND2MAC 6477 generic( 6478 tpdY_R : Time := 0 ns; 6479 tpdY_F : Time := 0 ns; 6480 strn : STRENGTH := strn_X01); 6481 port( 6482 I0 : in STD_LOGIC; 6483 I1 : in STD_LOGIC; 6484 Y : out STD_LOGIC); 6485 end component; 6486 6487begin 6488 6489 -- Netlist 6490 U1 : OR2MAC 6491 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 6492 port map( I0 => n1, I1 => i2, Y => q); 6493 6494 U2 : AND2MAC 6495 port map( I0 => i0, I1 => i1, Y => n1); 6496 6497 6498end UDSM; 6499 6500configuration CFG_oa22_x4_UDSM of oa22_x4 is 6501 for UDSM 6502 end for; 6503end CFG_oa22_x4_UDSM; 6504 6505 6506----- CELL on12_x1 ----- 6507library IEEE; 6508use IEEE.STD_LOGIC_1164.all; 6509library SYNOPSYS; 6510use SYNOPSYS.attributes.REAL_NAME; 6511 6512-- entity declaration -- 6513entity on12_x1 is 6514 generic( 6515 Timing_mesg: Boolean := True; 6516 Timing_xgen: Boolean := False; 6517 tpdi0_q_R : Time := 0.111 ns; 6518 tpdi0_q_F : Time := 0.234 ns; 6519 tpdi1_q_R : Time := 0.314 ns; 6520 tpdi1_q_F : Time := 0.291 ns; 6521 twdi0_R : Time := 0.000 ns; 6522 twdi0_F : Time := 0.000 ns; 6523 twdi1_R : Time := 0.000 ns; 6524 twdi1_F : Time := 0.000 ns); 6525 6526 port( 6527 i0 : in STD_LOGIC; 6528 i1 : in STD_LOGIC; 6529 q : out STD_LOGIC); 6530end on12_x1; 6531 6532-- architecture body -- 6533library IEEE_ASIC; 6534use IEEE.STD_LOGIC_MISC.all; 6535use SYNOPSYS.attributes.backplane; 6536use SYNOPSYS.attributes.PRIVATE; 6537use SYNOPSYS.attributes.ASIC_CELL; 6538 6539architecture UDSM of on12_x1 is 6540 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6541 attribute PRIVATE of UDSM : architecture is TRUE; 6542 attribute ASIC_CELL of UDSM : architecture is TRUE; 6543 6544 signal n1 : STD_LOGIC; 6545 6546 component NAND2MAC 6547 generic( 6548 tpdY_R : Time := 0 ns; 6549 tpdY_F : Time := 0 ns; 6550 strn : STRENGTH := strn_X01); 6551 port( 6552 I0 : in STD_LOGIC; 6553 I1 : in STD_LOGIC; 6554 Y : out STD_LOGIC); 6555 end component; 6556 6557 component INVMAC 6558 generic( 6559 tpdY_R : Time := 0 ns; 6560 tpdY_F : Time := 0 ns; 6561 strn : STRENGTH := strn_X01); 6562 port( 6563 I0 : in STD_LOGIC; 6564 Y : out STD_LOGIC); 6565 end component; 6566 6567begin 6568 6569 -- Netlist 6570 U1 : NAND2MAC 6571 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 6572 port map( I0 => i0, I1 => n1, Y => q); 6573 6574 U2 : INVMAC 6575 port map( I0 => i1, Y => n1); 6576 6577 6578end UDSM; 6579 6580configuration CFG_on12_x1_UDSM of on12_x1 is 6581 for UDSM 6582 end for; 6583end CFG_on12_x1_UDSM; 6584 6585 6586----- CELL on12_x4 ----- 6587library IEEE; 6588use IEEE.STD_LOGIC_1164.all; 6589library SYNOPSYS; 6590use SYNOPSYS.attributes.REAL_NAME; 6591 6592-- entity declaration -- 6593entity on12_x4 is 6594 generic( 6595 Timing_mesg: Boolean := True; 6596 Timing_xgen: Boolean := False; 6597 tpdi0_q_R : Time := 0.474 ns; 6598 tpdi0_q_F : Time := 0.499 ns; 6599 tpdi1_q_R : Time := 0.491 ns; 6600 tpdi1_q_F : Time := 0.394 ns; 6601 twdi0_R : Time := 0.000 ns; 6602 twdi0_F : Time := 0.000 ns; 6603 twdi1_R : Time := 0.000 ns; 6604 twdi1_F : Time := 0.000 ns); 6605 6606 port( 6607 i0 : in STD_LOGIC; 6608 i1 : in STD_LOGIC; 6609 q : out STD_LOGIC); 6610end on12_x4; 6611 6612-- architecture body -- 6613library IEEE_ASIC; 6614use IEEE.STD_LOGIC_MISC.all; 6615use SYNOPSYS.attributes.backplane; 6616use SYNOPSYS.attributes.PRIVATE; 6617use SYNOPSYS.attributes.ASIC_CELL; 6618 6619architecture UDSM of on12_x4 is 6620 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6621 attribute PRIVATE of UDSM : architecture is TRUE; 6622 attribute ASIC_CELL of UDSM : architecture is TRUE; 6623 6624 signal n1 : STD_LOGIC; 6625 6626 component NAND2MAC 6627 generic( 6628 tpdY_R : Time := 0 ns; 6629 tpdY_F : Time := 0 ns; 6630 strn : STRENGTH := strn_X01); 6631 port( 6632 I0 : in STD_LOGIC; 6633 I1 : in STD_LOGIC; 6634 Y : out STD_LOGIC); 6635 end component; 6636 6637 component INVMAC 6638 generic( 6639 tpdY_R : Time := 0 ns; 6640 tpdY_F : Time := 0 ns; 6641 strn : STRENGTH := strn_X01); 6642 port( 6643 I0 : in STD_LOGIC; 6644 Y : out STD_LOGIC); 6645 end component; 6646 6647begin 6648 6649 -- Netlist 6650 U1 : NAND2MAC 6651 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 6652 port map( I0 => i0, I1 => n1, Y => q); 6653 6654 U2 : INVMAC 6655 port map( I0 => i1, Y => n1); 6656 6657 6658end UDSM; 6659 6660configuration CFG_on12_x4_UDSM of on12_x4 is 6661 for UDSM 6662 end for; 6663end CFG_on12_x4_UDSM; 6664 6665 6666----- CELL one_x0 ----- 6667library IEEE; 6668use IEEE.STD_LOGIC_1164.all; 6669library SYNOPSYS; 6670use SYNOPSYS.attributes.REAL_NAME; 6671 6672-- entity declaration -- 6673entity one_x0 is 6674 generic( 6675 Timing_mesg: Boolean := True; 6676 Timing_xgen: Boolean := False); 6677 6678 port( 6679 q : out STD_LOGIC := '1'); 6680end one_x0; 6681 6682-- architecture body -- 6683library IEEE_ASIC; 6684use IEEE.STD_LOGIC_MISC.all; 6685use SYNOPSYS.attributes.backplane; 6686use SYNOPSYS.attributes.PRIVATE; 6687use SYNOPSYS.attributes.ASIC_CELL; 6688 6689architecture UDSM of one_x0 is 6690 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6691 attribute PRIVATE of UDSM : architecture is TRUE; 6692 attribute ASIC_CELL of UDSM : architecture is TRUE; 6693 6694begin 6695 6696 -- Netlist 6697 q <= '1'; 6698 6699end UDSM; 6700 6701configuration CFG_one_x0_UDSM of one_x0 is 6702 for UDSM 6703 end for; 6704end CFG_one_x0_UDSM; 6705 6706 6707----- CELL sff1_x4 ----- 6708library IEEE; 6709use IEEE.STD_LOGIC_1164.all; 6710library SYNOPSYS; 6711use SYNOPSYS.attributes.REAL_NAME; 6712 6713-- entity declaration -- 6714entity sff1_x4 is 6715 generic( 6716 Timing_mesg: Boolean := True; 6717 Timing_xgen: Boolean := False; 6718 tpdck_q_R : Time := 0.500 ns; 6719 tpdck_q_F : Time := 0.500 ns; 6720 tsui_ck : Time := 0.585 ns; 6721 thck_i : Time := 0.000 ns; 6722 twdi_R : Time := 0.000 ns; 6723 twdi_F : Time := 0.000 ns; 6724 twdck_R : Time := 0.000 ns; 6725 twdck_F : Time := 0.000 ns); 6726 6727 port( 6728 i : in STD_LOGIC; 6729 ck : in STD_LOGIC; 6730 q : out STD_LOGIC); 6731end sff1_x4; 6732 6733-- architecture body -- 6734library IEEE_ASIC; 6735use IEEE.STD_LOGIC_MISC.all; 6736use SYNOPSYS.attributes.backplane; 6737use SYNOPSYS.attributes.PRIVATE; 6738use SYNOPSYS.attributes.ASIC_CELL; 6739 6740architecture UDSM of sff1_x4 is 6741 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6742 attribute PRIVATE of UDSM : architecture is TRUE; 6743 attribute ASIC_CELL of UDSM : architecture is TRUE; 6744 6745 signal n1 : STD_LOGIC; 6746 6747 component DFFLMAC 6748 generic( 6749 tpdY_R : Time := 0 ns; 6750 tpdY_F : Time := 0 ns; 6751 strn : STRENGTH := strn_X01); 6752 port( 6753 D : in STD_LOGIC; 6754 CLK : in STD_LOGIC; 6755 CLR : in STD_LOGIC; 6756 Q : out STD_LOGIC); 6757 end component; 6758 6759begin 6760 6761 -- Netlist 6762 U1 : DFFLMAC 6763 generic map( tpdY_R => 2 ns, tpdY_F => 2 ns) 6764 port map( D => i, CLK => ck, CLR => n1, Q => q); 6765 6766 n1 <= '1'; 6767 6768end UDSM; 6769 6770configuration CFG_sff1_x4_UDSM of sff1_x4 is 6771 for UDSM 6772 end for; 6773end CFG_sff1_x4_UDSM; 6774 6775 6776----- CELL sff2_x4 ----- 6777library IEEE; 6778use IEEE.STD_LOGIC_1164.all; 6779library SYNOPSYS; 6780use SYNOPSYS.attributes.REAL_NAME; 6781 6782-- entity declaration -- 6783entity sff2_x4 is 6784 generic( 6785 Timing_mesg: Boolean := True; 6786 Timing_xgen: Boolean := False; 6787 tpdck_q_R : Time := 0.500 ns; 6788 tpdck_q_F : Time := 0.500 ns; 6789 tsui0_ck : Time := 0.764 ns; 6790 thck_i0 : Time := 0.000 ns; 6791 tsui1_ck : Time := 0.764 ns; 6792 thck_i1 : Time := 0.000 ns; 6793 tsucmd_ck : Time := 0.833 ns; 6794 thck_cmd : Time := 0.000 ns; 6795 twdi0_R : Time := 0.000 ns; 6796 twdi0_F : Time := 0.000 ns; 6797 twdi1_R : Time := 0.000 ns; 6798 twdi1_F : Time := 0.000 ns; 6799 twdcmd_R : Time := 0.000 ns; 6800 twdcmd_F : Time := 0.000 ns; 6801 twdck_R : Time := 0.000 ns; 6802 twdck_F : Time := 0.000 ns); 6803 6804 port( 6805 i0 : in STD_LOGIC; 6806 i1 : in STD_LOGIC; 6807 cmd : in STD_LOGIC; 6808 ck : in STD_LOGIC; 6809 q : out STD_LOGIC); 6810end sff2_x4; 6811 6812-- architecture body -- 6813library IEEE_ASIC; 6814use IEEE.STD_LOGIC_MISC.all; 6815use SYNOPSYS.attributes.backplane; 6816use SYNOPSYS.attributes.PRIVATE; 6817use SYNOPSYS.attributes.ASIC_CELL; 6818 6819architecture UDSM of sff2_x4 is 6820 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6821 attribute PRIVATE of UDSM : architecture is TRUE; 6822 attribute ASIC_CELL of UDSM : architecture is TRUE; 6823 6824 signal n1, n2 : STD_LOGIC; 6825 6826 component MUX2MAC 6827 generic( 6828 tpdY_R : Time := 0 ns; 6829 tpdY_F : Time := 0 ns; 6830 strn : STRENGTH := strn_X01); 6831 port( 6832 I0 : in STD_LOGIC; 6833 I1 : in STD_LOGIC; 6834 S0 : in STD_LOGIC; 6835 Y : out STD_LOGIC); 6836 end component; 6837 6838 component DFFLMAC 6839 generic( 6840 tpdY_R : Time := 0 ns; 6841 tpdY_F : Time := 0 ns; 6842 strn : STRENGTH := strn_X01); 6843 port( 6844 D : in STD_LOGIC; 6845 CLK : in STD_LOGIC; 6846 CLR : in STD_LOGIC; 6847 Q : out STD_LOGIC); 6848 end component; 6849 6850begin 6851 6852 -- Netlist 6853 U1 : MUX2MAC 6854 port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); 6855 6856 U2 : DFFLMAC 6857 generic map( tpdY_R => 2 ns, tpdY_F => 2 ns) 6858 port map( D => n1, CLK => ck, CLR => n2, Q => q); 6859 6860 n2 <= '1'; 6861 6862end UDSM; 6863 6864configuration CFG_sff2_x4_UDSM of sff2_x4 is 6865 for UDSM 6866 end for; 6867end CFG_sff2_x4_UDSM; 6868 6869 6870----- CELL ts_x4 ----- 6871library IEEE; 6872use IEEE.STD_LOGIC_1164.all; 6873library SYNOPSYS; 6874use SYNOPSYS.attributes.REAL_NAME; 6875 6876-- entity declaration -- 6877entity ts_x4 is 6878 generic( 6879 Timing_mesg: Boolean := True; 6880 Timing_xgen: Boolean := False; 6881 tpdcmd_q_R : Time := 0.492 ns; 6882 tpdcmd_q_F : Time := 0.409 ns; 6883 tpdcmd_q_LZ : Time := 0.492 ns; 6884 tpdcmd_q_HZ : Time := 0.409 ns; 6885 tpdi_q_R : Time := 0.475 ns; 6886 tpdi_q_F : Time := 0.444 ns; 6887 twdi_R : Time := 0.000 ns; 6888 twdi_F : Time := 0.000 ns; 6889 twdcmd_R : Time := 0.000 ns; 6890 twdcmd_F : Time := 0.000 ns); 6891 6892 port( 6893 i : in STD_LOGIC; 6894 cmd : in STD_LOGIC; 6895 q : out STD_LOGIC); 6896end ts_x4; 6897 6898-- architecture body -- 6899library IEEE_ASIC; 6900use IEEE.STD_LOGIC_MISC.all; 6901use SYNOPSYS.attributes.backplane; 6902use SYNOPSYS.attributes.PRIVATE; 6903use SYNOPSYS.attributes.ASIC_CELL; 6904 6905architecture UDSM of ts_x4 is 6906 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6907 attribute PRIVATE of UDSM : architecture is TRUE; 6908 attribute ASIC_CELL of UDSM : architecture is TRUE; 6909 6910 component BUF3SHEMAC 6911 generic( 6912 tpdY_R : Time := 0 ns; 6913 tpdY_F : Time := 0 ns; 6914 strn : STRENGTH := strn_X01); 6915 port( 6916 I0 : in STD_LOGIC; 6917 OE : in STD_LOGIC; 6918 Y : out STD_LOGIC); 6919 end component; 6920 6921begin 6922 6923 -- Netlist 6924 U1 : BUF3SHEMAC 6925 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 6926 port map( I0 => i, OE => cmd, Y => q); 6927 6928 6929end UDSM; 6930 6931configuration CFG_ts_x4_UDSM of ts_x4 is 6932 for UDSM 6933 end for; 6934end CFG_ts_x4_UDSM; 6935 6936 6937----- CELL ts_x8 ----- 6938library IEEE; 6939use IEEE.STD_LOGIC_1164.all; 6940library SYNOPSYS; 6941use SYNOPSYS.attributes.REAL_NAME; 6942 6943-- entity declaration -- 6944entity ts_x8 is 6945 generic( 6946 Timing_mesg: Boolean := True; 6947 Timing_xgen: Boolean := False; 6948 tpdcmd_q_R : Time := 0.626 ns; 6949 tpdcmd_q_F : Time := 0.466 ns; 6950 tpdcmd_q_LZ : Time := 0.626 ns; 6951 tpdcmd_q_HZ : Time := 0.466 ns; 6952 tpdi_q_R : Time := 0.613 ns; 6953 tpdi_q_F : Time := 0.569 ns; 6954 twdi_R : Time := 0.000 ns; 6955 twdi_F : Time := 0.000 ns; 6956 twdcmd_R : Time := 0.000 ns; 6957 twdcmd_F : Time := 0.000 ns); 6958 6959 port( 6960 i : in STD_LOGIC; 6961 cmd : in STD_LOGIC; 6962 q : out STD_LOGIC); 6963end ts_x8; 6964 6965-- architecture body -- 6966library IEEE_ASIC; 6967use IEEE.STD_LOGIC_MISC.all; 6968use SYNOPSYS.attributes.backplane; 6969use SYNOPSYS.attributes.PRIVATE; 6970use SYNOPSYS.attributes.ASIC_CELL; 6971 6972architecture UDSM of ts_x8 is 6973 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 6974 attribute PRIVATE of UDSM : architecture is TRUE; 6975 attribute ASIC_CELL of UDSM : architecture is TRUE; 6976 6977 component BUF3SHEMAC 6978 generic( 6979 tpdY_R : Time := 0 ns; 6980 tpdY_F : Time := 0 ns; 6981 strn : STRENGTH := strn_X01); 6982 port( 6983 I0 : in STD_LOGIC; 6984 OE : in STD_LOGIC; 6985 Y : out STD_LOGIC); 6986 end component; 6987 6988begin 6989 6990 -- Netlist 6991 U1 : BUF3SHEMAC 6992 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 6993 port map( I0 => i, OE => cmd, Y => q); 6994 6995 6996end UDSM; 6997 6998configuration CFG_ts_x8_UDSM of ts_x8 is 6999 for UDSM 7000 end for; 7001end CFG_ts_x8_UDSM; 7002 7003 7004----- CELL xr2_x1 ----- 7005library IEEE; 7006use IEEE.STD_LOGIC_1164.all; 7007library SYNOPSYS; 7008use SYNOPSYS.attributes.REAL_NAME; 7009 7010-- entity declaration -- 7011entity xr2_x1 is 7012 generic( 7013 Timing_mesg: Boolean := True; 7014 Timing_xgen: Boolean := False; 7015 tpdi0_q_R : Time := 0.292 ns; 7016 tpdi0_q_F : Time := 0.293 ns; 7017 tpdi1_q_R : Time := 0.377 ns; 7018 tpdi1_q_F : Time := 0.261 ns; 7019 twdi0_R : Time := 0.000 ns; 7020 twdi0_F : Time := 0.000 ns; 7021 twdi1_R : Time := 0.000 ns; 7022 twdi1_F : Time := 0.000 ns); 7023 7024 port( 7025 i0 : in STD_LOGIC; 7026 i1 : in STD_LOGIC; 7027 q : out STD_LOGIC); 7028end xr2_x1; 7029 7030-- architecture body -- 7031library IEEE_ASIC; 7032use IEEE.STD_LOGIC_MISC.all; 7033use SYNOPSYS.attributes.backplane; 7034use SYNOPSYS.attributes.PRIVATE; 7035use SYNOPSYS.attributes.ASIC_CELL; 7036 7037architecture UDSM of xr2_x1 is 7038 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 7039 attribute PRIVATE of UDSM : architecture is TRUE; 7040 attribute ASIC_CELL of UDSM : architecture is TRUE; 7041 7042 component XOR2MAC 7043 generic( 7044 tpdY_R : Time := 0 ns; 7045 tpdY_F : Time := 0 ns; 7046 strn : STRENGTH := strn_X01); 7047 port( 7048 I0 : in STD_LOGIC; 7049 I1 : in STD_LOGIC; 7050 Y : out STD_LOGIC); 7051 end component; 7052 7053begin 7054 7055 -- Netlist 7056 U1 : XOR2MAC 7057 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 7058 port map( I0 => i1, I1 => i0, Y => q); 7059 7060 7061end UDSM; 7062 7063configuration CFG_xr2_x1_UDSM of xr2_x1 is 7064 for UDSM 7065 end for; 7066end CFG_xr2_x1_UDSM; 7067 7068 7069----- CELL xr2_x4 ----- 7070library IEEE; 7071use IEEE.STD_LOGIC_1164.all; 7072library SYNOPSYS; 7073use SYNOPSYS.attributes.REAL_NAME; 7074 7075-- entity declaration -- 7076entity xr2_x4 is 7077 generic( 7078 Timing_mesg: Boolean := True; 7079 Timing_xgen: Boolean := False; 7080 tpdi0_q_R : Time := 0.521 ns; 7081 tpdi0_q_F : Time := 0.560 ns; 7082 tpdi1_q_R : Time := 0.541 ns; 7083 tpdi1_q_F : Time := 0.657 ns; 7084 twdi0_R : Time := 0.000 ns; 7085 twdi0_F : Time := 0.000 ns; 7086 twdi1_R : Time := 0.000 ns; 7087 twdi1_F : Time := 0.000 ns); 7088 7089 port( 7090 i0 : in STD_LOGIC; 7091 i1 : in STD_LOGIC; 7092 q : out STD_LOGIC); 7093end xr2_x4; 7094 7095-- architecture body -- 7096library IEEE_ASIC; 7097use IEEE.STD_LOGIC_MISC.all; 7098use SYNOPSYS.attributes.backplane; 7099use SYNOPSYS.attributes.PRIVATE; 7100use SYNOPSYS.attributes.ASIC_CELL; 7101 7102architecture UDSM of xr2_x4 is 7103 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 7104 attribute PRIVATE of UDSM : architecture is TRUE; 7105 attribute ASIC_CELL of UDSM : architecture is TRUE; 7106 7107 component XOR2MAC 7108 generic( 7109 tpdY_R : Time := 0 ns; 7110 tpdY_F : Time := 0 ns; 7111 strn : STRENGTH := strn_X01); 7112 port( 7113 I0 : in STD_LOGIC; 7114 I1 : in STD_LOGIC; 7115 Y : out STD_LOGIC); 7116 end component; 7117 7118begin 7119 7120 -- Netlist 7121 U1 : XOR2MAC 7122 generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) 7123 port map( I0 => i1, I1 => i0, Y => q); 7124 7125 7126end UDSM; 7127 7128configuration CFG_xr2_x4_UDSM of xr2_x4 is 7129 for UDSM 7130 end for; 7131end CFG_xr2_x4_UDSM; 7132 7133 7134----- CELL zero_x0 ----- 7135library IEEE; 7136use IEEE.STD_LOGIC_1164.all; 7137library SYNOPSYS; 7138use SYNOPSYS.attributes.REAL_NAME; 7139 7140-- entity declaration -- 7141entity zero_x0 is 7142 generic( 7143 Timing_mesg: Boolean := True; 7144 Timing_xgen: Boolean := False); 7145 7146 port( 7147 nq : out STD_LOGIC := '0'); 7148end zero_x0; 7149 7150-- architecture body -- 7151library IEEE_ASIC; 7152use IEEE.STD_LOGIC_MISC.all; 7153use SYNOPSYS.attributes.backplane; 7154use SYNOPSYS.attributes.PRIVATE; 7155use SYNOPSYS.attributes.ASIC_CELL; 7156 7157architecture UDSM of zero_x0 is 7158 attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; 7159 attribute PRIVATE of UDSM : architecture is TRUE; 7160 attribute ASIC_CELL of UDSM : architecture is TRUE; 7161 7162begin 7163 7164 -- Netlist 7165 nq <= '0'; 7166 7167end UDSM; 7168 7169configuration CFG_zero_x0_UDSM of zero_x0 is 7170 for UDSM 7171 end for; 7172end CFG_zero_x0_UDSM; 7173 7174 7175---- end of library ---- 7176