1library IEEE; 2use IEEE.STD_LOGIC_1164.ALL; 3use IEEE.STD_LOGIC_arith.ALL; 4use IEEE.STD_LOGIC_unsigned.ALL; 5 6entity Sra is 7 8 port ( Shift : in Std_Logic ; 9 LD : in Std_Logic ; 10 RST : in Std_Logic; 11 CLK : in Std_Logic ; 12 A : in Std_Logic_Vector(7 downto 0); 13 14 Done : out Std_Logic ; 15 LSB : out Std_Logic ); 16 17end Sra; 18 19 20---------------------------------------------------------------------- 21 22architecture DataFlow OF Sra is 23 24signal outsint : Std_Logic_Vector(7 downto 0); 25begin 26process (CLK) 27begin 28 if CLK'event and CLK='1' then 29 if RST ='1' then outsint <= (others => '0'); 30 elsif LD = '1' then outsint <= A ; 31 elsif Shift= '1' then 32 outsint(7 downto 0) <= '0' & outsint(7 downto 1); 33 else outsint <= outsint; 34 end if; 35 end if; 36end process; 37 38process( outsint ) 39 variable RESULT : Std_Logic; 40begin 41 RESULT := '0'; 42 for j in outsint'range loop 43 RESULT := outsint(j) or RESULT; 44 exit when RESULT = '1'; 45 end loop; 46 RESULT := not(RESULT); 47 48 Done <= RESULT; 49end process; 50LSB <= outsint(0); 51 52end DataFlow; 53 54 55---------------------------------------------------------------------- 56